git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/io_apic_32.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/bootmem.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/pci.h>
  35 #include <linux/msi.h>
  36 #include <linux/htirq.h>
  37 #include <linux/freezer.h>
  38 #include <linux/kthread.h>
  39 #include <linux/jiffies.h>      /* time_after() */
  40
  41 #include <asm/io.h>
  42 #include <asm/smp.h>
  43 #include <asm/desc.h>
  44 #include <asm/timer.h>
  45 #include <asm/i8259.h>
  46 #include <asm/nmi.h>
  47 #include <asm/msidef.h>
  48 #include <asm/hypertransport.h>
  49
  50 #include <mach_apic.h>
  51 #include <mach_apicdef.h>
  52
  53 int (*ioapic_renumber_irq)(int ioapic, int irq);
  54 atomic_t irq_mis_count;
  55
  56 /* Where if anywhere is the i8259 connect in external int mode */
  57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  58
  59 static DEFINE_SPINLOCK(ioapic_lock);
  60 static DEFINE_SPINLOCK(vector_lock);
  61
  62 static bool mask_ioapic_irq_2 __initdata;
  63
  64 void __init force_mask_ioapic_irq_2(void)
  65 {
  66         mask_ioapic_irq_2 = true;
  67 }
  68
  69 int timer_through_8259 __initdata;
  70
  71 /*
  72  *      Is the SiS APIC rmw bug present ?
  73  *      -1 = don't know, 0 = no, 1 = yes
  74  */
  75 int sis_apic_bug = -1;
  76
  77 /*
  78  * # of IRQ routing registers
  79  */
  80 int nr_ioapic_registers[MAX_IO_APICS];
  81
  82 /* I/O APIC entries */
  83 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
  84 int nr_ioapics;
  85
  86 /* MP IRQ source entries */
  87 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
  88
  89 /* # of MP IRQ source entries */
  90 int mp_irq_entries;
  91
  92 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  93 int mp_bus_id_to_type[MAX_MP_BUSSES];
  94 #endif
  95
  96 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  97
  98 static int disable_timer_pin_1 __initdata;
  99
 100 /*
 101  * Rough estimation of how many shared IRQs there are, can
 102  * be changed anytime.
 103  */
 104 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 105 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 106
 107 /*
 108  * This is performance-critical, we want to do it O(1)
 109  *
 110  * the indexing order of this array favors 1:1 mappings
 111  * between pins and IRQs.
 112  */
 113
 114 static struct irq_pin_list {
 115         int apic, pin, next;
 116 } irq_2_pin[PIN_MAP_SIZE];
 117
 118 struct io_apic {
 119         unsigned int index;
 120         unsigned int unused[3];
 121         unsigned int data;
 122 };
 123
 124 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 125 {
 126         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 127                 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
 128 }
 129
 130 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 131 {
 132         struct io_apic __iomem *io_apic = io_apic_base(apic);
 133         writel(reg, &io_apic->index);
 134         return readl(&io_apic->data);
 135 }
 136
 137 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 138 {
 139         struct io_apic __iomem *io_apic = io_apic_base(apic);
 140         writel(reg, &io_apic->index);
 141         writel(value, &io_apic->data);
 142 }
 143
 144 /*
 145  * Re-write a value: to be used for read-modify-write
 146  * cycles where the read already set up the index register.
 147  *
 148  * Older SiS APIC requires we rewrite the index register
 149  */
 150 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 151 {
 152         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 153         if (sis_apic_bug)
 154                 writel(reg, &io_apic->index);
 155         writel(value, &io_apic->data);
 156 }
 157
 158 union entry_union {
 159         struct { u32 w1, w2; };
 160         struct IO_APIC_route_entry entry;
 161 };
 162
 163 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 164 {
 165         union entry_union eu;
 166         unsigned long flags;
 167         spin_lock_irqsave(&ioapic_lock, flags);
 168         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 169         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 170         spin_unlock_irqrestore(&ioapic_lock, flags);
 171         return eu.entry;
 172 }
 173
 174 /*
 175  * When we write a new IO APIC routing entry, we need to write the high
 176  * word first! If the mask bit in the low word is clear, we will enable
 177  * the interrupt, and we need to make sure the entry is fully populated
 178  * before that happens.
 179  */
 180 static void
 181 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 182 {
 183         union entry_union eu;
 184         eu.entry = e;
 185         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 186         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 187 }
 188
 189 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 190 {
 191         unsigned long flags;
 192         spin_lock_irqsave(&ioapic_lock, flags);
 193         __ioapic_write_entry(apic, pin, e);
 194         spin_unlock_irqrestore(&ioapic_lock, flags);
 195 }
 196
 197 /*
 198  * When we mask an IO APIC routing entry, we need to write the low
 199  * word first, in order to set the mask bit before we change the
 200  * high bits!
 201  */
 202 static void ioapic_mask_entry(int apic, int pin)
 203 {
 204         unsigned long flags;
 205         union entry_union eu = { .entry.mask = 1 };
 206
 207         spin_lock_irqsave(&ioapic_lock, flags);
 208         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 209         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 210         spin_unlock_irqrestore(&ioapic_lock, flags);
 211 }
 212
 213 /*
 214  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 215  * shared ISA-space IRQs, so we have to support them. We are super
 216  * fast in the common case, and fast for shared ISA-space IRQs.
 217  */
 218 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 219 {
 220         static int first_free_entry = NR_IRQS;
 221         struct irq_pin_list *entry = irq_2_pin + irq;
 222
 223         while (entry->next)
 224                 entry = irq_2_pin + entry->next;
 225
 226         if (entry->pin != -1) {
 227                 entry->next = first_free_entry;
 228                 entry = irq_2_pin + entry->next;
 229                 if (++first_free_entry >= PIN_MAP_SIZE)
 230                         panic("io_apic.c: whoops");
 231         }
 232         entry->apic = apic;
 233         entry->pin = pin;
 234 }
 235
 236 /*
 237  * Reroute an IRQ to a different pin.
 238  */
 239 static void __init replace_pin_at_irq(unsigned int irq,
 240                                       int oldapic, int oldpin,
 241                                       int newapic, int newpin)
 242 {
 243         struct irq_pin_list *entry = irq_2_pin + irq;
 244
 245         while (1) {
 246                 if (entry->apic == oldapic && entry->pin == oldpin) {
 247                         entry->apic = newapic;
 248                         entry->pin = newpin;
 249                 }
 250                 if (!entry->next)
 251                         break;
 252                 entry = irq_2_pin + entry->next;
 253         }
 254 }
 255
 256 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
 257 {
 258         struct irq_pin_list *entry = irq_2_pin + irq;
 259         unsigned int pin, reg;
 260
 261         for (;;) {
 262                 pin = entry->pin;
 263                 if (pin == -1)
 264                         break;
 265                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 266                 reg &= ~disable;
 267                 reg |= enable;
 268                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 269                 if (!entry->next)
 270                         break;
 271                 entry = irq_2_pin + entry->next;
 272         }
 273 }
 274
 275 /* mask = 1 */
 276 static void __mask_IO_APIC_irq(unsigned int irq)
 277 {
 278         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
 279 }
 280
 281 /* mask = 0 */
 282 static void __unmask_IO_APIC_irq(unsigned int irq)
 283 {
 284         __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
 285 }
 286
 287 /* mask = 1, trigger = 0 */
 288 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
 289 {
 290         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
 291                                 IO_APIC_REDIR_LEVEL_TRIGGER);
 292 }
 293
 294 /* mask = 0, trigger = 1 */
 295 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
 296 {
 297         __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
 298                                 IO_APIC_REDIR_MASKED);
 299 }
 300
 301 static void mask_IO_APIC_irq(unsigned int irq)
 302 {
 303         unsigned long flags;
 304
 305         spin_lock_irqsave(&ioapic_lock, flags);
 306         __mask_IO_APIC_irq(irq);
 307         spin_unlock_irqrestore(&ioapic_lock, flags);
 308 }
 309
 310 static void unmask_IO_APIC_irq(unsigned int irq)
 311 {
 312         unsigned long flags;
 313
 314         spin_lock_irqsave(&ioapic_lock, flags);
 315         __unmask_IO_APIC_irq(irq);
 316         spin_unlock_irqrestore(&ioapic_lock, flags);
 317 }
 318
 319 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 320 {
 321         struct IO_APIC_route_entry entry;
 322
 323         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 324         entry = ioapic_read_entry(apic, pin);
 325         if (entry.delivery_mode == dest_SMI)
 326                 return;
 327
 328         /*
 329          * Disable it in the IO-APIC irq-routing table:
 330          */
 331         ioapic_mask_entry(apic, pin);
 332 }
 333
 334 static void clear_IO_APIC(void)
 335 {
 336         int apic, pin;
 337
 338         for (apic = 0; apic < nr_ioapics; apic++)
 339                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 340                         clear_IO_APIC_pin(apic, pin);
 341 }
 342
 343 #ifdef CONFIG_SMP
 344 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 345 {
 346         unsigned long flags;
 347         int pin;
 348         struct irq_pin_list *entry = irq_2_pin + irq;
 349         unsigned int apicid_value;
 350         cpumask_t tmp;
 351
 352         cpus_and(tmp, cpumask, cpu_online_map);
 353         if (cpus_empty(tmp))
 354                 tmp = TARGET_CPUS;
 355
 356         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 357
 358         apicid_value = cpu_mask_to_apicid(cpumask);
 359         /* Prepare to do the io_apic_write */
 360         apicid_value = apicid_value << 24;
 361         spin_lock_irqsave(&ioapic_lock, flags);
 362         for (;;) {
 363                 pin = entry->pin;
 364                 if (pin == -1)
 365                         break;
 366                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 367                 if (!entry->next)
 368                         break;
 369                 entry = irq_2_pin + entry->next;
 370         }
 371         irq_desc[irq].affinity = cpumask;
 372         spin_unlock_irqrestore(&ioapic_lock, flags);
 373 }
 374
 375 #if defined(CONFIG_IRQBALANCE)
 376 # include <asm/processor.h>     /* kernel_thread() */
 377 # include <linux/kernel_stat.h> /* kstat */
 378 # include <linux/slab.h>                /* kmalloc() */
 379 # include <linux/timer.h>
 380
 381 #define IRQBALANCE_CHECK_ARCH -999
 382 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 383 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 384 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 385 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 386
 387 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 388 static int physical_balance __read_mostly;
 389 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 390
 391 static struct irq_cpu_info {
 392         unsigned long *last_irq;
 393         unsigned long *irq_delta;
 394         unsigned long irq;
 395 } irq_cpu_data[NR_CPUS];
 396
 397 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 398 #define LAST_CPU_IRQ(cpu, irq)   (irq_cpu_data[cpu].last_irq[irq])
 399 #define IRQ_DELTA(cpu, irq)     (irq_cpu_data[cpu].irq_delta[irq])
 400
 401 #define IDLE_ENOUGH(cpu,now) \
 402         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 403
 404 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 405
 406 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
 407
 408 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 409         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 410 };
 411
 412 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 413 {
 414         balance_irq_affinity[irq] = mask;
 415 }
 416
 417 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 418                         unsigned long now, int direction)
 419 {
 420         int search_idle = 1;
 421         int cpu = curr_cpu;
 422
 423         goto inside;
 424
 425         do {
 426                 if (unlikely(cpu == curr_cpu))
 427                         search_idle = 0;
 428 inside:
 429                 if (direction == 1) {
 430                         cpu++;
 431                         if (cpu >= NR_CPUS)
 432                                 cpu = 0;
 433                 } else {
 434                         cpu--;
 435                         if (cpu == -1)
 436                                 cpu = NR_CPUS-1;
 437                 }
 438         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
 439                         (search_idle && !IDLE_ENOUGH(cpu, now)));
 440
 441         return cpu;
 442 }
 443
 444 static inline void balance_irq(int cpu, int irq)
 445 {
 446         unsigned long now = jiffies;
 447         cpumask_t allowed_mask;
 448         unsigned int new_cpu;
 449
 450         if (irqbalance_disabled)
 451                 return;
 452
 453         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 454         new_cpu = move(cpu, allowed_mask, now, 1);
 455         if (cpu != new_cpu)
 456                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 457 }
 458
 459 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 460 {
 461         int i, j;
 462
 463         for_each_online_cpu(i) {
 464                 for (j = 0; j < NR_IRQS; j++) {
 465                         if (!irq_desc[j].action)
 466                                 continue;
 467                         /* Is it a significant load ?  */
 468                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
 469                                                 useful_load_threshold)
 470                                 continue;
 471                         balance_irq(i, j);
 472                 }
 473         }
 474         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 475                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 476         return;
 477 }
 478
 479 static void do_irq_balance(void)
 480 {
 481         int i, j;
 482         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 483         unsigned long move_this_load = 0;
 484         int max_loaded = 0, min_loaded = 0;
 485         int load;
 486         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 487         int selected_irq;
 488         int tmp_loaded, first_attempt = 1;
 489         unsigned long tmp_cpu_irq;
 490         unsigned long imbalance = 0;
 491         cpumask_t allowed_mask, target_cpu_mask, tmp;
 492
 493         for_each_possible_cpu(i) {
 494                 int package_index;
 495                 CPU_IRQ(i) = 0;
 496                 if (!cpu_online(i))
 497                         continue;
 498                 package_index = CPU_TO_PACKAGEINDEX(i);
 499                 for (j = 0; j < NR_IRQS; j++) {
 500                         unsigned long value_now, delta;
 501                         /* Is this an active IRQ or balancing disabled ? */
 502                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 503                                 continue;
 504                         if (package_index == i)
 505                                 IRQ_DELTA(package_index, j) = 0;
 506                         /* Determine the total count per processor per IRQ */
 507                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 508
 509                         /* Determine the activity per processor per IRQ */
 510                         delta = value_now - LAST_CPU_IRQ(i, j);
 511
 512                         /* Update last_cpu_irq[][] for the next time */
 513                         LAST_CPU_IRQ(i, j) = value_now;
 514
 515                         /* Ignore IRQs whose rate is less than the clock */
 516                         if (delta < useful_load_threshold)
 517                                 continue;
 518                         /* update the load for the processor or package total */
 519                         IRQ_DELTA(package_index, j) += delta;
 520
 521                         /* Keep track of the higher numbered sibling as well */
 522                         if (i != package_index)
 523                                 CPU_IRQ(i) += delta;
 524                         /*
 525                          * We have sibling A and sibling B in the package
 526                          *
 527                          * cpu_irq[A] = load for cpu A + load for cpu B
 528                          * cpu_irq[B] = load for cpu B
 529                          */
 530                         CPU_IRQ(package_index) += delta;
 531                 }
 532         }
 533         /* Find the least loaded processor package */
 534         for_each_online_cpu(i) {
 535                 if (i != CPU_TO_PACKAGEINDEX(i))
 536                         continue;
 537                 if (min_cpu_irq > CPU_IRQ(i)) {
 538                         min_cpu_irq = CPU_IRQ(i);
 539                         min_loaded = i;
 540                 }
 541         }
 542         max_cpu_irq = ULONG_MAX;
 543
 544 tryanothercpu:
 545         /*
 546          * Look for heaviest loaded processor.
 547          * We may come back to get the next heaviest loaded processor.
 548          * Skip processors with trivial loads.
 549          */
 550         tmp_cpu_irq = 0;
 551         tmp_loaded = -1;
 552         for_each_online_cpu(i) {
 553                 if (i != CPU_TO_PACKAGEINDEX(i))
 554                         continue;
 555                 if (max_cpu_irq <= CPU_IRQ(i))
 556                         continue;
 557                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 558                         tmp_cpu_irq = CPU_IRQ(i);
 559                         tmp_loaded = i;
 560                 }
 561         }
 562
 563         if (tmp_loaded == -1) {
 564          /*
 565           * In the case of small number of heavy interrupt sources,
 566           * loading some of the cpus too much. We use Ingo's original
 567           * approach to rotate them around.
 568           */
 569                 if (!first_attempt && imbalance >= useful_load_threshold) {
 570                         rotate_irqs_among_cpus(useful_load_threshold);
 571                         return;
 572                 }
 573                 goto not_worth_the_effort;
 574         }
 575
 576         first_attempt = 0;              /* heaviest search */
 577         max_cpu_irq = tmp_cpu_irq;      /* load */
 578         max_loaded = tmp_loaded;        /* processor */
 579         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 580
 581         /*
 582          * if imbalance is less than approx 10% of max load, then
 583          * observe diminishing returns action. - quit
 584          */
 585         if (imbalance < (max_cpu_irq >> 3))
 586                 goto not_worth_the_effort;
 587
 588 tryanotherirq:
 589         /* if we select an IRQ to move that can't go where we want, then
 590          * see if there is another one to try.
 591          */
 592         move_this_load = 0;
 593         selected_irq = -1;
 594         for (j = 0; j < NR_IRQS; j++) {
 595                 /* Is this an active IRQ? */
 596                 if (!irq_desc[j].action)
 597                         continue;
 598                 if (imbalance <= IRQ_DELTA(max_loaded, j))
 599                         continue;
 600                 /* Try to find the IRQ that is closest to the imbalance
 601                  * without going over.
 602                  */
 603                 if (move_this_load < IRQ_DELTA(max_loaded, j)) {
 604                         move_this_load = IRQ_DELTA(max_loaded, j);
 605                         selected_irq = j;
 606                 }
 607         }
 608         if (selected_irq == -1)
 609                 goto tryanothercpu;
 610
 611         imbalance = move_this_load;
 612
 613         /* For physical_balance case, we accumulated both load
 614          * values in the one of the siblings cpu_irq[],
 615          * to use the same code for physical and logical processors
 616          * as much as possible.
 617          *
 618          * NOTE: the cpu_irq[] array holds the sum of the load for
 619          * sibling A and sibling B in the slot for the lowest numbered
 620          * sibling (A), _AND_ the load for sibling B in the slot for
 621          * the higher numbered sibling.
 622          *
 623          * We seek the least loaded sibling by making the comparison
 624          * (A+B)/2 vs B
 625          */
 626         load = CPU_IRQ(min_loaded) >> 1;
 627         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
 628                 if (load > CPU_IRQ(j)) {
 629                         /* This won't change cpu_sibling_map[min_loaded] */
 630                         load = CPU_IRQ(j);
 631                         min_loaded = j;
 632                 }
 633         }
 634
 635         cpus_and(allowed_mask,
 636                 cpu_online_map,
 637                 balance_irq_affinity[selected_irq]);
 638         target_cpu_mask = cpumask_of_cpu(min_loaded);
 639         cpus_and(tmp, target_cpu_mask, allowed_mask);
 640
 641         if (!cpus_empty(tmp)) {
 642                 /* mark for change destination */
 643                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 644
 645                 /* Since we made a change, come back sooner to
 646                  * check for more variation.
 647                  */
 648                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 649                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 650                 return;
 651         }
 652         goto tryanotherirq;
 653
 654 not_worth_the_effort:
 655         /*
 656          * if we did not find an IRQ to move, then adjust the time interval
 657          * upward
 658          */
 659         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 660                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 661         return;
 662 }
 663
 664 static int balanced_irq(void *unused)
 665 {
 666         int i;
 667         unsigned long prev_balance_time = jiffies;
 668         long time_remaining = balanced_irq_interval;
 669
 670         /* push everything to CPU 0 to give us a starting point.  */
 671         for (i = 0 ; i < NR_IRQS ; i++) {
 672                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 673                 set_pending_irq(i, cpumask_of_cpu(0));
 674         }
 675
 676         set_freezable();
 677         for ( ; ; ) {
 678                 time_remaining = schedule_timeout_interruptible(time_remaining);
 679                 try_to_freeze();
 680                 if (time_after(jiffies,
 681                                 prev_balance_time+balanced_irq_interval)) {
 682                         preempt_disable();
 683                         do_irq_balance();
 684                         prev_balance_time = jiffies;
 685                         time_remaining = balanced_irq_interval;
 686                         preempt_enable();
 687                 }
 688         }
 689         return 0;
 690 }
 691
 692 static int __init balanced_irq_init(void)
 693 {
 694         int i;
 695         struct cpuinfo_x86 *c;
 696         cpumask_t tmp;
 697
 698         cpus_shift_right(tmp, cpu_online_map, 2);
 699         c = &boot_cpu_data;
 700         /* When not overwritten by the command line ask subarchitecture. */
 701         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 702                 irqbalance_disabled = NO_BALANCE_IRQ;
 703         if (irqbalance_disabled)
 704                 return 0;
 705
 706          /* disable irqbalance completely if there is only one processor online */
 707         if (num_online_cpus() < 2) {
 708                 irqbalance_disabled = 1;
 709                 return 0;
 710         }
 711         /*
 712          * Enable physical balance only if more than 1 physical processor
 713          * is present
 714          */
 715         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 716                 physical_balance = 1;
 717
 718         for_each_online_cpu(i) {
 719                 irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 720                 irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 721                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 722                         printk(KERN_ERR "balanced_irq_init: out of memory");
 723                         goto failed;
 724                 }
 725         }
 726
 727         printk(KERN_INFO "Starting balanced_irq\n");
 728         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
 729                 return 0;
 730         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 731 failed:
 732         for_each_possible_cpu(i) {
 733                 kfree(irq_cpu_data[i].irq_delta);
 734                 irq_cpu_data[i].irq_delta = NULL;
 735                 kfree(irq_cpu_data[i].last_irq);
 736                 irq_cpu_data[i].last_irq = NULL;
 737         }
 738         return 0;
 739 }
 740
 741 int __devinit irqbalance_disable(char *str)
 742 {
 743         irqbalance_disabled = 1;
 744         return 1;
 745 }
 746
 747 __setup("noirqbalance", irqbalance_disable);
 748
 749 late_initcall(balanced_irq_init);
 750 #endif /* CONFIG_IRQBALANCE */
 751 #endif /* CONFIG_SMP */
 752
 753 #ifndef CONFIG_SMP
 754 void send_IPI_self(int vector)
 755 {
 756         unsigned int cfg;
 757
 758         /*
 759          * Wait for idle.
 760          */
 761         apic_wait_icr_idle();
 762         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 763         /*
 764          * Send the IPI. The write to APIC_ICR fires this off.
 765          */
 766         apic_write_around(APIC_ICR, cfg);
 767 }
 768 #endif /* !CONFIG_SMP */
 769
 770
 771 /*
 772  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 773  * specific CPU-side IRQs.
 774  */
 775
 776 #define MAX_PIRQS 8
 777 static int pirq_entries [MAX_PIRQS];
 778 static int pirqs_enabled;
 779 int skip_ioapic_setup;
 780
 781 static int __init ioapic_pirq_setup(char *str)
 782 {
 783         int i, max;
 784         int ints[MAX_PIRQS+1];
 785
 786         get_options(str, ARRAY_SIZE(ints), ints);
 787
 788         for (i = 0; i < MAX_PIRQS; i++)
 789                 pirq_entries[i] = -1;
 790
 791         pirqs_enabled = 1;
 792         apic_printk(APIC_VERBOSE, KERN_INFO
 793                         "PIRQ redirection, working around broken MP-BIOS.\n");
 794         max = MAX_PIRQS;
 795         if (ints[0] < MAX_PIRQS)
 796                 max = ints[0];
 797
 798         for (i = 0; i < max; i++) {
 799                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 800                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 801                 /*
 802                  * PIRQs are mapped upside down, usually.
 803                  */
 804                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 805         }
 806         return 1;
 807 }
 808
 809 __setup("pirq=", ioapic_pirq_setup);
 810
 811 /*
 812  * Find the IRQ entry number of a certain pin.
 813  */
 814 static int find_irq_entry(int apic, int pin, int type)
 815 {
 816         int i;
 817
 818         for (i = 0; i < mp_irq_entries; i++)
 819                 if (mp_irqs[i].mp_irqtype == type &&
 820                     (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
 821                      mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
 822                     mp_irqs[i].mp_dstirq == pin)
 823                         return i;
 824
 825         return -1;
 826 }
 827
 828 /*
 829  * Find the pin to which IRQ[irq] (ISA) is connected
 830  */
 831 static int __init find_isa_irq_pin(int irq, int type)
 832 {
 833         int i;
 834
 835         for (i = 0; i < mp_irq_entries; i++) {
 836                 int lbus = mp_irqs[i].mp_srcbus;
 837
 838                 if (test_bit(lbus, mp_bus_not_pci) &&
 839                     (mp_irqs[i].mp_irqtype == type) &&
 840                     (mp_irqs[i].mp_srcbusirq == irq))
 841
 842                         return mp_irqs[i].mp_dstirq;
 843         }
 844         return -1;
 845 }
 846
 847 static int __init find_isa_irq_apic(int irq, int type)
 848 {
 849         int i;
 850
 851         for (i = 0; i < mp_irq_entries; i++) {
 852                 int lbus = mp_irqs[i].mp_srcbus;
 853
 854                 if (test_bit(lbus, mp_bus_not_pci) &&
 855                     (mp_irqs[i].mp_irqtype == type) &&
 856                     (mp_irqs[i].mp_srcbusirq == irq))
 857                         break;
 858         }
 859         if (i < mp_irq_entries) {
 860                 int apic;
 861                 for (apic = 0; apic < nr_ioapics; apic++) {
 862                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
 863                                 return apic;
 864                 }
 865         }
 866
 867         return -1;
 868 }
 869
 870 /*
 871  * Find a specific PCI IRQ entry.
 872  * Not an __init, possibly needed by modules
 873  */
 874 static int pin_2_irq(int idx, int apic, int pin);
 875
 876 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 877 {
 878         int apic, i, best_guess = -1;
 879
 880         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 881                 "slot:%d, pin:%d.\n", bus, slot, pin);
 882         if (test_bit(bus, mp_bus_not_pci)) {
 883                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 884                 return -1;
 885         }
 886         for (i = 0; i < mp_irq_entries; i++) {
 887                 int lbus = mp_irqs[i].mp_srcbus;
 888
 889                 for (apic = 0; apic < nr_ioapics; apic++)
 890                         if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
 891                             mp_irqs[i].mp_dstapic == MP_APIC_ALL)
 892                                 break;
 893
 894                 if (!test_bit(lbus, mp_bus_not_pci) &&
 895                     !mp_irqs[i].mp_irqtype &&
 896                     (bus == lbus) &&
 897                     (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
 898                         int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
 899
 900                         if (!(apic || IO_APIC_IRQ(irq)))
 901                                 continue;
 902
 903                         if (pin == (mp_irqs[i].mp_srcbusirq & 3))
 904                                 return irq;
 905                         /*
 906                          * Use the first all-but-pin matching entry as a
 907                          * best-guess fuzzy result for broken mptables.
 908                          */
 909                         if (best_guess < 0)
 910                                 best_guess = irq;
 911                 }
 912         }
 913         return best_guess;
 914 }
 915 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 916
 917 /*
 918  * This function currently is only a helper for the i386 smp boot process where
 919  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 920  * so mask in all cases should simply be TARGET_CPUS
 921  */
 922 #ifdef CONFIG_SMP
 923 void __init setup_ioapic_dest(void)
 924 {
 925         int pin, ioapic, irq, irq_entry;
 926
 927         if (skip_ioapic_setup == 1)
 928                 return;
 929
 930         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 931                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 932                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 933                         if (irq_entry == -1)
 934                                 continue;
 935                         irq = pin_2_irq(irq_entry, ioapic, pin);
 936                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 937                 }
 938
 939         }
 940 }
 941 #endif
 942
 943 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 944 /*
 945  * EISA Edge/Level control register, ELCR
 946  */
 947 static int EISA_ELCR(unsigned int irq)
 948 {
 949         if (irq < 16) {
 950                 unsigned int port = 0x4d0 + (irq >> 3);
 951                 return (inb(port) >> (irq & 7)) & 1;
 952         }
 953         apic_printk(APIC_VERBOSE, KERN_INFO
 954                         "Broken MPtable reports ISA irq %d\n", irq);
 955         return 0;
 956 }
 957 #endif
 958
 959 /* ISA interrupts are always polarity zero edge triggered,
 960  * when listed as conforming in the MP table. */
 961
 962 #define default_ISA_trigger(idx)        (0)
 963 #define default_ISA_polarity(idx)       (0)
 964
 965 /* EISA interrupts are always polarity zero and can be edge or level
 966  * trigger depending on the ELCR value.  If an interrupt is listed as
 967  * EISA conforming in the MP table, that means its trigger type must
 968  * be read in from the ELCR */
 969
 970 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
 971 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 972
 973 /* PCI interrupts are always polarity one level triggered,
 974  * when listed as conforming in the MP table. */
 975
 976 #define default_PCI_trigger(idx)        (1)
 977 #define default_PCI_polarity(idx)       (1)
 978
 979 /* MCA interrupts are always polarity zero level triggered,
 980  * when listed as conforming in the MP table. */
 981
 982 #define default_MCA_trigger(idx)        (1)
 983 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
 984
 985 static int MPBIOS_polarity(int idx)
 986 {
 987         int bus = mp_irqs[idx].mp_srcbus;
 988         int polarity;
 989
 990         /*
 991          * Determine IRQ line polarity (high active or low active):
 992          */
 993         switch (mp_irqs[idx].mp_irqflag & 3) {
 994         case 0: /* conforms, ie. bus-type dependent polarity */
 995         {
 996                 polarity = test_bit(bus, mp_bus_not_pci)?
 997                         default_ISA_polarity(idx):
 998                         default_PCI_polarity(idx);
 999                 break;
1000         }
1001         case 1: /* high active */
1002         {
1003                 polarity = 0;
1004                 break;
1005         }
1006         case 2: /* reserved */
1007         {
1008                 printk(KERN_WARNING "broken BIOS!!\n");
1009                 polarity = 1;
1010                 break;
1011         }
1012         case 3: /* low active */
1013         {
1014                 polarity = 1;
1015                 break;
1016         }
1017         default: /* invalid */
1018         {
1019                 printk(KERN_WARNING "broken BIOS!!\n");
1020                 polarity = 1;
1021                 break;
1022         }
1023         }
1024         return polarity;
1025 }
1026
1027 static int MPBIOS_trigger(int idx)
1028 {
1029         int bus = mp_irqs[idx].mp_srcbus;
1030         int trigger;
1031
1032         /*
1033          * Determine IRQ trigger mode (edge or level sensitive):
1034          */
1035         switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
1036         case 0: /* conforms, ie. bus-type dependent */
1037         {
1038                 trigger = test_bit(bus, mp_bus_not_pci)?
1039                                 default_ISA_trigger(idx):
1040                                 default_PCI_trigger(idx);
1041 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1042                 switch (mp_bus_id_to_type[bus]) {
1043                 case MP_BUS_ISA: /* ISA pin */
1044                 {
1045                         /* set before the switch */
1046                         break;
1047                 }
1048                 case MP_BUS_EISA: /* EISA pin */
1049                 {
1050                         trigger = default_EISA_trigger(idx);
1051                         break;
1052                 }
1053                 case MP_BUS_PCI: /* PCI pin */
1054                 {
1055                         /* set before the switch */
1056                         break;
1057                 }
1058                 case MP_BUS_MCA: /* MCA pin */
1059                 {
1060                         trigger = default_MCA_trigger(idx);
1061                         break;
1062                 }
1063                 default:
1064                 {
1065                         printk(KERN_WARNING "broken BIOS!!\n");
1066                         trigger = 1;
1067                         break;
1068                 }
1069         }
1070 #endif
1071                 break;
1072         }
1073         case 1: /* edge */
1074         {
1075                 trigger = 0;
1076                 break;
1077         }
1078         case 2: /* reserved */
1079         {
1080                 printk(KERN_WARNING "broken BIOS!!\n");
1081                 trigger = 1;
1082                 break;
1083         }
1084         case 3: /* level */
1085         {
1086                 trigger = 1;
1087                 break;
1088         }
1089         default: /* invalid */
1090         {
1091                 printk(KERN_WARNING "broken BIOS!!\n");
1092                 trigger = 0;
1093                 break;
1094         }
1095         }
1096         return trigger;
1097 }
1098
1099 static inline int irq_polarity(int idx)
1100 {
1101         return MPBIOS_polarity(idx);
1102 }
1103
1104 static inline int irq_trigger(int idx)
1105 {
1106         return MPBIOS_trigger(idx);
1107 }
1108
1109 static int pin_2_irq(int idx, int apic, int pin)
1110 {
1111         int irq, i;
1112         int bus = mp_irqs[idx].mp_srcbus;
1113
1114         /*
1115          * Debugging check, we are in big trouble if this message pops up!
1116          */
1117         if (mp_irqs[idx].mp_dstirq != pin)
1118                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1119
1120         if (test_bit(bus, mp_bus_not_pci))
1121                 irq = mp_irqs[idx].mp_srcbusirq;
1122         else {
1123                 /*
1124                  * PCI IRQs are mapped in order
1125                  */
1126                 i = irq = 0;
1127                 while (i < apic)
1128                         irq += nr_ioapic_registers[i++];
1129                 irq += pin;
1130
1131                 /*
1132                  * For MPS mode, so far only needed by ES7000 platform
1133                  */
1134                 if (ioapic_renumber_irq)
1135                         irq = ioapic_renumber_irq(apic, irq);
1136         }
1137
1138         /*
1139          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1140          */
1141         if ((pin >= 16) && (pin <= 23)) {
1142                 if (pirq_entries[pin-16] != -1) {
1143                         if (!pirq_entries[pin-16]) {
1144                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1145                                                 "disabling PIRQ%d\n", pin-16);
1146                         } else {
1147                                 irq = pirq_entries[pin-16];
1148                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1149                                                 "using PIRQ%d -> IRQ %d\n",
1150                                                 pin-16, irq);
1151                         }
1152                 }
1153         }
1154         return irq;
1155 }
1156
1157 static inline int IO_APIC_irq_trigger(int irq)
1158 {
1159         int apic, idx, pin;
1160
1161         for (apic = 0; apic < nr_ioapics; apic++) {
1162                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1163                         idx = find_irq_entry(apic, pin, mp_INT);
1164                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1165                                 return irq_trigger(idx);
1166                 }
1167         }
1168         /*
1169          * nonexistent IRQs are edge default
1170          */
1171         return 0;
1172 }
1173
1174 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1175 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1176
1177 static int __assign_irq_vector(int irq)
1178 {
1179         static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1180         int vector, offset;
1181
1182         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1183
1184         if (irq_vector[irq] > 0)
1185                 return irq_vector[irq];
1186
1187         vector = current_vector;
1188         offset = current_offset;
1189 next:
1190         vector += 8;
1191         if (vector >= first_system_vector) {
1192                 offset = (offset + 1) % 8;
1193                 vector = FIRST_DEVICE_VECTOR + offset;
1194         }
1195         if (vector == current_vector)
1196                 return -ENOSPC;
1197         if (test_and_set_bit(vector, used_vectors))
1198                 goto next;
1199
1200         current_vector = vector;
1201         current_offset = offset;
1202         irq_vector[irq] = vector;
1203
1204         return vector;
1205 }
1206
1207 static int assign_irq_vector(int irq)
1208 {
1209         unsigned long flags;
1210         int vector;
1211
1212         spin_lock_irqsave(&vector_lock, flags);
1213         vector = __assign_irq_vector(irq);
1214         spin_unlock_irqrestore(&vector_lock, flags);
1215
1216         return vector;
1217 }
1218
1219 void setup_vector_irq(int cpu)
1220 {
1221 }
1222
1223 static struct irq_chip ioapic_chip;
1224
1225 #define IOAPIC_AUTO     -1
1226 #define IOAPIC_EDGE     0
1227 #define IOAPIC_LEVEL    1
1228
1229 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1230 {
1231         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1232             trigger == IOAPIC_LEVEL) {
1233                 irq_desc[irq].status |= IRQ_LEVEL;
1234                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1235                                          handle_fasteoi_irq, "fasteoi");
1236         } else {
1237                 irq_desc[irq].status &= ~IRQ_LEVEL;
1238                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1239                                          handle_edge_irq, "edge");
1240         }
1241         set_intr_gate(vector, interrupt[irq]);
1242 }
1243
1244 static void __init setup_IO_APIC_irqs(void)
1245 {
1246         struct IO_APIC_route_entry entry;
1247         int apic, pin, idx, irq, first_notcon = 1, vector;
1248
1249         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1250
1251         for (apic = 0; apic < nr_ioapics; apic++) {
1252         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1253
1254                 /*
1255                  * add it to the IO-APIC irq-routing table:
1256                  */
1257                 memset(&entry, 0, sizeof(entry));
1258
1259                 entry.delivery_mode = INT_DELIVERY_MODE;
1260                 entry.dest_mode = INT_DEST_MODE;
1261                 entry.mask = 0;                         /* enable IRQ */
1262                 entry.dest.logical.logical_dest =
1263                                         cpu_mask_to_apicid(TARGET_CPUS);
1264
1265                 idx = find_irq_entry(apic, pin, mp_INT);
1266                 if (idx == -1) {
1267                         if (first_notcon) {
1268                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1269                                                 " IO-APIC (apicid-pin) %d-%d",
1270                                                 mp_ioapics[apic].mp_apicid,
1271                                                 pin);
1272                                 first_notcon = 0;
1273                         } else
1274                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1275                                         mp_ioapics[apic].mp_apicid, pin);
1276                         continue;
1277                 }
1278
1279                 if (!first_notcon) {
1280                         apic_printk(APIC_VERBOSE, " not connected.\n");
1281                         first_notcon = 1;
1282                 }
1283
1284                 entry.trigger = irq_trigger(idx);
1285                 entry.polarity = irq_polarity(idx);
1286
1287                 if (irq_trigger(idx)) {
1288                         entry.trigger = 1;
1289                         entry.mask = 1;
1290                 }
1291
1292                 irq = pin_2_irq(idx, apic, pin);
1293                 /*
1294                  * skip adding the timer int on secondary nodes, which causes
1295                  * a small but painful rift in the time-space continuum
1296                  */
1297                 if (multi_timer_check(apic, irq))
1298                         continue;
1299                 else
1300                         add_pin_to_irq(irq, apic, pin);
1301
1302                 if (!apic && !IO_APIC_IRQ(irq))
1303                         continue;
1304
1305                 if (IO_APIC_IRQ(irq)) {
1306                         vector = assign_irq_vector(irq);
1307                         entry.vector = vector;
1308                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1309
1310                         if (!apic && (irq < 16))
1311                                 disable_8259A_irq(irq);
1312                 }
1313                 ioapic_write_entry(apic, pin, entry);
1314         }
1315         }
1316
1317         if (!first_notcon)
1318                 apic_printk(APIC_VERBOSE, " not connected.\n");
1319 }
1320
1321 /*
1322  * Set up the timer pin, possibly with the 8259A-master behind.
1323  */
1324 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1325                                         int vector)
1326 {
1327         struct IO_APIC_route_entry entry;
1328
1329         memset(&entry, 0, sizeof(entry));
1330
1331         /*
1332          * We use logical delivery to get the timer IRQ
1333          * to the first CPU.
1334          */
1335         entry.dest_mode = INT_DEST_MODE;
1336         entry.mask = 1;                                 /* mask IRQ now */
1337         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1338         entry.delivery_mode = INT_DELIVERY_MODE;
1339         entry.polarity = 0;
1340         entry.trigger = 0;
1341         entry.vector = vector;
1342
1343         /*
1344          * The timer IRQ doesn't have to know that behind the
1345          * scene we may have a 8259A-master in AEOI mode ...
1346          */
1347         ioapic_register_intr(0, vector, IOAPIC_EDGE);
1348
1349         /*
1350          * Add it to the IO-APIC irq-routing table:
1351          */
1352         ioapic_write_entry(apic, pin, entry);
1353 }
1354
1355 void __init print_IO_APIC(void)
1356 {
1357         int apic, i;
1358         union IO_APIC_reg_00 reg_00;
1359         union IO_APIC_reg_01 reg_01;
1360         union IO_APIC_reg_02 reg_02;
1361         union IO_APIC_reg_03 reg_03;
1362         unsigned long flags;
1363
1364         if (apic_verbosity == APIC_QUIET)
1365                 return;
1366
1367         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1368         for (i = 0; i < nr_ioapics; i++)
1369                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1370                        mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1371
1372         /*
1373          * We are a bit conservative about what we expect.  We have to
1374          * know about every hardware change ASAP.
1375          */
1376         printk(KERN_INFO "testing the IO APIC.......................\n");
1377
1378         for (apic = 0; apic < nr_ioapics; apic++) {
1379
1380         spin_lock_irqsave(&ioapic_lock, flags);
1381         reg_00.raw = io_apic_read(apic, 0);
1382         reg_01.raw = io_apic_read(apic, 1);
1383         if (reg_01.bits.version >= 0x10)
1384                 reg_02.raw = io_apic_read(apic, 2);
1385         if (reg_01.bits.version >= 0x20)
1386                 reg_03.raw = io_apic_read(apic, 3);
1387         spin_unlock_irqrestore(&ioapic_lock, flags);
1388
1389         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1390         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1391         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1392         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1393         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1394
1395         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1396         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1397
1398         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1399         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1400
1401         /*
1402          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1403          * but the value of reg_02 is read as the previous read register
1404          * value, so ignore it if reg_02 == reg_01.
1405          */
1406         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1407                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1408                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1409         }
1410
1411         /*
1412          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1413          * or reg_03, but the value of reg_0[23] is read as the previous read
1414          * register value, so ignore it if reg_03 == reg_0[12].
1415          */
1416         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1417             reg_03.raw != reg_01.raw) {
1418                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1419                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1420         }
1421
1422         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1423
1424         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1425                           " Stat Dest Deli Vect:   \n");
1426
1427         for (i = 0; i <= reg_01.bits.entries; i++) {
1428                 struct IO_APIC_route_entry entry;
1429
1430                 entry = ioapic_read_entry(apic, i);
1431
1432                 printk(KERN_DEBUG " %02x %03X %02X  ",
1433                         i,
1434                         entry.dest.logical.logical_dest,
1435                         entry.dest.physical.physical_dest
1436                 );
1437
1438                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1439                         entry.mask,
1440                         entry.trigger,
1441                         entry.irr,
1442                         entry.polarity,
1443                         entry.delivery_status,
1444                         entry.dest_mode,
1445                         entry.delivery_mode,
1446                         entry.vector
1447                 );
1448         }
1449         }
1450         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1451         for (i = 0; i < NR_IRQS; i++) {
1452                 struct irq_pin_list *entry = irq_2_pin + i;
1453                 if (entry->pin < 0)
1454                         continue;
1455                 printk(KERN_DEBUG "IRQ%d ", i);
1456                 for (;;) {
1457                         printk("-> %d:%d", entry->apic, entry->pin);
1458                         if (!entry->next)
1459                                 break;
1460                         entry = irq_2_pin + entry->next;
1461                 }
1462                 printk("\n");
1463         }
1464
1465         printk(KERN_INFO ".................................... done.\n");
1466
1467         return;
1468 }
1469
1470 #if 0
1471
1472 static void print_APIC_bitfield(int base)
1473 {
1474         unsigned int v;
1475         int i, j;
1476
1477         if (apic_verbosity == APIC_QUIET)
1478                 return;
1479
1480         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1481         for (i = 0; i < 8; i++) {
1482                 v = apic_read(base + i*0x10);
1483                 for (j = 0; j < 32; j++) {
1484                         if (v & (1<<j))
1485                                 printk("1");
1486                         else
1487                                 printk("0");
1488                 }
1489                 printk("\n");
1490         }
1491 }
1492
1493 void /*__init*/ print_local_APIC(void *dummy)
1494 {
1495         unsigned int v, ver, maxlvt;
1496
1497         if (apic_verbosity == APIC_QUIET)
1498                 return;
1499
1500         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1501                 smp_processor_id(), hard_smp_processor_id());
1502         v = apic_read(APIC_ID);
1503         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v,
1504                         GET_APIC_ID(read_apic_id()));
1505         v = apic_read(APIC_LVR);
1506         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1507         ver = GET_APIC_VERSION(v);
1508         maxlvt = lapic_get_maxlvt();
1509
1510         v = apic_read(APIC_TASKPRI);
1511         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1512
1513         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1514                 v = apic_read(APIC_ARBPRI);
1515                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1516                         v & APIC_ARBPRI_MASK);
1517                 v = apic_read(APIC_PROCPRI);
1518                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1519         }
1520
1521         v = apic_read(APIC_EOI);
1522         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1523         v = apic_read(APIC_RRR);
1524         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1525         v = apic_read(APIC_LDR);
1526         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1527         v = apic_read(APIC_DFR);
1528         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1529         v = apic_read(APIC_SPIV);
1530         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1531
1532         printk(KERN_DEBUG "... APIC ISR field:\n");
1533         print_APIC_bitfield(APIC_ISR);
1534         printk(KERN_DEBUG "... APIC TMR field:\n");
1535         print_APIC_bitfield(APIC_TMR);
1536         printk(KERN_DEBUG "... APIC IRR field:\n");
1537         print_APIC_bitfield(APIC_IRR);
1538
1539         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1540                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1541                         apic_write(APIC_ESR, 0);
1542                 v = apic_read(APIC_ESR);
1543                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1544         }
1545
1546         v = apic_read(APIC_ICR);
1547         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1548         v = apic_read(APIC_ICR2);
1549         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1550
1551         v = apic_read(APIC_LVTT);
1552         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1553
1554         if (maxlvt > 3) {                       /* PC is LVT#4. */
1555                 v = apic_read(APIC_LVTPC);
1556                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1557         }
1558         v = apic_read(APIC_LVT0);
1559         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1560         v = apic_read(APIC_LVT1);
1561         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1562
1563         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1564                 v = apic_read(APIC_LVTERR);
1565                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1566         }
1567
1568         v = apic_read(APIC_TMICT);
1569         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1570         v = apic_read(APIC_TMCCT);
1571         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1572         v = apic_read(APIC_TDCR);
1573         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1574         printk("\n");
1575 }
1576
1577 void print_all_local_APICs(void)
1578 {
1579         on_each_cpu(print_local_APIC, NULL, 1, 1);
1580 }
1581
1582 void /*__init*/ print_PIC(void)
1583 {
1584         unsigned int v;
1585         unsigned long flags;
1586
1587         if (apic_verbosity == APIC_QUIET)
1588                 return;
1589
1590         printk(KERN_DEBUG "\nprinting PIC contents\n");
1591
1592         spin_lock_irqsave(&i8259A_lock, flags);
1593
1594         v = inb(0xa1) << 8 | inb(0x21);
1595         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1596
1597         v = inb(0xa0) << 8 | inb(0x20);
1598         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1599
1600         outb(0x0b, 0xa0);
1601         outb(0x0b, 0x20);
1602         v = inb(0xa0) << 8 | inb(0x20);
1603         outb(0x0a, 0xa0);
1604         outb(0x0a, 0x20);
1605
1606         spin_unlock_irqrestore(&i8259A_lock, flags);
1607
1608         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1609
1610         v = inb(0x4d1) << 8 | inb(0x4d0);
1611         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1612 }
1613
1614 #endif  /*  0  */
1615
1616 static void __init enable_IO_APIC(void)
1617 {
1618         union IO_APIC_reg_01 reg_01;
1619         int i8259_apic, i8259_pin;
1620         int i, apic;
1621         unsigned long flags;
1622
1623         for (i = 0; i < PIN_MAP_SIZE; i++) {
1624                 irq_2_pin[i].pin = -1;
1625                 irq_2_pin[i].next = 0;
1626         }
1627         if (!pirqs_enabled)
1628                 for (i = 0; i < MAX_PIRQS; i++)
1629                         pirq_entries[i] = -1;
1630
1631         /*
1632          * The number of IO-APIC IRQ registers (== #pins):
1633          */
1634         for (apic = 0; apic < nr_ioapics; apic++) {
1635                 spin_lock_irqsave(&ioapic_lock, flags);
1636                 reg_01.raw = io_apic_read(apic, 1);
1637                 spin_unlock_irqrestore(&ioapic_lock, flags);
1638                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1639         }
1640         for (apic = 0; apic < nr_ioapics; apic++) {
1641                 int pin;
1642                 /* See if any of the pins is in ExtINT mode */
1643                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1644                         struct IO_APIC_route_entry entry;
1645                         entry = ioapic_read_entry(apic, pin);
1646
1647
1648                         /* If the interrupt line is enabled and in ExtInt mode
1649                          * I have found the pin where the i8259 is connected.
1650                          */
1651                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1652                                 ioapic_i8259.apic = apic;
1653                                 ioapic_i8259.pin  = pin;
1654                                 goto found_i8259;
1655                         }
1656                 }
1657         }
1658  found_i8259:
1659         /* Look to see what if the MP table has reported the ExtINT */
1660         /* If we could not find the appropriate pin by looking at the ioapic
1661          * the i8259 probably is not connected the ioapic but give the
1662          * mptable a chance anyway.
1663          */
1664         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1665         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1666         /* Trust the MP table if nothing is setup in the hardware */
1667         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1668                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1669                 ioapic_i8259.pin  = i8259_pin;
1670                 ioapic_i8259.apic = i8259_apic;
1671         }
1672         /* Complain if the MP table and the hardware disagree */
1673         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1674                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1675         {
1676                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1677         }
1678
1679         /*
1680          * Do not trust the IO-APIC being empty at bootup
1681          */
1682         clear_IO_APIC();
1683 }
1684
1685 /*
1686  * Not an __init, needed by the reboot code
1687  */
1688 void disable_IO_APIC(void)
1689 {
1690         /*
1691          * Clear the IO-APIC before rebooting:
1692          */
1693         clear_IO_APIC();
1694
1695         /*
1696          * If the i8259 is routed through an IOAPIC
1697          * Put that IOAPIC in virtual wire mode
1698          * so legacy interrupts can be delivered.
1699          */
1700         if (ioapic_i8259.pin != -1) {
1701                 struct IO_APIC_route_entry entry;
1702
1703                 memset(&entry, 0, sizeof(entry));
1704                 entry.mask            = 0; /* Enabled */
1705                 entry.trigger         = 0; /* Edge */
1706                 entry.irr             = 0;
1707                 entry.polarity        = 0; /* High */
1708                 entry.delivery_status = 0;
1709                 entry.dest_mode       = 0; /* Physical */
1710                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1711                 entry.vector          = 0;
1712                 entry.dest.physical.physical_dest =
1713                                         GET_APIC_ID(read_apic_id());
1714
1715                 /*
1716                  * Add it to the IO-APIC irq-routing table:
1717                  */
1718                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1719         }
1720         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1721 }
1722
1723 /*
1724  * function to set the IO-APIC physical IDs based on the
1725  * values stored in the MPC table.
1726  *
1727  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1728  */
1729
1730 static void __init setup_ioapic_ids_from_mpc(void)
1731 {
1732         union IO_APIC_reg_00 reg_00;
1733         physid_mask_t phys_id_present_map;
1734         int apic;
1735         int i;
1736         unsigned char old_id;
1737         unsigned long flags;
1738
1739 #ifdef CONFIG_X86_NUMAQ
1740         if (found_numaq)
1741                 return;
1742 #endif
1743
1744         /*
1745          * Don't check I/O APIC IDs for xAPIC systems.  They have
1746          * no meaning without the serial APIC bus.
1747          */
1748         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1749                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1750                 return;
1751         /*
1752          * This is broken; anything with a real cpu count has to
1753          * circumvent this idiocy regardless.
1754          */
1755         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1756
1757         /*
1758          * Set the IOAPIC ID to the value stored in the MPC table.
1759          */
1760         for (apic = 0; apic < nr_ioapics; apic++) {
1761
1762                 /* Read the register 0 value */
1763                 spin_lock_irqsave(&ioapic_lock, flags);
1764                 reg_00.raw = io_apic_read(apic, 0);
1765                 spin_unlock_irqrestore(&ioapic_lock, flags);
1766
1767                 old_id = mp_ioapics[apic].mp_apicid;
1768
1769                 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1770                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1771                                 apic, mp_ioapics[apic].mp_apicid);
1772                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1773                                 reg_00.bits.ID);
1774                         mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1775                 }
1776
1777                 /*
1778                  * Sanity check, is the ID really free? Every APIC in a
1779                  * system must have a unique ID or we get lots of nice
1780                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1781                  */
1782                 if (check_apicid_used(phys_id_present_map,
1783                                         mp_ioapics[apic].mp_apicid)) {
1784                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1785                                 apic, mp_ioapics[apic].mp_apicid);
1786                         for (i = 0; i < get_physical_broadcast(); i++)
1787                                 if (!physid_isset(i, phys_id_present_map))
1788                                         break;
1789                         if (i >= get_physical_broadcast())
1790                                 panic("Max APIC ID exceeded!\n");
1791                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1792                                 i);
1793                         physid_set(i, phys_id_present_map);
1794                         mp_ioapics[apic].mp_apicid = i;
1795                 } else {
1796                         physid_mask_t tmp;
1797                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1798                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1799                                         "phys_id_present_map\n",
1800                                         mp_ioapics[apic].mp_apicid);
1801                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1802                 }
1803
1804
1805                 /*
1806                  * We need to adjust the IRQ routing table
1807                  * if the ID changed.
1808                  */
1809                 if (old_id != mp_ioapics[apic].mp_apicid)
1810                         for (i = 0; i < mp_irq_entries; i++)
1811                                 if (mp_irqs[i].mp_dstapic == old_id)
1812                                         mp_irqs[i].mp_dstapic
1813                                                 = mp_ioapics[apic].mp_apicid;
1814
1815                 /*
1816                  * Read the right value from the MPC table and
1817                  * write it into the ID register.
1818                  */
1819                 apic_printk(APIC_VERBOSE, KERN_INFO
1820                         "...changing IO-APIC physical APIC ID to %d ...",
1821                         mp_ioapics[apic].mp_apicid);
1822
1823                 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1824                 spin_lock_irqsave(&ioapic_lock, flags);
1825                 io_apic_write(apic, 0, reg_00.raw);
1826                 spin_unlock_irqrestore(&ioapic_lock, flags);
1827
1828                 /*
1829                  * Sanity check
1830                  */
1831                 spin_lock_irqsave(&ioapic_lock, flags);
1832                 reg_00.raw = io_apic_read(apic, 0);
1833                 spin_unlock_irqrestore(&ioapic_lock, flags);
1834                 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1835                         printk("could not set ID!\n");
1836                 else
1837                         apic_printk(APIC_VERBOSE, " ok.\n");
1838         }
1839 }
1840
1841 int no_timer_check __initdata;
1842
1843 static int __init notimercheck(char *s)
1844 {
1845         no_timer_check = 1;
1846         return 1;
1847 }
1848 __setup("no_timer_check", notimercheck);
1849
1850 /*
1851  * There is a nasty bug in some older SMP boards, their mptable lies
1852  * about the timer IRQ. We do the following to work around the situation:
1853  *
1854  *      - timer IRQ defaults to IO-APIC IRQ
1855  *      - if this function detects that timer IRQs are defunct, then we fall
1856  *        back to ISA timer IRQs
1857  */
1858 static int __init timer_irq_works(void)
1859 {
1860         unsigned long t1 = jiffies;
1861         unsigned long flags;
1862
1863         if (no_timer_check)
1864                 return 1;
1865
1866         local_save_flags(flags);
1867         local_irq_enable();
1868         /* Let ten ticks pass... */
1869         mdelay((10 * 1000) / HZ);
1870         local_irq_restore(flags);
1871
1872         /*
1873          * Expect a few ticks at least, to be sure some possible
1874          * glue logic does not lock up after one or two first
1875          * ticks in a non-ExtINT mode.  Also the local APIC
1876          * might have cached one ExtINT interrupt.  Finally, at
1877          * least one tick may be lost due to delays.
1878          */
1879         if (time_after(jiffies, t1 + 4))
1880                 return 1;
1881
1882         return 0;
1883 }
1884
1885 /*
1886  * In the SMP+IOAPIC case it might happen that there are an unspecified
1887  * number of pending IRQ events unhandled. These cases are very rare,
1888  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1889  * better to do it this way as thus we do not have to be aware of
1890  * 'pending' interrupts in the IRQ path, except at this point.
1891  */
1892 /*
1893  * Edge triggered needs to resend any interrupt
1894  * that was delayed but this is now handled in the device
1895  * independent code.
1896  */
1897
1898 /*
1899  * Startup quirk:
1900  *
1901  * Starting up a edge-triggered IO-APIC interrupt is
1902  * nasty - we need to make sure that we get the edge.
1903  * If it is already asserted for some reason, we need
1904  * return 1 to indicate that is was pending.
1905  *
1906  * This is not complete - we should be able to fake
1907  * an edge even if it isn't on the 8259A...
1908  *
1909  * (We do this for level-triggered IRQs too - it cannot hurt.)
1910  */
1911 static unsigned int startup_ioapic_irq(unsigned int irq)
1912 {
1913         int was_pending = 0;
1914         unsigned long flags;
1915
1916         spin_lock_irqsave(&ioapic_lock, flags);
1917         if (irq < 16) {
1918                 disable_8259A_irq(irq);
1919                 if (i8259A_irq_pending(irq))
1920                         was_pending = 1;
1921         }
1922         __unmask_IO_APIC_irq(irq);
1923         spin_unlock_irqrestore(&ioapic_lock, flags);
1924
1925         return was_pending;
1926 }
1927
1928 static void ack_ioapic_irq(unsigned int irq)
1929 {
1930         move_native_irq(irq);
1931         ack_APIC_irq();
1932 }
1933
1934 static void ack_ioapic_quirk_irq(unsigned int irq)
1935 {
1936         unsigned long v;
1937         int i;
1938
1939         move_native_irq(irq);
1940 /*
1941  * It appears there is an erratum which affects at least version 0x11
1942  * of I/O APIC (that's the 82093AA and cores integrated into various
1943  * chipsets).  Under certain conditions a level-triggered interrupt is
1944  * erroneously delivered as edge-triggered one but the respective IRR
1945  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1946  * message but it will never arrive and further interrupts are blocked
1947  * from the source.  The exact reason is so far unknown, but the
1948  * phenomenon was observed when two consecutive interrupt requests
1949  * from a given source get delivered to the same CPU and the source is
1950  * temporarily disabled in between.
1951  *
1952  * A workaround is to simulate an EOI message manually.  We achieve it
1953  * by setting the trigger mode to edge and then to level when the edge
1954  * trigger mode gets detected in the TMR of a local APIC for a
1955  * level-triggered interrupt.  We mask the source for the time of the
1956  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1957  * The idea is from Manfred Spraul.  --macro
1958  */
1959         i = irq_vector[irq];
1960
1961         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1962
1963         ack_APIC_irq();
1964
1965         if (!(v & (1 << (i & 0x1f)))) {
1966                 atomic_inc(&irq_mis_count);
1967                 spin_lock(&ioapic_lock);
1968                 __mask_and_edge_IO_APIC_irq(irq);
1969                 __unmask_and_level_IO_APIC_irq(irq);
1970                 spin_unlock(&ioapic_lock);
1971         }
1972 }
1973
1974 static int ioapic_retrigger_irq(unsigned int irq)
1975 {
1976         send_IPI_self(irq_vector[irq]);
1977
1978         return 1;
1979 }
1980
1981 static struct irq_chip ioapic_chip __read_mostly = {
1982         .name           = "IO-APIC",
1983         .startup        = startup_ioapic_irq,
1984         .mask           = mask_IO_APIC_irq,
1985         .unmask         = unmask_IO_APIC_irq,
1986         .ack            = ack_ioapic_irq,
1987         .eoi            = ack_ioapic_quirk_irq,
1988 #ifdef CONFIG_SMP
1989         .set_affinity   = set_ioapic_affinity_irq,
1990 #endif
1991         .retrigger      = ioapic_retrigger_irq,
1992 };
1993
1994
1995 static inline void init_IO_APIC_traps(void)
1996 {
1997         int irq;
1998
1999         /*
2000          * NOTE! The local APIC isn't very good at handling
2001          * multiple interrupts at the same interrupt level.
2002          * As the interrupt level is determined by taking the
2003          * vector number and shifting that right by 4, we
2004          * want to spread these out a bit so that they don't
2005          * all fall in the same interrupt level.
2006          *
2007          * Also, we've got to be careful not to trash gate
2008          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2009          */
2010         for (irq = 0; irq < NR_IRQS ; irq++) {
2011                 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
2012                         /*
2013                          * Hmm.. We don't have an entry for this,
2014                          * so default to an old-fashioned 8259
2015                          * interrupt if we can..
2016                          */
2017                         if (irq < 16)
2018                                 make_8259A_irq(irq);
2019                         else
2020                                 /* Strange. Oh, well.. */
2021                                 irq_desc[irq].chip = &no_irq_chip;
2022                 }
2023         }
2024 }
2025
2026 /*
2027  * The local APIC irq-chip implementation:
2028  */
2029
2030 static void ack_apic(unsigned int irq)
2031 {
2032         ack_APIC_irq();
2033 }
2034
2035 static void mask_lapic_irq(unsigned int irq)
2036 {
2037         unsigned long v;
2038
2039         v = apic_read(APIC_LVT0);
2040         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2041 }
2042
2043 static void unmask_lapic_irq(unsigned int irq)
2044 {
2045         unsigned long v;
2046
2047         v = apic_read(APIC_LVT0);
2048         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2049 }
2050
2051 static struct irq_chip lapic_chip __read_mostly = {
2052         .name           = "local-APIC",
2053         .mask           = mask_lapic_irq,
2054         .unmask         = unmask_lapic_irq,
2055         .eoi            = ack_apic,
2056 };
2057
2058 static void __init setup_nmi(void)
2059 {
2060         /*
2061          * Dirty trick to enable the NMI watchdog ...
2062          * We put the 8259A master into AEOI mode and
2063          * unmask on all local APICs LVT0 as NMI.
2064          *
2065          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2066          * is from Maciej W. Rozycki - so we do not have to EOI from
2067          * the NMI handler or the timer interrupt.
2068          */
2069         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2070
2071         enable_NMI_through_LVT0();
2072
2073         apic_printk(APIC_VERBOSE, " done.\n");
2074 }
2075
2076 /*
2077  * This looks a bit hackish but it's about the only one way of sending
2078  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2079  * not support the ExtINT mode, unfortunately.  We need to send these
2080  * cycles as some i82489DX-based boards have glue logic that keeps the
2081  * 8259A interrupt line asserted until INTA.  --macro
2082  */
2083 static inline void __init unlock_ExtINT_logic(void)
2084 {
2085         int apic, pin, i;
2086         struct IO_APIC_route_entry entry0, entry1;
2087         unsigned char save_control, save_freq_select;
2088
2089         pin  = find_isa_irq_pin(8, mp_INT);
2090         if (pin == -1) {
2091                 WARN_ON_ONCE(1);
2092                 return;
2093         }
2094         apic = find_isa_irq_apic(8, mp_INT);
2095         if (apic == -1) {
2096                 WARN_ON_ONCE(1);
2097                 return;
2098         }
2099
2100         entry0 = ioapic_read_entry(apic, pin);
2101         clear_IO_APIC_pin(apic, pin);
2102
2103         memset(&entry1, 0, sizeof(entry1));
2104
2105         entry1.dest_mode = 0;                   /* physical delivery */
2106         entry1.mask = 0;                        /* unmask IRQ now */
2107         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2108         entry1.delivery_mode = dest_ExtINT;
2109         entry1.polarity = entry0.polarity;
2110         entry1.trigger = 0;
2111         entry1.vector = 0;
2112
2113         ioapic_write_entry(apic, pin, entry1);
2114
2115         save_control = CMOS_READ(RTC_CONTROL);
2116         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2117         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2118                    RTC_FREQ_SELECT);
2119         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2120
2121         i = 100;
2122         while (i-- > 0) {
2123                 mdelay(10);
2124                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2125                         i -= 10;
2126         }
2127
2128         CMOS_WRITE(save_control, RTC_CONTROL);
2129         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2130         clear_IO_APIC_pin(apic, pin);
2131
2132         ioapic_write_entry(apic, pin, entry0);
2133 }
2134
2135 /*
2136  * This code may look a bit paranoid, but it's supposed to cooperate with
2137  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2138  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2139  * fanatically on his truly buggy board.
2140  */
2141 static inline void __init check_timer(void)
2142 {
2143         int apic1, pin1, apic2, pin2;
2144         int no_pin1 = 0;
2145         int vector;
2146         unsigned int ver;
2147         unsigned long flags;
2148
2149         local_irq_save(flags);
2150
2151         ver = apic_read(APIC_LVR);
2152         ver = GET_APIC_VERSION(ver);
2153
2154         /*
2155          * get/set the timer IRQ vector:
2156          */
2157         disable_8259A_irq(0);
2158         vector = assign_irq_vector(0);
2159         set_intr_gate(vector, interrupt[0]);
2160
2161         /*
2162          * As IRQ0 is to be enabled in the 8259A, the virtual
2163          * wire has to be disabled in the local APIC.  Also
2164          * timer interrupts need to be acknowledged manually in
2165          * the 8259A for the i82489DX when using the NMI
2166          * watchdog as that APIC treats NMIs as level-triggered.
2167          * The AEOI mode will finish them in the 8259A
2168          * automatically.
2169          */
2170         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2171         init_8259A(1);
2172         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2173
2174         pin1  = find_isa_irq_pin(0, mp_INT);
2175         apic1 = find_isa_irq_apic(0, mp_INT);
2176         pin2  = ioapic_i8259.pin;
2177         apic2 = ioapic_i8259.apic;
2178
2179         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2180                 vector, apic1, pin1, apic2, pin2);
2181
2182         if (mask_ioapic_irq_2)
2183                 mask_IO_APIC_irq(2);
2184
2185         /*
2186          * Some BIOS writers are clueless and report the ExtINTA
2187          * I/O APIC input from the cascaded 8259A as the timer
2188          * interrupt input.  So just in case, if only one pin
2189          * was found above, try it both directly and through the
2190          * 8259A.
2191          */
2192         if (pin1 == -1) {
2193                 pin1 = pin2;
2194                 apic1 = apic2;
2195                 no_pin1 = 1;
2196         } else if (pin2 == -1) {
2197                 pin2 = pin1;
2198                 apic2 = apic1;
2199         }
2200
2201         if (pin1 != -1) {
2202                 /*
2203                  * Ok, does IRQ0 through the IOAPIC work?
2204                  */
2205                 if (no_pin1) {
2206                         add_pin_to_irq(0, apic1, pin1);
2207                         setup_timer_IRQ0_pin(apic1, pin1, vector);
2208                 }
2209                 unmask_IO_APIC_irq(0);
2210                 if (timer_irq_works()) {
2211                         if (nmi_watchdog == NMI_IO_APIC) {
2212                                 setup_nmi();
2213                                 enable_8259A_irq(0);
2214                         }
2215                         if (disable_timer_pin_1 > 0)
2216                                 clear_IO_APIC_pin(0, pin1);
2217                         goto out;
2218                 }
2219                 clear_IO_APIC_pin(apic1, pin1);
2220                 if (!no_pin1)
2221                         printk(KERN_ERR "..MP-BIOS bug: "
2222                                "8254 timer not connected to IO-APIC\n");
2223
2224                 printk(KERN_INFO "...trying to set up timer (IRQ0) "
2225                        "through the 8259A ... ");
2226                 printk("\n..... (found pin %d) ...", pin2);
2227                 /*
2228                  * legacy devices should be connected to IO APIC #0
2229                  */
2230                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2231                 setup_timer_IRQ0_pin(apic2, pin2, vector);
2232                 unmask_IO_APIC_irq(0);
2233                 enable_8259A_irq(0);
2234                 if (timer_irq_works()) {
2235                         printk("works.\n");
2236                         timer_through_8259 = 1;
2237                         if (nmi_watchdog == NMI_IO_APIC) {
2238                                 disable_8259A_irq(0);
2239                                 setup_nmi();
2240                                 enable_8259A_irq(0);
2241                         }
2242                         goto out;
2243                 }
2244                 /*
2245                  * Cleanup, just in case ...
2246                  */
2247                 disable_8259A_irq(0);
2248                 clear_IO_APIC_pin(apic2, pin2);
2249                 printk(" failed.\n");
2250         }
2251
2252         if (nmi_watchdog == NMI_IO_APIC) {
2253                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2254                 nmi_watchdog = NMI_NONE;
2255         }
2256         timer_ack = 0;
2257
2258         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2259
2260         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2261                                       "fasteoi");
2262         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2263         enable_8259A_irq(0);
2264
2265         if (timer_irq_works()) {
2266                 printk(" works.\n");
2267                 goto out;
2268         }
2269         disable_8259A_irq(0);
2270         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2271         printk(" failed.\n");
2272
2273         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2274
2275         init_8259A(0);
2276         make_8259A_irq(0);
2277         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2278
2279         unlock_ExtINT_logic();
2280
2281         if (timer_irq_works()) {
2282                 printk(" works.\n");
2283                 goto out;
2284         }
2285         printk(" failed :(.\n");
2286         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2287                 "report.  Then try booting with the 'noapic' option");
2288 out:
2289         local_irq_restore(flags);
2290 }
2291
2292 /*
2293  *
2294  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2295  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2296  *   Linux doesn't really care, as it's not actually used
2297  *   for any interrupt handling anyway.
2298  */
2299 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2300
2301 void __init setup_IO_APIC(void)
2302 {
2303         int i;
2304
2305         /* Reserve all the system vectors. */
2306         for (i = first_system_vector; i < NR_VECTORS; i++)
2307                 set_bit(i, used_vectors);
2308
2309         enable_IO_APIC();
2310
2311         if (acpi_ioapic)
2312                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2313         else
2314                 io_apic_irqs = ~PIC_IRQS;
2315
2316         printk("ENABLING IO-APIC IRQs\n");
2317
2318         /*
2319          * Set up IO-APIC IRQ routing.
2320          */
2321         if (!acpi_ioapic)
2322                 setup_ioapic_ids_from_mpc();
2323         sync_Arb_IDs();
2324         setup_IO_APIC_irqs();
2325         init_IO_APIC_traps();
2326         check_timer();
2327         if (!acpi_ioapic)
2328                 print_IO_APIC();
2329 }
2330
2331 /*
2332  *      Called after all the initialization is done. If we didnt find any
2333  *      APIC bugs then we can allow the modify fast path
2334  */
2335
2336 static int __init io_apic_bug_finalize(void)
2337 {
2338         if (sis_apic_bug == -1)
2339                 sis_apic_bug = 0;
2340         return 0;
2341 }
2342
2343 late_initcall(io_apic_bug_finalize);
2344
2345 struct sysfs_ioapic_data {
2346         struct sys_device dev;
2347         struct IO_APIC_route_entry entry[0];
2348 };
2349 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2350
2351 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2352 {
2353         struct IO_APIC_route_entry *entry;
2354         struct sysfs_ioapic_data *data;
2355         int i;
2356
2357         data = container_of(dev, struct sysfs_ioapic_data, dev);
2358         entry = data->entry;
2359         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2360                 entry[i] = ioapic_read_entry(dev->id, i);
2361
2362         return 0;
2363 }
2364
2365 static int ioapic_resume(struct sys_device *dev)
2366 {
2367         struct IO_APIC_route_entry *entry;
2368         struct sysfs_ioapic_data *data;
2369         unsigned long flags;
2370         union IO_APIC_reg_00 reg_00;
2371         int i;
2372
2373         data = container_of(dev, struct sysfs_ioapic_data, dev);
2374         entry = data->entry;
2375
2376         spin_lock_irqsave(&ioapic_lock, flags);
2377         reg_00.raw = io_apic_read(dev->id, 0);
2378         if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2379                 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2380                 io_apic_write(dev->id, 0, reg_00.raw);
2381         }
2382         spin_unlock_irqrestore(&ioapic_lock, flags);
2383         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2384                 ioapic_write_entry(dev->id, i, entry[i]);
2385
2386         return 0;
2387 }
2388
2389 static struct sysdev_class ioapic_sysdev_class = {
2390         .name = "ioapic",
2391         .suspend = ioapic_suspend,
2392         .resume = ioapic_resume,
2393 };
2394
2395 static int __init ioapic_init_sysfs(void)
2396 {
2397         struct sys_device *dev;
2398         int i, size, error = 0;
2399
2400         error = sysdev_class_register(&ioapic_sysdev_class);
2401         if (error)
2402                 return error;
2403
2404         for (i = 0; i < nr_ioapics; i++) {
2405                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2406                         * sizeof(struct IO_APIC_route_entry);
2407                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2408                 if (!mp_ioapic_data[i]) {
2409                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2410                         continue;
2411                 }
2412                 dev = &mp_ioapic_data[i]->dev;
2413                 dev->id = i;
2414                 dev->cls = &ioapic_sysdev_class;
2415                 error = sysdev_register(dev);
2416                 if (error) {
2417                         kfree(mp_ioapic_data[i]);
2418                         mp_ioapic_data[i] = NULL;
2419                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2420                         continue;
2421                 }
2422         }
2423
2424         return 0;
2425 }
2426
2427 device_initcall(ioapic_init_sysfs);
2428
2429 /*
2430  * Dynamic irq allocate and deallocation
2431  */
2432 int create_irq(void)
2433 {
2434         /* Allocate an unused irq */
2435         int irq, new, vector = 0;
2436         unsigned long flags;
2437
2438         irq = -ENOSPC;
2439         spin_lock_irqsave(&vector_lock, flags);
2440         for (new = (NR_IRQS - 1); new >= 0; new--) {
2441                 if (platform_legacy_irq(new))
2442                         continue;
2443                 if (irq_vector[new] != 0)
2444                         continue;
2445                 vector = __assign_irq_vector(new);
2446                 if (likely(vector > 0))
2447                         irq = new;
2448                 break;
2449         }
2450         spin_unlock_irqrestore(&vector_lock, flags);
2451
2452         if (irq >= 0) {
2453                 set_intr_gate(vector, interrupt[irq]);
2454                 dynamic_irq_init(irq);
2455         }
2456         return irq;
2457 }
2458
2459 void destroy_irq(unsigned int irq)
2460 {
2461         unsigned long flags;
2462
2463         dynamic_irq_cleanup(irq);
2464
2465         spin_lock_irqsave(&vector_lock, flags);
2466         clear_bit(irq_vector[irq], used_vectors);
2467         irq_vector[irq] = 0;
2468         spin_unlock_irqrestore(&vector_lock, flags);
2469 }
2470
2471 /*
2472  * MSI message composition
2473  */
2474 #ifdef CONFIG_PCI_MSI
2475 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2476 {
2477         int vector;
2478         unsigned dest;
2479
2480         vector = assign_irq_vector(irq);
2481         if (vector >= 0) {
2482                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2483
2484                 msg->address_hi = MSI_ADDR_BASE_HI;
2485                 msg->address_lo =
2486                         MSI_ADDR_BASE_LO |
2487                         ((INT_DEST_MODE == 0) ?
2488 MSI_ADDR_DEST_MODE_PHYSICAL:
2489                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2490                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2491                                 MSI_ADDR_REDIRECTION_CPU:
2492                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2493                         MSI_ADDR_DEST_ID(dest);
2494
2495                 msg->data =
2496                         MSI_DATA_TRIGGER_EDGE |
2497                         MSI_DATA_LEVEL_ASSERT |
2498                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2499 MSI_DATA_DELIVERY_FIXED:
2500                                 MSI_DATA_DELIVERY_LOWPRI) |
2501                         MSI_DATA_VECTOR(vector);
2502         }
2503         return vector;
2504 }
2505
2506 #ifdef CONFIG_SMP
2507 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2508 {
2509         struct msi_msg msg;
2510         unsigned int dest;
2511         cpumask_t tmp;
2512         int vector;
2513
2514         cpus_and(tmp, mask, cpu_online_map);
2515         if (cpus_empty(tmp))
2516                 tmp = TARGET_CPUS;
2517
2518         vector = assign_irq_vector(irq);
2519         if (vector < 0)
2520                 return;
2521
2522         dest = cpu_mask_to_apicid(mask);
2523
2524         read_msi_msg(irq, &msg);
2525
2526         msg.data &= ~MSI_DATA_VECTOR_MASK;
2527         msg.data |= MSI_DATA_VECTOR(vector);
2528         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2529         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2530
2531         write_msi_msg(irq, &msg);
2532         irq_desc[irq].affinity = mask;
2533 }
2534 #endif /* CONFIG_SMP */
2535
2536 /*
2537  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2538  * which implement the MSI or MSI-X Capability Structure.
2539  */
2540 static struct irq_chip msi_chip = {
2541         .name           = "PCI-MSI",
2542         .unmask         = unmask_msi_irq,
2543         .mask           = mask_msi_irq,
2544         .ack            = ack_ioapic_irq,
2545 #ifdef CONFIG_SMP
2546         .set_affinity   = set_msi_irq_affinity,
2547 #endif
2548         .retrigger      = ioapic_retrigger_irq,
2549 };
2550
2551 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2552 {
2553         struct msi_msg msg;
2554         int irq, ret;
2555         irq = create_irq();
2556         if (irq < 0)
2557                 return irq;
2558
2559         ret = msi_compose_msg(dev, irq, &msg);
2560         if (ret < 0) {
2561                 destroy_irq(irq);
2562                 return ret;
2563         }
2564
2565         set_irq_msi(irq, desc);
2566         write_msi_msg(irq, &msg);
2567
2568         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2569                                       "edge");
2570
2571         return 0;
2572 }
2573
2574 void arch_teardown_msi_irq(unsigned int irq)
2575 {
2576         destroy_irq(irq);
2577 }
2578
2579 #endif /* CONFIG_PCI_MSI */
2580
2581 /*
2582  * Hypertransport interrupt support
2583  */
2584 #ifdef CONFIG_HT_IRQ
2585
2586 #ifdef CONFIG_SMP
2587
2588 static void target_ht_irq(unsigned int irq, unsigned int dest)
2589 {
2590         struct ht_irq_msg msg;
2591         fetch_ht_irq_msg(irq, &msg);
2592
2593         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2594         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2595
2596         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2597         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2598
2599         write_ht_irq_msg(irq, &msg);
2600 }
2601
2602 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2603 {
2604         unsigned int dest;
2605         cpumask_t tmp;
2606
2607         cpus_and(tmp, mask, cpu_online_map);
2608         if (cpus_empty(tmp))
2609                 tmp = TARGET_CPUS;
2610
2611         cpus_and(mask, tmp, CPU_MASK_ALL);
2612
2613         dest = cpu_mask_to_apicid(mask);
2614
2615         target_ht_irq(irq, dest);
2616         irq_desc[irq].affinity = mask;
2617 }
2618 #endif
2619
2620 static struct irq_chip ht_irq_chip = {
2621         .name           = "PCI-HT",
2622         .mask           = mask_ht_irq,
2623         .unmask         = unmask_ht_irq,
2624         .ack            = ack_ioapic_irq,
2625 #ifdef CONFIG_SMP
2626         .set_affinity   = set_ht_irq_affinity,
2627 #endif
2628         .retrigger      = ioapic_retrigger_irq,
2629 };
2630
2631 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2632 {
2633         int vector;
2634
2635         vector = assign_irq_vector(irq);
2636         if (vector >= 0) {
2637                 struct ht_irq_msg msg;
2638                 unsigned dest;
2639                 cpumask_t tmp;
2640
2641                 cpus_clear(tmp);
2642                 cpu_set(vector >> 8, tmp);
2643                 dest = cpu_mask_to_apicid(tmp);
2644
2645                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2646
2647                 msg.address_lo =
2648                         HT_IRQ_LOW_BASE |
2649                         HT_IRQ_LOW_DEST_ID(dest) |
2650                         HT_IRQ_LOW_VECTOR(vector) |
2651                         ((INT_DEST_MODE == 0) ?
2652                                 HT_IRQ_LOW_DM_PHYSICAL :
2653                                 HT_IRQ_LOW_DM_LOGICAL) |
2654                         HT_IRQ_LOW_RQEOI_EDGE |
2655                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2656                                 HT_IRQ_LOW_MT_FIXED :
2657                                 HT_IRQ_LOW_MT_ARBITRATED) |
2658                         HT_IRQ_LOW_IRQ_MASKED;
2659
2660                 write_ht_irq_msg(irq, &msg);
2661
2662                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2663                                               handle_edge_irq, "edge");
2664         }
2665         return vector;
2666 }
2667 #endif /* CONFIG_HT_IRQ */
2668
2669 /* --------------------------------------------------------------------------
2670                         ACPI-based IOAPIC Configuration
2671    -------------------------------------------------------------------------- */
2672
2673 #ifdef CONFIG_ACPI
2674
2675 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2676 {
2677         union IO_APIC_reg_00 reg_00;
2678         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2679         physid_mask_t tmp;
2680         unsigned long flags;
2681         int i = 0;
2682
2683         /*
2684          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2685          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2686          * supports up to 16 on one shared APIC bus.
2687          *
2688          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2689          *      advantage of new APIC bus architecture.
2690          */
2691
2692         if (physids_empty(apic_id_map))
2693                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2694
2695         spin_lock_irqsave(&ioapic_lock, flags);
2696         reg_00.raw = io_apic_read(ioapic, 0);
2697         spin_unlock_irqrestore(&ioapic_lock, flags);
2698
2699         if (apic_id >= get_physical_broadcast()) {
2700                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2701                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2702                 apic_id = reg_00.bits.ID;
2703         }
2704
2705         /*
2706          * Every APIC in a system must have a unique ID or we get lots of nice
2707          * 'stuck on smp_invalidate_needed IPI wait' messages.
2708          */
2709         if (check_apicid_used(apic_id_map, apic_id)) {
2710
2711                 for (i = 0; i < get_physical_broadcast(); i++) {
2712                         if (!check_apicid_used(apic_id_map, i))
2713                                 break;
2714                 }
2715
2716                 if (i == get_physical_broadcast())
2717                         panic("Max apic_id exceeded!\n");
2718
2719                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2720                         "trying %d\n", ioapic, apic_id, i);
2721
2722                 apic_id = i;
2723         }
2724
2725         tmp = apicid_to_cpu_present(apic_id);
2726         physids_or(apic_id_map, apic_id_map, tmp);
2727
2728         if (reg_00.bits.ID != apic_id) {
2729                 reg_00.bits.ID = apic_id;
2730
2731                 spin_lock_irqsave(&ioapic_lock, flags);
2732                 io_apic_write(ioapic, 0, reg_00.raw);
2733                 reg_00.raw = io_apic_read(ioapic, 0);
2734                 spin_unlock_irqrestore(&ioapic_lock, flags);
2735
2736                 /* Sanity check */
2737                 if (reg_00.bits.ID != apic_id) {
2738                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2739                         return -1;
2740                 }
2741         }
2742
2743         apic_printk(APIC_VERBOSE, KERN_INFO
2744                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2745
2746         return apic_id;
2747 }
2748
2749
2750 int __init io_apic_get_version(int ioapic)
2751 {
2752         union IO_APIC_reg_01    reg_01;
2753         unsigned long flags;
2754
2755         spin_lock_irqsave(&ioapic_lock, flags);
2756         reg_01.raw = io_apic_read(ioapic, 1);
2757         spin_unlock_irqrestore(&ioapic_lock, flags);
2758
2759         return reg_01.bits.version;
2760 }
2761
2762
2763 int __init io_apic_get_redir_entries(int ioapic)
2764 {
2765         union IO_APIC_reg_01    reg_01;
2766         unsigned long flags;
2767
2768         spin_lock_irqsave(&ioapic_lock, flags);
2769         reg_01.raw = io_apic_read(ioapic, 1);
2770         spin_unlock_irqrestore(&ioapic_lock, flags);
2771
2772         return reg_01.bits.entries;
2773 }
2774
2775
2776 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2777 {
2778         struct IO_APIC_route_entry entry;
2779
2780         if (!IO_APIC_IRQ(irq)) {
2781                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2782                         ioapic);
2783                 return -EINVAL;
2784         }
2785
2786         /*
2787          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2788          * Note that we mask (disable) IRQs now -- these get enabled when the
2789          * corresponding device driver registers for this IRQ.
2790          */
2791
2792         memset(&entry, 0, sizeof(entry));
2793
2794         entry.delivery_mode = INT_DELIVERY_MODE;
2795         entry.dest_mode = INT_DEST_MODE;
2796         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2797         entry.trigger = edge_level;
2798         entry.polarity = active_high_low;
2799         entry.mask  = 1;
2800
2801         /*
2802          * IRQs < 16 are already in the irq_2_pin[] map
2803          */
2804         if (irq >= 16)
2805                 add_pin_to_irq(irq, ioapic, pin);
2806
2807         entry.vector = assign_irq_vector(irq);
2808
2809         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2810                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2811                 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2812                 edge_level, active_high_low);
2813
2814         ioapic_register_intr(irq, entry.vector, edge_level);
2815
2816         if (!ioapic && (irq < 16))
2817                 disable_8259A_irq(irq);
2818
2819         ioapic_write_entry(ioapic, pin, entry);
2820
2821         return 0;
2822 }
2823
2824 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2825 {
2826         int i;
2827
2828         if (skip_ioapic_setup)
2829                 return -1;
2830
2831         for (i = 0; i < mp_irq_entries; i++)
2832                 if (mp_irqs[i].mp_irqtype == mp_INT &&
2833                     mp_irqs[i].mp_srcbusirq == bus_irq)
2834                         break;
2835         if (i >= mp_irq_entries)
2836                 return -1;
2837
2838         *trigger = irq_trigger(i);
2839         *polarity = irq_polarity(i);
2840         return 0;
2841 }
2842
2843 #endif /* CONFIG_ACPI */
2844
2845 static int __init parse_disable_timer_pin_1(char *arg)
2846 {
2847         disable_timer_pin_1 = 1;
2848         return 0;
2849 }
2850 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2851
2852 static int __init parse_enable_timer_pin_1(char *arg)
2853 {
2854         disable_timer_pin_1 = -1;
2855         return 0;
2856 }
2857 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2858
2859 static int __init parse_noapic(char *arg)
2860 {
2861         /* disable IO-APIC */
2862         disable_ioapic_setup();
2863         return 0;
2864 }
2865 early_param("noapic", parse_noapic);
2866
2867 void __init ioapic_init_mappings(void)
2868 {
2869         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2870         int i;
2871
2872         for (i = 0; i < nr_ioapics; i++) {
2873                 if (smp_found_config) {
2874                         ioapic_phys = mp_ioapics[i].mp_apicaddr;
2875                         if (!ioapic_phys) {
2876                                 printk(KERN_ERR
2877                                        "WARNING: bogus zero IO-APIC "
2878                                        "address found in MPTABLE, "
2879                                        "disabling IO/APIC support!\n");
2880                                 smp_found_config = 0;
2881                                 skip_ioapic_setup = 1;
2882                                 goto fake_ioapic_page;
2883                         }
2884                 } else {
2885 fake_ioapic_page:
2886                         ioapic_phys = (unsigned long)
2887                                       alloc_bootmem_pages(PAGE_SIZE);
2888                         ioapic_phys = __pa(ioapic_phys);
2889                 }
2890                 set_fixmap_nocache(idx, ioapic_phys);
2891                 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
2892                        __fix_to_virt(idx), ioapic_phys);
2893                 idx++;
2894         }
2895 }
2896