2 * arch/ppc64/kernel/entry.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
12 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
14 * This file contains the system call entry code, context switch
15 * code, and exception/interrupt return code for PowerPC.
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
23 #include <linux/config.h>
24 #include <linux/errno.h>
25 #include <asm/unistd.h>
26 #include <asm/processor.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/cputable.h>
34 #ifdef CONFIG_PPC_ISERIES
35 #define DO_SOFT_DISABLE
43 .tc .sys_call_table[TC],.sys_call_table
45 /* This value is used to mark exception frames on the stack. */
47 .tc ID_72656773_68657265[TC],0x7265677368657265
54 .globl system_call_common
58 addi r1,r1,-INT_FRAME_SIZE
92 addi r9,r1,STACK_FRAME_OVERHEAD
93 ld r11,exception_marker@toc(r2)
94 std r11,-16(r9) /* "regshere" marker */
95 #ifdef CONFIG_PPC_ISERIES
96 /* Hack for handling interrupts when soft-enabling on iSeries */
97 cmpdi cr1,r0,0x5555 /* syscall 0x5555 */
98 andi. r10,r12,MSR_PR /* from kernel */
99 crand 4*cr0+eq,4*cr1+eq,4*cr0+eq
100 beq hardware_interrupt_entry
101 lbz r10,PACAPROCENABLED(r13)
113 addi r9,r1,STACK_FRAME_OVERHEAD
115 clrrdi r11,r1,THREAD_SHIFT
117 andi. r11,r10,_TIF_SYSCALL_T_OR_A
119 syscall_dotrace_cont:
120 cmpldi 0,r0,NR_syscalls
123 system_call: /* label this so stack traces look sane */
125 * Need to vector to 32 Bit or default sys_call_table here,
126 * based on caller's run-mode / personality.
128 ld r11,.SYS_CALL_TABLE@toc(2)
129 andi. r10,r10,_TIF_32BIT
131 addi r11,r11,8 /* use 32-bit syscall entries */
140 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
142 bctrl /* Call handler */
147 bl .do_show_syscall_exit
150 clrrdi r12,r1,THREAD_SHIFT
152 /* disable interrupts so current_thread_info()->flags can't change,
153 and so that we don't get interrupted after loading SRR0/1. */
163 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_RESTOREALL|_TIF_SAVE_NVGPRS|_TIF_NOERROR)
164 bne- syscall_exit_work
170 stdcx. r0,0,r1 /* to clear the reservation */
173 beq- 1f /* only restore r13 if */
174 ld r13,GPR13(r1) /* returning to usermode */
178 mtmsrd r11,1 /* clear MSR.RI */
185 b . /* prevent speculative execution */
188 oris r5,r5,0x1000 /* Set SO bit in CR */
193 /* Traced system call support */
196 addi r3,r1,STACK_FRAME_OVERHEAD
197 bl .do_syscall_trace_enter
198 ld r0,GPR0(r1) /* Restore original registers */
205 addi r9,r1,STACK_FRAME_OVERHEAD
206 clrrdi r10,r1,THREAD_SHIFT
208 b syscall_dotrace_cont
215 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
216 If TIF_NOERROR is set, just save r3 as it is. */
218 andi. r0,r9,_TIF_RESTOREALL
220 cmpld r3,r11 /* r10 is -LAST_ERRNO */
222 andi. r0,r9,_TIF_NOERROR
226 oris r5,r5,0x1000 /* Set SO bit in CR */
229 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
232 /* Clear per-syscall TIF flags if any are set, but _leave_
233 _TIF_SAVE_NVGPRS set in r9 since we haven't dealt with that
236 li r11,_TIF_PERSYSCALL_MASK
237 addi r12,r12,TI_FLAGS
242 subi r12,r12,TI_FLAGS
245 /* Anything else left to do? */
246 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SAVE_NVGPRS)
247 beq .ret_from_except_lite
249 /* Re-enable interrupts */
254 andi. r0,r9,_TIF_SAVE_NVGPRS
257 /* If tracing, re-enable interrupts and do it */
258 save_user_nvgprs_cont:
259 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
262 addi r3,r1,STACK_FRAME_OVERHEAD
263 bl .do_syscall_trace_leave
265 clrrdi r12,r1,THREAD_SHIFT
267 /* Disable interrupts again and handle other work if any */
273 b .ret_from_except_lite
275 /* Save non-volatile GPRs, if not already saved. */
287 ld r10,TI_SIGFRAME(r12)
288 andi. r0,r9,_TIF_32BIT
289 beq- save_user_nvgprs_64
291 /* 32-bit save to userspace */
293 .macro savewords start, end
294 1: stw \start,4*(\start)(r10)
295 .section __ex_table,"a"
297 .llong 1b,save_user_nvgprs_fault
300 savewords "(\start+1)",\end
304 b save_user_nvgprs_cont
307 /* 64-bit save to userspace */
309 .macro savelongs start, end
310 1: std \start,8*(\start)(r10)
311 .section __ex_table,"a"
313 .llong 1b,save_user_nvgprs_fault
316 savelongs "(\start+1)",\end
320 b save_user_nvgprs_cont
322 save_user_nvgprs_fault:
323 li r3,11 /* SIGSEGV */
327 clrrdi r12,r1,THREAD_SHIFT
329 b save_user_nvgprs_cont
332 * The sigsuspend and rt_sigsuspend system calls can call do_signal
333 * and thus put the process into the stopped state where we might
334 * want to examine its user state with ptrace. Therefore we need
335 * to save all the nonvolatile registers (r14 - r31) before calling
336 * the C code. Similarly, fork, vfork and clone need the full
337 * register state on the stack so that it can be copied to the child.
355 _GLOBAL(ret_from_fork)
362 * This routine switches between two different tasks. The process
363 * state of one is saved on its kernel stack. Then the state
364 * of the other is restored from its kernel stack. The memory
365 * management hardware is updated to the second process's state.
366 * Finally, we can return to the second process, via ret_from_except.
367 * On entry, r3 points to the THREAD for the current task, r4
368 * points to the THREAD for the new task.
370 * Note: there are two ways to get to the "going out" portion
371 * of this code; either by coming in via the entry (_switch)
372 * or via "fork" which must set up an environment equivalent
373 * to the "_switch" path. If you change this you'll have to change
374 * the fork code also.
376 * The code which creates the new task context is in 'copy_thread'
377 * in arch/ppc64/kernel/process.c
383 stdu r1,-SWITCH_FRAME_SIZE(r1)
384 /* r3-r13 are caller saved -- Cort */
387 mflr r20 /* Return to switch caller */
390 #ifdef CONFIG_ALTIVEC
392 oris r0,r0,MSR_VEC@h /* Disable altivec */
393 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
394 std r24,THREAD_VRSAVE(r3)
395 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
396 #endif /* CONFIG_ALTIVEC */
405 std r1,KSP(r3) /* Set old stack pointer */
408 /* We need a sync somewhere here to make sure that if the
409 * previous task gets rescheduled on another CPU, it sees all
410 * stores it has performed on this one.
413 #endif /* CONFIG_SMP */
415 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
416 std r6,PACACURRENT(r13) /* Set new 'current' */
418 ld r8,KSP(r4) /* new stack pointer */
420 clrrdi r6,r8,28 /* get its ESID */
421 clrrdi r9,r1,28 /* get current sp ESID */
422 clrldi. r0,r6,2 /* is new ESID c00000000? */
423 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
425 beq 2f /* if yes, don't slbie it */
427 /* Bolt in the new stack SLB entry */
428 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
429 oris r0,r6,(SLB_ESID_V)@h
430 ori r0,r0,(SLB_NUM_BOLTED-1)@l
432 slbie r6 /* Workaround POWER5 < DD2.1 issue */
437 END_FTR_SECTION_IFSET(CPU_FTR_SLB)
438 clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
439 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
440 because we don't need to leave the 288-byte ABI gap at the
441 top of the kernel stack. */
442 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
444 mr r1,r8 /* start using new stack pointer */
445 std r7,PACAKSAVE(r13)
450 #ifdef CONFIG_ALTIVEC
452 ld r0,THREAD_VRSAVE(r4)
453 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
454 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
455 #endif /* CONFIG_ALTIVEC */
457 /* r3-r13 are destroyed -- Cort */
461 /* convert old thread to its task_struct for return value */
463 ld r7,_NIP(r1) /* Return to _switch caller in new task */
465 addi r1,r1,SWITCH_FRAME_SIZE
469 _GLOBAL(ret_from_except)
472 bne .ret_from_except_lite
475 _GLOBAL(ret_from_except_lite)
477 * Disable interrupts so that current_thread_info()->flags
478 * can't change between when we test it and when we return
479 * from the interrupt.
481 mfmsr r10 /* Get current interrupt state */
482 rldicl r9,r10,48,1 /* clear MSR_EE */
484 mtmsrd r9,1 /* Update machine state */
486 #ifdef CONFIG_PREEMPT
487 clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
488 li r0,_TIF_NEED_RESCHED /* bits to check */
491 /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
492 rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
493 and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
496 #else /* !CONFIG_PREEMPT */
497 ld r3,_MSR(r1) /* Returning to user mode? */
499 beq restore /* if not, just restore regs and return */
501 /* Check current_thread_info()->flags */
502 clrrdi r9,r1,THREAD_SHIFT
504 andi. r0,r4,_TIF_USER_WORK_MASK
509 #ifdef CONFIG_PPC_ISERIES
513 /* Check for pending interrupts (iSeries) */
514 ld r3,PACALPPACAPTR(r13)
515 ld r3,LPPACAANYINT(r3)
517 beq+ 4f /* skip do_IRQ if no interrupts */
520 stb r3,PACAPROCENABLED(r13) /* ensure we are soft-disabled */
522 mtmsrd r10 /* hard-enable again */
523 addi r3,r1,STACK_FRAME_OVERHEAD
525 b .ret_from_except_lite /* loop back and handle more */
527 4: stb r5,PACAPROCENABLED(r13)
537 * r13 is our per cpu area, only restore it if we are returning to
552 stdcx. r0,0,r1 /* to clear the reservation */
574 b . /* prevent speculative execution */
576 /* Note: this must change if we start using the TIF_NOTIFY_RESUME bit */
578 #ifdef CONFIG_PREEMPT
579 andi. r0,r3,MSR_PR /* Returning to user mode? */
581 /* Check that preempt_count() == 0 and interrupts are enabled */
582 lwz r8,TI_PREEMPT(r9)
584 #ifdef CONFIG_PPC_ISERIES
590 crandc eq,cr1*4+eq,eq
592 /* here we are preempting the current task */
594 #ifdef CONFIG_PPC_ISERIES
596 stb r0,PACAPROCENABLED(r13)
599 mtmsrd r10,1 /* reenable interrupts */
602 clrrdi r9,r1,THREAD_SHIFT
603 rldicl r10,r10,48,1 /* disable interrupts again */
607 andi. r0,r4,_TIF_NEED_RESCHED
613 /* Enable interrupts */
617 andi. r0,r4,_TIF_NEED_RESCHED
620 b .ret_from_except_lite
624 addi r4,r1,STACK_FRAME_OVERHEAD
629 addi r3,r1,STACK_FRAME_OVERHEAD
630 bl .unrecoverable_exception
633 #ifdef CONFIG_PPC_RTAS
635 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
636 * called with the MMU off.
638 * In addition, we need to be in 32b mode, at least for now.
640 * Note: r3 is an input parameter to rtas, so don't trash it...
645 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
647 /* Because RTAS is running in 32b mode, it clobbers the high order half
648 * of all registers that it saves. We therefore save those registers
649 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
651 SAVE_GPR(2, r1) /* Save the TOC */
652 SAVE_GPR(13, r1) /* Save paca */
653 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
654 SAVE_10GPRS(22, r1) /* ditto */
671 /* There is no way it is acceptable to get here with interrupts enabled,
672 * check it with the asm equivalent of WARN_ON
677 .section __bug_table,"a"
678 .llong 1b,__LINE__ + 0x1000000, 1f, 2f
682 2: .asciz "enter_rtas"
685 /* Unfortunately, the stack pointer and the MSR are also clobbered,
686 * so they are saved in the PACA which allows us to restore
687 * our original state after RTAS returns.
690 std r6,PACASAVEDMSR(r13)
692 /* Setup our real return addr */
693 LOAD_REG_ADDR(r4,.rtas_return_loc)
694 clrldi r4,r4,2 /* convert to realmode address */
698 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
702 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
703 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP
706 sync /* disable interrupts so SRR0/1 */
707 mtmsrd r0 /* don't get trashed */
709 LOAD_REG_ADDR(r4, rtas)
710 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
711 ld r4,RTASBASE(r4) /* get the rtas->base value */
716 b . /* prevent speculative execution */
718 _STATIC(rtas_return_loc)
719 /* relocation is off at this point */
720 mfspr r4,SPRN_SPRG3 /* Get PACA */
721 clrldi r4,r4,2 /* convert to realmode address */
729 ld r1,PACAR1(r4) /* Restore our SP */
730 LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs)
731 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
736 b . /* prevent speculative execution */
738 _STATIC(rtas_restore_regs)
739 /* relocation is on at this point */
740 REST_GPR(2, r1) /* Restore the TOC */
741 REST_GPR(13, r1) /* Restore paca */
742 REST_8GPRS(14, r1) /* Restore the non-volatiles */
743 REST_10GPRS(22, r1) /* ditto */
762 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
763 ld r0,16(r1) /* get return address */
766 blr /* return to caller */
768 #endif /* CONFIG_PPC_RTAS */
770 #ifdef CONFIG_PPC_MULTIPLATFORM
775 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
777 /* Because PROM is running in 32b mode, it clobbers the high order half
778 * of all registers that it saves. We therefore save those registers
779 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
802 /* Get the PROM entrypoint */
806 /* Switch MSR to 32 bits mode
810 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
813 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
818 /* Restore arguments & enter PROM here... */
822 /* Just make sure that r1 top 32 bits didn't get
827 /* Restore the MSR (back to 64 bits) */
832 /* Restore other registers */
852 addi r1,r1,PROM_FRAME_SIZE
857 #endif /* CONFIG_PPC_MULTIPLATFORM */