1 #ifndef OXYGEN_REGS_H_INCLUDED
2 #define OXYGEN_REGS_H_INCLUDED
4 /* recording channel A */
5 #define OXYGEN_DMA_A_ADDRESS 0x00 /* 32-bit base address */
6 #define OXYGEN_DMA_A_COUNT 0x04 /* buffer counter (dwords) */
7 #define OXYGEN_DMA_A_TCOUNT 0x06 /* interrupt counter (dwords) */
9 /* recording channel B */
10 #define OXYGEN_DMA_B_ADDRESS 0x08
11 #define OXYGEN_DMA_B_COUNT 0x0c
12 #define OXYGEN_DMA_B_TCOUNT 0x0e
14 /* recording channel C */
15 #define OXYGEN_DMA_C_ADDRESS 0x10
16 #define OXYGEN_DMA_C_COUNT 0x14
17 #define OXYGEN_DMA_C_TCOUNT 0x16
19 /* SPDIF playback channel */
20 #define OXYGEN_DMA_SPDIF_ADDRESS 0x18
21 #define OXYGEN_DMA_SPDIF_COUNT 0x1c
22 #define OXYGEN_DMA_SPDIF_TCOUNT 0x1e
24 /* multichannel playback channel */
25 #define OXYGEN_DMA_MULTICH_ADDRESS 0x20
26 #define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 32 bits */
27 #define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 32 bits */
29 /* AC'97 (front panel) playback channel */
30 #define OXYGEN_DMA_AC97_ADDRESS 0x30
31 #define OXYGEN_DMA_AC97_COUNT 0x34
32 #define OXYGEN_DMA_AC97_TCOUNT 0x36
34 /* all registers 0x00..0x36 return current position on read */
36 #define OXYGEN_DMA_STATUS 0x40 /* 1 = running, 0 = stop */
37 #define OXYGEN_CHANNEL_A 0x01
38 #define OXYGEN_CHANNEL_B 0x02
39 #define OXYGEN_CHANNEL_C 0x04
40 #define OXYGEN_CHANNEL_SPDIF 0x08
41 #define OXYGEN_CHANNEL_MULTICH 0x10
42 #define OXYGEN_CHANNEL_AC97 0x20
44 #define OXYGEN_DMA_RESET 0x42
45 /* OXYGEN_CHANNEL_* */
47 #define OXYGEN_PLAY_CHANNELS 0x43
48 #define OXYGEN_PLAY_CHANNELS_MASK 0x03
49 #define OXYGEN_PLAY_CHANNELS_2 0x00
50 #define OXYGEN_PLAY_CHANNELS_4 0x01
51 #define OXYGEN_PLAY_CHANNELS_6 0x02
52 #define OXYGEN_PLAY_CHANNELS_8 0x03
54 #define OXYGEN_INTERRUPT_MASK 0x44
55 /* OXYGEN_CHANNEL_* */
56 #define OXYGEN_INT_SPDIF_IN_CHANGE 0x0100
57 #define OXYGEN_INT_GPIO 0x0800
59 #define OXYGEN_INTERRUPT_STATUS 0x46
60 /* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */
61 #define OXYGEN_INT_MIDI 0x1000
63 #define OXYGEN_MISC 0x48
64 #define OXYGEN_MISC_MAGIC 0x20
65 #define OXYGEN_MISC_MIDI 0x40
67 #define OXYGEN_REC_FORMAT 0x4a
68 #define OXYGEN_REC_FORMAT_A_MASK 0x03
69 #define OXYGEN_REC_FORMAT_A_SHIFT 0
70 #define OXYGEN_REC_FORMAT_B_MASK 0x0c
71 #define OXYGEN_REC_FORMAT_B_SHIFT 2
72 #define OXYGEN_REC_FORMAT_C_MASK 0x30
73 #define OXYGEN_REC_FORMAT_C_SHIFT 4
74 #define OXYGEN_FORMAT_16 0x00
75 #define OXYGEN_FORMAT_24 0x01
76 #define OXYGEN_FORMAT_32 0x02
78 #define OXYGEN_PLAY_FORMAT 0x4b
79 #define OXYGEN_SPDIF_FORMAT_MASK 0x03
80 #define OXYGEN_SPDIF_FORMAT_SHIFT 0
81 #define OXYGEN_MULTICH_FORMAT_MASK 0x0c
82 #define OXYGEN_MULTICH_FORMAT_SHIFT 2
83 #define OXYGEN_AC97_FORMAT_MASK 0x30
84 #define OXYGEN_AC97_FORMAT_SHIFT 4
87 #define OXYGEN_REC_CHANNELS 0x4c
88 #define OXYGEN_REC_A_CHANNELS_MASK 0x07
89 #define OXYGEN_REC_CHANNELS_2 0x00
90 #define OXYGEN_REC_CHANNELS_4 0x01
91 #define OXYGEN_REC_CHANNELS_6 0x03 /* or 0x02 */
92 #define OXYGEN_REC_CHANNELS_8 0x04
94 #define OXYGEN_FUNCTION 0x50
95 #define OXYGEN_FUNCTION_RESET_CODEC 0x02
96 #define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80
98 #define OXYGEN_I2S_MULTICH_FORMAT 0x60
99 #define OXYGEN_I2S_RATE_MASK 0x0007
100 #define OXYGEN_RATE_32000 0x0000
101 #define OXYGEN_RATE_44100 0x0001
102 #define OXYGEN_RATE_48000 0x0002
103 #define OXYGEN_RATE_64000 0x0003
104 #define OXYGEN_RATE_88200 0x0004
105 #define OXYGEN_RATE_96000 0x0005
106 #define OXYGEN_RATE_176400 0x0006
107 #define OXYGEN_RATE_192000 0x0007
108 #define OXYGEN_I2S_MAGIC1_MASK 0x0008
109 #define OXYGEN_I2S_MAGIC2_MASK 0x0030
110 #define OXYGEN_I2S_FORMAT_MASK 0x00c0
111 #define OXYGEN_I2S_FORMAT_16 0x0000
112 #define OXYGEN_I2S_FORMAT_20 0x0040
113 #define OXYGEN_I2S_FORMAT_24 0x0080
114 #define OXYGEN_I2S_FORMAT_32 0x00c0
116 #define OXYGEN_I2S_A_FORMAT 0x62
117 #define OXYGEN_I2S_B_FORMAT 0x64
118 #define OXYGEN_I2S_C_FORMAT 0x66
119 /* OXYGEN_I2S_RATE_* and OXYGEN_I2S_FORMAT_* */
121 #define OXYGEN_SPDIF_CONTROL 0x70
122 #define OXYGEN_SPDIF_OUT_ENABLE 0x00000002
123 #define OXYGEN_SPDIF_LOOPBACK 0x00000004
124 #define OXYGEN_SPDIF_MAGIC2 0x00000020
125 #define OXYGEN_SPDIF_MAGIC3 0x00000040
126 #define OXYGEN_SPDIF_IN_VALID 0x00001000
127 #define OXYGEN_SPDIF_IN_CHANGE 0x00008000 /* r/wc */
128 #define OXYGEN_SPDIF_IN_INVERT 0x00010000 /* ? */
129 #define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000
130 #define OXYGEN_SPDIF_OUT_RATE_SHIFT 24
131 /* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */
133 #define OXYGEN_SPDIF_OUTPUT_BITS 0x74
134 #define OXYGEN_SPDIF_NONAUDIO 0x00000002
135 #define OXYGEN_SPDIF_C 0x00000004
136 #define OXYGEN_SPDIF_PREEMPHASIS 0x00000008
137 #define OXYGEN_SPDIF_CATEGORY_MASK 0x000007f0
138 #define OXYGEN_SPDIF_CATEGORY_SHIFT 4
139 #define OXYGEN_SPDIF_ORIGINAL 0x00000800
140 #define OXYGEN_SPDIF_CS_RATE_MASK 0x0000f000
141 #define OXYGEN_SPDIF_CS_RATE_SHIFT 12
142 #define OXYGEN_SPDIF_V 0x00010000 /* 0 = valid */
144 #define OXYGEN_SPDIF_INPUT_BITS 0x78
145 /* 32 bits, IEC958_AES_* */
147 #define OXYGEN_2WIRE_CONTROL 0x90
148 #define OXYGEN_2WIRE_DIR_MASK 0x01
149 #define OXYGEN_2WIRE_DIR_WRITE 0x00 /* ? */
150 #define OXYGEN_2WIRE_DIR_READ 0x01 /* ? */
151 #define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */
152 #define OXYGEN_2WIRE_ADDRESS_SHIFT 1
154 #define OXYGEN_2WIRE_MAP 0x91 /* address, 8 bits */
155 #define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */
157 #define OXYGEN_2WIRE_BUS_STATUS 0x94
158 #define OXYGEN_2WIRE_BUSY 0x01
160 #define OXYGEN_SPI_CONTROL 0x98
161 #define OXYGEN_SPI_BUSY 0x01 /* read */
162 #define OXYGEN_SPI_TRIGGER_WRITE 0x01 /* write */
163 #define OXYGEN_SPI_DATA_LENGTH_MASK 0x02
164 #define OXYGEN_SPI_DATA_LENGTH_2 0x00
165 #define OXYGEN_SPI_DATA_LENGTH_3 0x02
166 #define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */
167 #define OXYGEN_SPI_CODEC_SHIFT 4
168 #define OXYGEN_SPI_MAGIC 0x80
170 #define OXYGEN_SPI_DATA1 0x99
171 #define OXYGEN_SPI_DATA2 0x9a
172 #define OXYGEN_SPI_DATA3 0x9b
174 #define OXYGEN_MPU401 0xa0
176 #define OXYGEN_GPI_DATA 0xa4
178 #define OXYGEN_GPI_INTERRUPT_MASK 0xa5
180 #define OXYGEN_GPIO_DATA 0xa6
182 #define OXYGEN_GPIO_CONTROL 0xa8
183 /* 0: input, 1: output */
185 #define OXYGEN_GPIO_INTERRUPT_MASK 0xaa
187 #define OXYGEN_DEVICE_SENSE 0xac /* ? */
189 #define OXYGEN_PLAY_ROUTING 0xc0
190 #define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300
191 #define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0700
192 #define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000
193 #define OXYGEN_PLAY_DAC3_SOURCE_MASK 0x7000
195 #define OXYGEN_REC_ROUTING 0xc2
197 #define OXYGEN_ADC_MONITOR 0xc3
198 #define OXYGEN_ADC_MONITOR_MULTICH 0x01
199 #define OXYGEN_ADC_MONITOR_AC97 0x04
200 #define OXYGEN_ADC_MONITOR_SPDIF 0x10
202 #define OXYGEN_A_MONITOR_ROUTING 0xc4
204 #define OXYGEN_AC97_CONTROL 0xd0
205 #define OXYGEN_AC97_RESET1 0x0001
206 #define OXYGEN_AC97_RESET1_BUSY 0x0002
207 #define OXYGEN_AC97_RESET2 0x0008
208 #define OXYGEN_AC97_CODEC_0 0x0010
209 #define OXYGEN_AC97_CODEC_1 0x0020
211 #define OXYGEN_AC97_INTERRUPT_MASK 0xd2
213 #define OXYGEN_AC97_INTERRUPT_STATUS 0xd3
214 #define OXYGEN_AC97_READ_COMPLETE 0x01
215 #define OXYGEN_AC97_WRITE_COMPLETE 0x02
217 #define OXYGEN_AC97_OUT_CONFIG 0xd4
218 #define OXYGEN_AC97_OUT_MAGIC1 0x00000011
219 #define OXYGEN_AC97_OUT_MAGIC2 0x00000033
220 #define OXYGEN_AC97_OUT_MAGIC3 0x0000ff00
222 #define OXYGEN_AC97_IN_CONFIG 0xd8
223 #define OXYGEN_AC97_IN_MAGIC1 0x00000011
224 #define OXYGEN_AC97_IN_MAGIC2 0x00000033
225 #define OXYGEN_AC97_IN_MAGIC3 0x00000300
227 #define OXYGEN_AC97_REGS 0xdc
228 #define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff
229 #define OXYGEN_AC97_REG_ADDR_MASK 0x007f0000
230 #define OXYGEN_AC97_REG_ADDR_SHIFT 16
231 #define OXYGEN_AC97_REG_DIR_MASK 0x00800000
232 #define OXYGEN_AC97_REG_DIR_WRITE 0x00000000
233 #define OXYGEN_AC97_REG_DIR_READ 0x00800000
234 #define OXYGEN_AC97_REG_CODEC_MASK 0x01000000
235 #define OXYGEN_AC97_REG_CODEC_SHIFT 24
237 #define OXYGEN_DMA_FLUSH 0xe1
238 /* OXYGEN_CHANNEL_* */
240 #define OXYGEN_CODEC_VERSION 0xe4
242 #define OXYGEN_REVISION 0xe6
243 #define OXYGEN_REVISION_2 0x08 /* bit flag */
244 #define OXYGEN_REVISION_8787 0x14 /* all 8 bits */