Merge branch 'topic/cleanup' into for-linus
[linux-2.6] / drivers / infiniband / hw / ipath / ipath_iba7220.c
1 /*
2  * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33 /*
34  * This file contains all of the code that is specific to the
35  * InfiniPath 7220 chip (except that specific to the SerDes)
36  */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <rdma/ib_verbs.h>
43
44 #include "ipath_kernel.h"
45 #include "ipath_registers.h"
46 #include "ipath_7220.h"
47
48 static void ipath_setup_7220_setextled(struct ipath_devdata *, u64, u64);
49
50 static unsigned ipath_compat_ddr_negotiate = 1;
51
52 module_param_named(compat_ddr_negotiate, ipath_compat_ddr_negotiate, uint,
53                         S_IWUSR | S_IRUGO);
54 MODULE_PARM_DESC(compat_ddr_negotiate,
55                 "Attempt pre-IBTA 1.2 DDR speed negotiation");
56
57 static unsigned ipath_sdma_fetch_arb = 1;
58 module_param_named(fetch_arb, ipath_sdma_fetch_arb, uint, S_IRUGO);
59 MODULE_PARM_DESC(fetch_arb, "IBA7220: change SDMA descriptor arbitration");
60
61 /*
62  * This file contains almost all the chip-specific register information and
63  * access functions for the QLogic InfiniPath 7220 PCI-Express chip, with the
64  * exception of SerDes support, which in in ipath_sd7220.c.
65  *
66  * This lists the InfiniPath registers, in the actual chip layout.
67  * This structure should never be directly accessed.
68  */
69 struct _infinipath_do_not_use_kernel_regs {
70         unsigned long long Revision;
71         unsigned long long Control;
72         unsigned long long PageAlign;
73         unsigned long long PortCnt;
74         unsigned long long DebugPortSelect;
75         unsigned long long DebugSigsIntSel; /* was Reserved0;*/
76         unsigned long long SendRegBase;
77         unsigned long long UserRegBase;
78         unsigned long long CounterRegBase;
79         unsigned long long Scratch;
80         unsigned long long EEPROMAddrCmd; /* was Reserved1; */
81         unsigned long long EEPROMData; /* was Reserved2; */
82         unsigned long long IntBlocked;
83         unsigned long long IntMask;
84         unsigned long long IntStatus;
85         unsigned long long IntClear;
86         unsigned long long ErrorMask;
87         unsigned long long ErrorStatus;
88         unsigned long long ErrorClear;
89         unsigned long long HwErrMask;
90         unsigned long long HwErrStatus;
91         unsigned long long HwErrClear;
92         unsigned long long HwDiagCtrl;
93         unsigned long long MDIO;
94         unsigned long long IBCStatus;
95         unsigned long long IBCCtrl;
96         unsigned long long ExtStatus;
97         unsigned long long ExtCtrl;
98         unsigned long long GPIOOut;
99         unsigned long long GPIOMask;
100         unsigned long long GPIOStatus;
101         unsigned long long GPIOClear;
102         unsigned long long RcvCtrl;
103         unsigned long long RcvBTHQP;
104         unsigned long long RcvHdrSize;
105         unsigned long long RcvHdrCnt;
106         unsigned long long RcvHdrEntSize;
107         unsigned long long RcvTIDBase;
108         unsigned long long RcvTIDCnt;
109         unsigned long long RcvEgrBase;
110         unsigned long long RcvEgrCnt;
111         unsigned long long RcvBufBase;
112         unsigned long long RcvBufSize;
113         unsigned long long RxIntMemBase;
114         unsigned long long RxIntMemSize;
115         unsigned long long RcvPartitionKey;
116         unsigned long long RcvQPMulticastPort;
117         unsigned long long RcvPktLEDCnt;
118         unsigned long long IBCDDRCtrl;
119         unsigned long long HRTBT_GUID;
120         unsigned long long IB_SDTEST_IF_TX;
121         unsigned long long IB_SDTEST_IF_RX;
122         unsigned long long IBCDDRCtrl2;
123         unsigned long long IBCDDRStatus;
124         unsigned long long JIntReload;
125         unsigned long long IBNCModeCtrl;
126         unsigned long long SendCtrl;
127         unsigned long long SendBufBase;
128         unsigned long long SendBufSize;
129         unsigned long long SendBufCnt;
130         unsigned long long SendAvailAddr;
131         unsigned long long TxIntMemBase;
132         unsigned long long TxIntMemSize;
133         unsigned long long SendDmaBase;
134         unsigned long long SendDmaLenGen;
135         unsigned long long SendDmaTail;
136         unsigned long long SendDmaHead;
137         unsigned long long SendDmaHeadAddr;
138         unsigned long long SendDmaBufMask0;
139         unsigned long long SendDmaBufMask1;
140         unsigned long long SendDmaBufMask2;
141         unsigned long long SendDmaStatus;
142         unsigned long long SendBufferError;
143         unsigned long long SendBufferErrorCONT1;
144         unsigned long long SendBufErr2; /* was Reserved6SBE[0/6] */
145         unsigned long long Reserved6L[2];
146         unsigned long long AvailUpdCount;
147         unsigned long long RcvHdrAddr0;
148         unsigned long long RcvHdrAddrs[16]; /* Why enumerate? */
149         unsigned long long Reserved7hdtl; /* Align next to 300 */
150         unsigned long long RcvHdrTailAddr0; /* 300, like others */
151         unsigned long long RcvHdrTailAddrs[16];
152         unsigned long long Reserved9SW[7]; /* was [8]; we have 17 ports */
153         unsigned long long IbsdEpbAccCtl; /* IB Serdes EPB access control */
154         unsigned long long IbsdEpbTransReg; /* IB Serdes EPB Transaction */
155         unsigned long long Reserved10sds; /* was SerdesStatus on */
156         unsigned long long XGXSConfig;
157         unsigned long long IBSerDesCtrl; /* Was IBPLLCfg on Monty */
158         unsigned long long EEPCtlStat; /* for "boot" EEPROM/FLASH */
159         unsigned long long EEPAddrCmd;
160         unsigned long long EEPData;
161         unsigned long long PcieEpbAccCtl;
162         unsigned long long PcieEpbTransCtl;
163         unsigned long long EfuseCtl; /* E-Fuse control */
164         unsigned long long EfuseData[4];
165         unsigned long long ProcMon;
166         /* this chip moves following two from previous 200, 208 */
167         unsigned long long PCIeRBufTestReg0;
168         unsigned long long PCIeRBufTestReg1;
169         /* added for this chip */
170         unsigned long long PCIeRBufTestReg2;
171         unsigned long long PCIeRBufTestReg3;
172         /* added for this chip, debug only */
173         unsigned long long SPC_JTAG_ACCESS_REG;
174         unsigned long long LAControlReg;
175         unsigned long long GPIODebugSelReg;
176         unsigned long long DebugPortValueReg;
177         /* added for this chip, DMA */
178         unsigned long long SendDmaBufUsed[3];
179         unsigned long long SendDmaReqTagUsed;
180         /*
181          * added for this chip, EFUSE: note that these program 64-bit
182          * words 2 and 3 */
183         unsigned long long efuse_pgm_data[2];
184         unsigned long long Reserved11LAalign[10]; /* Skip 4B0..4F8 */
185         /* we have 30 regs for DDS and RXEQ in IB SERDES */
186         unsigned long long SerDesDDSRXEQ[30];
187         unsigned long long Reserved12LAalign[2]; /* Skip 5F0, 5F8 */
188         /* added for LA debug support */
189         unsigned long long LAMemory[32];
190 };
191
192 struct _infinipath_do_not_use_counters {
193         __u64 LBIntCnt;
194         __u64 LBFlowStallCnt;
195         __u64 TxSDmaDescCnt;    /* was Reserved1 */
196         __u64 TxUnsupVLErrCnt;
197         __u64 TxDataPktCnt;
198         __u64 TxFlowPktCnt;
199         __u64 TxDwordCnt;
200         __u64 TxLenErrCnt;
201         __u64 TxMaxMinLenErrCnt;
202         __u64 TxUnderrunCnt;
203         __u64 TxFlowStallCnt;
204         __u64 TxDroppedPktCnt;
205         __u64 RxDroppedPktCnt;
206         __u64 RxDataPktCnt;
207         __u64 RxFlowPktCnt;
208         __u64 RxDwordCnt;
209         __u64 RxLenErrCnt;
210         __u64 RxMaxMinLenErrCnt;
211         __u64 RxICRCErrCnt;
212         __u64 RxVCRCErrCnt;
213         __u64 RxFlowCtrlErrCnt;
214         __u64 RxBadFormatCnt;
215         __u64 RxLinkProblemCnt;
216         __u64 RxEBPCnt;
217         __u64 RxLPCRCErrCnt;
218         __u64 RxBufOvflCnt;
219         __u64 RxTIDFullErrCnt;
220         __u64 RxTIDValidErrCnt;
221         __u64 RxPKeyMismatchCnt;
222         __u64 RxP0HdrEgrOvflCnt;
223         __u64 RxP1HdrEgrOvflCnt;
224         __u64 RxP2HdrEgrOvflCnt;
225         __u64 RxP3HdrEgrOvflCnt;
226         __u64 RxP4HdrEgrOvflCnt;
227         __u64 RxP5HdrEgrOvflCnt;
228         __u64 RxP6HdrEgrOvflCnt;
229         __u64 RxP7HdrEgrOvflCnt;
230         __u64 RxP8HdrEgrOvflCnt;
231         __u64 RxP9HdrEgrOvflCnt;        /* was Reserved6 */
232         __u64 RxP10HdrEgrOvflCnt;       /* was Reserved7 */
233         __u64 RxP11HdrEgrOvflCnt;       /* new for IBA7220 */
234         __u64 RxP12HdrEgrOvflCnt;       /* new for IBA7220 */
235         __u64 RxP13HdrEgrOvflCnt;       /* new for IBA7220 */
236         __u64 RxP14HdrEgrOvflCnt;       /* new for IBA7220 */
237         __u64 RxP15HdrEgrOvflCnt;       /* new for IBA7220 */
238         __u64 RxP16HdrEgrOvflCnt;       /* new for IBA7220 */
239         __u64 IBStatusChangeCnt;
240         __u64 IBLinkErrRecoveryCnt;
241         __u64 IBLinkDownedCnt;
242         __u64 IBSymbolErrCnt;
243         /* The following are new for IBA7220 */
244         __u64 RxVL15DroppedPktCnt;
245         __u64 RxOtherLocalPhyErrCnt;
246         __u64 PcieRetryBufDiagQwordCnt;
247         __u64 ExcessBufferOvflCnt;
248         __u64 LocalLinkIntegrityErrCnt;
249         __u64 RxVlErrCnt;
250         __u64 RxDlidFltrCnt;
251         __u64 Reserved8[7];
252         __u64 PSStat;
253         __u64 PSStart;
254         __u64 PSInterval;
255         __u64 PSRcvDataCount;
256         __u64 PSRcvPktsCount;
257         __u64 PSXmitDataCount;
258         __u64 PSXmitPktsCount;
259         __u64 PSXmitWaitCount;
260 };
261
262 #define IPATH_KREG_OFFSET(field) (offsetof( \
263         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
264 #define IPATH_CREG_OFFSET(field) (offsetof( \
265         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
266
267 static const struct ipath_kregs ipath_7220_kregs = {
268         .kr_control = IPATH_KREG_OFFSET(Control),
269         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
270         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
271         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
272         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
273         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
274         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
275         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
276         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
277         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
278         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
279         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
280         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
281         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
282         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
283         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
284         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
285         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
286         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
287         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
288         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
289         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
290         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
291         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
292         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
293         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
294         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
295         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
296         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
297         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
298         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
299         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
300         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
301         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
302         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
303         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
304         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
305         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
306         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
307         .kr_revision = IPATH_KREG_OFFSET(Revision),
308         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
309         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
310         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
311         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendAvailAddr),
312         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendBufBase),
313         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendBufCnt),
314         .kr_sendpiosize = IPATH_KREG_OFFSET(SendBufSize),
315         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
316         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
317         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
318         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
319
320         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
321
322         /* send dma related regs */
323         .kr_senddmabase = IPATH_KREG_OFFSET(SendDmaBase),
324         .kr_senddmalengen = IPATH_KREG_OFFSET(SendDmaLenGen),
325         .kr_senddmatail = IPATH_KREG_OFFSET(SendDmaTail),
326         .kr_senddmahead = IPATH_KREG_OFFSET(SendDmaHead),
327         .kr_senddmaheadaddr = IPATH_KREG_OFFSET(SendDmaHeadAddr),
328         .kr_senddmabufmask0 = IPATH_KREG_OFFSET(SendDmaBufMask0),
329         .kr_senddmabufmask1 = IPATH_KREG_OFFSET(SendDmaBufMask1),
330         .kr_senddmabufmask2 = IPATH_KREG_OFFSET(SendDmaBufMask2),
331         .kr_senddmastatus = IPATH_KREG_OFFSET(SendDmaStatus),
332
333         /* SerDes related regs */
334         .kr_ibserdesctrl = IPATH_KREG_OFFSET(IBSerDesCtrl),
335         .kr_ib_epbacc = IPATH_KREG_OFFSET(IbsdEpbAccCtl),
336         .kr_ib_epbtrans = IPATH_KREG_OFFSET(IbsdEpbTransReg),
337         .kr_pcie_epbacc = IPATH_KREG_OFFSET(PcieEpbAccCtl),
338         .kr_pcie_epbtrans = IPATH_KREG_OFFSET(PcieEpbTransCtl),
339         .kr_ib_ddsrxeq = IPATH_KREG_OFFSET(SerDesDDSRXEQ),
340
341         /*
342          * These should not be used directly via ipath_read_kreg64(),
343          * use them with ipath_read_kreg64_port()
344          */
345         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
346         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
347
348         /*
349          * The rcvpktled register controls one of the debug port signals, so
350          * a packet activity LED can be connected to it.
351          */
352         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
353         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
354         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
355
356         .kr_hrtbt_guid = IPATH_KREG_OFFSET(HRTBT_GUID),
357         .kr_ibcddrctrl = IPATH_KREG_OFFSET(IBCDDRCtrl),
358         .kr_ibcddrstatus = IPATH_KREG_OFFSET(IBCDDRStatus),
359         .kr_jintreload = IPATH_KREG_OFFSET(JIntReload)
360 };
361
362 static const struct ipath_cregs ipath_7220_cregs = {
363         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
364         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
365         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
366         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
367         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
368         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
369         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
370         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
371         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
372         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
373         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
374         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
375         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
376         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
377         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
378         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
379         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
380         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
381         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
382         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
383         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
384         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
385         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
386         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
387         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
388         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
389         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
390         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
391         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
392         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
393         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
394         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
395         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt),
396         .cr_vl15droppedpktcnt = IPATH_CREG_OFFSET(RxVL15DroppedPktCnt),
397         .cr_rxotherlocalphyerrcnt =
398                 IPATH_CREG_OFFSET(RxOtherLocalPhyErrCnt),
399         .cr_excessbufferovflcnt = IPATH_CREG_OFFSET(ExcessBufferOvflCnt),
400         .cr_locallinkintegrityerrcnt =
401                 IPATH_CREG_OFFSET(LocalLinkIntegrityErrCnt),
402         .cr_rxvlerrcnt = IPATH_CREG_OFFSET(RxVlErrCnt),
403         .cr_rxdlidfltrcnt = IPATH_CREG_OFFSET(RxDlidFltrCnt),
404         .cr_psstat = IPATH_CREG_OFFSET(PSStat),
405         .cr_psstart = IPATH_CREG_OFFSET(PSStart),
406         .cr_psinterval = IPATH_CREG_OFFSET(PSInterval),
407         .cr_psrcvdatacount = IPATH_CREG_OFFSET(PSRcvDataCount),
408         .cr_psrcvpktscount = IPATH_CREG_OFFSET(PSRcvPktsCount),
409         .cr_psxmitdatacount = IPATH_CREG_OFFSET(PSXmitDataCount),
410         .cr_psxmitpktscount = IPATH_CREG_OFFSET(PSXmitPktsCount),
411         .cr_psxmitwaitcount = IPATH_CREG_OFFSET(PSXmitWaitCount),
412 };
413
414 /* kr_control bits */
415 #define INFINIPATH_C_RESET (1U<<7)
416
417 /* kr_intstatus, kr_intclear, kr_intmask bits */
418 #define INFINIPATH_I_RCVURG_MASK ((1ULL<<17)-1)
419 #define INFINIPATH_I_RCVURG_SHIFT 32
420 #define INFINIPATH_I_RCVAVAIL_MASK ((1ULL<<17)-1)
421 #define INFINIPATH_I_RCVAVAIL_SHIFT 0
422 #define INFINIPATH_I_SERDESTRIMDONE (1ULL<<27)
423
424 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
425 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x00000000000000ffULL
426 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
427 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
428 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
429 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
430 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
431 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
432 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
433 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
434 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
435 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
436 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
437 /* specific to this chip */
438 #define INFINIPATH_HWE_PCIECPLDATAQUEUEERR         0x0000000000000040ULL
439 #define INFINIPATH_HWE_PCIECPLHDRQUEUEERR          0x0000000000000080ULL
440 #define INFINIPATH_HWE_SDMAMEMREADERR              0x0000000010000000ULL
441 #define INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED         0x2000000000000000ULL
442 #define INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT   0x0100000000000000ULL
443 #define INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT   0x0200000000000000ULL
444 #define INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT   0x0400000000000000ULL
445 #define INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT   0x0800000000000000ULL
446 #define INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR      0x0000008000000000ULL
447 #define INFINIPATH_HWE_IB_UC_MEMORYPARITYERR       0x0000004000000000ULL
448 #define INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
449 #define INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
450
451 #define IBA7220_IBCS_LINKTRAININGSTATE_MASK 0x1F
452 #define IBA7220_IBCS_LINKSTATE_SHIFT 5
453 #define IBA7220_IBCS_LINKSPEED_SHIFT 8
454 #define IBA7220_IBCS_LINKWIDTH_SHIFT 9
455
456 #define IBA7220_IBCC_LINKINITCMD_MASK 0x7ULL
457 #define IBA7220_IBCC_LINKCMD_SHIFT 19
458 #define IBA7220_IBCC_MAXPKTLEN_SHIFT 21
459
460 /* kr_ibcddrctrl bits */
461 #define IBA7220_IBC_DLIDLMC_MASK        0xFFFFFFFFUL
462 #define IBA7220_IBC_DLIDLMC_SHIFT       32
463 #define IBA7220_IBC_HRTBT_MASK  3
464 #define IBA7220_IBC_HRTBT_SHIFT 16
465 #define IBA7220_IBC_HRTBT_ENB   0x10000UL
466 #define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
467 #define IBA7220_IBC_LREV_MASK   1
468 #define IBA7220_IBC_LREV_SHIFT  8
469 #define IBA7220_IBC_RXPOL_MASK  1
470 #define IBA7220_IBC_RXPOL_SHIFT 7
471 #define IBA7220_IBC_WIDTH_SHIFT 5
472 #define IBA7220_IBC_WIDTH_MASK  0x3
473 #define IBA7220_IBC_WIDTH_1X_ONLY       (0<<IBA7220_IBC_WIDTH_SHIFT)
474 #define IBA7220_IBC_WIDTH_4X_ONLY       (1<<IBA7220_IBC_WIDTH_SHIFT)
475 #define IBA7220_IBC_WIDTH_AUTONEG       (2<<IBA7220_IBC_WIDTH_SHIFT)
476 #define IBA7220_IBC_SPEED_AUTONEG       (1<<1)
477 #define IBA7220_IBC_SPEED_SDR           (1<<2)
478 #define IBA7220_IBC_SPEED_DDR           (1<<3)
479 #define IBA7220_IBC_SPEED_AUTONEG_MASK  (0x7<<1)
480 #define IBA7220_IBC_IBTA_1_2_MASK       (1)
481
482 /* kr_ibcddrstatus */
483 /* link latency shift is 0, don't bother defining */
484 #define IBA7220_DDRSTAT_LINKLAT_MASK    0x3ffffff
485
486 /* kr_extstatus bits */
487 #define INFINIPATH_EXTS_FREQSEL 0x2
488 #define INFINIPATH_EXTS_SERDESSEL 0x4
489 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
490 #define INFINIPATH_EXTS_MEMBIST_DISABLED    0x0000000000008000
491
492 /* kr_xgxsconfig bits */
493 #define INFINIPATH_XGXS_RESET          0x5ULL
494 #define INFINIPATH_XGXS_FC_SAFE        (1ULL<<63)
495
496 /* kr_rcvpktledcnt */
497 #define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
498 #define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
499
500 #define _IPATH_GPIO_SDA_NUM 1
501 #define _IPATH_GPIO_SCL_NUM 0
502
503 #define IPATH_GPIO_SDA (1ULL << \
504         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
505 #define IPATH_GPIO_SCL (1ULL << \
506         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
507
508 #define IBA7220_R_INTRAVAIL_SHIFT 17
509 #define IBA7220_R_TAILUPD_SHIFT 35
510 #define IBA7220_R_PORTCFG_SHIFT 36
511
512 #define INFINIPATH_JINT_PACKETSHIFT 16
513 #define INFINIPATH_JINT_DEFAULT_IDLE_TICKS  0
514 #define INFINIPATH_JINT_DEFAULT_MAX_PACKETS 0
515
516 #define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
517
518 /*
519  * the size bits give us 2^N, in KB units.  0 marks as invalid,
520  * and 7 is reserved.  We currently use only 2KB and 4KB
521  */
522 #define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
523 #define IBA7220_TID_SZ_2K (1UL<<IBA7220_TID_SZ_SHIFT) /* 2KB */
524 #define IBA7220_TID_SZ_4K (2UL<<IBA7220_TID_SZ_SHIFT) /* 4KB */
525 #define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
526
527 #define IPATH_AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
528
529 static char int_type[16] = "auto";
530 module_param_string(interrupt_type, int_type, sizeof(int_type), 0444);
531 MODULE_PARM_DESC(int_type, " interrupt_type=auto|force_msi|force_intx");
532
533 /* packet rate matching delay; chip has support */
534 static u8 rate_to_delay[2][2] = {
535         /* 1x, 4x */
536         {   8, 2 }, /* SDR */
537         {   4, 1 }  /* DDR */
538 };
539
540 /* 7220 specific hardware errors... */
541 static const struct ipath_hwerror_msgs ipath_7220_hwerror_msgs[] = {
542         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
543         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
544         /*
545          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
546          * parity or memory parity error failures, because most likely we
547          * won't be able to talk to the core of the chip.  Nonetheless, we
548          * might see them, if they are in parts of the PCIe core that aren't
549          * essential.
550          */
551         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
552         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
553         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
554         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
555         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
556         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
557         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
558         INFINIPATH_HWE_MSG(PCIECPLDATAQUEUEERR, "PCIe cpl header queue"),
559         INFINIPATH_HWE_MSG(PCIECPLHDRQUEUEERR, "PCIe cpl data queue"),
560         INFINIPATH_HWE_MSG(SDMAMEMREADERR, "Send DMA memory read"),
561         INFINIPATH_HWE_MSG(CLK_UC_PLLNOTLOCKED, "uC PLL clock not locked"),
562         INFINIPATH_HWE_MSG(PCIESERDESQ0PCLKNOTDETECT,
563                 "PCIe serdes Q0 no clock"),
564         INFINIPATH_HWE_MSG(PCIESERDESQ1PCLKNOTDETECT,
565                 "PCIe serdes Q1 no clock"),
566         INFINIPATH_HWE_MSG(PCIESERDESQ2PCLKNOTDETECT,
567                 "PCIe serdes Q2 no clock"),
568         INFINIPATH_HWE_MSG(PCIESERDESQ3PCLKNOTDETECT,
569                 "PCIe serdes Q3 no clock"),
570         INFINIPATH_HWE_MSG(DDSRXEQMEMORYPARITYERR,
571                 "DDS RXEQ memory parity"),
572         INFINIPATH_HWE_MSG(IB_UC_MEMORYPARITYERR, "IB uC memory parity"),
573         INFINIPATH_HWE_MSG(PCIE_UC_OCT0MEMORYPARITYERR,
574                 "PCIe uC oct0 memory parity"),
575         INFINIPATH_HWE_MSG(PCIE_UC_OCT1MEMORYPARITYERR,
576                 "PCIe uC oct1 memory parity"),
577 };
578
579 static void autoneg_work(struct work_struct *);
580
581 /*
582  * the offset is different for different configured port numbers, since
583  * port0 is fixed in size, but others can vary.   Make it a function to
584  * make the issue more obvious.
585 */
586 static inline u32 port_egrtid_idx(struct ipath_devdata *dd, unsigned port)
587 {
588          return port ? dd->ipath_p0_rcvegrcnt +
589                  (port-1) * dd->ipath_rcvegrcnt : 0;
590 }
591
592 static void ipath_7220_txe_recover(struct ipath_devdata *dd)
593 {
594         ++ipath_stats.sps_txeparity;
595
596         dev_info(&dd->pcidev->dev,
597                 "Recovering from TXE PIO parity error\n");
598         ipath_disarm_senderrbufs(dd);
599 }
600
601
602 /**
603  * ipath_7220_handle_hwerrors - display hardware errors.
604  * @dd: the infinipath device
605  * @msg: the output buffer
606  * @msgl: the size of the output buffer
607  *
608  * Use same msg buffer as regular errors to avoid excessive stack
609  * use.  Most hardware errors are catastrophic, but for right now,
610  * we'll print them and continue.  We reuse the same message buffer as
611  * ipath_handle_errors() to avoid excessive stack usage.
612  */
613 static void ipath_7220_handle_hwerrors(struct ipath_devdata *dd, char *msg,
614                                        size_t msgl)
615 {
616         ipath_err_t hwerrs;
617         u32 bits, ctrl;
618         int isfatal = 0;
619         char bitsmsg[64];
620         int log_idx;
621
622         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
623         if (!hwerrs) {
624                 /*
625                  * better than printing cofusing messages
626                  * This seems to be related to clearing the crc error, or
627                  * the pll error during init.
628                  */
629                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
630                 goto bail;
631         } else if (hwerrs == ~0ULL) {
632                 ipath_dev_err(dd, "Read of hardware error status failed "
633                               "(all bits set); ignoring\n");
634                 goto bail;
635         }
636         ipath_stats.sps_hwerrs++;
637
638         /*
639          * Always clear the error status register, except MEMBISTFAIL,
640          * regardless of whether we continue or stop using the chip.
641          * We want that set so we know it failed, even across driver reload.
642          * We'll still ignore it in the hwerrmask.  We do this partly for
643          * diagnostics, but also for support.
644          */
645         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
646                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
647
648         hwerrs &= dd->ipath_hwerrmask;
649
650         /* We log some errors to EEPROM, check if we have any of those. */
651         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
652                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
653                         ipath_inc_eeprom_err(dd, log_idx, 1);
654         /*
655          * Make sure we get this much out, unless told to be quiet,
656          * or it's occurred within the last 5 seconds.
657          */
658         if ((hwerrs & ~(dd->ipath_lasthwerror |
659                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
660                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
661                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
662             (ipath_debug & __IPATH_VERBDBG))
663                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
664                          "(cleared)\n", (unsigned long long) hwerrs);
665         dd->ipath_lasthwerror |= hwerrs;
666
667         if (hwerrs & ~dd->ipath_hwe_bitsextant)
668                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
669                               "%llx set\n", (unsigned long long)
670                               (hwerrs & ~dd->ipath_hwe_bitsextant));
671
672         if (hwerrs & INFINIPATH_HWE_IB_UC_MEMORYPARITYERR)
673                 ipath_sd7220_clr_ibpar(dd);
674
675         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
676         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
677                 /*
678                  * Parity errors in send memory are recoverable by h/w
679                  * just do housekeeping, exit freeze mode and continue.
680                  */
681                 if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
682                                INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
683                               << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
684                         ipath_7220_txe_recover(dd);
685                         hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
686                                      INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
687                                     << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
688                 }
689                 if (hwerrs) {
690                         /*
691                          * If any set that we aren't ignoring only make the
692                          * complaint once, in case it's stuck or recurring,
693                          * and we get here multiple times
694                          * Force link down, so switch knows, and
695                          * LEDs are turned off.
696                          */
697                         if (dd->ipath_flags & IPATH_INITTED) {
698                                 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
699                                 ipath_setup_7220_setextled(dd,
700                                         INFINIPATH_IBCS_L_STATE_DOWN,
701                                         INFINIPATH_IBCS_LT_STATE_DISABLED);
702                                 ipath_dev_err(dd, "Fatal Hardware Error "
703                                               "(freeze mode), no longer"
704                                               " usable, SN %.16s\n",
705                                                   dd->ipath_serial);
706                                 isfatal = 1;
707                         }
708                         /*
709                          * Mark as having had an error for driver, and also
710                          * for /sys and status word mapped to user programs.
711                          * This marks unit as not usable, until reset.
712                          */
713                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
714                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
715                         dd->ipath_flags &= ~IPATH_INITTED;
716                 } else {
717                         ipath_dbg("Clearing freezemode on ignored or "
718                                 "recovered hardware error\n");
719                         ipath_clear_freeze(dd);
720                 }
721         }
722
723         *msg = '\0';
724
725         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
726                 strlcat(msg, "[Memory BIST test failed, "
727                         "InfiniPath hardware unusable]", msgl);
728                 /* ignore from now on, so disable until driver reloaded */
729                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
730                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
731                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
732                                  dd->ipath_hwerrmask);
733         }
734
735         ipath_format_hwerrors(hwerrs,
736                               ipath_7220_hwerror_msgs,
737                               ARRAY_SIZE(ipath_7220_hwerror_msgs),
738                               msg, msgl);
739
740         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
741                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
742                 bits = (u32) ((hwerrs >>
743                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
744                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
745                 snprintf(bitsmsg, sizeof bitsmsg,
746                          "[PCIe Mem Parity Errs %x] ", bits);
747                 strlcat(msg, bitsmsg, msgl);
748         }
749
750 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
751                          INFINIPATH_HWE_COREPLL_RFSLIP)
752
753         if (hwerrs & _IPATH_PLL_FAIL) {
754                 snprintf(bitsmsg, sizeof bitsmsg,
755                          "[PLL failed (%llx), InfiniPath hardware unusable]",
756                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
757                 strlcat(msg, bitsmsg, msgl);
758                 /* ignore from now on, so disable until driver reloaded */
759                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
760                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
761                                  dd->ipath_hwerrmask);
762         }
763
764         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
765                 /*
766                  * If it occurs, it is left masked since the eternal
767                  * interface is unused.
768                  */
769                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
770                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
771                                  dd->ipath_hwerrmask);
772         }
773
774         ipath_dev_err(dd, "%s hardware error\n", msg);
775         /*
776          * For /sys status file. if no trailing } is copied, we'll
777          * know it was truncated.
778          */
779         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
780                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
781                          "{%s}", msg);
782 bail:;
783 }
784
785 /**
786  * ipath_7220_boardname - fill in the board name
787  * @dd: the infinipath device
788  * @name: the output buffer
789  * @namelen: the size of the output buffer
790  *
791  * info is based on the board revision register
792  */
793 static int ipath_7220_boardname(struct ipath_devdata *dd, char *name,
794         size_t namelen)
795 {
796         char *n = NULL;
797         u8 boardrev = dd->ipath_boardrev;
798         int ret;
799
800         if (boardrev == 15) {
801                 /*
802                  * Emulator sometimes comes up all-ones, rather than zero.
803                  */
804                 boardrev = 0;
805                 dd->ipath_boardrev = boardrev;
806         }
807         switch (boardrev) {
808         case 0:
809                 n = "InfiniPath_7220_Emulation";
810                 break;
811         case 1:
812                 n = "InfiniPath_QLE7240";
813                 break;
814         case 2:
815                 n = "InfiniPath_QLE7280";
816                 break;
817         case 3:
818                 n = "InfiniPath_QLE7242";
819                 break;
820         case 4:
821                 n = "InfiniPath_QEM7240";
822                 break;
823         case 5:
824                 n = "InfiniPath_QMI7240";
825                 break;
826         case 6:
827                 n = "InfiniPath_QMI7264";
828                 break;
829         case 7:
830                 n = "InfiniPath_QMH7240";
831                 break;
832         case 8:
833                 n = "InfiniPath_QME7240";
834                 break;
835         case 9:
836                 n = "InfiniPath_QLE7250";
837                 break;
838         case 10:
839                 n = "InfiniPath_QLE7290";
840                 break;
841         case 11:
842                 n = "InfiniPath_QEM7250";
843                 break;
844         case 12:
845                 n = "InfiniPath_QLE-Bringup";
846                 break;
847         default:
848                 ipath_dev_err(dd,
849                               "Don't yet know about board with ID %u\n",
850                               boardrev);
851                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
852                          boardrev);
853                 break;
854         }
855         if (n)
856                 snprintf(name, namelen, "%s", n);
857
858         if (dd->ipath_majrev != 5 || !dd->ipath_minrev ||
859                 dd->ipath_minrev > 2) {
860                 ipath_dev_err(dd, "Unsupported InfiniPath hardware "
861                               "revision %u.%u!\n",
862                               dd->ipath_majrev, dd->ipath_minrev);
863                 ret = 1;
864         } else if (dd->ipath_minrev == 1 &&
865                 !(dd->ipath_flags & IPATH_INITTED)) {
866                 /* Rev1 chips are prototype. Complain at init, but allow use */
867                 ipath_dev_err(dd, "Unsupported hardware "
868                               "revision %u.%u, Contact support@qlogic.com\n",
869                               dd->ipath_majrev, dd->ipath_minrev);
870                 ret = 0;
871         } else
872                 ret = 0;
873
874         /*
875          * Set here not in ipath_init_*_funcs because we have to do
876          * it after we can read chip registers.
877          */
878         dd->ipath_ureg_align = 0x10000;  /* 64KB alignment */
879
880         return ret;
881 }
882
883 /**
884  * ipath_7220_init_hwerrors - enable hardware errors
885  * @dd: the infinipath device
886  *
887  * now that we have finished initializing everything that might reasonably
888  * cause a hardware error, and cleared those errors bits as they occur,
889  * we can enable hardware errors in the mask (potentially enabling
890  * freeze mode), and enable hardware errors as errors (along with
891  * everything else) in errormask
892  */
893 static void ipath_7220_init_hwerrors(struct ipath_devdata *dd)
894 {
895         ipath_err_t val;
896         u64 extsval;
897
898         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
899
900         if (!(extsval & (INFINIPATH_EXTS_MEMBIST_ENDTEST |
901                         INFINIPATH_EXTS_MEMBIST_DISABLED)))
902                 ipath_dev_err(dd, "MemBIST did not complete!\n");
903         if (extsval & INFINIPATH_EXTS_MEMBIST_DISABLED)
904                 dev_info(&dd->pcidev->dev, "MemBIST is disabled.\n");
905
906         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
907
908         if (!dd->ipath_boardrev)        /* no PLL for Emulator */
909                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
910
911         if (dd->ipath_minrev == 1)
912                 val &= ~(1ULL << 42); /* TXE LaunchFIFO Parity rev1 issue */
913
914         val &= ~INFINIPATH_HWE_IB_UC_MEMORYPARITYERR;
915         dd->ipath_hwerrmask = val;
916
917         /*
918          * special trigger "error" is for debugging purposes. It
919          * works around a processor/chipset problem.  The error
920          * interrupt allows us to count occurrences, but we don't
921          * want to pay the overhead for normal use.  Emulation only
922          */
923         if (!dd->ipath_boardrev)
924                 dd->ipath_maskederrs = INFINIPATH_E_SENDSPECIALTRIGGER;
925 }
926
927 /*
928  * All detailed interaction with the SerDes has been moved to ipath_sd7220.c
929  *
930  * The portion of IBA7220-specific bringup_serdes() that actually deals with
931  * registers and memory within the SerDes itself is ipath_sd7220_init().
932  */
933
934 /**
935  * ipath_7220_bringup_serdes - bring up the serdes
936  * @dd: the infinipath device
937  */
938 static int ipath_7220_bringup_serdes(struct ipath_devdata *dd)
939 {
940         int ret = 0;
941         u64 val, prev_val, guid;
942         int was_reset;          /* Note whether uC was reset */
943
944         ipath_dbg("Trying to bringup serdes\n");
945
946         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
947             INFINIPATH_HWE_SERDESPLLFAILED) {
948                 ipath_dbg("At start, serdes PLL failed bit set "
949                           "in hwerrstatus, clearing and continuing\n");
950                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
951                                  INFINIPATH_HWE_SERDESPLLFAILED);
952         }
953
954         dd->ibdeltainprog = 1;
955         dd->ibsymsnap =
956              ipath_read_creg32(dd, dd->ipath_cregs->cr_ibsymbolerrcnt);
957         dd->iblnkerrsnap =
958              ipath_read_creg32(dd, dd->ipath_cregs->cr_iblinkerrrecovcnt);
959
960         if (!dd->ipath_ibcddrctrl) {
961                 /* not on re-init after reset */
962                 dd->ipath_ibcddrctrl =
963                         ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrctrl);
964
965                 if (dd->ipath_link_speed_enabled ==
966                         (IPATH_IB_SDR | IPATH_IB_DDR))
967                         dd->ipath_ibcddrctrl |=
968                                 IBA7220_IBC_SPEED_AUTONEG_MASK |
969                                 IBA7220_IBC_IBTA_1_2_MASK;
970                 else
971                         dd->ipath_ibcddrctrl |=
972                                 dd->ipath_link_speed_enabled == IPATH_IB_DDR
973                                 ?  IBA7220_IBC_SPEED_DDR :
974                                 IBA7220_IBC_SPEED_SDR;
975                 if ((dd->ipath_link_width_enabled & (IB_WIDTH_1X |
976                         IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X))
977                         dd->ipath_ibcddrctrl |= IBA7220_IBC_WIDTH_AUTONEG;
978                 else
979                         dd->ipath_ibcddrctrl |=
980                                 dd->ipath_link_width_enabled == IB_WIDTH_4X
981                                 ? IBA7220_IBC_WIDTH_4X_ONLY :
982                                 IBA7220_IBC_WIDTH_1X_ONLY;
983
984                 /* always enable these on driver reload, not sticky */
985                 dd->ipath_ibcddrctrl |=
986                         IBA7220_IBC_RXPOL_MASK << IBA7220_IBC_RXPOL_SHIFT;
987                 dd->ipath_ibcddrctrl |=
988                         IBA7220_IBC_HRTBT_MASK << IBA7220_IBC_HRTBT_SHIFT;
989                 /*
990                  * automatic lane reversal detection for receive
991                  * doesn't work correctly in rev 1, so disable it
992                  * on that rev, otherwise enable (disabling not
993                  * sticky across reload for >rev1)
994                  */
995                 if (dd->ipath_minrev == 1)
996                         dd->ipath_ibcddrctrl &=
997                         ~IBA7220_IBC_LANE_REV_SUPPORTED;
998                 else
999                         dd->ipath_ibcddrctrl |=
1000                                 IBA7220_IBC_LANE_REV_SUPPORTED;
1001         }
1002
1003         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
1004                         dd->ipath_ibcddrctrl);
1005
1006         ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl), 0Ull);
1007
1008         /* IBA7220 has SERDES MPU reset in D0 of what _was_ IBPLLCfg */
1009         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibserdesctrl);
1010         /* remember if uC was in Reset or not, for dactrim */
1011         was_reset = (val & 1);
1012         ipath_cdbg(VERBOSE, "IBReset %s xgxsconfig %llx\n",
1013                    was_reset ? "Asserted" : "Negated", (unsigned long long)
1014                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1015
1016         if (dd->ipath_boardrev) {
1017                 /*
1018                  * Hardware is not emulator, and may have been reset. Init it.
1019                  * Below will release reset, but needs to know if chip was
1020                  * originally in reset, to only trim DACs on first time
1021                  * after chip reset or powercycle (not driver reload)
1022                  */
1023                 ret = ipath_sd7220_init(dd, was_reset);
1024         }
1025
1026         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1027         prev_val = val;
1028         val |= INFINIPATH_XGXS_FC_SAFE;
1029         if (val != prev_val) {
1030                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1031                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1032         }
1033         if (val & INFINIPATH_XGXS_RESET)
1034                 val &= ~INFINIPATH_XGXS_RESET;
1035         if (val != prev_val)
1036                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1037
1038         ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n",
1039                    (unsigned long long)
1040                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig),
1041                    (unsigned long long) prev_val);
1042
1043         guid = be64_to_cpu(dd->ipath_guid);
1044
1045         if (!guid) {
1046                 /* have to have something, so use likely unique tsc */
1047                 guid = get_cycles();
1048                 ipath_dbg("No GUID for heartbeat, faking %llx\n",
1049                         (unsigned long long)guid);
1050         } else
1051                 ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n",
1052                         (unsigned long long) guid);
1053         ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid);
1054         return ret;
1055 }
1056
1057 static void ipath_7220_config_jint(struct ipath_devdata *dd,
1058                                    u16 idle_ticks, u16 max_packets)
1059 {
1060
1061         /*
1062          * We can request a receive interrupt for 1 or more packets
1063          * from current offset.
1064          */
1065         if (idle_ticks == 0 || max_packets == 0)
1066                 /* interrupt after one packet if no mitigation */
1067                 dd->ipath_rhdrhead_intr_off =
1068                         1ULL << IBA7220_HDRHEAD_PKTINT_SHIFT;
1069         else
1070                 /* Turn off RcvHdrHead interrupts if using mitigation */
1071                 dd->ipath_rhdrhead_intr_off = 0ULL;
1072
1073         /* refresh kernel RcvHdrHead registers... */
1074         ipath_write_ureg(dd, ur_rcvhdrhead,
1075                          dd->ipath_rhdrhead_intr_off |
1076                          dd->ipath_pd[0]->port_head, 0);
1077
1078         dd->ipath_jint_max_packets = max_packets;
1079         dd->ipath_jint_idle_ticks = idle_ticks;
1080         ipath_write_kreg(dd, dd->ipath_kregs->kr_jintreload,
1081                          ((u64) max_packets << INFINIPATH_JINT_PACKETSHIFT) |
1082                          idle_ticks);
1083 }
1084
1085 /**
1086  * ipath_7220_quiet_serdes - set serdes to txidle
1087  * @dd: the infinipath device
1088  * Called when driver is being unloaded
1089  */
1090 static void ipath_7220_quiet_serdes(struct ipath_devdata *dd)
1091 {
1092         u64 val;
1093         if (dd->ibsymdelta || dd->iblnkerrdelta ||
1094             dd->ibdeltainprog) {
1095                 u64 diagc;
1096                 /* enable counter writes */
1097                 diagc = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwdiagctrl);
1098                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl,
1099                                  diagc | INFINIPATH_DC_COUNTERWREN);
1100
1101                 if (dd->ibsymdelta || dd->ibdeltainprog) {
1102                         val = ipath_read_creg32(dd,
1103                                         dd->ipath_cregs->cr_ibsymbolerrcnt);
1104                         if (dd->ibdeltainprog)
1105                                 val -= val - dd->ibsymsnap;
1106                         val -= dd->ibsymdelta;
1107                         ipath_write_creg(dd,
1108                                   dd->ipath_cregs->cr_ibsymbolerrcnt, val);
1109                 }
1110                 if (dd->iblnkerrdelta || dd->ibdeltainprog) {
1111                         val = ipath_read_creg32(dd,
1112                                         dd->ipath_cregs->cr_iblinkerrrecovcnt);
1113                         if (dd->ibdeltainprog)
1114                                 val -= val - dd->iblnkerrsnap;
1115                         val -= dd->iblnkerrdelta;
1116                         ipath_write_creg(dd,
1117                                    dd->ipath_cregs->cr_iblinkerrrecovcnt, val);
1118              }
1119
1120              /* and disable counter writes */
1121              ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl, diagc);
1122         }
1123
1124         dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
1125         wake_up(&dd->ipath_autoneg_wait);
1126         cancel_delayed_work(&dd->ipath_autoneg_work);
1127         flush_scheduled_work();
1128         ipath_shutdown_relock_poll(dd);
1129         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1130         val |= INFINIPATH_XGXS_RESET;
1131         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1132 }
1133
1134 static int ipath_7220_intconfig(struct ipath_devdata *dd)
1135 {
1136         ipath_7220_config_jint(dd, dd->ipath_jint_idle_ticks,
1137                                dd->ipath_jint_max_packets);
1138         return 0;
1139 }
1140
1141 /**
1142  * ipath_setup_7220_setextled - set the state of the two external LEDs
1143  * @dd: the infinipath device
1144  * @lst: the L state
1145  * @ltst: the LT state
1146  *
1147  * These LEDs indicate the physical and logical state of IB link.
1148  * For this chip (at least with recommended board pinouts), LED1
1149  * is Yellow (logical state) and LED2 is Green (physical state),
1150  *
1151  * Note:  We try to match the Mellanox HCA LED behavior as best
1152  * we can.  Green indicates physical link state is OK (something is
1153  * plugged in, and we can train).
1154  * Amber indicates the link is logically up (ACTIVE).
1155  * Mellanox further blinks the amber LED to indicate data packet
1156  * activity, but we have no hardware support for that, so it would
1157  * require waking up every 10-20 msecs and checking the counters
1158  * on the chip, and then turning the LED off if appropriate.  That's
1159  * visible overhead, so not something we will do.
1160  *
1161  */
1162 static void ipath_setup_7220_setextled(struct ipath_devdata *dd, u64 lst,
1163                                        u64 ltst)
1164 {
1165         u64 extctl, ledblink = 0;
1166         unsigned long flags = 0;
1167
1168         /* the diags use the LED to indicate diag info, so we leave
1169          * the external LED alone when the diags are running */
1170         if (ipath_diag_inuse)
1171                 return;
1172
1173         /* Allow override of LED display for, e.g. Locating system in rack */
1174         if (dd->ipath_led_override) {
1175                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1176                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
1177                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
1178                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1179                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
1180                         : INFINIPATH_IBCS_L_STATE_DOWN;
1181         }
1182
1183         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1184         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1185                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
1186         if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP) {
1187                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1188                 /*
1189                  * counts are in chip clock (4ns) periods.
1190                  * This is 1/16 sec (66.6ms) on,
1191                  * 3/16 sec (187.5 ms) off, with packets rcvd
1192                  */
1193                 ledblink = ((66600*1000UL/4) << IBA7220_LEDBLINK_ON_SHIFT)
1194                         | ((187500*1000UL/4) << IBA7220_LEDBLINK_OFF_SHIFT);
1195         }
1196         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1197                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1198         dd->ipath_extctrl = extctl;
1199         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1200         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1201
1202         if (ledblink) /* blink the LED on packet receive */
1203                 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvpktledcnt,
1204                         ledblink);
1205 }
1206
1207 /*
1208  * Similar to pci_intx(pdev, 1), except that we make sure
1209  * msi is off...
1210  */
1211 static void ipath_enable_intx(struct pci_dev *pdev)
1212 {
1213         u16 cw, new;
1214         int pos;
1215
1216         /* first, turn on INTx */
1217         pci_read_config_word(pdev, PCI_COMMAND, &cw);
1218         new = cw & ~PCI_COMMAND_INTX_DISABLE;
1219         if (new != cw)
1220                 pci_write_config_word(pdev, PCI_COMMAND, new);
1221
1222         /* then turn off MSI */
1223         pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1224         if (pos) {
1225                 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1226                 new = cw & ~PCI_MSI_FLAGS_ENABLE;
1227                 if (new != cw)
1228                         pci_write_config_word(pdev, pos + PCI_MSI_FLAGS, new);
1229         }
1230 }
1231
1232 static int ipath_msi_enabled(struct pci_dev *pdev)
1233 {
1234         int pos, ret = 0;
1235
1236         pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1237         if (pos) {
1238                 u16 cw;
1239
1240                 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &cw);
1241                 ret = !!(cw & PCI_MSI_FLAGS_ENABLE);
1242         }
1243         return ret;
1244 }
1245
1246 /*
1247  * disable msi interrupt if enabled, and clear the flag.
1248  * flag is used primarily for the fallback to INTx, but
1249  * is also used in reinit after reset as a flag.
1250  */
1251 static void ipath_7220_nomsi(struct ipath_devdata *dd)
1252 {
1253         dd->ipath_msi_lo = 0;
1254
1255         if (ipath_msi_enabled(dd->pcidev)) {
1256                 /*
1257                  * free, but don't zero; later kernels require
1258                  * it be freed before disable_msi, so the intx
1259                  * setup has to request it again.
1260                  */
1261                  if (dd->ipath_irq)
1262                         free_irq(dd->ipath_irq, dd);
1263                 pci_disable_msi(dd->pcidev);
1264         }
1265 }
1266
1267 /*
1268  * ipath_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1269  * @dd: the infinipath device
1270  *
1271  * Nothing but msi interrupt cleanup for now.
1272  *
1273  * This is called during driver unload.
1274  */
1275 static void ipath_setup_7220_cleanup(struct ipath_devdata *dd)
1276 {
1277         ipath_7220_nomsi(dd);
1278 }
1279
1280
1281 static void ipath_7220_pcie_params(struct ipath_devdata *dd, u32 boardrev)
1282 {
1283         u16 linkstat, minwidth, speed;
1284         int pos;
1285
1286         pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
1287         if (!pos) {
1288                 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
1289                 goto bail;
1290         }
1291
1292         pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
1293                              &linkstat);
1294         /*
1295          * speed is bits 0-4, linkwidth is bits 4-8
1296          * no defines for them in headers
1297          */
1298         speed = linkstat & 0xf;
1299         linkstat >>= 4;
1300         linkstat &= 0x1f;
1301         dd->ipath_lbus_width = linkstat;
1302         switch (boardrev) {
1303         case 0:
1304         case 2:
1305         case 10:
1306         case 12:
1307                 minwidth = 16; /* x16 capable boards */
1308                 break;
1309         default:
1310                 minwidth = 8; /* x8 capable boards */
1311                 break;
1312         }
1313
1314         switch (speed) {
1315         case 1:
1316                 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
1317                 break;
1318         case 2:
1319                 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
1320                 break;
1321         default: /* not defined, assume gen1 */
1322                 dd->ipath_lbus_speed = 2500;
1323                 break;
1324         }
1325
1326         if (linkstat < minwidth)
1327                 ipath_dev_err(dd,
1328                         "PCIe width %u (x%u HCA), performance "
1329                         "reduced\n", linkstat, minwidth);
1330         else
1331                 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x%u HCA)\n",
1332                         dd->ipath_lbus_speed, linkstat, minwidth);
1333
1334         if (speed != 1)
1335                 ipath_dev_err(dd,
1336                         "PCIe linkspeed %u is incorrect; "
1337                         "should be 1 (2500)!\n", speed);
1338
1339 bail:
1340         /* fill in string, even on errors */
1341         snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
1342                 "PCIe,%uMHz,x%u\n",
1343                 dd->ipath_lbus_speed,
1344                 dd->ipath_lbus_width);
1345         return;
1346 }
1347
1348
1349 /**
1350  * ipath_setup_7220_config - setup PCIe config related stuff
1351  * @dd: the infinipath device
1352  * @pdev: the PCI device
1353  *
1354  * The pci_enable_msi() call will fail on systems with MSI quirks
1355  * such as those with AMD8131, even if the device of interest is not
1356  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
1357  * late in 2.6.16).
1358  * All that can be done is to edit the kernel source to remove the quirk
1359  * check until that is fixed.
1360  * We do not need to call enable_msi() for our HyperTransport chip,
1361  * even though it uses MSI, and we want to avoid the quirk warning, so
1362  * So we call enable_msi only for PCIe.  If we do end up needing
1363  * pci_enable_msi at some point in the future for HT, we'll move the
1364  * call back into the main init_one code.
1365  * We save the msi lo and hi values, so we can restore them after
1366  * chip reset (the kernel PCI infrastructure doesn't yet handle that
1367  * correctly).
1368  */
1369 static int ipath_setup_7220_config(struct ipath_devdata *dd,
1370                                    struct pci_dev *pdev)
1371 {
1372         int pos, ret = -1;
1373         u32 boardrev;
1374
1375         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
1376
1377         pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
1378         if (!strcmp(int_type, "force_msi") || !strcmp(int_type, "auto"))
1379                 ret = pci_enable_msi(pdev);
1380         if (ret) {
1381                 if (!strcmp(int_type, "force_msi")) {
1382                         ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1383                                       "force_msi is on, so not continuing.\n",
1384                                       ret);
1385                         return ret;
1386                 }
1387
1388                 ipath_enable_intx(pdev);
1389                 if (!strcmp(int_type, "auto"))
1390                         ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1391                                       "falling back to INTx\n", ret);
1392         } else if (pos) {
1393                 u16 control;
1394                 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
1395                                       &dd->ipath_msi_lo);
1396                 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI,
1397                                       &dd->ipath_msi_hi);
1398                 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS,
1399                                      &control);
1400                 /* now save the data (vector) info */
1401                 pci_read_config_word(pdev,
1402                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
1403                                             ? PCI_MSI_DATA_64 :
1404                                             PCI_MSI_DATA_32),
1405                                      &dd->ipath_msi_data);
1406         } else
1407                 ipath_dev_err(dd, "Can't find MSI capability, "
1408                               "can't save MSI settings for reset\n");
1409
1410         dd->ipath_irq = pdev->irq;
1411
1412         /*
1413          * We save the cachelinesize also, although it doesn't
1414          * really matter.
1415          */
1416         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1417                              &dd->ipath_pci_cacheline);
1418
1419         /*
1420          * this function called early, ipath_boardrev not set yet.  Can't
1421          * use ipath_read_kreg64() yet, too early in init, so use readq()
1422          */
1423         boardrev = (readq(&dd->ipath_kregbase[dd->ipath_kregs->kr_revision])
1424                  >> INFINIPATH_R_BOARDID_SHIFT) & INFINIPATH_R_BOARDID_MASK;
1425
1426         ipath_7220_pcie_params(dd, boardrev);
1427
1428         dd->ipath_flags |= IPATH_NODMA_RTAIL | IPATH_HAS_SEND_DMA |
1429                 IPATH_HAS_PBC_CNT | IPATH_HAS_THRESH_UPDATE;
1430         dd->ipath_pioupd_thresh = 4U; /* set default update threshold */
1431         return 0;
1432 }
1433
1434 static void ipath_init_7220_variables(struct ipath_devdata *dd)
1435 {
1436         /*
1437          * setup the register offsets, since they are different for each
1438          * chip
1439          */
1440         dd->ipath_kregs = &ipath_7220_kregs;
1441         dd->ipath_cregs = &ipath_7220_cregs;
1442
1443         /*
1444          * bits for selecting i2c direction and values,
1445          * used for I2C serial flash
1446          */
1447         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1448         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1449         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1450         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1451
1452         /*
1453          * Fill in data for field-values that change in IBA7220.
1454          * We dynamically specify only the mask for LINKTRAININGSTATE
1455          * and only the shift for LINKSTATE, as they are the only ones
1456          * that change.  Also precalculate the 3 link states of interest
1457          * and the combined mask.
1458          */
1459         dd->ibcs_ls_shift = IBA7220_IBCS_LINKSTATE_SHIFT;
1460         dd->ibcs_lts_mask = IBA7220_IBCS_LINKTRAININGSTATE_MASK;
1461         dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1462                 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1463         dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1464                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1465                 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1466         dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1467                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1468                 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1469         dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1470                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1471                 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1472
1473         /*
1474          * Fill in data for ibcc field-values that change in IBA7220.
1475          * We dynamically specify only the mask for LINKINITCMD
1476          * and only the shift for LINKCMD and MAXPKTLEN, as they are
1477          * the only ones that change.
1478          */
1479         dd->ibcc_lic_mask = IBA7220_IBCC_LINKINITCMD_MASK;
1480         dd->ibcc_lc_shift = IBA7220_IBCC_LINKCMD_SHIFT;
1481         dd->ibcc_mpl_shift = IBA7220_IBCC_MAXPKTLEN_SHIFT;
1482
1483         /* Fill in shifts for RcvCtrl. */
1484         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1485         dd->ipath_r_intravail_shift = IBA7220_R_INTRAVAIL_SHIFT;
1486         dd->ipath_r_tailupd_shift = IBA7220_R_TAILUPD_SHIFT;
1487         dd->ipath_r_portcfg_shift = IBA7220_R_PORTCFG_SHIFT;
1488
1489         /* variables for sanity checking interrupt and errors */
1490         dd->ipath_hwe_bitsextant =
1491                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1492                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1493                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1494                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1495                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1496                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1497                 INFINIPATH_HWE_PCIE1PLLFAILED |
1498                 INFINIPATH_HWE_PCIE0PLLFAILED |
1499                 INFINIPATH_HWE_PCIEPOISONEDTLP |
1500                 INFINIPATH_HWE_PCIECPLTIMEOUT |
1501                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1502                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1503                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1504                 INFINIPATH_HWE_MEMBISTFAILED |
1505                 INFINIPATH_HWE_COREPLL_FBSLIP |
1506                 INFINIPATH_HWE_COREPLL_RFSLIP |
1507                 INFINIPATH_HWE_SERDESPLLFAILED |
1508                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1509                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR |
1510                 INFINIPATH_HWE_PCIECPLDATAQUEUEERR |
1511                 INFINIPATH_HWE_PCIECPLHDRQUEUEERR |
1512                 INFINIPATH_HWE_SDMAMEMREADERR |
1513                 INFINIPATH_HWE_CLK_UC_PLLNOTLOCKED |
1514                 INFINIPATH_HWE_PCIESERDESQ0PCLKNOTDETECT |
1515                 INFINIPATH_HWE_PCIESERDESQ1PCLKNOTDETECT |
1516                 INFINIPATH_HWE_PCIESERDESQ2PCLKNOTDETECT |
1517                 INFINIPATH_HWE_PCIESERDESQ3PCLKNOTDETECT |
1518                 INFINIPATH_HWE_DDSRXEQMEMORYPARITYERR |
1519                 INFINIPATH_HWE_IB_UC_MEMORYPARITYERR |
1520                 INFINIPATH_HWE_PCIE_UC_OCT0MEMORYPARITYERR |
1521                 INFINIPATH_HWE_PCIE_UC_OCT1MEMORYPARITYERR;
1522         dd->ipath_i_bitsextant =
1523                 INFINIPATH_I_SDMAINT | INFINIPATH_I_SDMADISABLED |
1524                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1525                 (INFINIPATH_I_RCVAVAIL_MASK <<
1526                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1527                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1528                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO |
1529                 INFINIPATH_I_JINT | INFINIPATH_I_SERDESTRIMDONE;
1530         dd->ipath_e_bitsextant =
1531                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1532                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1533                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1534                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1535                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1536                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1537                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1538                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1539                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1540                 INFINIPATH_E_SENDSPECIALTRIGGER |
1541                 INFINIPATH_E_SDMADISABLED | INFINIPATH_E_SMINPKTLEN |
1542                 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNDERRUN |
1543                 INFINIPATH_E_SPKTLEN | INFINIPATH_E_SDROPPEDSMPPKT |
1544                 INFINIPATH_E_SDROPPEDDATAPKT |
1545                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1546                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_SENDBUFMISUSE |
1547                 INFINIPATH_E_SDMAGENMISMATCH | INFINIPATH_E_SDMAOUTOFBOUND |
1548                 INFINIPATH_E_SDMATAILOUTOFBOUND | INFINIPATH_E_SDMABASE |
1549                 INFINIPATH_E_SDMA1STDESC | INFINIPATH_E_SDMARPYTAG |
1550                 INFINIPATH_E_SDMADWEN | INFINIPATH_E_SDMAMISSINGDW |
1551                 INFINIPATH_E_SDMAUNEXPDATA |
1552                 INFINIPATH_E_IBSTATUSCHANGED | INFINIPATH_E_INVALIDADDR |
1553                 INFINIPATH_E_RESET | INFINIPATH_E_HARDWARE |
1554                 INFINIPATH_E_SDMADESCADDRMISALIGN |
1555                 INFINIPATH_E_INVALIDEEPCMD;
1556
1557         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1558         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1559         dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1560         dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1561         dd->ipath_flags |= IPATH_INTREG_64 | IPATH_HAS_MULT_IB_SPEED
1562                 | IPATH_HAS_LINK_LATENCY;
1563
1564         /*
1565          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1566          * 2 is Some Misc, 3 is reserved for future.
1567          */
1568         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1569                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1570                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1571
1572         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1573                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1574                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1575
1576         dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1577
1578         ipath_linkrecovery = 0;
1579
1580         init_waitqueue_head(&dd->ipath_autoneg_wait);
1581         INIT_DELAYED_WORK(&dd->ipath_autoneg_work,  autoneg_work);
1582
1583         dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1584         dd->ipath_link_speed_supported = IPATH_IB_SDR | IPATH_IB_DDR;
1585
1586         dd->ipath_link_width_enabled = dd->ipath_link_width_supported;
1587         dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1588         /*
1589          * set the initial values to reasonable default, will be set
1590          * for real when link is up.
1591          */
1592         dd->ipath_link_width_active = IB_WIDTH_4X;
1593         dd->ipath_link_speed_active = IPATH_IB_SDR;
1594         dd->delay_mult = rate_to_delay[0][1];
1595 }
1596
1597
1598 /*
1599  * Setup the MSI stuff again after a reset.  I'd like to just call
1600  * pci_enable_msi() and request_irq() again, but when I do that,
1601  * the MSI enable bit doesn't get set in the command word, and
1602  * we switch to to a different interrupt vector, which is confusing,
1603  * so I instead just do it all inline.  Perhaps somehow can tie this
1604  * into the PCIe hotplug support at some point
1605  * Note, because I'm doing it all here, I don't call pci_disable_msi()
1606  * or free_irq() at the start of ipath_setup_7220_reset().
1607  */
1608 static int ipath_reinit_msi(struct ipath_devdata *dd)
1609 {
1610         int ret = 0;
1611
1612         int pos;
1613         u16 control;
1614         if (!dd->ipath_msi_lo) /* Using intX, or init problem */
1615                 goto bail;
1616
1617         pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
1618         if (!pos) {
1619                 ipath_dev_err(dd, "Can't find MSI capability, "
1620                               "can't restore MSI settings\n");
1621                 goto bail;
1622         }
1623         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1624                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1625         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1626                                dd->ipath_msi_lo);
1627         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1628                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1629         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1630                                dd->ipath_msi_hi);
1631         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1632         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1633                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1634                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1635                            control, control | PCI_MSI_FLAGS_ENABLE);
1636                 control |= PCI_MSI_FLAGS_ENABLE;
1637                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1638                                       control);
1639         }
1640         /* now rewrite the data (vector) info */
1641         pci_write_config_word(dd->pcidev, pos +
1642                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1643                               dd->ipath_msi_data);
1644         ret = 1;
1645
1646 bail:
1647         if (!ret) {
1648                 ipath_dbg("Using INTx, MSI disabled or not configured\n");
1649                 ipath_enable_intx(dd->pcidev);
1650                 ret = 1;
1651         }
1652         /*
1653          * We restore the cachelinesize also, although it doesn't really
1654          * matter.
1655          */
1656         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1657                               dd->ipath_pci_cacheline);
1658         /* and now set the pci master bit again */
1659         pci_set_master(dd->pcidev);
1660
1661         return ret;
1662 }
1663
1664 /*
1665  * This routine sleeps, so it can only be called from user context, not
1666  * from interrupt context.  If we need interrupt context, we can split
1667  * it into two routines.
1668  */
1669 static int ipath_setup_7220_reset(struct ipath_devdata *dd)
1670 {
1671         u64 val;
1672         int i;
1673         int ret;
1674         u16 cmdval;
1675
1676         pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
1677
1678         /* Use dev_err so it shows up in logs, etc. */
1679         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1680
1681         /* keep chip from being accessed in a few places */
1682         dd->ipath_flags &= ~(IPATH_INITTED | IPATH_PRESENT);
1683         val = dd->ipath_control | INFINIPATH_C_RESET;
1684         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1685         mb();
1686
1687         for (i = 1; i <= 5; i++) {
1688                 int r;
1689
1690                 /*
1691                  * Allow MBIST, etc. to complete; longer on each retry.
1692                  * We sometimes get machine checks from bus timeout if no
1693                  * response, so for now, make it *really* long.
1694                  */
1695                 msleep(1000 + (1 + i) * 2000);
1696                 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1697                                            dd->ipath_pcibar0);
1698                 if (r)
1699                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n", r);
1700                 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1701                                            dd->ipath_pcibar1);
1702                 if (r)
1703                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n", r);
1704                 /* now re-enable memory access */
1705                 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
1706                 r = pci_enable_device(dd->pcidev);
1707                 if (r)
1708                         ipath_dev_err(dd, "pci_enable_device failed after "
1709                                       "reset: %d\n", r);
1710                 /*
1711                  * whether it fully enabled or not, mark as present,
1712                  * again (but not INITTED)
1713                  */
1714                 dd->ipath_flags |= IPATH_PRESENT;
1715                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1716                 if (val == dd->ipath_revision) {
1717                         ipath_cdbg(VERBOSE, "Got matching revision "
1718                                    "register %llx on try %d\n",
1719                                    (unsigned long long) val, i);
1720                         ret = ipath_reinit_msi(dd);
1721                         goto bail;
1722                 }
1723                 /* Probably getting -1 back */
1724                 ipath_dbg("Didn't get expected revision register, "
1725                           "got %llx, try %d\n", (unsigned long long) val,
1726                           i + 1);
1727         }
1728         ret = 0; /* failed */
1729
1730 bail:
1731         if (ret)
1732                 ipath_7220_pcie_params(dd, dd->ipath_boardrev);
1733
1734         return ret;
1735 }
1736
1737 /**
1738  * ipath_7220_put_tid - write a TID to the chip
1739  * @dd: the infinipath device
1740  * @tidptr: pointer to the expected TID (in chip) to udpate
1741  * @tidtype: 0 for eager, 1 for expected
1742  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1743  *
1744  * This exists as a separate routine to allow for selection of the
1745  * appropriate "flavor". The static calls in cleanup just use the
1746  * revision-agnostic form, as they are not performance critical.
1747  */
1748 static void ipath_7220_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1749                              u32 type, unsigned long pa)
1750 {
1751         if (pa != dd->ipath_tidinvalid) {
1752                 u64 chippa = pa >> IBA7220_TID_PA_SHIFT;
1753
1754                 /* paranoia checks */
1755                 if (pa != (chippa << IBA7220_TID_PA_SHIFT)) {
1756                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1757                                  "not 2KB aligned!\n", pa);
1758                         return;
1759                 }
1760                 if (chippa >= (1UL << IBA7220_TID_SZ_SHIFT)) {
1761                         ipath_dev_err(dd,
1762                                       "BUG: Physical page address 0x%lx "
1763                                       "larger than supported\n", pa);
1764                         return;
1765                 }
1766
1767                 if (type == RCVHQ_RCV_TYPE_EAGER)
1768                         chippa |= dd->ipath_tidtemplate;
1769                 else /* for now, always full 4KB page */
1770                         chippa |= IBA7220_TID_SZ_4K;
1771                 writeq(chippa, tidptr);
1772         } else
1773                 writeq(pa, tidptr);
1774         mmiowb();
1775 }
1776
1777 /**
1778  * ipath_7220_clear_tid - clear all TID entries for a port, expected and eager
1779  * @dd: the infinipath device
1780  * @port: the port
1781  *
1782  * clear all TID entries for a port, expected and eager.
1783  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1784  * not 64, but they are still on 64 bit boundaries, so tidbase
1785  * is declared as u64 * for the pointer math, even though we write 32 bits
1786  */
1787 static void ipath_7220_clear_tids(struct ipath_devdata *dd, unsigned port)
1788 {
1789         u64 __iomem *tidbase;
1790         unsigned long tidinv;
1791         int i;
1792
1793         if (!dd->ipath_kregbase)
1794                 return;
1795
1796         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1797
1798         tidinv = dd->ipath_tidinvalid;
1799         tidbase = (u64 __iomem *)
1800                 ((char __iomem *)(dd->ipath_kregbase) +
1801                  dd->ipath_rcvtidbase +
1802                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1803
1804         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1805                 ipath_7220_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1806                                    tidinv);
1807
1808         tidbase = (u64 __iomem *)
1809                 ((char __iomem *)(dd->ipath_kregbase) +
1810                  dd->ipath_rcvegrbase + port_egrtid_idx(dd, port)
1811                  * sizeof(*tidbase));
1812
1813         for (i = port ? dd->ipath_rcvegrcnt : dd->ipath_p0_rcvegrcnt; i; i--)
1814                 ipath_7220_put_tid(dd, &tidbase[i-1], RCVHQ_RCV_TYPE_EAGER,
1815                         tidinv);
1816 }
1817
1818 /**
1819  * ipath_7220_tidtemplate - setup constants for TID updates
1820  * @dd: the infinipath device
1821  *
1822  * We setup stuff that we use a lot, to avoid calculating each time
1823  */
1824 static void ipath_7220_tidtemplate(struct ipath_devdata *dd)
1825 {
1826         /* For now, we always allocate 4KB buffers (at init) so we can
1827          * receive max size packets.  We may want a module parameter to
1828          * specify 2KB or 4KB and/or make be per port instead of per device
1829          * for those who want to reduce memory footprint.  Note that the
1830          * ipath_rcvhdrentsize size must be large enough to hold the largest
1831          * IB header (currently 96 bytes) that we expect to handle (plus of
1832          * course the 2 dwords of RHF).
1833          */
1834         if (dd->ipath_rcvegrbufsize == 2048)
1835                 dd->ipath_tidtemplate = IBA7220_TID_SZ_2K;
1836         else if (dd->ipath_rcvegrbufsize == 4096)
1837                 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1838         else {
1839                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1840                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1841                          4096);
1842                 dd->ipath_tidtemplate = IBA7220_TID_SZ_4K;
1843         }
1844         dd->ipath_tidinvalid = 0;
1845 }
1846
1847 static int ipath_7220_early_init(struct ipath_devdata *dd)
1848 {
1849         u32 i, s;
1850
1851         if (strcmp(int_type, "auto") &&
1852             strcmp(int_type, "force_msi") &&
1853             strcmp(int_type, "force_intx")) {
1854                 ipath_dev_err(dd, "Invalid interrupt_type: '%s', expecting "
1855                               "auto, force_msi or force_intx\n", int_type);
1856                 return -EINVAL;
1857         }
1858
1859         /*
1860          * Control[4] has been added to change the arbitration within
1861          * the SDMA engine between favoring data fetches over descriptor
1862          * fetches.  ipath_sdma_fetch_arb==0 gives data fetches priority.
1863          */
1864         if (ipath_sdma_fetch_arb && (dd->ipath_minrev > 1))
1865                 dd->ipath_control |= 1<<4;
1866
1867         dd->ipath_flags |= IPATH_4BYTE_TID;
1868
1869         /*
1870          * For openfabrics, we need to be able to handle an IB header of
1871          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1872          * made them the same size as the PIO buffers.  This chip does not
1873          * handle arbitrary size buffers, so we need the header large enough
1874          * to handle largest IB header, but still have room for a 2KB MTU
1875          * standard IB packet.
1876          */
1877         dd->ipath_rcvhdrentsize = 24;
1878         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1879         dd->ipath_rhf_offset =
1880                 dd->ipath_rcvhdrentsize - sizeof(u64) / sizeof(u32);
1881
1882         dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048;
1883         /*
1884          * the min() check here is currently a nop, but it may not always
1885          * be, depending on just how we do ipath_rcvegrbufsize
1886          */
1887         dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k :
1888                                  dd->ipath_piosize2k,
1889                                  dd->ipath_rcvegrbufsize +
1890                                  (dd->ipath_rcvhdrentsize << 2));
1891         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1892
1893         ipath_7220_config_jint(dd, INFINIPATH_JINT_DEFAULT_IDLE_TICKS,
1894                                INFINIPATH_JINT_DEFAULT_MAX_PACKETS);
1895
1896         if (dd->ipath_boardrev) /* no eeprom on emulator */
1897                 ipath_get_eeprom_info(dd);
1898
1899         /* start of code to check and print procmon */
1900         s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1901         s &= ~(1U<<31); /* clear done bit */
1902         s |= 1U<<14; /* clear counter (write 1 to clear) */
1903         ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1904         /* make sure clear_counter low long enough before start */
1905         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1906         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1907
1908         s &= ~(1U<<14); /* allow counter to count (before starting) */
1909         ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1910         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1911         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1912         s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1913
1914         s |= 1U<<15; /* start the counter */
1915         s &= ~(1U<<31); /* clear done bit */
1916         s &= ~0x7ffU; /* clear frequency bits */
1917         s |= 0xe29; /* set frequency bits, in case cleared */
1918         ipath_write_kreg(dd, IPATH_KREG_OFFSET(ProcMon), s);
1919
1920         s = 0;
1921         for (i = 500; i > 0 && !(s&(1ULL<<31)); i--) {
1922                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1923                 s = ipath_read_kreg32(dd, IPATH_KREG_OFFSET(ProcMon));
1924         }
1925         if (!(s&(1U<<31)))
1926                 ipath_dev_err(dd, "ProcMon register not valid: 0x%x\n", s);
1927         else
1928                 ipath_dbg("ProcMon=0x%x, count=0x%x\n", s, (s>>16)&0x1ff);
1929
1930         return 0;
1931 }
1932
1933 /**
1934  * ipath_init_7220_get_base_info - set chip-specific flags for user code
1935  * @pd: the infinipath port
1936  * @kbase: ipath_base_info pointer
1937  *
1938  * We set the PCIE flag because the lower bandwidth on PCIe vs
1939  * HyperTransport can affect some user packet algorithims.
1940  */
1941 static int ipath_7220_get_base_info(struct ipath_portdata *pd, void *kbase)
1942 {
1943         struct ipath_base_info *kinfo = kbase;
1944
1945         kinfo->spi_runtime_flags |=
1946                 IPATH_RUNTIME_PCIE | IPATH_RUNTIME_NODMA_RTAIL |
1947                 IPATH_RUNTIME_SDMA;
1948
1949         return 0;
1950 }
1951
1952 static void ipath_7220_free_irq(struct ipath_devdata *dd)
1953 {
1954         free_irq(dd->ipath_irq, dd);
1955         dd->ipath_irq = 0;
1956 }
1957
1958 static struct ipath_message_header *
1959 ipath_7220_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1960 {
1961         u32 offset = ipath_hdrget_offset(rhf_addr);
1962
1963         return (struct ipath_message_header *)
1964                 (rhf_addr - dd->ipath_rhf_offset + offset);
1965 }
1966
1967 static void ipath_7220_config_ports(struct ipath_devdata *dd, ushort cfgports)
1968 {
1969         u32 nchipports;
1970
1971         nchipports = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1972         if (!cfgports) {
1973                 int ncpus = num_online_cpus();
1974
1975                 if (ncpus <= 4)
1976                         dd->ipath_portcnt = 5;
1977                 else if (ncpus <= 8)
1978                         dd->ipath_portcnt = 9;
1979                 if (dd->ipath_portcnt)
1980                         ipath_dbg("Auto-configured for %u ports, %d cpus "
1981                                 "online\n", dd->ipath_portcnt, ncpus);
1982         } else if (cfgports <= nchipports)
1983                 dd->ipath_portcnt = cfgports;
1984         if (!dd->ipath_portcnt) /* none of the above, set to max */
1985                 dd->ipath_portcnt = nchipports;
1986         /*
1987          * chip can be configured for 5, 9, or 17 ports, and choice
1988          * affects number of eager TIDs per port (1K, 2K, 4K).
1989          */
1990         if (dd->ipath_portcnt > 9)
1991                 dd->ipath_rcvctrl |= 2ULL << IBA7220_R_PORTCFG_SHIFT;
1992         else if (dd->ipath_portcnt > 5)
1993                 dd->ipath_rcvctrl |= 1ULL << IBA7220_R_PORTCFG_SHIFT;
1994         /* else configure for default 5 receive ports */
1995         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1996                          dd->ipath_rcvctrl);
1997         dd->ipath_p0_rcvegrcnt = 2048; /* always */
1998         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1999                 dd->ipath_pioreserved = 3; /* kpiobufs used for PIO */
2000 }
2001
2002
2003 static int ipath_7220_get_ib_cfg(struct ipath_devdata *dd, int which)
2004 {
2005         int lsb, ret = 0;
2006         u64 maskr; /* right-justified mask */
2007
2008         switch (which) {
2009         case IPATH_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
2010                 lsb = IBA7220_IBC_HRTBT_SHIFT;
2011                 maskr = IBA7220_IBC_HRTBT_MASK;
2012                 break;
2013
2014         case IPATH_IB_CFG_LWID_ENB: /* Get allowed Link-width */
2015                 ret = dd->ipath_link_width_enabled;
2016                 goto done;
2017
2018         case IPATH_IB_CFG_LWID: /* Get currently active Link-width */
2019                 ret = dd->ipath_link_width_active;
2020                 goto done;
2021
2022         case IPATH_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
2023                 ret = dd->ipath_link_speed_enabled;
2024                 goto done;
2025
2026         case IPATH_IB_CFG_SPD: /* Get current Link spd */
2027                 ret = dd->ipath_link_speed_active;
2028                 goto done;
2029
2030         case IPATH_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
2031                 lsb = IBA7220_IBC_RXPOL_SHIFT;
2032                 maskr = IBA7220_IBC_RXPOL_MASK;
2033                 break;
2034
2035         case IPATH_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
2036                 lsb = IBA7220_IBC_LREV_SHIFT;
2037                 maskr = IBA7220_IBC_LREV_MASK;
2038                 break;
2039
2040         case IPATH_IB_CFG_LINKLATENCY:
2041                 ret = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcddrstatus)
2042                         & IBA7220_DDRSTAT_LINKLAT_MASK;
2043                 goto done;
2044
2045         default:
2046                 ret = -ENOTSUPP;
2047                 goto done;
2048         }
2049         ret = (int)((dd->ipath_ibcddrctrl >> lsb) & maskr);
2050 done:
2051         return ret;
2052 }
2053
2054 static int ipath_7220_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
2055 {
2056         int lsb, ret = 0, setforce = 0;
2057         u64 maskr; /* right-justified mask */
2058
2059         switch (which) {
2060         case IPATH_IB_CFG_LIDLMC:
2061                 /*
2062                  * Set LID and LMC. Combined to avoid possible hazard
2063                  * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2064                  */
2065                 lsb = IBA7220_IBC_DLIDLMC_SHIFT;
2066                 maskr = IBA7220_IBC_DLIDLMC_MASK;
2067                 break;
2068
2069         case IPATH_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
2070                 if (val & IPATH_IB_HRTBT_ON &&
2071                         (dd->ipath_flags & IPATH_NO_HRTBT))
2072                         goto bail;
2073                 lsb = IBA7220_IBC_HRTBT_SHIFT;
2074                 maskr = IBA7220_IBC_HRTBT_MASK;
2075                 break;
2076
2077         case IPATH_IB_CFG_LWID_ENB: /* set allowed Link-width */
2078                 /*
2079                  * As with speed, only write the actual register if
2080                  * the link is currently down, otherwise takes effect
2081                  * on next link change.
2082                  */
2083                 dd->ipath_link_width_enabled = val;
2084                 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2085                         IPATH_LINKDOWN)
2086                         goto bail;
2087                 /*
2088                  * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2089                  * will get called because we want update
2090                  * link_width_active, and the change may not take
2091                  * effect for some time (if we are in POLL), so this
2092                  * flag will force the updown routine to be called
2093                  * on the next ibstatuschange down interrupt, even
2094                  * if it's not an down->up transition.
2095                  */
2096                 val--; /* convert from IB to chip */
2097                 maskr = IBA7220_IBC_WIDTH_MASK;
2098                 lsb = IBA7220_IBC_WIDTH_SHIFT;
2099                 setforce = 1;
2100                 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2101                 break;
2102
2103         case IPATH_IB_CFG_SPD_ENB: /* set allowed Link speeds */
2104                 /*
2105                  * If we turn off IB1.2, need to preset SerDes defaults,
2106                  * but not right now. Set a flag for the next time
2107                  * we command the link down.  As with width, only write the
2108                  * actual register if the link is currently down, otherwise
2109                  * takes effect on next link change.  Since setting is being
2110                  * explictly requested (via MAD or sysfs), clear autoneg
2111                  * failure status if speed autoneg is enabled.
2112                  */
2113                 dd->ipath_link_speed_enabled = val;
2114                 if (dd->ipath_ibcddrctrl & IBA7220_IBC_IBTA_1_2_MASK &&
2115                     !(val & (val - 1)))
2116                         dd->ipath_presets_needed = 1;
2117                 if ((dd->ipath_flags & (IPATH_LINKDOWN|IPATH_LINKINIT)) !=
2118                         IPATH_LINKDOWN)
2119                         goto bail;
2120                 /*
2121                  * We set the IPATH_IB_FORCE_NOTIFY bit so updown
2122                  * will get called because we want update
2123                  * link_speed_active, and the change may not take
2124                  * effect for some time (if we are in POLL), so this
2125                  * flag will force the updown routine to be called
2126                  * on the next ibstatuschange down interrupt, even
2127                  * if it's not an down->up transition.  When setting
2128                  * speed autoneg, clear AUTONEG_FAILED.
2129                  */
2130                 if (val == (IPATH_IB_SDR | IPATH_IB_DDR)) {
2131                         val = IBA7220_IBC_SPEED_AUTONEG_MASK |
2132                                 IBA7220_IBC_IBTA_1_2_MASK;
2133                         dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2134                 } else
2135                         val = val == IPATH_IB_DDR ?  IBA7220_IBC_SPEED_DDR
2136                                 : IBA7220_IBC_SPEED_SDR;
2137                 maskr = IBA7220_IBC_SPEED_AUTONEG_MASK |
2138                         IBA7220_IBC_IBTA_1_2_MASK;
2139                 lsb = 0; /* speed bits are low bits */
2140                 setforce = 1;
2141                 break;
2142
2143         case IPATH_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
2144                 lsb = IBA7220_IBC_RXPOL_SHIFT;
2145                 maskr = IBA7220_IBC_RXPOL_MASK;
2146                 break;
2147
2148         case IPATH_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
2149                 lsb = IBA7220_IBC_LREV_SHIFT;
2150                 maskr = IBA7220_IBC_LREV_MASK;
2151                 break;
2152
2153         default:
2154                 ret = -ENOTSUPP;
2155                 goto bail;
2156         }
2157         dd->ipath_ibcddrctrl &= ~(maskr << lsb);
2158         dd->ipath_ibcddrctrl |= (((u64) val & maskr) << lsb);
2159         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2160                          dd->ipath_ibcddrctrl);
2161         if (setforce)
2162                 dd->ipath_flags |= IPATH_IB_FORCE_NOTIFY;
2163 bail:
2164         return ret;
2165 }
2166
2167 static void ipath_7220_read_counters(struct ipath_devdata *dd,
2168                                      struct infinipath_counters *cntrs)
2169 {
2170         u64 *counters = (u64 *) cntrs;
2171         int i;
2172
2173         for (i = 0; i < sizeof(*cntrs) / sizeof(u64); i++)
2174                 counters[i] = ipath_snap_cntr(dd, i);
2175 }
2176
2177 /* if we are using MSI, try to fallback to INTx */
2178 static int ipath_7220_intr_fallback(struct ipath_devdata *dd)
2179 {
2180         if (dd->ipath_msi_lo) {
2181                 dev_info(&dd->pcidev->dev, "MSI interrupt not detected,"
2182                         " trying INTx interrupts\n");
2183                 ipath_7220_nomsi(dd);
2184                 ipath_enable_intx(dd->pcidev);
2185                 /*
2186                  * some newer kernels require free_irq before disable_msi,
2187                  * and irq can be changed during disable and intx enable
2188                  * and we need to therefore use the pcidev->irq value,
2189                  * not our saved MSI value.
2190                  */
2191                 dd->ipath_irq = dd->pcidev->irq;
2192                 if (request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
2193                         IPATH_DRV_NAME, dd))
2194                         ipath_dev_err(dd,
2195                                 "Could not re-request_irq for INTx\n");
2196                 return 1;
2197         }
2198         return 0;
2199 }
2200
2201 /*
2202  * reset the XGXS (between serdes and IBC).  Slightly less intrusive
2203  * than resetting the IBC or external link state, and useful in some
2204  * cases to cause some retraining.  To do this right, we reset IBC
2205  * as well.
2206  */
2207 static void ipath_7220_xgxs_reset(struct ipath_devdata *dd)
2208 {
2209         u64 val, prev_val;
2210
2211         prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2212         val = prev_val | INFINIPATH_XGXS_RESET;
2213         prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
2214         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2215                          dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
2216         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2217         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
2218         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
2219         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2220                          dd->ipath_control);
2221 }
2222
2223
2224 /* Still needs cleanup, too much hardwired stuff */
2225 static void autoneg_send(struct ipath_devdata *dd,
2226         u32 *hdr, u32 dcnt, u32 *data)
2227 {
2228         int i;
2229         u64 cnt;
2230         u32 __iomem *piobuf;
2231         u32 pnum;
2232
2233         i = 0;
2234         cnt = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
2235         while (!(piobuf = ipath_getpiobuf(dd, cnt, &pnum))) {
2236                 if (i++ > 15) {
2237                         ipath_dbg("Couldn't get pio buffer for send\n");
2238                         return;
2239                 }
2240                 udelay(2);
2241         }
2242         if (dd->ipath_flags&IPATH_HAS_PBC_CNT)
2243                 cnt |= 0x80000000UL<<32; /* mark as VL15 */
2244         writeq(cnt, piobuf);
2245         ipath_flush_wc();
2246         __iowrite32_copy(piobuf + 2, hdr, 7);
2247         __iowrite32_copy(piobuf + 9, data, dcnt);
2248         ipath_flush_wc();
2249 }
2250
2251 /*
2252  * _start packet gets sent twice at start, _done gets sent twice at end
2253  */
2254 static void ipath_autoneg_send(struct ipath_devdata *dd, int which)
2255 {
2256         static u32 swapped;
2257         u32 dw, i, hcnt, dcnt, *data;
2258         static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
2259         static u32 madpayload_start[0x40] = {
2260                 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2261                 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2262                 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
2263                 };
2264         static u32 madpayload_done[0x40] = {
2265                 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
2266                 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
2267                 0x40000001, 0x1388, 0x15e, /* rest 0's */
2268                 };
2269         dcnt = ARRAY_SIZE(madpayload_start);
2270         hcnt = ARRAY_SIZE(hdr);
2271         if (!swapped) {
2272                 /* for maintainability, do it at runtime */
2273                 for (i = 0; i < hcnt; i++) {
2274                         dw = (__force u32) cpu_to_be32(hdr[i]);
2275                         hdr[i] = dw;
2276                 }
2277                 for (i = 0; i < dcnt; i++) {
2278                         dw = (__force u32) cpu_to_be32(madpayload_start[i]);
2279                         madpayload_start[i] = dw;
2280                         dw = (__force u32) cpu_to_be32(madpayload_done[i]);
2281                         madpayload_done[i] = dw;
2282                 }
2283                 swapped = 1;
2284         }
2285
2286         data = which ? madpayload_done : madpayload_start;
2287         ipath_cdbg(PKT, "Sending %s special MADs\n", which?"done":"start");
2288
2289         autoneg_send(dd, hdr, dcnt, data);
2290         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2291         udelay(2);
2292         autoneg_send(dd, hdr, dcnt, data);
2293         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2294         udelay(2);
2295 }
2296
2297
2298
2299 /*
2300  * Do the absolute minimum to cause an IB speed change, and make it
2301  * ready, but don't actually trigger the change.   The caller will
2302  * do that when ready (if link is in Polling training state, it will
2303  * happen immediately, otherwise when link next goes down)
2304  *
2305  * This routine should only be used as part of the DDR autonegotation
2306  * code for devices that are not compliant with IB 1.2 (or code that
2307  * fixes things up for same).
2308  *
2309  * When link has gone down, and autoneg enabled, or autoneg has
2310  * failed and we give up until next time we set both speeds, and
2311  * then we want IBTA enabled as well as "use max enabled speed.
2312  */
2313 static void set_speed_fast(struct ipath_devdata *dd, u32 speed)
2314 {
2315         dd->ipath_ibcddrctrl &= ~(IBA7220_IBC_SPEED_AUTONEG_MASK |
2316                 IBA7220_IBC_IBTA_1_2_MASK |
2317                 (IBA7220_IBC_WIDTH_MASK << IBA7220_IBC_WIDTH_SHIFT));
2318
2319         if (speed == (IPATH_IB_SDR | IPATH_IB_DDR))
2320                 dd->ipath_ibcddrctrl |= IBA7220_IBC_SPEED_AUTONEG_MASK |
2321                         IBA7220_IBC_IBTA_1_2_MASK;
2322         else
2323                 dd->ipath_ibcddrctrl |= speed == IPATH_IB_DDR ?
2324                         IBA7220_IBC_SPEED_DDR : IBA7220_IBC_SPEED_SDR;
2325
2326         /*
2327          * Convert from IB-style 1 = 1x, 2 = 4x, 3 = auto
2328          * to chip-centric       0 = 1x, 1 = 4x, 2 = auto
2329          */
2330         dd->ipath_ibcddrctrl |= (u64)(dd->ipath_link_width_enabled - 1) <<
2331                 IBA7220_IBC_WIDTH_SHIFT;
2332         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcddrctrl,
2333                         dd->ipath_ibcddrctrl);
2334         ipath_cdbg(VERBOSE, "setup for IB speed (%x) done\n", speed);
2335 }
2336
2337
2338 /*
2339  * this routine is only used when we are not talking to another
2340  * IB 1.2-compliant device that we think can do DDR.
2341  * (This includes all existing switch chips as of Oct 2007.)
2342  * 1.2-compliant devices go directly to DDR prior to reaching INIT
2343  */
2344 static void try_auto_neg(struct ipath_devdata *dd)
2345 {
2346         /*
2347          * required for older non-IB1.2 DDR switches.  Newer
2348          * non-IB-compliant switches don't need it, but so far,
2349          * aren't bothered by it either.  "Magic constant"
2350          */
2351         ipath_write_kreg(dd, IPATH_KREG_OFFSET(IBNCModeCtrl),
2352                 0x3b9dc07);
2353         dd->ipath_flags |= IPATH_IB_AUTONEG_INPROG;
2354         ipath_autoneg_send(dd, 0);
2355         set_speed_fast(dd, IPATH_IB_DDR);
2356         ipath_toggle_rclkrls(dd);
2357         /* 2 msec is minimum length of a poll cycle */
2358         schedule_delayed_work(&dd->ipath_autoneg_work,
2359                 msecs_to_jiffies(2));
2360 }
2361
2362
2363 static int ipath_7220_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
2364 {
2365         int ret = 0, symadj = 0;
2366         u32 ltstate = ipath_ib_linkstate(dd, ibcs);
2367
2368         dd->ipath_link_width_active =
2369                 ((ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1) ?
2370                     IB_WIDTH_4X : IB_WIDTH_1X;
2371         dd->ipath_link_speed_active =
2372                 ((ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1) ?
2373                     IPATH_IB_DDR : IPATH_IB_SDR;
2374
2375         if (!ibup) {
2376                 /*
2377                  * when link goes down we don't want aeq running, so it
2378                  * won't't interfere with IBC training, etc., and we need
2379                  * to go back to the static SerDes preset values
2380                  */
2381                 if (dd->ipath_x1_fix_tries &&
2382                          ltstate <= INFINIPATH_IBCS_LT_STATE_SLEEPQUIET &&
2383                         ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP)
2384                         dd->ipath_x1_fix_tries = 0;
2385                 if (!(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2386                         IPATH_IB_AUTONEG_INPROG)))
2387                         set_speed_fast(dd, dd->ipath_link_speed_enabled);
2388                 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)) {
2389                         ipath_cdbg(VERBOSE, "Setting RXEQ defaults\n");
2390                         ipath_sd7220_presets(dd);
2391                 }
2392                 /* this might better in ipath_sd7220_presets() */
2393                 ipath_set_relock_poll(dd, ibup);
2394         } else {
2395                 if (ipath_compat_ddr_negotiate &&
2396                     !(dd->ipath_flags & (IPATH_IB_AUTONEG_FAILED |
2397                         IPATH_IB_AUTONEG_INPROG)) &&
2398                         dd->ipath_link_speed_active == IPATH_IB_SDR &&
2399                         (dd->ipath_link_speed_enabled &
2400                             (IPATH_IB_DDR | IPATH_IB_SDR)) ==
2401                             (IPATH_IB_DDR | IPATH_IB_SDR) &&
2402                         dd->ipath_autoneg_tries < IPATH_AUTONEG_TRIES) {
2403                         /* we are SDR, and DDR auto-negotiation enabled */
2404                         ++dd->ipath_autoneg_tries;
2405                         ipath_dbg("DDR negotiation try, %u/%u\n",
2406                                 dd->ipath_autoneg_tries,
2407                                 IPATH_AUTONEG_TRIES);
2408                         if (!dd->ibdeltainprog) {
2409                                 dd->ibdeltainprog = 1;
2410                                 dd->ibsymsnap = ipath_read_creg32(dd,
2411                                         dd->ipath_cregs->cr_ibsymbolerrcnt);
2412                                 dd->iblnkerrsnap = ipath_read_creg32(dd,
2413                                         dd->ipath_cregs->cr_iblinkerrrecovcnt);
2414                         }
2415                         try_auto_neg(dd);
2416                         ret = 1; /* no other IB status change processing */
2417                 } else if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)
2418                         && dd->ipath_link_speed_active == IPATH_IB_SDR) {
2419                         ipath_autoneg_send(dd, 1);
2420                         set_speed_fast(dd, IPATH_IB_DDR);
2421                         udelay(2);
2422                         ipath_toggle_rclkrls(dd);
2423                         ret = 1; /* no other IB status change processing */
2424                 } else {
2425                         if ((dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) &&
2426                                 (dd->ipath_link_speed_active & IPATH_IB_DDR)) {
2427                                 ipath_dbg("Got to INIT with DDR autoneg\n");
2428                                 dd->ipath_flags &= ~(IPATH_IB_AUTONEG_INPROG
2429                                         | IPATH_IB_AUTONEG_FAILED);
2430                                 dd->ipath_autoneg_tries = 0;
2431                                 /* re-enable SDR, for next link down */
2432                                 set_speed_fast(dd,
2433                                         dd->ipath_link_speed_enabled);
2434                                 wake_up(&dd->ipath_autoneg_wait);
2435                                 symadj = 1;
2436                         } else if (dd->ipath_flags & IPATH_IB_AUTONEG_FAILED) {
2437                                 /*
2438                                  * clear autoneg failure flag, and do setup
2439                                  * so we'll try next time link goes down and
2440                                  * back to INIT (possibly connected to different
2441                                  * device).
2442                                  */
2443                                 ipath_dbg("INIT %sDR after autoneg failure\n",
2444                                         (dd->ipath_link_speed_active &
2445                                           IPATH_IB_DDR) ? "D" : "S");
2446                                 dd->ipath_flags &= ~IPATH_IB_AUTONEG_FAILED;
2447                                 dd->ipath_ibcddrctrl |=
2448                                         IBA7220_IBC_IBTA_1_2_MASK;
2449                                 ipath_write_kreg(dd,
2450                                         IPATH_KREG_OFFSET(IBNCModeCtrl), 0);
2451                                 symadj = 1;
2452                         }
2453                 }
2454                 /*
2455                  * if we are in 1X on rev1 only, and are in autoneg width,
2456                  * it could be due to an xgxs problem, so if we haven't
2457                  * already tried, try twice to get to 4X; if we
2458                  * tried, and couldn't, report it, since it will
2459                  * probably not be what is desired.
2460                  */
2461                 if (dd->ipath_minrev == 1 &&
2462                     (dd->ipath_link_width_enabled & (IB_WIDTH_1X |
2463                         IB_WIDTH_4X)) == (IB_WIDTH_1X | IB_WIDTH_4X)
2464                         && dd->ipath_link_width_active == IB_WIDTH_1X
2465                         && dd->ipath_x1_fix_tries < 3) {
2466                      if (++dd->ipath_x1_fix_tries == 3) {
2467                                 dev_info(&dd->pcidev->dev,
2468                                         "IB link is in 1X mode\n");
2469                                 if (!(dd->ipath_flags &
2470                                       IPATH_IB_AUTONEG_INPROG))
2471                                         symadj = 1;
2472                      }
2473                         else {
2474                                 ipath_cdbg(VERBOSE, "IB 1X in "
2475                                         "auto-width, try %u to be "
2476                                         "sure it's really 1X; "
2477                                         "ltstate %u\n",
2478                                          dd->ipath_x1_fix_tries,
2479                                          ltstate);
2480                                 dd->ipath_f_xgxs_reset(dd);
2481                                 ret = 1; /* skip other processing */
2482                         }
2483                 } else if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG))
2484                         symadj = 1;
2485
2486                 if (!ret) {
2487                         dd->delay_mult = rate_to_delay
2488                             [(ibcs >> IBA7220_IBCS_LINKSPEED_SHIFT) & 1]
2489                             [(ibcs >> IBA7220_IBCS_LINKWIDTH_SHIFT) & 1];
2490
2491                         ipath_set_relock_poll(dd, ibup);
2492                 }
2493         }
2494
2495         if (symadj) {
2496                 if (dd->ibdeltainprog) {
2497                         dd->ibdeltainprog = 0;
2498                         dd->ibsymdelta += ipath_read_creg32(dd,
2499                                 dd->ipath_cregs->cr_ibsymbolerrcnt) -
2500                                 dd->ibsymsnap;
2501                         dd->iblnkerrdelta += ipath_read_creg32(dd,
2502                                 dd->ipath_cregs->cr_iblinkerrrecovcnt) -
2503                                 dd->iblnkerrsnap;
2504                 }
2505         } else if (!ibup && !dd->ibdeltainprog
2506                    && !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG)) {
2507                 dd->ibdeltainprog = 1;
2508                 dd->ibsymsnap = ipath_read_creg32(dd,
2509                                      dd->ipath_cregs->cr_ibsymbolerrcnt);
2510                 dd->iblnkerrsnap = ipath_read_creg32(dd,
2511                                      dd->ipath_cregs->cr_iblinkerrrecovcnt);
2512         }
2513
2514         if (!ret)
2515                 ipath_setup_7220_setextled(dd, ipath_ib_linkstate(dd, ibcs),
2516                         ltstate);
2517         return ret;
2518 }
2519
2520
2521 /*
2522  * Handle the empirically determined mechanism for auto-negotiation
2523  * of DDR speed with switches.
2524  */
2525 static void autoneg_work(struct work_struct *work)
2526 {
2527         struct ipath_devdata *dd;
2528         u64 startms;
2529         u32 lastlts, i;
2530
2531         dd = container_of(work, struct ipath_devdata,
2532                 ipath_autoneg_work.work);
2533
2534         startms = jiffies_to_msecs(jiffies);
2535
2536         /*
2537          * busy wait for this first part, it should be at most a
2538          * few hundred usec, since we scheduled ourselves for 2msec.
2539          */
2540         for (i = 0; i < 25; i++) {
2541                 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat);
2542                 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
2543                         ipath_set_linkstate(dd, IPATH_IB_LINKDOWN_DISABLE);
2544                         break;
2545                 }
2546                 udelay(100);
2547         }
2548
2549         if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG))
2550                 goto done; /* we got there early or told to stop */
2551
2552         /* we expect this to timeout */
2553         if (wait_event_timeout(dd->ipath_autoneg_wait,
2554                 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2555                 msecs_to_jiffies(90)))
2556                 goto done;
2557
2558         ipath_toggle_rclkrls(dd);
2559
2560         /* we expect this to timeout */
2561         if (wait_event_timeout(dd->ipath_autoneg_wait,
2562                 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2563                 msecs_to_jiffies(1700)))
2564                 goto done;
2565
2566         set_speed_fast(dd, IPATH_IB_SDR);
2567         ipath_toggle_rclkrls(dd);
2568
2569         /*
2570          * wait up to 250 msec for link to train and get to INIT at DDR;
2571          * this should terminate early
2572          */
2573         wait_event_timeout(dd->ipath_autoneg_wait,
2574                 !(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG),
2575                 msecs_to_jiffies(250));
2576 done:
2577         if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
2578                 ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n",
2579                         ipath_ib_state(dd, dd->ipath_lastibcstat),
2580                         (unsigned long long) jiffies_to_msecs(jiffies)-startms);
2581                 dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG;
2582                 if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) {
2583                         dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED;
2584                         ipath_dbg("Giving up on DDR until next IB "
2585                                 "link Down\n");
2586                         dd->ipath_autoneg_tries = 0;
2587                 }
2588                 set_speed_fast(dd, dd->ipath_link_speed_enabled);
2589         }
2590 }
2591
2592
2593 /**
2594  * ipath_init_iba7220_funcs - set up the chip-specific function pointers
2595  * @dd: the infinipath device
2596  *
2597  * This is global, and is called directly at init to set up the
2598  * chip-specific function pointers for later use.
2599  */
2600 void ipath_init_iba7220_funcs(struct ipath_devdata *dd)
2601 {
2602         dd->ipath_f_intrsetup = ipath_7220_intconfig;
2603         dd->ipath_f_bus = ipath_setup_7220_config;
2604         dd->ipath_f_reset = ipath_setup_7220_reset;
2605         dd->ipath_f_get_boardname = ipath_7220_boardname;
2606         dd->ipath_f_init_hwerrors = ipath_7220_init_hwerrors;
2607         dd->ipath_f_early_init = ipath_7220_early_init;
2608         dd->ipath_f_handle_hwerrors = ipath_7220_handle_hwerrors;
2609         dd->ipath_f_quiet_serdes = ipath_7220_quiet_serdes;
2610         dd->ipath_f_bringup_serdes = ipath_7220_bringup_serdes;
2611         dd->ipath_f_clear_tids = ipath_7220_clear_tids;
2612         dd->ipath_f_put_tid = ipath_7220_put_tid;
2613         dd->ipath_f_cleanup = ipath_setup_7220_cleanup;
2614         dd->ipath_f_setextled = ipath_setup_7220_setextled;
2615         dd->ipath_f_get_base_info = ipath_7220_get_base_info;
2616         dd->ipath_f_free_irq = ipath_7220_free_irq;
2617         dd->ipath_f_tidtemplate = ipath_7220_tidtemplate;
2618         dd->ipath_f_intr_fallback = ipath_7220_intr_fallback;
2619         dd->ipath_f_xgxs_reset = ipath_7220_xgxs_reset;
2620         dd->ipath_f_get_ib_cfg = ipath_7220_get_ib_cfg;
2621         dd->ipath_f_set_ib_cfg = ipath_7220_set_ib_cfg;
2622         dd->ipath_f_config_jint = ipath_7220_config_jint;
2623         dd->ipath_f_config_ports = ipath_7220_config_ports;
2624         dd->ipath_f_read_counters = ipath_7220_read_counters;
2625         dd->ipath_f_get_msgheader = ipath_7220_get_msgheader;
2626         dd->ipath_f_ib_updown = ipath_7220_ib_updown;
2627
2628         /* initialize chip-specific variables */
2629         ipath_init_7220_variables(dd);
2630 }