git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005, 2006 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/time.h>
  21 #include <linux/pci.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/byteorder.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_cmnd.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/scsi_tcq.h>
  35
  36 #define DRV_NAME "stex"
  37 #define ST_DRIVER_VERSION "3.1.0.1"
  38 #define ST_VER_MAJOR            3
  39 #define ST_VER_MINOR            1
  40 #define ST_OEM                  0
  41 #define ST_BUILD_VER            1
  42
  43 enum {
  44         /* MU register offset */
  45         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  46         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  47         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  48         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  49         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  50         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  51         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  52         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  53         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  54         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  55
  56         /* MU register value */
  57         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
  58         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
  59         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
  60         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
  61         MU_INBOUND_DOORBELL_RESET               = 16,
  62
  63         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
  64         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  65         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
  66         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
  67         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
  68
  69         /* MU status code */
  70         MU_STATE_STARTING                       = 1,
  71         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
  72         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
  73         MU_STATE_STARTED                        = 4,
  74         MU_STATE_RESETTING                      = 5,
  75
  76         MU_MAX_DELAY                            = 120,
  77         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  78         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  79         MU_HARD_RESET_WAIT                      = 30000,
  80         HMU_PARTNER_TYPE                        = 2,
  81
  82         /* firmware returned values */
  83         SRB_STATUS_SUCCESS                      = 0x01,
  84         SRB_STATUS_ERROR                        = 0x04,
  85         SRB_STATUS_BUSY                         = 0x05,
  86         SRB_STATUS_INVALID_REQUEST              = 0x06,
  87         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  88         SRB_SEE_SENSE                           = 0x80,
  89
  90         /* task attribute */
  91         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
  92         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
  93         TASK_ATTRIBUTE_ORDERED                  = 0x2,
  94         TASK_ATTRIBUTE_ACA                      = 0x4,
  95
  96         /* request count, etc. */
  97         MU_MAX_REQUEST                          = 32,
  98
  99         /* one message wasted, use MU_MAX_REQUEST+1
 100                 to handle MU_MAX_REQUEST messages */
 101         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
 102         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
 103
 104         STEX_CDB_LENGTH                         = MAX_COMMAND_SIZE,
 105         REQ_VARIABLE_LEN                        = 1024,
 106         STATUS_VAR_LEN                          = 128,
 107         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
 108         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
 109         ST_MAX_SG                               = 32,
 110
 111         /* sg flags */
 112         SG_CF_EOT                               = 0x80, /* end of table */
 113         SG_CF_64B                               = 0x40, /* 64 bit item */
 114         SG_CF_HOST                              = 0x20, /* sg in host memory */
 115
 116         st_shasta                               = 0,
 117         st_vsc                                  = 1,
 118         st_vsc1                                 = 2,
 119         st_yosemite                             = 3,
 120
 121         PASSTHRU_REQ_TYPE                       = 0x00000001,
 122         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 123         ST_INTERNAL_TIMEOUT                     = 30,
 124
 125         ST_TO_CMD                               = 0,
 126         ST_FROM_CMD                             = 1,
 127
 128         /* vendor specific commands of Promise */
 129         MGT_CMD                                 = 0xd8,
 130         SINBAND_MGT_CMD                         = 0xd9,
 131         ARRAY_CMD                               = 0xe0,
 132         CONTROLLER_CMD                          = 0xe1,
 133         DEBUGGING_CMD                           = 0xe2,
 134         PASSTHRU_CMD                            = 0xe3,
 135
 136         PASSTHRU_GET_ADAPTER                    = 0x05,
 137         PASSTHRU_GET_DRVVER                     = 0x10,
 138
 139         CTLR_CONFIG_CMD                         = 0x03,
 140         CTLR_SHUTDOWN                           = 0x0d,
 141
 142         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 143         CTLR_POWER_SAVING                       = 0x01,
 144
 145         PASSTHRU_SIGNATURE                      = 0x4e415041,
 146         MGT_CMD_SIGNATURE                       = 0xba,
 147
 148         INQUIRY_EVPD                            = 0x01,
 149
 150         ST_ADDITIONAL_MEM                       = 0x200000,
 151 };
 152
 153 /* SCSI inquiry data */
 154 typedef struct st_inq {
 155         u8 DeviceType                   :5;
 156         u8 DeviceTypeQualifier          :3;
 157         u8 DeviceTypeModifier           :7;
 158         u8 RemovableMedia               :1;
 159         u8 Versions;
 160         u8 ResponseDataFormat           :4;
 161         u8 HiSupport                    :1;
 162         u8 NormACA                      :1;
 163         u8 ReservedBit                  :1;
 164         u8 AERC                         :1;
 165         u8 AdditionalLength;
 166         u8 Reserved[2];
 167         u8 SoftReset                    :1;
 168         u8 CommandQueue                 :1;
 169         u8 Reserved2                    :1;
 170         u8 LinkedCommands               :1;
 171         u8 Synchronous                  :1;
 172         u8 Wide16Bit                    :1;
 173         u8 Wide32Bit                    :1;
 174         u8 RelativeAddressing           :1;
 175         u8 VendorId[8];
 176         u8 ProductId[16];
 177         u8 ProductRevisionLevel[4];
 178         u8 VendorSpecific[20];
 179         u8 Reserved3[40];
 180 } ST_INQ;
 181
 182 struct st_sgitem {
 183         u8 ctrl;        /* SG_CF_xxx */
 184         u8 reserved[3];
 185         __le32 count;
 186         __le32 addr;
 187         __le32 addr_hi;
 188 };
 189
 190 struct st_sgtable {
 191         __le16 sg_count;
 192         __le16 max_sg_count;
 193         __le32 sz_in_byte;
 194         struct st_sgitem table[ST_MAX_SG];
 195 };
 196
 197 struct handshake_frame {
 198         __le32 rb_phy;          /* request payload queue physical address */
 199         __le32 rb_phy_hi;
 200         __le16 req_sz;          /* size of each request payload */
 201         __le16 req_cnt;         /* count of reqs the buffer can hold */
 202         __le16 status_sz;       /* size of each status payload */
 203         __le16 status_cnt;      /* count of status the buffer can hold */
 204         __le32 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 205         __le32 hosttime_hi;
 206         u8 partner_type;        /* who sends this frame */
 207         u8 reserved0[7];
 208         __le32 partner_ver_major;
 209         __le32 partner_ver_minor;
 210         __le32 partner_ver_oem;
 211         __le32 partner_ver_build;
 212         __le32 extra_offset;    /* NEW */
 213         __le32 extra_size;      /* NEW */
 214         u32 reserved1[2];
 215 };
 216
 217 struct req_msg {
 218         __le16 tag;
 219         u8 lun;
 220         u8 target;
 221         u8 task_attr;
 222         u8 task_manage;
 223         u8 prd_entry;
 224         u8 payload_sz;          /* payload size in 4-byte, not used */
 225         u8 cdb[STEX_CDB_LENGTH];
 226         u8 variable[REQ_VARIABLE_LEN];
 227 };
 228
 229 struct status_msg {
 230         __le16 tag;
 231         u8 lun;
 232         u8 target;
 233         u8 srb_status;
 234         u8 scsi_status;
 235         u8 reserved;
 236         u8 payload_sz;          /* payload size in 4-byte */
 237         u8 variable[STATUS_VAR_LEN];
 238 };
 239
 240 struct ver_info {
 241         u32 major;
 242         u32 minor;
 243         u32 oem;
 244         u32 build;
 245         u32 reserved[2];
 246 };
 247
 248 struct st_frame {
 249         u32 base[6];
 250         u32 rom_addr;
 251
 252         struct ver_info drv_ver;
 253         struct ver_info bios_ver;
 254
 255         u32 bus;
 256         u32 slot;
 257         u32 irq_level;
 258         u32 irq_vec;
 259         u32 id;
 260         u32 subid;
 261
 262         u32 dimm_size;
 263         u8 dimm_type;
 264         u8 reserved[3];
 265
 266         u32 channel;
 267         u32 reserved1;
 268 };
 269
 270 struct st_drvver {
 271         u32 major;
 272         u32 minor;
 273         u32 oem;
 274         u32 build;
 275         u32 signature[2];
 276         u8 console_id;
 277         u8 host_no;
 278         u8 reserved0[2];
 279         u32 reserved[3];
 280 };
 281
 282 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
 283 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
 284 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
 285 #define STEX_EXTRA_SIZE         max(sizeof(struct st_frame), sizeof(ST_INQ))
 286 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
 287
 288 struct st_ccb {
 289         struct req_msg *req;
 290         struct scsi_cmnd *cmd;
 291
 292         void *sense_buffer;
 293         unsigned int sense_bufflen;
 294         int sg_count;
 295
 296         u32 req_type;
 297         u8 srb_status;
 298         u8 scsi_status;
 299 };
 300
 301 struct st_hba {
 302         void __iomem *mmio_base;        /* iomapped PCI memory space */
 303         void *dma_mem;
 304         dma_addr_t dma_handle;
 305         size_t dma_size;
 306
 307         struct Scsi_Host *host;
 308         struct pci_dev *pdev;
 309
 310         u32 req_head;
 311         u32 req_tail;
 312         u32 status_head;
 313         u32 status_tail;
 314
 315         struct status_msg *status_buffer;
 316         void *copy_buffer; /* temp buffer for driver-handled commands */
 317         struct st_ccb ccb[MU_MAX_REQUEST];
 318         struct st_ccb *wait_ccb;
 319         wait_queue_head_t waitq;
 320
 321         unsigned int mu_status;
 322         int out_req_cnt;
 323
 324         unsigned int cardtype;
 325 };
 326
 327 static const char console_inq_page[] =
 328 {
 329         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 330         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 331         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 332         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 333         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 334         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 335         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 336         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 337 };
 338
 339 MODULE_AUTHOR("Ed Lin");
 340 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 341 MODULE_LICENSE("GPL");
 342 MODULE_VERSION(ST_DRIVER_VERSION);
 343
 344 static void stex_gettime(__le32 *time)
 345 {
 346         struct timeval tv;
 347         do_gettimeofday(&tv);
 348
 349         *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
 350         *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
 351 }
 352
 353 static struct status_msg *stex_get_status(struct st_hba *hba)
 354 {
 355         struct status_msg *status =
 356                 hba->status_buffer + hba->status_tail;
 357
 358         ++hba->status_tail;
 359         hba->status_tail %= MU_STATUS_COUNT;
 360
 361         return status;
 362 }
 363
 364 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
 365 {
 366         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 367
 368         cmd->sense_buffer[0] = 0x70;    /* fixed format, current */
 369         cmd->sense_buffer[2] = sk;
 370         cmd->sense_buffer[7] = 18 - 8;  /* additional sense length */
 371         cmd->sense_buffer[12] = asc;
 372         cmd->sense_buffer[13] = ascq;
 373 }
 374
 375 static void stex_invalid_field(struct scsi_cmnd *cmd,
 376                                void (*done)(struct scsi_cmnd *))
 377 {
 378         /* "Invalid field in cbd" */
 379         stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
 380         done(cmd);
 381 }
 382
 383 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 384 {
 385         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
 386                 hba->req_head;
 387
 388         ++hba->req_head;
 389         hba->req_head %= MU_REQ_COUNT;
 390
 391         return req;
 392 }
 393
 394 static int stex_map_sg(struct st_hba *hba,
 395         struct req_msg *req, struct st_ccb *ccb)
 396 {
 397         struct pci_dev *pdev = hba->pdev;
 398         struct scsi_cmnd *cmd;
 399         dma_addr_t dma_handle;
 400         struct scatterlist *src;
 401         struct st_sgtable *dst;
 402         int i;
 403
 404         cmd = ccb->cmd;
 405         dst = (struct st_sgtable *)req->variable;
 406         dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
 407         dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
 408
 409         if (cmd->use_sg) {
 410                 int n_elem;
 411
 412                 src = (struct scatterlist *) cmd->request_buffer;
 413                 n_elem = pci_map_sg(pdev, src,
 414                         cmd->use_sg, cmd->sc_data_direction);
 415                 if (n_elem <= 0)
 416                         return -EIO;
 417
 418                 ccb->sg_count = n_elem;
 419                 dst->sg_count = cpu_to_le16((u16)n_elem);
 420
 421                 for (i = 0; i < n_elem; i++, src++) {
 422                         dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
 423                         dst->table[i].addr =
 424                                 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
 425                         dst->table[i].addr_hi =
 426                                 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
 427                         dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 428                 }
 429                 dst->table[--i].ctrl |= SG_CF_EOT;
 430                 return 0;
 431         }
 432
 433         dma_handle = pci_map_single(pdev, cmd->request_buffer,
 434                 cmd->request_bufflen, cmd->sc_data_direction);
 435         cmd->SCp.dma_handle = dma_handle;
 436
 437         ccb->sg_count = 1;
 438         dst->sg_count = cpu_to_le16(1);
 439         dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
 440         dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
 441         dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
 442         dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
 443
 444         return 0;
 445 }
 446
 447 static void stex_internal_copy(struct scsi_cmnd *cmd,
 448         const void *src, size_t *count, int sg_count, int direction)
 449 {
 450         size_t lcount;
 451         size_t len;
 452         void *s, *d, *base = NULL;
 453         if (*count > cmd->request_bufflen)
 454                 *count = cmd->request_bufflen;
 455         lcount = *count;
 456         while (lcount) {
 457                 len = lcount;
 458                 s = (void *)src;
 459                 if (cmd->use_sg) {
 460                         size_t offset = *count - lcount;
 461                         s += offset;
 462                         base = scsi_kmap_atomic_sg(cmd->request_buffer,
 463                                 sg_count, &offset, &len);
 464                         if (base == NULL) {
 465                                 *count -= lcount;
 466                                 return;
 467                         }
 468                         d = base + offset;
 469                 } else
 470                         d = cmd->request_buffer;
 471
 472                 if (direction == ST_TO_CMD)
 473                         memcpy(d, s, len);
 474                 else
 475                         memcpy(s, d, len);
 476
 477                 lcount -= len;
 478                 if (cmd->use_sg)
 479                         scsi_kunmap_atomic_sg(base);
 480         }
 481 }
 482
 483 static int stex_direct_copy(struct scsi_cmnd *cmd,
 484         const void *src, size_t count)
 485 {
 486         struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
 487         size_t cp_len = count;
 488         int n_elem = 0;
 489
 490         if (cmd->use_sg) {
 491                 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
 492                         cmd->use_sg, cmd->sc_data_direction);
 493                 if (n_elem <= 0)
 494                         return 0;
 495         }
 496
 497         stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
 498
 499         if (cmd->use_sg)
 500                 pci_unmap_sg(hba->pdev, cmd->request_buffer,
 501                         cmd->use_sg, cmd->sc_data_direction);
 502         return cp_len == count;
 503 }
 504
 505 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 506 {
 507         struct st_frame *p;
 508         size_t count = sizeof(struct st_frame);
 509
 510         p = hba->copy_buffer;
 511         stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
 512         memset(p->base, 0, sizeof(u32)*6);
 513         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 514         p->rom_addr = 0;
 515
 516         p->drv_ver.major = ST_VER_MAJOR;
 517         p->drv_ver.minor = ST_VER_MINOR;
 518         p->drv_ver.oem = ST_OEM;
 519         p->drv_ver.build = ST_BUILD_VER;
 520
 521         p->bus = hba->pdev->bus->number;
 522         p->slot = hba->pdev->devfn;
 523         p->irq_level = 0;
 524         p->irq_vec = hba->pdev->irq;
 525         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 526         p->subid =
 527                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 528
 529         stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
 530 }
 531
 532 static void
 533 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 534 {
 535         req->tag = cpu_to_le16(tag);
 536         req->task_attr = TASK_ATTRIBUTE_SIMPLE;
 537         req->task_manage = 0; /* not supported yet */
 538
 539         hba->ccb[tag].req = req;
 540         hba->out_req_cnt++;
 541
 542         writel(hba->req_head, hba->mmio_base + IMR0);
 543         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 544         readl(hba->mmio_base + IDBL); /* flush */
 545 }
 546
 547 static int
 548 stex_slave_alloc(struct scsi_device *sdev)
 549 {
 550         /* Cheat: usually extracted from Inquiry data */
 551         sdev->tagged_supported = 1;
 552
 553         scsi_activate_tcq(sdev, sdev->host->can_queue);
 554
 555         return 0;
 556 }
 557
 558 static int
 559 stex_slave_config(struct scsi_device *sdev)
 560 {
 561         sdev->use_10_for_rw = 1;
 562         sdev->use_10_for_ms = 1;
 563         sdev->timeout = 60 * HZ;
 564         sdev->tagged_supported = 1;
 565
 566         return 0;
 567 }
 568
 569 static void
 570 stex_slave_destroy(struct scsi_device *sdev)
 571 {
 572         scsi_deactivate_tcq(sdev, 1);
 573 }
 574
 575 static int
 576 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 577 {
 578         struct st_hba *hba;
 579         struct Scsi_Host *host;
 580         unsigned int id,lun;
 581         struct req_msg *req;
 582         u16 tag;
 583         host = cmd->device->host;
 584         id = cmd->device->id;
 585         lun = cmd->device->lun;
 586         hba = (struct st_hba *) &host->hostdata[0];
 587
 588         switch (cmd->cmnd[0]) {
 589         case MODE_SENSE_10:
 590         {
 591                 static char ms10_caching_page[12] =
 592                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 593                 unsigned char page;
 594                 page = cmd->cmnd[2] & 0x3f;
 595                 if (page == 0x8 || page == 0x3f) {
 596                         stex_direct_copy(cmd, ms10_caching_page,
 597                                         sizeof(ms10_caching_page));
 598                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 599                         done(cmd);
 600                 } else
 601                         stex_invalid_field(cmd, done);
 602                 return 0;
 603         }
 604         case REPORT_LUNS:
 605                 /*
 606                  * The shasta firmware does not report actual luns in the
 607                  * target, so fail the command to force sequential lun scan.
 608                  * Also, the console device does not support this command.
 609                  */
 610                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 611                         stex_invalid_field(cmd, done);
 612                         return 0;
 613                 }
 614                 break;
 615         case TEST_UNIT_READY:
 616                 if (id == host->max_id - 1) {
 617                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 618                         done(cmd);
 619                         return 0;
 620                 }
 621                 break;
 622         case INQUIRY:
 623                 if (id != host->max_id - 1)
 624                         break;
 625                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 626                         stex_direct_copy(cmd, console_inq_page,
 627                                 sizeof(console_inq_page));
 628                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 629                         done(cmd);
 630                 } else
 631                         stex_invalid_field(cmd, done);
 632                 return 0;
 633         case PASSTHRU_CMD:
 634                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 635                         struct st_drvver ver;
 636                         ver.major = ST_VER_MAJOR;
 637                         ver.minor = ST_VER_MINOR;
 638                         ver.oem = ST_OEM;
 639                         ver.build = ST_BUILD_VER;
 640                         ver.signature[0] = PASSTHRU_SIGNATURE;
 641                         ver.console_id = host->max_id - 1;
 642                         ver.host_no = hba->host->host_no;
 643                         cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
 644                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 645                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 646                         done(cmd);
 647                         return 0;
 648                 }
 649         default:
 650                 break;
 651         }
 652
 653         cmd->scsi_done = done;
 654
 655         tag = cmd->request->tag;
 656
 657         if (unlikely(tag >= host->can_queue))
 658                 return SCSI_MLQUEUE_HOST_BUSY;
 659
 660         req = stex_alloc_req(hba);
 661
 662         req->lun = lun;
 663         req->target = id;
 664
 665         /* cdb */
 666         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 667
 668         hba->ccb[tag].cmd = cmd;
 669         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 670         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 671         hba->ccb[tag].req_type = 0;
 672
 673         if (cmd->sc_data_direction != DMA_NONE)
 674                 stex_map_sg(hba, req, &hba->ccb[tag]);
 675
 676         stex_send_cmd(hba, req, tag);
 677         return 0;
 678 }
 679
 680 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
 681 {
 682         if (cmd->sc_data_direction != DMA_NONE) {
 683                 if (cmd->use_sg)
 684                         pci_unmap_sg(hba->pdev, cmd->request_buffer,
 685                                 cmd->use_sg, cmd->sc_data_direction);
 686                 else
 687                         pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
 688                                 cmd->request_bufflen, cmd->sc_data_direction);
 689         }
 690 }
 691
 692 static void stex_scsi_done(struct st_ccb *ccb)
 693 {
 694         struct scsi_cmnd *cmd = ccb->cmd;
 695         int result;
 696
 697         if (ccb->srb_status == SRB_STATUS_SUCCESS ||  ccb->srb_status == 0) {
 698                 result = ccb->scsi_status;
 699                 switch (ccb->scsi_status) {
 700                 case SAM_STAT_GOOD:
 701                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 702                         break;
 703                 case SAM_STAT_CHECK_CONDITION:
 704                         result |= DRIVER_SENSE << 24;
 705                         break;
 706                 case SAM_STAT_BUSY:
 707                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 708                         break;
 709                 default:
 710                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 711                         break;
 712                 }
 713         }
 714         else if (ccb->srb_status & SRB_SEE_SENSE)
 715                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 716         else switch (ccb->srb_status) {
 717                 case SRB_STATUS_SELECTION_TIMEOUT:
 718                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 719                         break;
 720                 case SRB_STATUS_BUSY:
 721                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 722                         break;
 723                 case SRB_STATUS_INVALID_REQUEST:
 724                 case SRB_STATUS_ERROR:
 725                 default:
 726                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 727                         break;
 728         }
 729
 730         cmd->result = result;
 731         cmd->scsi_done(cmd);
 732 }
 733
 734 static void stex_copy_data(struct st_ccb *ccb,
 735         struct status_msg *resp, unsigned int variable)
 736 {
 737         size_t count = variable;
 738         if (resp->scsi_status != SAM_STAT_GOOD) {
 739                 if (ccb->sense_buffer != NULL)
 740                         memcpy(ccb->sense_buffer, resp->variable,
 741                                 min(variable, ccb->sense_bufflen));
 742                 return;
 743         }
 744
 745         if (ccb->cmd == NULL)
 746                 return;
 747         stex_internal_copy(ccb->cmd,
 748                 resp->variable, &count, ccb->sg_count, ST_TO_CMD);
 749 }
 750
 751 static void stex_ys_commands(struct st_hba *hba,
 752         struct st_ccb *ccb, struct status_msg *resp)
 753 {
 754         size_t count;
 755
 756         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 757                 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
 758                 ccb->cmd->request_bufflen =
 759                         le32_to_cpu(*(__le32 *)&resp->variable[0]);
 760                 return;
 761         }
 762
 763         if (resp->srb_status != 0)
 764                 return;
 765
 766         /* determine inquiry command status by DeviceTypeQualifier */
 767         if (ccb->cmd->cmnd[0] == INQUIRY &&
 768                 resp->scsi_status == SAM_STAT_GOOD) {
 769                 ST_INQ *inq_data;
 770
 771                 count = STEX_EXTRA_SIZE;
 772                 stex_internal_copy(ccb->cmd, hba->copy_buffer,
 773                         &count, ccb->sg_count, ST_FROM_CMD);
 774                 inq_data = (ST_INQ *)hba->copy_buffer;
 775                 if (inq_data->DeviceTypeQualifier != 0)
 776                         ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
 777                 else
 778                         ccb->srb_status = SRB_STATUS_SUCCESS;
 779         }
 780 }
 781
 782 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 783 {
 784         void __iomem *base = hba->mmio_base;
 785         struct status_msg *resp;
 786         struct st_ccb *ccb;
 787         unsigned int size;
 788         u16 tag;
 789
 790         if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
 791                 return;
 792
 793         /* status payloads */
 794         hba->status_head = readl(base + OMR1);
 795         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
 796                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 797                         pci_name(hba->pdev));
 798                 return;
 799         }
 800
 801         /*
 802          * it's not a valid status payload if:
 803          * 1. there are no pending requests(e.g. during init stage)
 804          * 2. there are some pending requests, but the controller is in
 805          *     reset status, and its type is not st_yosemite
 806          * firmware of st_yosemite in reset status will return pending requests
 807          * to driver, so we allow it to pass
 808          */
 809         if (unlikely(hba->out_req_cnt <= 0 ||
 810                         (hba->mu_status == MU_STATE_RESETTING &&
 811                          hba->cardtype != st_yosemite))) {
 812                 hba->status_tail = hba->status_head;
 813                 goto update_status;
 814         }
 815
 816         while (hba->status_tail != hba->status_head) {
 817                 resp = stex_get_status(hba);
 818                 tag = le16_to_cpu(resp->tag);
 819                 if (unlikely(tag >= hba->host->can_queue)) {
 820                         printk(KERN_WARNING DRV_NAME
 821                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 822                         continue;
 823                 }
 824
 825                 ccb = &hba->ccb[tag];
 826                 if (hba->wait_ccb == ccb)
 827                         hba->wait_ccb = NULL;
 828                 if (unlikely(ccb->req == NULL)) {
 829                         printk(KERN_WARNING DRV_NAME
 830                                 "(%s): lagging req\n", pci_name(hba->pdev));
 831                         hba->out_req_cnt--;
 832                         continue;
 833                 }
 834
 835                 size = resp->payload_sz * sizeof(u32); /* payload size */
 836                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 837                         size > sizeof(*resp))) {
 838                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 839                                 pci_name(hba->pdev));
 840                 } else {
 841                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 842                         if (size)
 843                                 stex_copy_data(ccb, resp, size);
 844                 }
 845
 846                 ccb->srb_status = resp->srb_status;
 847                 ccb->scsi_status = resp->scsi_status;
 848
 849                 if (likely(ccb->cmd != NULL)) {
 850                         if (hba->cardtype == st_yosemite)
 851                                 stex_ys_commands(hba, ccb, resp);
 852
 853                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 854                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 855                                 stex_controller_info(hba, ccb);
 856
 857                         stex_unmap_sg(hba, ccb->cmd);
 858                         stex_scsi_done(ccb);
 859                         hba->out_req_cnt--;
 860                 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
 861                         hba->out_req_cnt--;
 862                         if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
 863                                 ccb->req_type = 0;
 864                                 continue;
 865                         }
 866                         ccb->req_type = 0;
 867                         if (waitqueue_active(&hba->waitq))
 868                                 wake_up(&hba->waitq);
 869                 }
 870         }
 871
 872 update_status:
 873         writel(hba->status_head, base + IMR1);
 874         readl(base + IMR1); /* flush */
 875 }
 876
 877 static irqreturn_t stex_intr(int irq, void *__hba)
 878 {
 879         struct st_hba *hba = __hba;
 880         void __iomem *base = hba->mmio_base;
 881         u32 data;
 882         unsigned long flags;
 883         int handled = 0;
 884
 885         spin_lock_irqsave(hba->host->host_lock, flags);
 886
 887         data = readl(base + ODBL);
 888
 889         if (data && data != 0xffffffff) {
 890                 /* clear the interrupt */
 891                 writel(data, base + ODBL);
 892                 readl(base + ODBL); /* flush */
 893                 stex_mu_intr(hba, data);
 894                 handled = 1;
 895         }
 896
 897         spin_unlock_irqrestore(hba->host->host_lock, flags);
 898
 899         return IRQ_RETVAL(handled);
 900 }
 901
 902 static int stex_handshake(struct st_hba *hba)
 903 {
 904         void __iomem *base = hba->mmio_base;
 905         struct handshake_frame *h;
 906         dma_addr_t status_phys;
 907         u32 data;
 908         unsigned long before;
 909
 910         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 911                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 912                 readl(base + IDBL);
 913                 before = jiffies;
 914                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 915                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 916                                 printk(KERN_ERR DRV_NAME
 917                                         "(%s): no handshake signature\n",
 918                                         pci_name(hba->pdev));
 919                                 return -1;
 920                         }
 921                         rmb();
 922                         msleep(1);
 923                 }
 924         }
 925
 926         udelay(10);
 927
 928         data = readl(base + OMR1);
 929         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 930                 data &= 0x0000ffff;
 931                 if (hba->host->can_queue > data)
 932                         hba->host->can_queue = data;
 933         }
 934
 935         h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
 936         h->rb_phy = cpu_to_le32(hba->dma_handle);
 937         h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
 938         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
 939         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
 940         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 941         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
 942         stex_gettime(&h->hosttime);
 943         h->partner_type = HMU_PARTNER_TYPE;
 944         if (hba->dma_size > STEX_BUFFER_SIZE) {
 945                 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
 946                 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
 947         } else
 948                 h->extra_offset = h->extra_size = 0;
 949
 950         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
 951         writel(status_phys, base + IMR0);
 952         readl(base + IMR0);
 953         writel((status_phys >> 16) >> 16, base + IMR1);
 954         readl(base + IMR1);
 955
 956         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
 957         readl(base + OMR0);
 958         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 959         readl(base + IDBL); /* flush */
 960
 961         udelay(10);
 962         before = jiffies;
 963         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 964                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 965                         printk(KERN_ERR DRV_NAME
 966                                 "(%s): no signature after handshake frame\n",
 967                                 pci_name(hba->pdev));
 968                         return -1;
 969                 }
 970                 rmb();
 971                 msleep(1);
 972         }
 973
 974         writel(0, base + IMR0);
 975         readl(base + IMR0);
 976         writel(0, base + OMR0);
 977         readl(base + OMR0);
 978         writel(0, base + IMR1);
 979         readl(base + IMR1);
 980         writel(0, base + OMR1);
 981         readl(base + OMR1); /* flush */
 982         hba->mu_status = MU_STATE_STARTED;
 983         return 0;
 984 }
 985
 986 static int stex_abort(struct scsi_cmnd *cmd)
 987 {
 988         struct Scsi_Host *host = cmd->device->host;
 989         struct st_hba *hba = (struct st_hba *)host->hostdata;
 990         u16 tag = cmd->request->tag;
 991         void __iomem *base;
 992         u32 data;
 993         int result = SUCCESS;
 994         unsigned long flags;
 995         base = hba->mmio_base;
 996         spin_lock_irqsave(host->host_lock, flags);
 997         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
 998                 hba->wait_ccb = &hba->ccb[tag];
 999         else {
1000                 for (tag = 0; tag < host->can_queue; tag++)
1001                         if (hba->ccb[tag].cmd == cmd) {
1002                                 hba->wait_ccb = &hba->ccb[tag];
1003                                 break;
1004                         }
1005                 if (tag >= host->can_queue)
1006                         goto out;
1007         }
1008
1009         data = readl(base + ODBL);
1010         if (data == 0 || data == 0xffffffff)
1011                 goto fail_out;
1012
1013         writel(data, base + ODBL);
1014         readl(base + ODBL); /* flush */
1015
1016         stex_mu_intr(hba, data);
1017
1018         if (hba->wait_ccb == NULL) {
1019                 printk(KERN_WARNING DRV_NAME
1020                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1021                 goto out;
1022         }
1023
1024 fail_out:
1025         stex_unmap_sg(hba, cmd);
1026         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1027         hba->wait_ccb = NULL;
1028         result = FAILED;
1029 out:
1030         spin_unlock_irqrestore(host->host_lock, flags);
1031         return result;
1032 }
1033
1034 static void stex_hard_reset(struct st_hba *hba)
1035 {
1036         struct pci_bus *bus;
1037         int i;
1038         u16 pci_cmd;
1039         u8 pci_bctl;
1040
1041         for (i = 0; i < 16; i++)
1042                 pci_read_config_dword(hba->pdev, i * 4,
1043                         &hba->pdev->saved_config_space[i]);
1044
1045         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1046            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1047         bus = hba->pdev->bus;
1048         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1049         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1050         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1051
1052         /*
1053          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1054          * require more time to finish bus reset. Use 100 ms here for safety
1055          */
1056         msleep(100);
1057         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1058         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1059
1060         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1061                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1062                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1063                         break;
1064                 msleep(1);
1065         }
1066
1067         ssleep(5);
1068         for (i = 0; i < 16; i++)
1069                 pci_write_config_dword(hba->pdev, i * 4,
1070                         hba->pdev->saved_config_space[i]);
1071 }
1072
1073 static int stex_reset(struct scsi_cmnd *cmd)
1074 {
1075         struct st_hba *hba;
1076         unsigned long flags;
1077         unsigned long before;
1078         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1079
1080         hba->mu_status = MU_STATE_RESETTING;
1081
1082         if (hba->cardtype == st_shasta)
1083                 stex_hard_reset(hba);
1084
1085         if (hba->cardtype != st_yosemite) {
1086                 if (stex_handshake(hba)) {
1087                         printk(KERN_WARNING DRV_NAME
1088                                 "(%s): resetting: handshake failed\n",
1089                                 pci_name(hba->pdev));
1090                         return FAILED;
1091                 }
1092                 spin_lock_irqsave(hba->host->host_lock, flags);
1093                 hba->req_head = 0;
1094                 hba->req_tail = 0;
1095                 hba->status_head = 0;
1096                 hba->status_tail = 0;
1097                 hba->out_req_cnt = 0;
1098                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1099                 return SUCCESS;
1100         }
1101
1102         /* st_yosemite */
1103         writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1104         readl(hba->mmio_base + IDBL); /* flush */
1105         before = jiffies;
1106         while (hba->out_req_cnt > 0) {
1107                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1108                         printk(KERN_WARNING DRV_NAME
1109                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1110                         return FAILED;
1111                 }
1112                 msleep(1);
1113         }
1114
1115         hba->mu_status = MU_STATE_STARTED;
1116         return SUCCESS;
1117 }
1118
1119 static int stex_biosparam(struct scsi_device *sdev,
1120         struct block_device *bdev, sector_t capacity, int geom[])
1121 {
1122         int heads = 255, sectors = 63;
1123
1124         if (capacity < 0x200000) {
1125                 heads = 64;
1126                 sectors = 32;
1127         }
1128
1129         sector_div(capacity, heads * sectors);
1130
1131         geom[0] = heads;
1132         geom[1] = sectors;
1133         geom[2] = capacity;
1134
1135         return 0;
1136 }
1137
1138 static struct scsi_host_template driver_template = {
1139         .module                         = THIS_MODULE,
1140         .name                           = DRV_NAME,
1141         .proc_name                      = DRV_NAME,
1142         .bios_param                     = stex_biosparam,
1143         .queuecommand                   = stex_queuecommand,
1144         .slave_alloc                    = stex_slave_alloc,
1145         .slave_configure                = stex_slave_config,
1146         .slave_destroy                  = stex_slave_destroy,
1147         .eh_abort_handler               = stex_abort,
1148         .eh_host_reset_handler          = stex_reset,
1149         .can_queue                      = ST_CAN_QUEUE,
1150         .this_id                        = -1,
1151         .sg_tablesize                   = ST_MAX_SG,
1152         .cmd_per_lun                    = ST_CMD_PER_LUN,
1153 };
1154
1155 static int stex_set_dma_mask(struct pci_dev * pdev)
1156 {
1157         int ret;
1158         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1159                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1160                 return 0;
1161         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1162         if (!ret)
1163                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1164         return ret;
1165 }
1166
1167 static int __devinit
1168 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1169 {
1170         struct st_hba *hba;
1171         struct Scsi_Host *host;
1172         int err;
1173
1174         err = pci_enable_device(pdev);
1175         if (err)
1176                 return err;
1177
1178         pci_set_master(pdev);
1179
1180         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1181
1182         if (!host) {
1183                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1184                         pci_name(pdev));
1185                 err = -ENOMEM;
1186                 goto out_disable;
1187         }
1188
1189         hba = (struct st_hba *)host->hostdata;
1190         memset(hba, 0, sizeof(struct st_hba));
1191
1192         err = pci_request_regions(pdev, DRV_NAME);
1193         if (err < 0) {
1194                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1195                         pci_name(pdev));
1196                 goto out_scsi_host_put;
1197         }
1198
1199         hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1200                 pci_resource_len(pdev, 0));
1201         if ( !hba->mmio_base) {
1202                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1203                         pci_name(pdev));
1204                 err = -ENOMEM;
1205                 goto out_release_regions;
1206         }
1207
1208         err = stex_set_dma_mask(pdev);
1209         if (err) {
1210                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1211                         pci_name(pdev));
1212                 goto out_iounmap;
1213         }
1214
1215         hba->cardtype = (unsigned int) id->driver_data;
1216         if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1217                 hba->cardtype = st_vsc1;
1218         hba->dma_size = (hba->cardtype == st_vsc1) ?
1219                 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1220         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1221                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1222         if (!hba->dma_mem) {
1223                 err = -ENOMEM;
1224                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1225                         pci_name(pdev));
1226                 goto out_iounmap;
1227         }
1228
1229         hba->status_buffer =
1230                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1231         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1232         hba->mu_status = MU_STATE_STARTING;
1233
1234         if (hba->cardtype == st_shasta) {
1235                 host->max_lun = 8;
1236                 host->max_id = 16 + 1;
1237         } else if (hba->cardtype == st_yosemite) {
1238                 host->max_lun = 128;
1239                 host->max_id = 1 + 1;
1240         } else {
1241                 /* st_vsc and st_vsc1 */
1242                 host->max_lun = 1;
1243                 host->max_id = 128 + 1;
1244         }
1245         host->max_channel = 0;
1246         host->unique_id = host->host_no;
1247         host->max_cmd_len = STEX_CDB_LENGTH;
1248
1249         hba->host = host;
1250         hba->pdev = pdev;
1251         init_waitqueue_head(&hba->waitq);
1252
1253         err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1254         if (err) {
1255                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1256                         pci_name(pdev));
1257                 goto out_pci_free;
1258         }
1259
1260         err = stex_handshake(hba);
1261         if (err)
1262                 goto out_free_irq;
1263
1264         err = scsi_init_shared_tag_map(host, host->can_queue);
1265         if (err) {
1266                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1267                         pci_name(pdev));
1268                 goto out_free_irq;
1269         }
1270
1271         pci_set_drvdata(pdev, hba);
1272
1273         err = scsi_add_host(host, &pdev->dev);
1274         if (err) {
1275                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1276                         pci_name(pdev));
1277                 goto out_free_irq;
1278         }
1279
1280         scsi_scan_host(host);
1281
1282         return 0;
1283
1284 out_free_irq:
1285         free_irq(pdev->irq, hba);
1286 out_pci_free:
1287         dma_free_coherent(&pdev->dev, hba->dma_size,
1288                           hba->dma_mem, hba->dma_handle);
1289 out_iounmap:
1290         iounmap(hba->mmio_base);
1291 out_release_regions:
1292         pci_release_regions(pdev);
1293 out_scsi_host_put:
1294         scsi_host_put(host);
1295 out_disable:
1296         pci_disable_device(pdev);
1297
1298         return err;
1299 }
1300
1301 static void stex_hba_stop(struct st_hba *hba)
1302 {
1303         struct req_msg *req;
1304         unsigned long flags;
1305         unsigned long before;
1306         u16 tag = 0;
1307
1308         spin_lock_irqsave(hba->host->host_lock, flags);
1309         req = stex_alloc_req(hba);
1310         memset(req->cdb, 0, STEX_CDB_LENGTH);
1311
1312         if (hba->cardtype == st_yosemite) {
1313                 req->cdb[0] = MGT_CMD;
1314                 req->cdb[1] = MGT_CMD_SIGNATURE;
1315                 req->cdb[2] = CTLR_CONFIG_CMD;
1316                 req->cdb[3] = CTLR_SHUTDOWN;
1317         } else {
1318                 req->cdb[0] = CONTROLLER_CMD;
1319                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1320                 req->cdb[2] = CTLR_POWER_SAVING;
1321         }
1322
1323         hba->ccb[tag].cmd = NULL;
1324         hba->ccb[tag].sg_count = 0;
1325         hba->ccb[tag].sense_bufflen = 0;
1326         hba->ccb[tag].sense_buffer = NULL;
1327         hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1328
1329         stex_send_cmd(hba, req, tag);
1330         spin_unlock_irqrestore(hba->host->host_lock, flags);
1331
1332         before = jiffies;
1333         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1334                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1335                         return;
1336                 msleep(10);
1337         }
1338 }
1339
1340 static void stex_hba_free(struct st_hba *hba)
1341 {
1342         free_irq(hba->pdev->irq, hba);
1343
1344         iounmap(hba->mmio_base);
1345
1346         pci_release_regions(hba->pdev);
1347
1348         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1349                           hba->dma_mem, hba->dma_handle);
1350 }
1351
1352 static void stex_remove(struct pci_dev *pdev)
1353 {
1354         struct st_hba *hba = pci_get_drvdata(pdev);
1355
1356         scsi_remove_host(hba->host);
1357
1358         pci_set_drvdata(pdev, NULL);
1359
1360         stex_hba_stop(hba);
1361
1362         stex_hba_free(hba);
1363
1364         scsi_host_put(hba->host);
1365
1366         pci_disable_device(pdev);
1367 }
1368
1369 static void stex_shutdown(struct pci_dev *pdev)
1370 {
1371         struct st_hba *hba = pci_get_drvdata(pdev);
1372
1373         stex_hba_stop(hba);
1374 }
1375
1376 static struct pci_device_id stex_pci_tbl[] = {
1377         /* st_shasta */
1378         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1379                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1380         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1381                 st_shasta }, /* SuperTrak EX12350 */
1382         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1383                 st_shasta }, /* SuperTrak EX4350 */
1384         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1385                 st_shasta }, /* SuperTrak EX24350 */
1386
1387         /* st_vsc */
1388         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1389
1390         /* st_yosemite */
1391         { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1392                 st_yosemite }, /* SuperTrak EX4650 */
1393         { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1394                 st_yosemite }, /* SuperTrak EX4650o */
1395         { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1396                 st_yosemite }, /* SuperTrak EX8650EL */
1397         { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1398                 st_yosemite }, /* SuperTrak EX8650 */
1399         { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1400                 st_yosemite }, /* SuperTrak EX8654 */
1401         { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1402                 st_yosemite }, /* generic st_yosemite */
1403         { }     /* terminate list */
1404 };
1405 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1406
1407 static struct pci_driver stex_pci_driver = {
1408         .name           = DRV_NAME,
1409         .id_table       = stex_pci_tbl,
1410         .probe          = stex_probe,
1411         .remove         = __devexit_p(stex_remove),
1412         .shutdown       = stex_shutdown,
1413 };
1414
1415 static int __init stex_init(void)
1416 {
1417         printk(KERN_INFO DRV_NAME
1418                 ": Promise SuperTrak EX Driver version: %s\n",
1419                  ST_DRIVER_VERSION);
1420
1421         return pci_register_driver(&stex_pci_driver);
1422 }
1423
1424 static void __exit stex_exit(void)
1425 {
1426         pci_unregister_driver(&stex_pci_driver);
1427 }
1428
1429 module_init(stex_init);
1430 module_exit(stex_exit);