2 * linux/arch/arm/mach-clps7500/core.c
4 * Copyright (C) 1998 Russell King
5 * Copyright (C) 1999 Nexus Electronics Ltd
7 * Extra MM routines for CL7500 architecture
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/serial_8250.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/mach/irq.h>
21 #include <asm/mach/time.h>
23 #include <asm/hardware.h>
24 #include <asm/hardware/iomd.h>
27 #include <asm/mach-types.h>
29 unsigned int vram_size;
31 static void cl7500_ack_irq_a(unsigned int irq)
33 unsigned int val, mask;
36 val = iomd_readb(IOMD_IRQMASKA);
37 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
38 iomd_writeb(mask, IOMD_IRQCLRA);
41 static void cl7500_mask_irq_a(unsigned int irq)
43 unsigned int val, mask;
46 val = iomd_readb(IOMD_IRQMASKA);
47 iomd_writeb(val & ~mask, IOMD_IRQMASKA);
50 static void cl7500_unmask_irq_a(unsigned int irq)
52 unsigned int val, mask;
55 val = iomd_readb(IOMD_IRQMASKA);
56 iomd_writeb(val | mask, IOMD_IRQMASKA);
59 static struct irqchip clps7500_a_chip = {
60 .ack = cl7500_ack_irq_a,
61 .mask = cl7500_mask_irq_a,
62 .unmask = cl7500_unmask_irq_a,
65 static void cl7500_mask_irq_b(unsigned int irq)
67 unsigned int val, mask;
69 mask = 1 << (irq & 7);
70 val = iomd_readb(IOMD_IRQMASKB);
71 iomd_writeb(val & ~mask, IOMD_IRQMASKB);
74 static void cl7500_unmask_irq_b(unsigned int irq)
76 unsigned int val, mask;
78 mask = 1 << (irq & 7);
79 val = iomd_readb(IOMD_IRQMASKB);
80 iomd_writeb(val | mask, IOMD_IRQMASKB);
83 static struct irqchip clps7500_b_chip = {
84 .ack = cl7500_mask_irq_b,
85 .mask = cl7500_mask_irq_b,
86 .unmask = cl7500_unmask_irq_b,
89 static void cl7500_mask_irq_c(unsigned int irq)
91 unsigned int val, mask;
93 mask = 1 << (irq & 7);
94 val = iomd_readb(IOMD_IRQMASKC);
95 iomd_writeb(val & ~mask, IOMD_IRQMASKC);
98 static void cl7500_unmask_irq_c(unsigned int irq)
100 unsigned int val, mask;
102 mask = 1 << (irq & 7);
103 val = iomd_readb(IOMD_IRQMASKC);
104 iomd_writeb(val | mask, IOMD_IRQMASKC);
107 static struct irqchip clps7500_c_chip = {
108 .ack = cl7500_mask_irq_c,
109 .mask = cl7500_mask_irq_c,
110 .unmask = cl7500_unmask_irq_c,
113 static void cl7500_mask_irq_d(unsigned int irq)
115 unsigned int val, mask;
117 mask = 1 << (irq & 7);
118 val = iomd_readb(IOMD_IRQMASKD);
119 iomd_writeb(val & ~mask, IOMD_IRQMASKD);
122 static void cl7500_unmask_irq_d(unsigned int irq)
124 unsigned int val, mask;
126 mask = 1 << (irq & 7);
127 val = iomd_readb(IOMD_IRQMASKD);
128 iomd_writeb(val | mask, IOMD_IRQMASKD);
131 static struct irqchip clps7500_d_chip = {
132 .ack = cl7500_mask_irq_d,
133 .mask = cl7500_mask_irq_d,
134 .unmask = cl7500_unmask_irq_d,
137 static void cl7500_mask_irq_dma(unsigned int irq)
139 unsigned int val, mask;
141 mask = 1 << (irq & 7);
142 val = iomd_readb(IOMD_DMAMASK);
143 iomd_writeb(val & ~mask, IOMD_DMAMASK);
146 static void cl7500_unmask_irq_dma(unsigned int irq)
148 unsigned int val, mask;
150 mask = 1 << (irq & 7);
151 val = iomd_readb(IOMD_DMAMASK);
152 iomd_writeb(val | mask, IOMD_DMAMASK);
155 static struct irqchip clps7500_dma_chip = {
156 .ack = cl7500_mask_irq_dma,
157 .mask = cl7500_mask_irq_dma,
158 .unmask = cl7500_unmask_irq_dma,
161 static void cl7500_mask_irq_fiq(unsigned int irq)
163 unsigned int val, mask;
165 mask = 1 << (irq & 7);
166 val = iomd_readb(IOMD_FIQMASK);
167 iomd_writeb(val & ~mask, IOMD_FIQMASK);
170 static void cl7500_unmask_irq_fiq(unsigned int irq)
172 unsigned int val, mask;
174 mask = 1 << (irq & 7);
175 val = iomd_readb(IOMD_FIQMASK);
176 iomd_writeb(val | mask, IOMD_FIQMASK);
179 static struct irqchip clps7500_fiq_chip = {
180 .ack = cl7500_mask_irq_fiq,
181 .mask = cl7500_mask_irq_fiq,
182 .unmask = cl7500_unmask_irq_fiq,
185 static void cl7500_no_action(unsigned int irq)
189 static struct irqchip clps7500_no_chip = {
190 .ack = cl7500_no_action,
191 .mask = cl7500_no_action,
192 .unmask = cl7500_no_action,
195 static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL };
197 static void __init clps7500_init_irq(void)
199 unsigned int irq, flags;
201 iomd_writeb(0, IOMD_IRQMASKA);
202 iomd_writeb(0, IOMD_IRQMASKB);
203 iomd_writeb(0, IOMD_FIQMASK);
204 iomd_writeb(0, IOMD_DMAMASK);
206 for (irq = 0; irq < NR_IRQS; irq++) {
209 if (irq <= 6 || (irq >= 9 && irq <= 15) ||
210 (irq >= 48 && irq <= 55))
215 set_irq_chip(irq, &clps7500_a_chip);
216 set_irq_handler(irq, do_level_IRQ);
217 set_irq_flags(irq, flags);
221 set_irq_chip(irq, &clps7500_b_chip);
222 set_irq_handler(irq, do_level_IRQ);
223 set_irq_flags(irq, flags);
227 set_irq_chip(irq, &clps7500_dma_chip);
228 set_irq_handler(irq, do_level_IRQ);
229 set_irq_flags(irq, flags);
233 set_irq_chip(irq, &clps7500_c_chip);
234 set_irq_handler(irq, do_level_IRQ);
235 set_irq_flags(irq, flags);
239 set_irq_chip(irq, &clps7500_d_chip);
240 set_irq_handler(irq, do_level_IRQ);
241 set_irq_flags(irq, flags);
245 set_irq_chip(irq, &clps7500_no_chip);
246 set_irq_handler(irq, do_level_IRQ);
247 set_irq_flags(irq, flags);
251 set_irq_chip(irq, &clps7500_fiq_chip);
252 set_irq_handler(irq, do_level_IRQ);
253 set_irq_flags(irq, flags);
258 setup_irq(IRQ_ISA, &irq_isa);
261 static struct map_desc cl7500_io_desc[] __initdata = {
264 .pfn = __phys_to_pfn(IO_START),
269 .pfn = __phys_to_pfn(ISA_START),
273 .virtual = FLASH_BASE,
274 .pfn = __phys_to_pfn(FLASH_START),
275 .length = FLASH_SIZE,
279 .pfn = __phys_to_pfn(LED_START),
285 static void __init clps7500_map_io(void)
287 iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
290 extern void ioctime_init(void);
291 extern unsigned long ioc_timer_gettimeoffset(void);
294 clps7500_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
296 write_seqlock(&xtime_lock);
300 /* Why not using do_leds interface?? */
302 /* Twinkle the lights. */
303 static int count, state = 0xff00;
307 *((volatile unsigned int *)LED_ADDRESS) = state;
311 write_sequnlock(&xtime_lock);
316 static struct irqaction clps7500_timer_irq = {
317 .name = "CLPS7500 Timer Tick",
318 .flags = SA_INTERRUPT | SA_TIMER,
319 .handler = clps7500_timer_interrupt,
323 * Set up timer interrupt.
325 static void __init clps7500_timer_init(void)
328 setup_irq(IRQ_TIMER, &clps7500_timer_irq);
331 static struct sys_timer clps7500_timer = {
332 .init = clps7500_timer_init,
333 .offset = ioc_timer_gettimeoffset,
336 static struct plat_serial8250_port serial_platform_data[] = {
338 .mapbase = 0x03010fe0,
343 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
346 .mapbase = 0x03010be0,
351 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
354 .iobase = ISASLOT_IO + 0x2e8,
359 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
362 .iobase = ISASLOT_IO + 0x3e8,
367 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
372 static struct platform_device serial_device = {
373 .name = "serial8250",
374 .id = PLAT8250_DEV_PLATFORM,
376 .platform_data = serial_platform_data,
380 static void __init clps7500_init(void)
382 platform_device_register(&serial_device);
385 MACHINE_START(CLPS7500, "CL-PS7500")
386 /* Maintainer: Philip Blundell */
387 .phys_ram = 0x10000000,
388 .phys_io = 0x03000000,
389 .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
390 .map_io = clps7500_map_io,
391 .init_irq = clps7500_init_irq,
392 .init_machine = clps7500_init,
393 .timer = &clps7500_timer,