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   1 /*
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (c) 2001-2005 Silicon Graphics, Inc.  All rights reserved.
   8  */
   9
  10 #ifndef _ASM_IA64_SN_SHUB_MMR_H
  11 #define _ASM_IA64_SN_SHUB_MMR_H
  12
  13 /* ==================================================================== */
  14 /*                        Register "SH_IPI_INT"                         */
  15 /*               SHub Inter-Processor Interrupt Registers               */
  16 /* ==================================================================== */
  17 #define SH1_IPI_INT                               0x0000000110000380
  18 #define SH2_IPI_INT                               0x0000000010000380
  19
  20 /*   SH_IPI_INT_TYPE                                                    */
  21 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
  22 #define SH_IPI_INT_TYPE_SHFT                     0
  23 #define SH_IPI_INT_TYPE_MASK                     0x0000000000000007
  24
  25 /*   SH_IPI_INT_AGT                                                     */
  26 /*   Description:  Agent, must be 0 for SHub                            */
  27 #define SH_IPI_INT_AGT_SHFT                      3
  28 #define SH_IPI_INT_AGT_MASK                      0x0000000000000008
  29
  30 /*   SH_IPI_INT_PID                                                     */
  31 /*   Description:  Processor ID, same setting as on targeted McKinley  */
  32 #define SH_IPI_INT_PID_SHFT                      4
  33 #define SH_IPI_INT_PID_MASK                      0x00000000000ffff0
  34
  35 /*   SH_IPI_INT_BASE                                                    */
  36 /*   Description:  Optional interrupt vector area, 2MB aligned          */
  37 #define SH_IPI_INT_BASE_SHFT                     21
  38 #define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000
  39
  40 /*   SH_IPI_INT_IDX                                                     */
  41 /*   Description:  Targeted McKinley interrupt vector                   */
  42 #define SH_IPI_INT_IDX_SHFT                      52
  43 #define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000
  44
  45 /*   SH_IPI_INT_SEND                                                    */
  46 /*   Description:  Send Interrupt Message to PI, This generates a puls  */
  47 #define SH_IPI_INT_SEND_SHFT                     63
  48 #define SH_IPI_INT_SEND_MASK                     0x8000000000000000
  49
  50 /* ==================================================================== */
  51 /*                     Register "SH_EVENT_OCCURRED"                     */
  52 /*                    SHub Interrupt Event Occurred                     */
  53 /* ==================================================================== */
  54 #define SH1_EVENT_OCCURRED                        0x0000000110010000
  55 #define SH1_EVENT_OCCURRED_ALIAS                  0x0000000110010008
  56 #define SH2_EVENT_OCCURRED                        0x0000000010010000
  57 #define SH2_EVENT_OCCURRED_ALIAS                  0x0000000010010008
  58
  59 /* ==================================================================== */
  60 /*                     Register "SH_PI_CAM_CONTROL"                     */
  61 /*                      CRB CAM MMR Access Control                      */
  62 /* ==================================================================== */
  63 #define SH1_PI_CAM_CONTROL                        0x0000000120050300
  64
  65 /* ==================================================================== */
  66 /*                        Register "SH_SHUB_ID"                         */
  67 /*                            SHub ID Number                            */
  68 /* ==================================================================== */
  69 #define SH1_SHUB_ID                               0x0000000110060580
  70 #define SH1_SHUB_ID_REVISION_SHFT                 28
  71 #define SH1_SHUB_ID_REVISION_MASK                 0x00000000f0000000
  72
  73 /* ==================================================================== */
  74 /*                          Register "SH_RTC"                           */
  75 /*                           Real-time Clock                            */
  76 /* ==================================================================== */
  77 #define SH1_RTC                                   0x00000001101c0000
  78 #define SH2_RTC                                   0x00000002101c0000
  79 #define SH_RTC_MASK                               0x007fffffffffffff
  80
  81 /* ==================================================================== */
  82 /*                   Register "SH_PIO_WRITE_STATUS_0|1"                 */
  83 /*                      PIO Write Status for CPU 0 & 1                  */
  84 /* ==================================================================== */
  85 #define SH1_PIO_WRITE_STATUS_0                    0x0000000120070200
  86 #define SH1_PIO_WRITE_STATUS_1                    0x0000000120070280
  87 #define SH2_PIO_WRITE_STATUS_0                    0x0000000020070200
  88 #define SH2_PIO_WRITE_STATUS_1                    0x0000000020070280
  89 #define SH2_PIO_WRITE_STATUS_2                    0x0000000020070300
  90 #define SH2_PIO_WRITE_STATUS_3                    0x0000000020070380
  91
  92 /*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
  93 /*   Description:  Deadlock response detected                           */
  94 #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
  95 #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002
  96
  97 /*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
  98 /*   Description:  Count of currently pending PIO writes                */
  99 #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
 100 #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
 101
 102 /* ==================================================================== */
 103 /*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
 104 /* ==================================================================== */
 105 #define SH1_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208
 106 #define SH2_PIO_WRITE_STATUS_0_ALIAS              0x0000000020070208
 107
 108 /* ==================================================================== */
 109 /*                     Register "SH_EVENT_OCCURRED"                     */
 110 /*                    SHub Interrupt Event Occurred                     */
 111 /* ==================================================================== */
 112 /*   SH_EVENT_OCCURRED_UART_INT                                         */
 113 /*   Description:  Pending Junk Bus UART Interrupt                      */
 114 #define SH_EVENT_OCCURRED_UART_INT_SHFT          20
 115 #define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
 116
 117 /*   SH_EVENT_OCCURRED_IPI_INT                                          */
 118 /*   Description:  Pending IPI Interrupt                                */
 119 #define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
 120 #define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
 121
 122 /*   SH_EVENT_OCCURRED_II_INT0                                          */
 123 /*   Description:  Pending II 0 Interrupt                               */
 124 #define SH_EVENT_OCCURRED_II_INT0_SHFT           29
 125 #define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
 126
 127 /*   SH_EVENT_OCCURRED_II_INT1                                          */
 128 /*   Description:  Pending II 1 Interrupt                               */
 129 #define SH_EVENT_OCCURRED_II_INT1_SHFT           30
 130 #define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
 131
 132 /*   SH2_EVENT_OCCURRED_EXTIO_INT2                                      */
 133 /*   Description:  Pending SHUB 2 EXT IO INT2                           */
 134 #define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT       33
 135 #define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK       0x0000000200000000
 136
 137 /*   SH2_EVENT_OCCURRED_EXTIO_INT3                                      */
 138 /*   Description:  Pending SHUB 2 EXT IO INT3                           */
 139 #define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT       34
 140 #define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK       0x0000000400000000
 141
 142 #define SH_ALL_INT_MASK \
 143         (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
 144          SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
 145          SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
 146          SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
 147
 148
 149 /* ==================================================================== */
 150 /*                         LEDS                                         */
 151 /* ==================================================================== */
 152 #define SH1_REAL_JUNK_BUS_LED0                   0x7fed00000UL
 153 #define SH1_REAL_JUNK_BUS_LED1                   0x7fed10000UL
 154 #define SH1_REAL_JUNK_BUS_LED2                   0x7fed20000UL
 155 #define SH1_REAL_JUNK_BUS_LED3                   0x7fed30000UL
 156
 157 #define SH2_REAL_JUNK_BUS_LED0                   0xf0000000UL
 158 #define SH2_REAL_JUNK_BUS_LED1                   0xf0010000UL
 159 #define SH2_REAL_JUNK_BUS_LED2                   0xf0020000UL
 160 #define SH2_REAL_JUNK_BUS_LED3                   0xf0030000UL
 161
 162 /* ==================================================================== */
 163 /*                         Register "SH1_PTC_0"                         */
 164 /*       Puge Translation Cache Message Configuration Information       */
 165 /* ==================================================================== */
 166 #define SH1_PTC_0                                 0x00000001101a0000
 167
 168 /*   SH1_PTC_0_A                                                        */
 169 /*   Description:  Type                                                 */
 170 #define SH1_PTC_0_A_SHFT                          0
 171
 172 /*   SH1_PTC_0_PS                                                       */
 173 /*   Description:  Page Size                                            */
 174 #define SH1_PTC_0_PS_SHFT                         2
 175
 176 /*   SH1_PTC_0_RID                                                      */
 177 /*   Description:  Region ID                                            */
 178 #define SH1_PTC_0_RID_SHFT                        8
 179
 180 /*   SH1_PTC_0_START                                                    */
 181 /*   Description:  Start                                                */
 182 #define SH1_PTC_0_START_SHFT                      63
 183
 184 /* ==================================================================== */
 185 /*                         Register "SH1_PTC_1"                         */
 186 /*       Puge Translation Cache Message Configuration Information       */
 187 /* ==================================================================== */
 188 #define SH1_PTC_1                                 0x00000001101a0080
 189
 190 /*   SH1_PTC_1_START                                                    */
 191 /*   Description:  PTC_1 Start                                          */
 192 #define SH1_PTC_1_START_SHFT                      63
 193
 194
 195 /* ==================================================================== */
 196 /*                         Register "SH2_PTC"                           */
 197 /*       Puge Translation Cache Message Configuration Information       */
 198 /* ==================================================================== */
 199 #define SH2_PTC                                   0x0000000170000000
 200
 201 /*   SH2_PTC_A                                                          */
 202 /*   Description:  Type                                                 */
 203 #define SH2_PTC_A_SHFT                            0
 204
 205 /*   SH2_PTC_PS                                                         */
 206 /*   Description:  Page Size                                            */
 207 #define SH2_PTC_PS_SHFT                           2
 208
 209 /*   SH2_PTC_RID                                                      */
 210 /*   Description:  Region ID                                            */
 211 #define SH2_PTC_RID_SHFT                          4
 212
 213 /*   SH2_PTC_START                                                      */
 214 /*   Description:  Start                                                */
 215 #define SH2_PTC_START_SHFT                        63
 216
 217 /*   SH2_PTC_ADDR_RID                                                   */
 218 /*   Description:  Region ID                                            */
 219 #define SH2_PTC_ADDR_SHFT                         4
 220 #define SH2_PTC_ADDR_MASK                         0x1ffffffffffff000
 221
 222 /* ==================================================================== */
 223 /*                    Register "SH_RTC1_INT_CONFIG"                     */
 224 /*                SHub RTC 1 Interrupt Config Registers                 */
 225 /* ==================================================================== */
 226
 227 #define SH1_RTC1_INT_CONFIG                      0x0000000110001480
 228 #define SH2_RTC1_INT_CONFIG                      0x0000000010001480
 229 #define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 230 #define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
 231
 232 /*   SH_RTC1_INT_CONFIG_TYPE                                            */
 233 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 234 #define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
 235 #define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
 236
 237 /*   SH_RTC1_INT_CONFIG_AGT                                             */
 238 /*   Description:  Agent, must be 0 for SHub                            */
 239 #define SH_RTC1_INT_CONFIG_AGT_SHFT              3
 240 #define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
 241
 242 /*   SH_RTC1_INT_CONFIG_PID                                             */
 243 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 244 #define SH_RTC1_INT_CONFIG_PID_SHFT              4
 245 #define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
 246
 247 /*   SH_RTC1_INT_CONFIG_BASE                                            */
 248 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 249 #define SH_RTC1_INT_CONFIG_BASE_SHFT             21
 250 #define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 251
 252 /*   SH_RTC1_INT_CONFIG_IDX                                             */
 253 /*   Description:  Targeted McKinley interrupt vector                   */
 254 #define SH_RTC1_INT_CONFIG_IDX_SHFT              52
 255 #define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 256
 257 /* ==================================================================== */
 258 /*                    Register "SH_RTC1_INT_ENABLE"                     */
 259 /*                SHub RTC 1 Interrupt Enable Registers                 */
 260 /* ==================================================================== */
 261
 262 #define SH1_RTC1_INT_ENABLE                      0x0000000110001500
 263 #define SH2_RTC1_INT_ENABLE                      0x0000000010001500
 264 #define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
 265 #define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
 266
 267 /*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
 268 /*   Description:  Enable RTC 1 Interrupt                               */
 269 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
 270 #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
 271
 272 /* ==================================================================== */
 273 /*                    Register "SH_RTC2_INT_CONFIG"                     */
 274 /*                SHub RTC 2 Interrupt Config Registers                 */
 275 /* ==================================================================== */
 276
 277 #define SH1_RTC2_INT_CONFIG                      0x0000000110001580
 278 #define SH2_RTC2_INT_CONFIG                      0x0000000010001580
 279 #define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 280 #define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
 281
 282 /*   SH_RTC2_INT_CONFIG_TYPE                                            */
 283 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 284 #define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
 285 #define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
 286
 287 /*   SH_RTC2_INT_CONFIG_AGT                                             */
 288 /*   Description:  Agent, must be 0 for SHub                            */
 289 #define SH_RTC2_INT_CONFIG_AGT_SHFT              3
 290 #define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
 291
 292 /*   SH_RTC2_INT_CONFIG_PID                                             */
 293 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 294 #define SH_RTC2_INT_CONFIG_PID_SHFT              4
 295 #define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
 296
 297 /*   SH_RTC2_INT_CONFIG_BASE                                            */
 298 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 299 #define SH_RTC2_INT_CONFIG_BASE_SHFT             21
 300 #define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 301
 302 /*   SH_RTC2_INT_CONFIG_IDX                                             */
 303 /*   Description:  Targeted McKinley interrupt vector                   */
 304 #define SH_RTC2_INT_CONFIG_IDX_SHFT              52
 305 #define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 306
 307 /* ==================================================================== */
 308 /*                    Register "SH_RTC2_INT_ENABLE"                     */
 309 /*                SHub RTC 2 Interrupt Enable Registers                 */
 310 /* ==================================================================== */
 311
 312 #define SH1_RTC2_INT_ENABLE                      0x0000000110001600
 313 #define SH2_RTC2_INT_ENABLE                      0x0000000010001600
 314 #define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
 315 #define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
 316
 317 /*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
 318 /*   Description:  Enable RTC 2 Interrupt                               */
 319 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
 320 #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
 321
 322 /* ==================================================================== */
 323 /*                    Register "SH_RTC3_INT_CONFIG"                     */
 324 /*                SHub RTC 3 Interrupt Config Registers                 */
 325 /* ==================================================================== */
 326
 327 #define SH1_RTC3_INT_CONFIG                      0x0000000110001680
 328 #define SH2_RTC3_INT_CONFIG                      0x0000000010001680
 329 #define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
 330 #define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
 331
 332 /*   SH_RTC3_INT_CONFIG_TYPE                                            */
 333 /*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
 334 #define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
 335 #define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
 336
 337 /*   SH_RTC3_INT_CONFIG_AGT                                             */
 338 /*   Description:  Agent, must be 0 for SHub                            */
 339 #define SH_RTC3_INT_CONFIG_AGT_SHFT              3
 340 #define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
 341
 342 /*   SH_RTC3_INT_CONFIG_PID                                             */
 343 /*   Description:  Processor ID, same setting as on targeted McKinley  */
 344 #define SH_RTC3_INT_CONFIG_PID_SHFT              4
 345 #define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
 346
 347 /*   SH_RTC3_INT_CONFIG_BASE                                            */
 348 /*   Description:  Optional interrupt vector area, 2MB aligned          */
 349 #define SH_RTC3_INT_CONFIG_BASE_SHFT             21
 350 #define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
 351
 352 /*   SH_RTC3_INT_CONFIG_IDX                                             */
 353 /*   Description:  Targeted McKinley interrupt vector                   */
 354 #define SH_RTC3_INT_CONFIG_IDX_SHFT              52
 355 #define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
 356
 357 /* ==================================================================== */
 358 /*                    Register "SH_RTC3_INT_ENABLE"                     */
 359 /*                SHub RTC 3 Interrupt Enable Registers                 */
 360 /* ==================================================================== */
 361
 362 #define SH1_RTC3_INT_ENABLE                      0x0000000110001700
 363 #define SH2_RTC3_INT_ENABLE                      0x0000000010001700
 364 #define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
 365 #define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
 366
 367 /*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
 368 /*   Description:  Enable RTC 3 Interrupt                               */
 369 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
 370 #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
 371
 372 /*   SH_EVENT_OCCURRED_RTC1_INT                                         */
 373 /*   Description:  Pending RTC 1 Interrupt                              */
 374 #define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
 375 #define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
 376
 377 /*   SH_EVENT_OCCURRED_RTC2_INT                                         */
 378 /*   Description:  Pending RTC 2 Interrupt                              */
 379 #define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
 380 #define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
 381
 382 /*   SH_EVENT_OCCURRED_RTC3_INT                                         */
 383 /*   Description:  Pending RTC 3 Interrupt                              */
 384 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
 385 #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
 386
 387 /* ==================================================================== */
 388 /*                       Register "SH_IPI_ACCESS"                       */
 389 /*                 CPU interrupt Access Permission Bits                 */
 390 /* ==================================================================== */
 391
 392 #define SH1_IPI_ACCESS                           0x0000000110060480
 393 #define SH2_IPI_ACCESS0                          0x0000000010060c00
 394 #define SH2_IPI_ACCESS1                          0x0000000010060c80
 395 #define SH2_IPI_ACCESS2                          0x0000000010060d00
 396 #define SH2_IPI_ACCESS3                          0x0000000010060d80
 397
 398 /* ==================================================================== */
 399 /*                        Register "SH_INT_CMPB"                        */
 400 /*                  RTC Compare Value for Processor B                   */
 401 /* ==================================================================== */
 402
 403 #define SH1_INT_CMPB                             0x00000001101b0080
 404 #define SH2_INT_CMPB                             0x00000000101b0080
 405 #define SH_INT_CMPB_MASK                         0x007fffffffffffff
 406 #define SH_INT_CMPB_INIT                         0x0000000000000000
 407
 408 /*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
 409 /*   Description:  Real Time Clock Compare                              */
 410 #define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
 411 #define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
 412
 413 /* ==================================================================== */
 414 /*                        Register "SH_INT_CMPC"                        */
 415 /*                  RTC Compare Value for Processor C                   */
 416 /* ==================================================================== */
 417
 418 #define SH1_INT_CMPC                             0x00000001101b0100
 419 #define SH2_INT_CMPC                             0x00000000101b0100
 420 #define SH_INT_CMPC_MASK                         0x007fffffffffffff
 421 #define SH_INT_CMPC_INIT                         0x0000000000000000
 422
 423 /*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
 424 /*   Description:  Real Time Clock Compare                              */
 425 #define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
 426 #define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
 427
 428 /* ==================================================================== */
 429 /*                        Register "SH_INT_CMPD"                        */
 430 /*                  RTC Compare Value for Processor D                   */
 431 /* ==================================================================== */
 432
 433 #define SH1_INT_CMPD                             0x00000001101b0180
 434 #define SH2_INT_CMPD                             0x00000000101b0180
 435 #define SH_INT_CMPD_MASK                         0x007fffffffffffff
 436 #define SH_INT_CMPD_INIT                         0x0000000000000000
 437
 438 /*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
 439 /*   Description:  Real Time Clock Compare                              */
 440 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
 441 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
 442
 443 /* ==================================================================== */
 444 /*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
 445 /*                      privilege vector for acc=0                      */
 446 /* ==================================================================== */
 447
 448 #define SH1_MD_DQLP_MMR_DIR_PRIVEC0              0x0000000100030300
 449
 450 /* ==================================================================== */
 451 /*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
 452 /*                      privilege vector for acc=0                      */
 453 /* ==================================================================== */
 454
 455 #define SH1_MD_DQRP_MMR_DIR_PRIVEC0              0x0000000100050300
 456
 457 /* ==================================================================== */
 458 /* Some MMRs are functionally identical (or close enough) on both SHUB1 */
 459 /* and SHUB2 that it makes sense to define a geberic name for the MMR.  */
 460 /* It is acceptible to use (for example) SH_IPI_INT to reference the    */
 461 /* the IPI MMR. The value of SH_IPI_INT is determined at runtime based  */
 462 /* on the type of the SHUB. Do not use these #defines in performance    */
 463 /* critical code  or loops - there is a small performance penalty.      */
 464 /* ==================================================================== */
 465 #define shubmmr(a,b)            (is_shub2() ? a##2_##b : a##1_##b)
 466
 467 #define SH_REAL_JUNK_BUS_LED0   shubmmr(SH, REAL_JUNK_BUS_LED0)
 468 #define SH_IPI_INT              shubmmr(SH, IPI_INT)
 469 #define SH_EVENT_OCCURRED       shubmmr(SH, EVENT_OCCURRED)
 470 #define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
 471 #define SH_RTC                  shubmmr(SH, RTC)
 472 #define SH_RTC1_INT_CONFIG      shubmmr(SH, RTC1_INT_CONFIG)
 473 #define SH_RTC1_INT_ENABLE      shubmmr(SH, RTC1_INT_ENABLE)
 474 #define SH_RTC2_INT_CONFIG      shubmmr(SH, RTC2_INT_CONFIG)
 475 #define SH_RTC2_INT_ENABLE      shubmmr(SH, RTC2_INT_ENABLE)
 476 #define SH_RTC3_INT_CONFIG      shubmmr(SH, RTC3_INT_CONFIG)
 477 #define SH_RTC3_INT_ENABLE      shubmmr(SH, RTC3_INT_ENABLE)
 478 #define SH_INT_CMPB             shubmmr(SH, INT_CMPB)
 479 #define SH_INT_CMPC             shubmmr(SH, INT_CMPC)
 480 #define SH_INT_CMPD             shubmmr(SH, INT_CMPD)
 481
 482 /* ========================================================================== */
 483 /*                        Register "SH2_BT_ENG_CSR_0"                         */
 484 /*                    Engine 0 Control and Status Register                    */
 485 /* ========================================================================== */
 486
 487 #define SH2_BT_ENG_CSR_0                         0x0000000030040000
 488 #define SH2_BT_ENG_SRC_ADDR_0                    0x0000000030040080
 489 #define SH2_BT_ENG_DEST_ADDR_0                   0x0000000030040100
 490 #define SH2_BT_ENG_NOTIF_ADDR_0                  0x0000000030040180
 491
 492 /* ========================================================================== */
 493 /*                       BTE interfaces 1-3                                   */
 494 /* ========================================================================== */
 495
 496 #define SH2_BT_ENG_CSR_1                         0x0000000030050000
 497 #define SH2_BT_ENG_CSR_2                         0x0000000030060000
 498 #define SH2_BT_ENG_CSR_3                         0x0000000030070000
 499
 500 #endif /* _ASM_IA64_SN_SHUB_MMR_H */