2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
4 * MPC85xx Device descriptions
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
8 * Copyright 2005 Freescale Semiconductor Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/serial_8250.h>
20 #include <linux/fsl_devices.h>
21 #include <asm/mpc85xx.h>
23 #include <asm/ppc_sys.h>
25 /* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
28 struct gianfar_mdio_data mpc85xx_mdio_pdata = {
31 static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
32 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
33 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
34 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
37 static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
38 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
39 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
40 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
43 static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
51 static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
52 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
53 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
54 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
55 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
56 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
59 static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
60 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
61 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
62 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
63 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
64 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
68 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
69 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
70 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
71 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
72 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
75 static struct gianfar_platform_data mpc85xx_fec_pdata = {
79 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
80 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
83 static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
87 static struct plat_serial8250_port serial_platform_data[] = {
90 .irq = MPC85xx_IRQ_DUART,
92 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
96 .irq = MPC85xx_IRQ_DUART,
98 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
103 struct platform_device ppc_sys_platform_devices[] = {
105 .name = "fsl-gianfar",
107 .dev.platform_data = &mpc85xx_tsec1_pdata,
109 .resource = (struct resource[]) {
111 .start = MPC85xx_ENET1_OFFSET,
112 .end = MPC85xx_ENET1_OFFSET +
113 MPC85xx_ENET1_SIZE - 1,
114 .flags = IORESOURCE_MEM,
118 .start = MPC85xx_IRQ_TSEC1_TX,
119 .end = MPC85xx_IRQ_TSEC1_TX,
120 .flags = IORESOURCE_IRQ,
124 .start = MPC85xx_IRQ_TSEC1_RX,
125 .end = MPC85xx_IRQ_TSEC1_RX,
126 .flags = IORESOURCE_IRQ,
130 .start = MPC85xx_IRQ_TSEC1_ERROR,
131 .end = MPC85xx_IRQ_TSEC1_ERROR,
132 .flags = IORESOURCE_IRQ,
137 .name = "fsl-gianfar",
139 .dev.platform_data = &mpc85xx_tsec2_pdata,
141 .resource = (struct resource[]) {
143 .start = MPC85xx_ENET2_OFFSET,
144 .end = MPC85xx_ENET2_OFFSET +
145 MPC85xx_ENET2_SIZE - 1,
146 .flags = IORESOURCE_MEM,
150 .start = MPC85xx_IRQ_TSEC2_TX,
151 .end = MPC85xx_IRQ_TSEC2_TX,
152 .flags = IORESOURCE_IRQ,
156 .start = MPC85xx_IRQ_TSEC2_RX,
157 .end = MPC85xx_IRQ_TSEC2_RX,
158 .flags = IORESOURCE_IRQ,
162 .start = MPC85xx_IRQ_TSEC2_ERROR,
163 .end = MPC85xx_IRQ_TSEC2_ERROR,
164 .flags = IORESOURCE_IRQ,
169 .name = "fsl-gianfar",
171 .dev.platform_data = &mpc85xx_fec_pdata,
173 .resource = (struct resource[]) {
175 .start = MPC85xx_ENET3_OFFSET,
176 .end = MPC85xx_ENET3_OFFSET +
177 MPC85xx_ENET3_SIZE - 1,
178 .flags = IORESOURCE_MEM,
182 .start = MPC85xx_IRQ_FEC,
183 .end = MPC85xx_IRQ_FEC,
184 .flags = IORESOURCE_IRQ,
191 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
193 .resource = (struct resource[]) {
195 .start = MPC85xx_IIC1_OFFSET,
196 .end = MPC85xx_IIC1_OFFSET +
197 MPC85xx_IIC1_SIZE - 1,
198 .flags = IORESOURCE_MEM,
201 .start = MPC85xx_IRQ_IIC1,
202 .end = MPC85xx_IRQ_IIC1,
203 .flags = IORESOURCE_IRQ,
211 .resource = (struct resource[]) {
213 .start = MPC85xx_DMA0_OFFSET,
214 .end = MPC85xx_DMA0_OFFSET +
215 MPC85xx_DMA0_SIZE - 1,
216 .flags = IORESOURCE_MEM,
219 .start = MPC85xx_IRQ_DMA0,
220 .end = MPC85xx_IRQ_DMA0,
221 .flags = IORESOURCE_IRQ,
229 .resource = (struct resource[]) {
231 .start = MPC85xx_DMA1_OFFSET,
232 .end = MPC85xx_DMA1_OFFSET +
233 MPC85xx_DMA1_SIZE - 1,
234 .flags = IORESOURCE_MEM,
237 .start = MPC85xx_IRQ_DMA1,
238 .end = MPC85xx_IRQ_DMA1,
239 .flags = IORESOURCE_IRQ,
247 .resource = (struct resource[]) {
249 .start = MPC85xx_DMA2_OFFSET,
250 .end = MPC85xx_DMA2_OFFSET +
251 MPC85xx_DMA2_SIZE - 1,
252 .flags = IORESOURCE_MEM,
255 .start = MPC85xx_IRQ_DMA2,
256 .end = MPC85xx_IRQ_DMA2,
257 .flags = IORESOURCE_IRQ,
265 .resource = (struct resource[]) {
267 .start = MPC85xx_DMA3_OFFSET,
268 .end = MPC85xx_DMA3_OFFSET +
269 MPC85xx_DMA3_SIZE - 1,
270 .flags = IORESOURCE_MEM,
273 .start = MPC85xx_IRQ_DMA3,
274 .end = MPC85xx_IRQ_DMA3,
275 .flags = IORESOURCE_IRQ,
280 .name = "serial8250",
281 .id = PLAT8250_DEV_PLATFORM,
282 .dev.platform_data = serial_platform_data,
284 [MPC85xx_PERFMON] = {
285 .name = "fsl-perfmon",
288 .resource = (struct resource[]) {
290 .start = MPC85xx_PERFMON_OFFSET,
291 .end = MPC85xx_PERFMON_OFFSET +
292 MPC85xx_PERFMON_SIZE - 1,
293 .flags = IORESOURCE_MEM,
296 .start = MPC85xx_IRQ_PERFMON,
297 .end = MPC85xx_IRQ_PERFMON,
298 .flags = IORESOURCE_IRQ,
306 .resource = (struct resource[]) {
308 .start = MPC85xx_SEC2_OFFSET,
309 .end = MPC85xx_SEC2_OFFSET +
310 MPC85xx_SEC2_SIZE - 1,
311 .flags = IORESOURCE_MEM,
314 .start = MPC85xx_IRQ_SEC2,
315 .end = MPC85xx_IRQ_SEC2,
316 .flags = IORESOURCE_IRQ,
320 [MPC85xx_CPM_FCC1] = {
321 .name = "fsl-cpm-fcc",
324 .resource = (struct resource[]) {
328 .flags = IORESOURCE_MEM,
333 .flags = IORESOURCE_MEM,
336 .start = SIU_INT_FCC1,
338 .flags = IORESOURCE_IRQ,
342 [MPC85xx_CPM_FCC2] = {
343 .name = "fsl-cpm-fcc",
346 .resource = (struct resource[]) {
350 .flags = IORESOURCE_MEM,
355 .flags = IORESOURCE_MEM,
358 .start = SIU_INT_FCC2,
360 .flags = IORESOURCE_IRQ,
364 [MPC85xx_CPM_FCC3] = {
365 .name = "fsl-cpm-fcc",
368 .resource = (struct resource[]) {
372 .flags = IORESOURCE_MEM,
377 .flags = IORESOURCE_MEM,
380 .start = SIU_INT_FCC3,
382 .flags = IORESOURCE_IRQ,
386 [MPC85xx_CPM_I2C] = {
387 .name = "fsl-cpm-i2c",
390 .resource = (struct resource[]) {
394 .flags = IORESOURCE_MEM,
397 .start = SIU_INT_I2C,
399 .flags = IORESOURCE_IRQ,
403 [MPC85xx_CPM_SCC1] = {
404 .name = "fsl-cpm-scc",
407 .resource = (struct resource[]) {
411 .flags = IORESOURCE_MEM,
414 .start = SIU_INT_SCC1,
416 .flags = IORESOURCE_IRQ,
420 [MPC85xx_CPM_SCC2] = {
421 .name = "fsl-cpm-scc",
424 .resource = (struct resource[]) {
428 .flags = IORESOURCE_MEM,
431 .start = SIU_INT_SCC2,
433 .flags = IORESOURCE_IRQ,
437 [MPC85xx_CPM_SCC3] = {
438 .name = "fsl-cpm-scc",
441 .resource = (struct resource[]) {
445 .flags = IORESOURCE_MEM,
448 .start = SIU_INT_SCC3,
450 .flags = IORESOURCE_IRQ,
454 [MPC85xx_CPM_SCC4] = {
455 .name = "fsl-cpm-scc",
458 .resource = (struct resource[]) {
462 .flags = IORESOURCE_MEM,
465 .start = SIU_INT_SCC4,
467 .flags = IORESOURCE_IRQ,
471 [MPC85xx_CPM_SPI] = {
472 .name = "fsl-cpm-spi",
475 .resource = (struct resource[]) {
479 .flags = IORESOURCE_MEM,
482 .start = SIU_INT_SPI,
484 .flags = IORESOURCE_IRQ,
488 [MPC85xx_CPM_MCC1] = {
489 .name = "fsl-cpm-mcc",
492 .resource = (struct resource[]) {
496 .flags = IORESOURCE_MEM,
499 .start = SIU_INT_MCC1,
501 .flags = IORESOURCE_IRQ,
505 [MPC85xx_CPM_MCC2] = {
506 .name = "fsl-cpm-mcc",
509 .resource = (struct resource[]) {
513 .flags = IORESOURCE_MEM,
516 .start = SIU_INT_MCC2,
518 .flags = IORESOURCE_IRQ,
522 [MPC85xx_CPM_SMC1] = {
523 .name = "fsl-cpm-smc",
526 .resource = (struct resource[]) {
530 .flags = IORESOURCE_MEM,
533 .start = SIU_INT_SMC1,
535 .flags = IORESOURCE_IRQ,
539 [MPC85xx_CPM_SMC2] = {
540 .name = "fsl-cpm-smc",
543 .resource = (struct resource[]) {
547 .flags = IORESOURCE_MEM,
550 .start = SIU_INT_SMC2,
552 .flags = IORESOURCE_IRQ,
556 [MPC85xx_CPM_USB] = {
557 .name = "fsl-cpm-usb",
560 .resource = (struct resource[]) {
564 .flags = IORESOURCE_MEM,
567 .start = SIU_INT_USB,
569 .flags = IORESOURCE_IRQ,
574 .name = "fsl-gianfar",
576 .dev.platform_data = &mpc85xx_etsec1_pdata,
578 .resource = (struct resource[]) {
580 .start = MPC85xx_ENET1_OFFSET,
581 .end = MPC85xx_ENET1_OFFSET +
582 MPC85xx_ENET1_SIZE - 1,
583 .flags = IORESOURCE_MEM,
587 .start = MPC85xx_IRQ_TSEC1_TX,
588 .end = MPC85xx_IRQ_TSEC1_TX,
589 .flags = IORESOURCE_IRQ,
593 .start = MPC85xx_IRQ_TSEC1_RX,
594 .end = MPC85xx_IRQ_TSEC1_RX,
595 .flags = IORESOURCE_IRQ,
599 .start = MPC85xx_IRQ_TSEC1_ERROR,
600 .end = MPC85xx_IRQ_TSEC1_ERROR,
601 .flags = IORESOURCE_IRQ,
606 .name = "fsl-gianfar",
608 .dev.platform_data = &mpc85xx_etsec2_pdata,
610 .resource = (struct resource[]) {
612 .start = MPC85xx_ENET2_OFFSET,
613 .end = MPC85xx_ENET2_OFFSET +
614 MPC85xx_ENET2_SIZE - 1,
615 .flags = IORESOURCE_MEM,
619 .start = MPC85xx_IRQ_TSEC2_TX,
620 .end = MPC85xx_IRQ_TSEC2_TX,
621 .flags = IORESOURCE_IRQ,
625 .start = MPC85xx_IRQ_TSEC2_RX,
626 .end = MPC85xx_IRQ_TSEC2_RX,
627 .flags = IORESOURCE_IRQ,
631 .start = MPC85xx_IRQ_TSEC2_ERROR,
632 .end = MPC85xx_IRQ_TSEC2_ERROR,
633 .flags = IORESOURCE_IRQ,
638 .name = "fsl-gianfar",
640 .dev.platform_data = &mpc85xx_etsec3_pdata,
642 .resource = (struct resource[]) {
644 .start = MPC85xx_ENET3_OFFSET,
645 .end = MPC85xx_ENET3_OFFSET +
646 MPC85xx_ENET3_SIZE - 1,
647 .flags = IORESOURCE_MEM,
651 .start = MPC85xx_IRQ_TSEC3_TX,
652 .end = MPC85xx_IRQ_TSEC3_TX,
653 .flags = IORESOURCE_IRQ,
657 .start = MPC85xx_IRQ_TSEC3_RX,
658 .end = MPC85xx_IRQ_TSEC3_RX,
659 .flags = IORESOURCE_IRQ,
663 .start = MPC85xx_IRQ_TSEC3_ERROR,
664 .end = MPC85xx_IRQ_TSEC3_ERROR,
665 .flags = IORESOURCE_IRQ,
670 .name = "fsl-gianfar",
672 .dev.platform_data = &mpc85xx_etsec4_pdata,
674 .resource = (struct resource[]) {
678 .flags = IORESOURCE_MEM,
682 .start = MPC85xx_IRQ_TSEC4_TX,
683 .end = MPC85xx_IRQ_TSEC4_TX,
684 .flags = IORESOURCE_IRQ,
688 .start = MPC85xx_IRQ_TSEC4_RX,
689 .end = MPC85xx_IRQ_TSEC4_RX,
690 .flags = IORESOURCE_IRQ,
694 .start = MPC85xx_IRQ_TSEC4_ERROR,
695 .end = MPC85xx_IRQ_TSEC4_ERROR,
696 .flags = IORESOURCE_IRQ,
703 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
705 .resource = (struct resource[]) {
709 .flags = IORESOURCE_MEM,
712 .start = MPC85xx_IRQ_IIC1,
713 .end = MPC85xx_IRQ_IIC1,
714 .flags = IORESOURCE_IRQ,
719 .name = "fsl-gianfar_mdio",
721 .dev.platform_data = &mpc85xx_mdio_pdata,
723 .resource = (struct resource[]) {
727 .flags = IORESOURCE_MEM,
733 static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
735 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
739 static int __init mach_mpc85xx_init(void)
741 ppc_sys_device_fixup = mach_mpc85xx_fixup;
745 postcore_initcall(mach_mpc85xx_init);