3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
47 #include "phy_common.h"
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
103 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
147 .max_antenna_gain = 0, \
150 static struct ieee80211_channel b43_2ghz_chantable[] = {
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
173 .max_antenna_gain = 0, \
176 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
234 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
257 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
265 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
273 static struct ieee80211_supported_band b43_band_2GHz = {
274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
281 static void b43_wireless_core_exit(struct b43_wldev *dev);
282 static int b43_wireless_core_init(struct b43_wldev *dev);
283 static void b43_wireless_core_stop(struct b43_wldev *dev);
284 static int b43_wireless_core_start(struct b43_wldev *dev);
286 static int b43_ratelimit(struct b43_wl *wl)
288 if (!wl || !wl->current_dev)
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
297 void b43info(struct b43_wl *wl, const char *fmt, ...)
301 if (!b43_ratelimit(wl))
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
310 void b43err(struct b43_wl *wl, const char *fmt, ...)
314 if (!b43_ratelimit(wl))
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
323 void b43warn(struct b43_wl *wl, const char *fmt, ...)
327 if (!b43_ratelimit(wl))
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
337 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
353 B43_WARN_ON(offset % 4 != 0);
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
364 static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
369 /* "offset" is the WORD offset. */
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
376 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
380 if (routing == B43_SHM_SHARED) {
381 B43_WARN_ON(offset & 0x0001);
382 if (offset & 0x0003) {
383 /* Unaligned access */
384 b43_shm_control_word(dev, routing, offset >> 2);
385 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
387 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
388 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
394 b43_shm_control_word(dev, routing, offset);
395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
400 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
402 struct b43_wl *wl = dev->wl;
406 spin_lock_irqsave(&wl->shm_lock, flags);
407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
413 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
417 if (routing == B43_SHM_SHARED) {
418 B43_WARN_ON(offset & 0x0001);
419 if (offset & 0x0003) {
420 /* Unaligned access */
421 b43_shm_control_word(dev, routing, offset >> 2);
422 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
428 b43_shm_control_word(dev, routing, offset);
429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
434 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
436 struct b43_wl *wl = dev->wl;
440 spin_lock_irqsave(&wl->shm_lock, flags);
441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
447 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
449 if (routing == B43_SHM_SHARED) {
450 B43_WARN_ON(offset & 0x0001);
451 if (offset & 0x0003) {
452 /* Unaligned access */
453 b43_shm_control_word(dev, routing, offset >> 2);
454 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
455 (value >> 16) & 0xffff);
456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
462 b43_shm_control_word(dev, routing, offset);
463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
466 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
468 struct b43_wl *wl = dev->wl;
471 spin_lock_irqsave(&wl->shm_lock, flags);
472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
476 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
488 b43_shm_control_word(dev, routing, offset);
489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
492 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
494 struct b43_wl *wl = dev->wl;
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
499 spin_unlock_irqrestore(&wl->shm_lock, flags);
503 u64 b43_hf_read(struct b43_wldev * dev)
507 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
509 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
516 /* Write HostFlags */
517 void b43_hf_write(struct b43_wldev *dev, u64 value)
521 lo = (value & 0x00000000FFFFULL);
522 mi = (value & 0x0000FFFF0000ULL) >> 16;
523 hi = (value & 0xFFFF00000000ULL) >> 32;
524 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
529 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
531 /* We need to be careful. As we read the TSF from multiple
532 * registers, we should take care of register overflows.
533 * In theory, the whole tsf read process should be atomic.
534 * We try to be atomic here, by restaring the read process,
535 * if any of the high registers changed (overflew).
537 if (dev->dev->id.revision >= 3) {
538 u32 low, high, high2;
541 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
542 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
543 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
544 } while (unlikely(high != high2));
552 u16 test1, test2, test3;
555 v3 = b43_read16(dev, B43_MMIO_TSF_3);
556 v2 = b43_read16(dev, B43_MMIO_TSF_2);
557 v1 = b43_read16(dev, B43_MMIO_TSF_1);
558 v0 = b43_read16(dev, B43_MMIO_TSF_0);
560 test3 = b43_read16(dev, B43_MMIO_TSF_3);
561 test2 = b43_read16(dev, B43_MMIO_TSF_2);
562 test1 = b43_read16(dev, B43_MMIO_TSF_1);
563 } while (v3 != test3 || v2 != test2 || v1 != test1);
577 static void b43_time_lock(struct b43_wldev *dev)
581 macctl = b43_read32(dev, B43_MMIO_MACCTL);
582 macctl |= B43_MACCTL_TBTTHOLD;
583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
588 static void b43_time_unlock(struct b43_wldev *dev)
592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
593 macctl &= ~B43_MACCTL_TBTTHOLD;
594 b43_write32(dev, B43_MMIO_MACCTL, macctl);
595 /* Commit the write */
596 b43_read32(dev, B43_MMIO_MACCTL);
599 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
601 /* Be careful with the in-progress timer.
602 * First zero out the low register, so we have a full
603 * register-overflow duration to complete the operation.
605 if (dev->dev->id.revision >= 3) {
606 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
607 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
615 u16 v0 = (tsf & 0x000000000000FFFFULL);
616 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
617 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
618 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
620 b43_write16(dev, B43_MMIO_TSF_0, 0);
622 b43_write16(dev, B43_MMIO_TSF_3, v3);
624 b43_write16(dev, B43_MMIO_TSF_2, v2);
626 b43_write16(dev, B43_MMIO_TSF_1, v1);
628 b43_write16(dev, B43_MMIO_TSF_0, v0);
632 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
635 b43_tsf_write_locked(dev, tsf);
636 b43_time_unlock(dev);
640 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
642 static const u8 zero_addr[ETH_ALEN] = { 0 };
649 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
653 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
656 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
662 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
666 u8 mac_bssid[ETH_ALEN * 2];
670 bssid = dev->wl->bssid;
671 mac = dev->wl->mac_addr;
673 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
675 memcpy(mac_bssid, mac, ETH_ALEN);
676 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
678 /* Write our MAC address and BSSID to template ram */
679 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
680 tmp = (u32) (mac_bssid[i + 0]);
681 tmp |= (u32) (mac_bssid[i + 1]) << 8;
682 tmp |= (u32) (mac_bssid[i + 2]) << 16;
683 tmp |= (u32) (mac_bssid[i + 3]) << 24;
684 b43_ram_write(dev, 0x20 + i, tmp);
688 static void b43_upload_card_macaddress(struct b43_wldev *dev)
690 b43_write_mac_bssid_templates(dev);
691 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
694 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
696 /* slot_time is in usec. */
697 if (dev->phy.type != B43_PHYTYPE_G)
699 b43_write16(dev, 0x684, 510 + slot_time);
700 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
703 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
705 b43_set_slot_time(dev, 9);
709 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
711 b43_set_slot_time(dev, 20);
715 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
716 * Returns the _previously_ enabled IRQ mask.
718 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
722 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
723 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
728 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
729 * Returns the _previously_ enabled IRQ mask.
731 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
735 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
736 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
741 /* Synchronize IRQ top- and bottom-half.
742 * IRQs must be masked before calling this.
743 * This must not be called with the irq_lock held.
745 static void b43_synchronize_irq(struct b43_wldev *dev)
747 synchronize_irq(dev->dev->irq);
748 tasklet_kill(&dev->isr_tasklet);
751 /* DummyTransmission function, as documented on
752 * http://bcm-specs.sipsolutions.net/DummyTransmission
754 void b43_dummy_transmission(struct b43_wldev *dev)
756 struct b43_wl *wl = dev->wl;
757 struct b43_phy *phy = &dev->phy;
758 unsigned int i, max_loop;
771 buffer[0] = 0x000201CC;
776 buffer[0] = 0x000B846E;
783 spin_lock_irq(&wl->irq_lock);
784 write_lock(&wl->tx_lock);
786 for (i = 0; i < 5; i++)
787 b43_ram_write(dev, i * 4, buffer[i]);
790 b43_read32(dev, B43_MMIO_MACCTL);
792 b43_write16(dev, 0x0568, 0x0000);
793 b43_write16(dev, 0x07C0, 0x0000);
794 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
795 b43_write16(dev, 0x050C, value);
796 b43_write16(dev, 0x0508, 0x0000);
797 b43_write16(dev, 0x050A, 0x0000);
798 b43_write16(dev, 0x054C, 0x0000);
799 b43_write16(dev, 0x056A, 0x0014);
800 b43_write16(dev, 0x0568, 0x0826);
801 b43_write16(dev, 0x0500, 0x0000);
802 b43_write16(dev, 0x0502, 0x0030);
804 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
805 b43_radio_write16(dev, 0x0051, 0x0017);
806 for (i = 0x00; i < max_loop; i++) {
807 value = b43_read16(dev, 0x050E);
812 for (i = 0x00; i < 0x0A; i++) {
813 value = b43_read16(dev, 0x050E);
818 for (i = 0x00; i < 0x19; i++) {
819 value = b43_read16(dev, 0x0690);
820 if (!(value & 0x0100))
824 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
825 b43_radio_write16(dev, 0x0051, 0x0037);
827 write_unlock(&wl->tx_lock);
828 spin_unlock_irq(&wl->irq_lock);
831 static void key_write(struct b43_wldev *dev,
832 u8 index, u8 algorithm, const u8 * key)
839 /* Key index/algo block */
840 kidx = b43_kidx_to_fw(dev, index);
841 value = ((kidx << 4) | algorithm);
842 b43_shm_write16(dev, B43_SHM_SHARED,
843 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
845 /* Write the key to the Key Table Pointer offset */
846 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
847 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
849 value |= (u16) (key[i + 1]) << 8;
850 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
854 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
856 u32 addrtmp[2] = { 0, 0, };
857 u8 per_sta_keys_start = 8;
859 if (b43_new_kidx_api(dev))
860 per_sta_keys_start = 4;
862 B43_WARN_ON(index < per_sta_keys_start);
863 /* We have two default TX keys and possibly two default RX keys.
864 * Physical mac 0 is mapped to physical key 4 or 8, depending
865 * on the firmware version.
866 * So we must adjust the index here.
868 index -= per_sta_keys_start;
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
879 if (dev->dev->id.revision >= 5) {
880 /* Receive match transmitter address mechanism */
881 b43_shm_write32(dev, B43_SHM_RCMTA,
882 (index * 2) + 0, addrtmp[0]);
883 b43_shm_write16(dev, B43_SHM_RCMTA,
884 (index * 2) + 1, addrtmp[1]);
886 /* RXE (Receive Engine) and
887 * PSM (Programmable State Machine) mechanism
890 /* TODO write to RCM 16, 19, 22 and 25 */
892 b43_shm_write32(dev, B43_SHM_SHARED,
893 B43_SHM_SH_PSM + (index * 6) + 0,
895 b43_shm_write16(dev, B43_SHM_SHARED,
896 B43_SHM_SH_PSM + (index * 6) + 4,
902 static void do_key_write(struct b43_wldev *dev,
903 u8 index, u8 algorithm,
904 const u8 * key, size_t key_len, const u8 * mac_addr)
906 u8 buf[B43_SEC_KEYSIZE] = { 0, };
907 u8 per_sta_keys_start = 8;
909 if (b43_new_kidx_api(dev))
910 per_sta_keys_start = 4;
912 B43_WARN_ON(index >= dev->max_nr_keys);
913 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
915 if (index >= per_sta_keys_start)
916 keymac_write(dev, index, NULL); /* First zero out mac. */
918 memcpy(buf, key, key_len);
919 key_write(dev, index, algorithm, buf);
920 if (index >= per_sta_keys_start)
921 keymac_write(dev, index, mac_addr);
923 dev->key[index].algorithm = algorithm;
926 static int b43_key_write(struct b43_wldev *dev,
927 int index, u8 algorithm,
928 const u8 * key, size_t key_len,
930 struct ieee80211_key_conf *keyconf)
935 if (key_len > B43_SEC_KEYSIZE)
937 for (i = 0; i < dev->max_nr_keys; i++) {
938 /* Check that we don't already have this key. */
939 B43_WARN_ON(dev->key[i].keyconf == keyconf);
942 /* Either pairwise key or address is 00:00:00:00:00:00
943 * for transmit-only keys. Search the index. */
944 if (b43_new_kidx_api(dev))
948 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
949 if (!dev->key[i].keyconf) {
956 b43err(dev->wl, "Out of hardware key memory\n");
960 B43_WARN_ON(index > 3);
962 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
963 if ((index <= 3) && !b43_new_kidx_api(dev)) {
965 B43_WARN_ON(mac_addr);
966 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
968 keyconf->hw_key_idx = index;
969 dev->key[index].keyconf = keyconf;
974 static int b43_key_clear(struct b43_wldev *dev, int index)
976 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
978 do_key_write(dev, index, B43_SEC_ALGO_NONE,
979 NULL, B43_SEC_KEYSIZE, NULL);
980 if ((index <= 3) && !b43_new_kidx_api(dev)) {
981 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
982 NULL, B43_SEC_KEYSIZE, NULL);
984 dev->key[index].keyconf = NULL;
989 static void b43_clear_keys(struct b43_wldev *dev)
993 for (i = 0; i < dev->max_nr_keys; i++)
994 b43_key_clear(dev, i);
997 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1005 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1006 (ps_flags & B43_PS_DISABLED));
1007 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1009 if (ps_flags & B43_PS_ENABLED) {
1011 } else if (ps_flags & B43_PS_DISABLED) {
1014 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1015 // and thus is not an AP and we are associated, set bit 25
1017 if (ps_flags & B43_PS_AWAKE) {
1019 } else if (ps_flags & B43_PS_ASLEEP) {
1022 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1023 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1024 // successful, set bit26
1027 /* FIXME: For now we force awake-on and hwps-off */
1031 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1033 macctl |= B43_MACCTL_HWPS;
1035 macctl &= ~B43_MACCTL_HWPS;
1037 macctl |= B43_MACCTL_AWAKE;
1039 macctl &= ~B43_MACCTL_AWAKE;
1040 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1042 b43_read32(dev, B43_MMIO_MACCTL);
1043 if (awake && dev->dev->id.revision >= 5) {
1044 /* Wait for the microcode to wake up. */
1045 for (i = 0; i < 100; i++) {
1046 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1047 B43_SHM_SH_UCODESTAT);
1048 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1055 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1060 flags |= B43_TMSLOW_PHYCLKEN;
1061 flags |= B43_TMSLOW_PHYRESET;
1062 ssb_device_enable(dev->dev, flags);
1063 msleep(2); /* Wait for the PLL to turn on. */
1065 /* Now take the PHY out of Reset again */
1066 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1067 tmslow |= SSB_TMSLOW_FGC;
1068 tmslow &= ~B43_TMSLOW_PHYRESET;
1069 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1070 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1072 tmslow &= ~SSB_TMSLOW_FGC;
1073 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1074 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1077 /* Turn Analog ON, but only if we already know the PHY-type.
1078 * This protects against very early setup where we don't know the
1079 * PHY-type, yet. wireless_core_reset will be called once again later,
1080 * when we know the PHY-type. */
1082 dev->phy.ops->switch_analog(dev, 1);
1084 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1085 macctl &= ~B43_MACCTL_GMODE;
1086 if (flags & B43_TMSLOW_GMODE)
1087 macctl |= B43_MACCTL_GMODE;
1088 macctl |= B43_MACCTL_IHR_ENABLED;
1089 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1092 static void handle_irq_transmit_status(struct b43_wldev *dev)
1096 struct b43_txstatus stat;
1099 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1100 if (!(v0 & 0x00000001))
1102 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1104 stat.cookie = (v0 >> 16);
1105 stat.seq = (v1 & 0x0000FFFF);
1106 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1107 tmp = (v0 & 0x0000FFFF);
1108 stat.frame_count = ((tmp & 0xF000) >> 12);
1109 stat.rts_count = ((tmp & 0x0F00) >> 8);
1110 stat.supp_reason = ((tmp & 0x001C) >> 2);
1111 stat.pm_indicated = !!(tmp & 0x0080);
1112 stat.intermediate = !!(tmp & 0x0040);
1113 stat.for_ampdu = !!(tmp & 0x0020);
1114 stat.acked = !!(tmp & 0x0002);
1116 b43_handle_txstatus(dev, &stat);
1120 static void drain_txstatus_queue(struct b43_wldev *dev)
1124 if (dev->dev->id.revision < 5)
1126 /* Read all entries from the microcode TXstatus FIFO
1127 * and throw them away.
1130 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1131 if (!(dummy & 0x00000001))
1133 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1137 static u32 b43_jssi_read(struct b43_wldev *dev)
1141 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1143 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1148 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1150 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1151 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1154 static void b43_generate_noise_sample(struct b43_wldev *dev)
1156 b43_jssi_write(dev, 0x7F7F7F7F);
1157 b43_write32(dev, B43_MMIO_MACCMD,
1158 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1161 static void b43_calculate_link_quality(struct b43_wldev *dev)
1163 /* Top half of Link Quality calculation. */
1165 if (dev->phy.type != B43_PHYTYPE_G)
1167 if (dev->noisecalc.calculation_running)
1169 dev->noisecalc.calculation_running = 1;
1170 dev->noisecalc.nr_samples = 0;
1172 b43_generate_noise_sample(dev);
1175 static void handle_irq_noise(struct b43_wldev *dev)
1177 struct b43_phy_g *phy = dev->phy.g;
1183 /* Bottom half of Link Quality calculation. */
1185 if (dev->phy.type != B43_PHYTYPE_G)
1188 /* Possible race condition: It might be possible that the user
1189 * changed to a different channel in the meantime since we
1190 * started the calculation. We ignore that fact, since it's
1191 * not really that much of a problem. The background noise is
1192 * an estimation only anyway. Slightly wrong results will get damped
1193 * by the averaging of the 8 sample rounds. Additionally the
1194 * value is shortlived. So it will be replaced by the next noise
1195 * calculation round soon. */
1197 B43_WARN_ON(!dev->noisecalc.calculation_running);
1198 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1199 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1200 noise[2] == 0x7F || noise[3] == 0x7F)
1203 /* Get the noise samples. */
1204 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1205 i = dev->noisecalc.nr_samples;
1206 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1207 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1208 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1209 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1210 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1211 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1212 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1213 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1214 dev->noisecalc.nr_samples++;
1215 if (dev->noisecalc.nr_samples == 8) {
1216 /* Calculate the Link Quality by the noise samples. */
1218 for (i = 0; i < 8; i++) {
1219 for (j = 0; j < 4; j++)
1220 average += dev->noisecalc.samples[i][j];
1226 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1227 tmp = (tmp / 128) & 0x1F;
1237 dev->stats.link_noise = average;
1238 dev->noisecalc.calculation_running = 0;
1242 b43_generate_noise_sample(dev);
1245 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1247 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1250 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1251 b43_power_saving_ctl_bits(dev, 0);
1253 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1257 static void handle_irq_atim_end(struct b43_wldev *dev)
1259 if (dev->dfq_valid) {
1260 b43_write32(dev, B43_MMIO_MACCMD,
1261 b43_read32(dev, B43_MMIO_MACCMD)
1262 | B43_MACCMD_DFQ_VALID);
1267 static void handle_irq_pmq(struct b43_wldev *dev)
1274 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1275 if (!(tmp & 0x00000008))
1278 /* 16bit write is odd, but correct. */
1279 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1282 static void b43_write_template_common(struct b43_wldev *dev,
1283 const u8 * data, u16 size,
1285 u16 shm_size_offset, u8 rate)
1288 struct b43_plcp_hdr4 plcp;
1291 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1292 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1293 ram_offset += sizeof(u32);
1294 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1295 * So leave the first two bytes of the next write blank.
1297 tmp = (u32) (data[0]) << 16;
1298 tmp |= (u32) (data[1]) << 24;
1299 b43_ram_write(dev, ram_offset, tmp);
1300 ram_offset += sizeof(u32);
1301 for (i = 2; i < size; i += sizeof(u32)) {
1302 tmp = (u32) (data[i + 0]);
1304 tmp |= (u32) (data[i + 1]) << 8;
1306 tmp |= (u32) (data[i + 2]) << 16;
1308 tmp |= (u32) (data[i + 3]) << 24;
1309 b43_ram_write(dev, ram_offset + i - 2, tmp);
1311 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1312 size + sizeof(struct b43_plcp_hdr6));
1315 /* Check if the use of the antenna that ieee80211 told us to
1316 * use is possible. This will fall back to DEFAULT.
1317 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1318 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1323 if (antenna_nr == 0) {
1324 /* Zero means "use default antenna". That's always OK. */
1328 /* Get the mask of available antennas. */
1330 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1332 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1334 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1335 /* This antenna is not available. Fall back to default. */
1342 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
1344 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
1346 case 0: /* default/diversity */
1347 return B43_ANTENNA_DEFAULT;
1348 case 1: /* Antenna 0 */
1349 return B43_ANTENNA0;
1350 case 2: /* Antenna 1 */
1351 return B43_ANTENNA1;
1352 case 3: /* Antenna 2 */
1353 return B43_ANTENNA2;
1354 case 4: /* Antenna 3 */
1355 return B43_ANTENNA3;
1357 return B43_ANTENNA_DEFAULT;
1361 /* Convert a b43 antenna number value to the PHY TX control value. */
1362 static u16 b43_antenna_to_phyctl(int antenna)
1366 return B43_TXH_PHY_ANT0;
1368 return B43_TXH_PHY_ANT1;
1370 return B43_TXH_PHY_ANT2;
1372 return B43_TXH_PHY_ANT3;
1373 case B43_ANTENNA_AUTO:
1374 return B43_TXH_PHY_ANT01AUTO;
1380 static void b43_write_beacon_template(struct b43_wldev *dev,
1382 u16 shm_size_offset)
1384 unsigned int i, len, variable_len;
1385 const struct ieee80211_mgmt *bcn;
1391 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1393 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1394 len = min((size_t) dev->wl->current_beacon->len,
1395 0x200 - sizeof(struct b43_plcp_hdr6));
1396 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1398 b43_write_template_common(dev, (const u8 *)bcn,
1399 len, ram_offset, shm_size_offset, rate);
1401 /* Write the PHY TX control parameters. */
1402 antenna = b43_antenna_from_ieee80211(dev, info->antenna_sel_tx);
1403 antenna = b43_antenna_to_phyctl(antenna);
1404 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1405 /* We can't send beacons with short preamble. Would get PHY errors. */
1406 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1407 ctl &= ~B43_TXH_PHY_ANT;
1408 ctl &= ~B43_TXH_PHY_ENC;
1410 if (b43_is_cck_rate(rate))
1411 ctl |= B43_TXH_PHY_ENC_CCK;
1413 ctl |= B43_TXH_PHY_ENC_OFDM;
1414 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1416 /* Find the position of the TIM and the DTIM_period value
1417 * and write them to SHM. */
1418 ie = bcn->u.beacon.variable;
1419 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1420 for (i = 0; i < variable_len - 2; ) {
1421 uint8_t ie_id, ie_len;
1428 /* This is the TIM Information Element */
1430 /* Check whether the ie_len is in the beacon data range. */
1431 if (variable_len < ie_len + 2 + i)
1433 /* A valid TIM is at least 4 bytes long. */
1438 tim_position = sizeof(struct b43_plcp_hdr6);
1439 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1442 dtim_period = ie[i + 3];
1444 b43_shm_write16(dev, B43_SHM_SHARED,
1445 B43_SHM_SH_TIMBPOS, tim_position);
1446 b43_shm_write16(dev, B43_SHM_SHARED,
1447 B43_SHM_SH_DTIMPER, dtim_period);
1454 * If ucode wants to modify TIM do it behind the beacon, this
1455 * will happen, for example, when doing mesh networking.
1457 b43_shm_write16(dev, B43_SHM_SHARED,
1459 len + sizeof(struct b43_plcp_hdr6));
1460 b43_shm_write16(dev, B43_SHM_SHARED,
1461 B43_SHM_SH_DTIMPER, 0);
1463 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1466 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1467 u16 shm_offset, u16 size,
1468 struct ieee80211_rate *rate)
1470 struct b43_plcp_hdr4 plcp;
1475 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1476 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1479 /* Write PLCP in two parts and timing for packet transfer */
1480 tmp = le32_to_cpu(plcp.data);
1481 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1482 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1483 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1486 /* Instead of using custom probe response template, this function
1487 * just patches custom beacon template by:
1488 * 1) Changing packet type
1489 * 2) Patching duration field
1492 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1494 struct ieee80211_rate *rate)
1498 u16 src_size, elem_size, src_pos, dest_pos;
1500 struct ieee80211_hdr *hdr;
1503 src_size = dev->wl->current_beacon->len;
1504 src_data = (const u8 *)dev->wl->current_beacon->data;
1506 /* Get the start offset of the variable IEs in the packet. */
1507 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1508 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1510 if (B43_WARN_ON(src_size < ie_start))
1513 dest_data = kmalloc(src_size, GFP_ATOMIC);
1514 if (unlikely(!dest_data))
1517 /* Copy the static data and all Information Elements, except the TIM. */
1518 memcpy(dest_data, src_data, ie_start);
1520 dest_pos = ie_start;
1521 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1522 elem_size = src_data[src_pos + 1] + 2;
1523 if (src_data[src_pos] == 5) {
1524 /* This is the TIM. */
1527 memcpy(dest_data + dest_pos, src_data + src_pos,
1529 dest_pos += elem_size;
1531 *dest_size = dest_pos;
1532 hdr = (struct ieee80211_hdr *)dest_data;
1534 /* Set the frame control. */
1535 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1536 IEEE80211_STYPE_PROBE_RESP);
1537 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1538 dev->wl->vif, *dest_size,
1540 hdr->duration_id = dur;
1545 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1547 u16 shm_size_offset,
1548 struct ieee80211_rate *rate)
1550 const u8 *probe_resp_data;
1553 size = dev->wl->current_beacon->len;
1554 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1555 if (unlikely(!probe_resp_data))
1558 /* Looks like PLCP headers plus packet timings are stored for
1559 * all possible basic rates
1561 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1562 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1563 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1564 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1566 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1567 b43_write_template_common(dev, probe_resp_data,
1568 size, ram_offset, shm_size_offset,
1570 kfree(probe_resp_data);
1573 static void b43_upload_beacon0(struct b43_wldev *dev)
1575 struct b43_wl *wl = dev->wl;
1577 if (wl->beacon0_uploaded)
1579 b43_write_beacon_template(dev, 0x68, 0x18);
1580 /* FIXME: Probe resp upload doesn't really belong here,
1581 * but we don't use that feature anyway. */
1582 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1583 &__b43_ratetable[3]);
1584 wl->beacon0_uploaded = 1;
1587 static void b43_upload_beacon1(struct b43_wldev *dev)
1589 struct b43_wl *wl = dev->wl;
1591 if (wl->beacon1_uploaded)
1593 b43_write_beacon_template(dev, 0x468, 0x1A);
1594 wl->beacon1_uploaded = 1;
1597 static void handle_irq_beacon(struct b43_wldev *dev)
1599 struct b43_wl *wl = dev->wl;
1600 u32 cmd, beacon0_valid, beacon1_valid;
1602 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1603 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1606 /* This is the bottom half of the asynchronous beacon update. */
1608 /* Ignore interrupt in the future. */
1609 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1611 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1612 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1613 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1615 /* Schedule interrupt manually, if busy. */
1616 if (beacon0_valid && beacon1_valid) {
1617 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1618 dev->irq_savedstate |= B43_IRQ_BEACON;
1622 if (unlikely(wl->beacon_templates_virgin)) {
1623 /* We never uploaded a beacon before.
1624 * Upload both templates now, but only mark one valid. */
1625 wl->beacon_templates_virgin = 0;
1626 b43_upload_beacon0(dev);
1627 b43_upload_beacon1(dev);
1628 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1629 cmd |= B43_MACCMD_BEACON0_VALID;
1630 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1632 if (!beacon0_valid) {
1633 b43_upload_beacon0(dev);
1634 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1635 cmd |= B43_MACCMD_BEACON0_VALID;
1636 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1637 } else if (!beacon1_valid) {
1638 b43_upload_beacon1(dev);
1639 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1640 cmd |= B43_MACCMD_BEACON1_VALID;
1641 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1646 static void b43_beacon_update_trigger_work(struct work_struct *work)
1648 struct b43_wl *wl = container_of(work, struct b43_wl,
1649 beacon_update_trigger);
1650 struct b43_wldev *dev;
1652 mutex_lock(&wl->mutex);
1653 dev = wl->current_dev;
1654 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1655 spin_lock_irq(&wl->irq_lock);
1656 /* update beacon right away or defer to irq */
1657 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1658 handle_irq_beacon(dev);
1659 /* The handler might have updated the IRQ mask. */
1660 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1661 dev->irq_savedstate);
1663 spin_unlock_irq(&wl->irq_lock);
1665 mutex_unlock(&wl->mutex);
1668 /* Asynchronously update the packet templates in template RAM.
1669 * Locking: Requires wl->irq_lock to be locked. */
1670 static void b43_update_templates(struct b43_wl *wl)
1672 struct sk_buff *beacon;
1674 /* This is the top half of the ansynchronous beacon update.
1675 * The bottom half is the beacon IRQ.
1676 * Beacon update must be asynchronous to avoid sending an
1677 * invalid beacon. This can happen for example, if the firmware
1678 * transmits a beacon while we are updating it. */
1680 /* We could modify the existing beacon and set the aid bit in
1681 * the TIM field, but that would probably require resizing and
1682 * moving of data within the beacon template.
1683 * Simply request a new beacon and let mac80211 do the hard work. */
1684 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1685 if (unlikely(!beacon))
1688 if (wl->current_beacon)
1689 dev_kfree_skb_any(wl->current_beacon);
1690 wl->current_beacon = beacon;
1691 wl->beacon0_uploaded = 0;
1692 wl->beacon1_uploaded = 0;
1693 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1696 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1701 len = min((u16) ssid_len, (u16) 0x100);
1702 for (i = 0; i < len; i += sizeof(u32)) {
1703 tmp = (u32) (ssid[i + 0]);
1705 tmp |= (u32) (ssid[i + 1]) << 8;
1707 tmp |= (u32) (ssid[i + 2]) << 16;
1709 tmp |= (u32) (ssid[i + 3]) << 24;
1710 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1712 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1715 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1718 if (dev->dev->id.revision >= 3) {
1719 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1720 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1722 b43_write16(dev, 0x606, (beacon_int >> 6));
1723 b43_write16(dev, 0x610, beacon_int);
1725 b43_time_unlock(dev);
1726 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1729 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1733 /* Read the register that contains the reason code for the panic. */
1734 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1735 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1739 b43dbg(dev->wl, "The panic reason is unknown.\n");
1741 case B43_FWPANIC_DIE:
1742 /* Do not restart the controller or firmware.
1743 * The device is nonfunctional from now on.
1744 * Restarting would result in this panic to trigger again,
1745 * so we avoid that recursion. */
1747 case B43_FWPANIC_RESTART:
1748 b43_controller_restart(dev, "Microcode panic");
1753 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1755 unsigned int i, cnt;
1756 u16 reason, marker_id, marker_line;
1759 /* The proprietary firmware doesn't have this IRQ. */
1760 if (!dev->fw.opensource)
1763 /* Read the register that contains the reason code for this IRQ. */
1764 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1767 case B43_DEBUGIRQ_PANIC:
1768 b43_handle_firmware_panic(dev);
1770 case B43_DEBUGIRQ_DUMP_SHM:
1772 break; /* Only with driver debugging enabled. */
1773 buf = kmalloc(4096, GFP_ATOMIC);
1775 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1778 for (i = 0; i < 4096; i += 2) {
1779 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1780 buf[i / 2] = cpu_to_le16(tmp);
1782 b43info(dev->wl, "Shared memory dump:\n");
1783 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1784 16, 2, buf, 4096, 1);
1787 case B43_DEBUGIRQ_DUMP_REGS:
1789 break; /* Only with driver debugging enabled. */
1790 b43info(dev->wl, "Microcode register dump:\n");
1791 for (i = 0, cnt = 0; i < 64; i++) {
1792 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1795 printk("r%02u: 0x%04X ", i, tmp);
1804 case B43_DEBUGIRQ_MARKER:
1806 break; /* Only with driver debugging enabled. */
1807 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1809 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1810 B43_MARKER_LINE_REG);
1811 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1812 "at line number %u\n",
1813 marker_id, marker_line);
1816 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1820 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1821 b43_shm_write16(dev, B43_SHM_SCRATCH,
1822 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1825 /* Interrupt handler bottom-half */
1826 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1829 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1830 u32 merged_dma_reason = 0;
1832 unsigned long flags;
1834 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1836 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1838 reason = dev->irq_reason;
1839 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1840 dma_reason[i] = dev->dma_reason[i];
1841 merged_dma_reason |= dma_reason[i];
1844 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1845 b43err(dev->wl, "MAC transmission error\n");
1847 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1848 b43err(dev->wl, "PHY transmission error\n");
1850 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1851 atomic_set(&dev->phy.txerr_cnt,
1852 B43_PHY_TX_BADNESS_LIMIT);
1853 b43err(dev->wl, "Too many PHY TX errors, "
1854 "restarting the controller\n");
1855 b43_controller_restart(dev, "PHY TX errors");
1859 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1860 B43_DMAIRQ_NONFATALMASK))) {
1861 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1862 b43err(dev->wl, "Fatal DMA error: "
1863 "0x%08X, 0x%08X, 0x%08X, "
1864 "0x%08X, 0x%08X, 0x%08X\n",
1865 dma_reason[0], dma_reason[1],
1866 dma_reason[2], dma_reason[3],
1867 dma_reason[4], dma_reason[5]);
1868 b43_controller_restart(dev, "DMA error");
1870 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1873 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1874 b43err(dev->wl, "DMA error: "
1875 "0x%08X, 0x%08X, 0x%08X, "
1876 "0x%08X, 0x%08X, 0x%08X\n",
1877 dma_reason[0], dma_reason[1],
1878 dma_reason[2], dma_reason[3],
1879 dma_reason[4], dma_reason[5]);
1883 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1884 handle_irq_ucode_debug(dev);
1885 if (reason & B43_IRQ_TBTT_INDI)
1886 handle_irq_tbtt_indication(dev);
1887 if (reason & B43_IRQ_ATIM_END)
1888 handle_irq_atim_end(dev);
1889 if (reason & B43_IRQ_BEACON)
1890 handle_irq_beacon(dev);
1891 if (reason & B43_IRQ_PMQ)
1892 handle_irq_pmq(dev);
1893 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1895 if (reason & B43_IRQ_NOISESAMPLE_OK)
1896 handle_irq_noise(dev);
1898 /* Check the DMA reason registers for received data. */
1899 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1900 if (b43_using_pio_transfers(dev))
1901 b43_pio_rx(dev->pio.rx_queue);
1903 b43_dma_rx(dev->dma.rx_ring);
1905 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1906 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1907 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1908 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1909 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1911 if (reason & B43_IRQ_TX_OK)
1912 handle_irq_transmit_status(dev);
1914 b43_interrupt_enable(dev, dev->irq_savedstate);
1916 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1919 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1921 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1923 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1924 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1925 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1926 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1927 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1928 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1931 /* Interrupt handler top-half */
1932 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1934 irqreturn_t ret = IRQ_NONE;
1935 struct b43_wldev *dev = dev_id;
1941 spin_lock(&dev->wl->irq_lock);
1943 if (b43_status(dev) < B43_STAT_STARTED)
1945 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1946 if (reason == 0xffffffff) /* shared IRQ */
1949 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1953 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1955 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1957 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1959 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1961 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1963 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1966 b43_interrupt_ack(dev, reason);
1967 /* disable all IRQs. They are enabled again in the bottom half. */
1968 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1969 /* save the reason code and call our bottom half. */
1970 dev->irq_reason = reason;
1971 tasklet_schedule(&dev->isr_tasklet);
1974 spin_unlock(&dev->wl->irq_lock);
1979 static void do_release_fw(struct b43_firmware_file *fw)
1981 release_firmware(fw->data);
1983 fw->filename = NULL;
1986 static void b43_release_firmware(struct b43_wldev *dev)
1988 do_release_fw(&dev->fw.ucode);
1989 do_release_fw(&dev->fw.pcm);
1990 do_release_fw(&dev->fw.initvals);
1991 do_release_fw(&dev->fw.initvals_band);
1994 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1998 text = "You must go to "
1999 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
2000 "and download the latest firmware (version 4).\n";
2007 static int do_request_fw(struct b43_wldev *dev,
2009 struct b43_firmware_file *fw,
2012 char path[sizeof(modparam_fwpostfix) + 32];
2013 const struct firmware *blob;
2014 struct b43_fw_header *hdr;
2019 /* Don't fetch anything. Free possibly cached firmware. */
2024 if (strcmp(fw->filename, name) == 0)
2025 return 0; /* Already have this fw. */
2026 /* Free the cached firmware first. */
2030 snprintf(path, ARRAY_SIZE(path),
2032 modparam_fwpostfix, name);
2033 err = request_firmware(&blob, path, dev->dev->dev);
2034 if (err == -ENOENT) {
2036 b43err(dev->wl, "Firmware file \"%s\" not found\n",
2041 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2045 if (blob->size < sizeof(struct b43_fw_header))
2047 hdr = (struct b43_fw_header *)(blob->data);
2048 switch (hdr->type) {
2049 case B43_FW_TYPE_UCODE:
2050 case B43_FW_TYPE_PCM:
2051 size = be32_to_cpu(hdr->size);
2052 if (size != blob->size - sizeof(struct b43_fw_header))
2055 case B43_FW_TYPE_IV:
2064 fw->filename = name;
2069 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
2070 release_firmware(blob);
2075 static int b43_request_firmware(struct b43_wldev *dev)
2077 struct b43_firmware *fw = &dev->fw;
2078 const u8 rev = dev->dev->id.revision;
2079 const char *filename;
2084 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2085 if ((rev >= 5) && (rev <= 10))
2086 filename = "ucode5";
2087 else if ((rev >= 11) && (rev <= 12))
2088 filename = "ucode11";
2090 filename = "ucode13";
2093 err = do_request_fw(dev, filename, &fw->ucode, 0);
2098 if ((rev >= 5) && (rev <= 10))
2104 fw->pcm_request_failed = 0;
2105 err = do_request_fw(dev, filename, &fw->pcm, 1);
2106 if (err == -ENOENT) {
2107 /* We did not find a PCM file? Not fatal, but
2108 * core rev <= 10 must do without hwcrypto then. */
2109 fw->pcm_request_failed = 1;
2114 switch (dev->phy.type) {
2116 if ((rev >= 5) && (rev <= 10)) {
2117 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2118 filename = "a0g1initvals5";
2120 filename = "a0g0initvals5";
2122 goto err_no_initvals;
2125 if ((rev >= 5) && (rev <= 10))
2126 filename = "b0g0initvals5";
2128 filename = "b0g0initvals13";
2130 goto err_no_initvals;
2133 if ((rev >= 11) && (rev <= 12))
2134 filename = "n0initvals11";
2136 goto err_no_initvals;
2139 goto err_no_initvals;
2141 err = do_request_fw(dev, filename, &fw->initvals, 0);
2145 /* Get bandswitch initvals */
2146 switch (dev->phy.type) {
2148 if ((rev >= 5) && (rev <= 10)) {
2149 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2150 filename = "a0g1bsinitvals5";
2152 filename = "a0g0bsinitvals5";
2153 } else if (rev >= 11)
2156 goto err_no_initvals;
2159 if ((rev >= 5) && (rev <= 10))
2160 filename = "b0g0bsinitvals5";
2164 goto err_no_initvals;
2167 if ((rev >= 11) && (rev <= 12))
2168 filename = "n0bsinitvals11";
2170 goto err_no_initvals;
2173 goto err_no_initvals;
2175 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
2182 b43_print_fw_helptext(dev->wl, 1);
2187 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2192 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2197 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2198 "core rev %u\n", dev->phy.type, rev);
2202 b43_release_firmware(dev);
2206 static int b43_upload_microcode(struct b43_wldev *dev)
2208 const size_t hdr_len = sizeof(struct b43_fw_header);
2210 unsigned int i, len;
2211 u16 fwrev, fwpatch, fwdate, fwtime;
2215 /* Jump the microcode PSM to offset 0 */
2216 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2217 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2218 macctl |= B43_MACCTL_PSM_JMP0;
2219 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2220 /* Zero out all microcode PSM registers and shared memory. */
2221 for (i = 0; i < 64; i++)
2222 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2223 for (i = 0; i < 4096; i += 2)
2224 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2226 /* Upload Microcode. */
2227 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2228 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2229 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2230 for (i = 0; i < len; i++) {
2231 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2235 if (dev->fw.pcm.data) {
2236 /* Upload PCM data. */
2237 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2238 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2239 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2240 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2241 /* No need for autoinc bit in SHM_HW */
2242 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2243 for (i = 0; i < len; i++) {
2244 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2249 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2251 /* Start the microcode PSM */
2252 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2253 macctl &= ~B43_MACCTL_PSM_JMP0;
2254 macctl |= B43_MACCTL_PSM_RUN;
2255 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2257 /* Wait for the microcode to load and respond */
2260 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2261 if (tmp == B43_IRQ_MAC_SUSPENDED)
2265 b43err(dev->wl, "Microcode not responding\n");
2266 b43_print_fw_helptext(dev->wl, 1);
2270 msleep_interruptible(50);
2271 if (signal_pending(current)) {
2276 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2278 /* Get and check the revisions. */
2279 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2280 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2281 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2282 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2284 if (fwrev <= 0x128) {
2285 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2286 "binary drivers older than version 4.x is unsupported. "
2287 "You must upgrade your firmware files.\n");
2288 b43_print_fw_helptext(dev->wl, 1);
2292 dev->fw.rev = fwrev;
2293 dev->fw.patch = fwpatch;
2294 dev->fw.opensource = (fwdate == 0xFFFF);
2296 if (dev->fw.opensource) {
2297 /* Patchlevel info is encoded in the "time" field. */
2298 dev->fw.patch = fwtime;
2299 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2300 dev->fw.rev, dev->fw.patch,
2301 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
2303 b43info(dev->wl, "Loading firmware version %u.%u "
2304 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2306 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2307 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2308 if (dev->fw.pcm_request_failed) {
2309 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2310 "Hardware accelerated cryptography is disabled.\n");
2311 b43_print_fw_helptext(dev->wl, 0);
2315 if (b43_is_old_txhdr_format(dev)) {
2316 b43warn(dev->wl, "You are using an old firmware image. "
2317 "Support for old firmware will be removed in July 2008.\n");
2318 b43_print_fw_helptext(dev->wl, 0);
2324 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2325 macctl &= ~B43_MACCTL_PSM_RUN;
2326 macctl |= B43_MACCTL_PSM_JMP0;
2327 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2332 static int b43_write_initvals(struct b43_wldev *dev,
2333 const struct b43_iv *ivals,
2337 const struct b43_iv *iv;
2342 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2344 for (i = 0; i < count; i++) {
2345 if (array_size < sizeof(iv->offset_size))
2347 array_size -= sizeof(iv->offset_size);
2348 offset = be16_to_cpu(iv->offset_size);
2349 bit32 = !!(offset & B43_IV_32BIT);
2350 offset &= B43_IV_OFFSET_MASK;
2351 if (offset >= 0x1000)
2356 if (array_size < sizeof(iv->data.d32))
2358 array_size -= sizeof(iv->data.d32);
2360 value = get_unaligned_be32(&iv->data.d32);
2361 b43_write32(dev, offset, value);
2363 iv = (const struct b43_iv *)((const uint8_t *)iv +
2369 if (array_size < sizeof(iv->data.d16))
2371 array_size -= sizeof(iv->data.d16);
2373 value = be16_to_cpu(iv->data.d16);
2374 b43_write16(dev, offset, value);
2376 iv = (const struct b43_iv *)((const uint8_t *)iv +
2387 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2388 b43_print_fw_helptext(dev->wl, 1);
2393 static int b43_upload_initvals(struct b43_wldev *dev)
2395 const size_t hdr_len = sizeof(struct b43_fw_header);
2396 const struct b43_fw_header *hdr;
2397 struct b43_firmware *fw = &dev->fw;
2398 const struct b43_iv *ivals;
2402 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2403 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2404 count = be32_to_cpu(hdr->size);
2405 err = b43_write_initvals(dev, ivals, count,
2406 fw->initvals.data->size - hdr_len);
2409 if (fw->initvals_band.data) {
2410 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2411 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2412 count = be32_to_cpu(hdr->size);
2413 err = b43_write_initvals(dev, ivals, count,
2414 fw->initvals_band.data->size - hdr_len);
2423 /* Initialize the GPIOs
2424 * http://bcm-specs.sipsolutions.net/GPIO
2426 static int b43_gpio_init(struct b43_wldev *dev)
2428 struct ssb_bus *bus = dev->dev->bus;
2429 struct ssb_device *gpiodev, *pcidev = NULL;
2432 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2433 & ~B43_MACCTL_GPOUTSMSK);
2435 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2440 if (dev->dev->bus->chip_id == 0x4301) {
2444 if (0 /* FIXME: conditional unknown */ ) {
2445 b43_write16(dev, B43_MMIO_GPIO_MASK,
2446 b43_read16(dev, B43_MMIO_GPIO_MASK)
2451 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2452 b43_write16(dev, B43_MMIO_GPIO_MASK,
2453 b43_read16(dev, B43_MMIO_GPIO_MASK)
2458 if (dev->dev->id.revision >= 2)
2459 mask |= 0x0010; /* FIXME: This is redundant. */
2461 #ifdef CONFIG_SSB_DRIVER_PCICORE
2462 pcidev = bus->pcicore.dev;
2464 gpiodev = bus->chipco.dev ? : pcidev;
2467 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2468 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2474 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2475 static void b43_gpio_cleanup(struct b43_wldev *dev)
2477 struct ssb_bus *bus = dev->dev->bus;
2478 struct ssb_device *gpiodev, *pcidev = NULL;
2480 #ifdef CONFIG_SSB_DRIVER_PCICORE
2481 pcidev = bus->pcicore.dev;
2483 gpiodev = bus->chipco.dev ? : pcidev;
2486 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2489 /* http://bcm-specs.sipsolutions.net/EnableMac */
2490 void b43_mac_enable(struct b43_wldev *dev)
2492 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2495 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2496 B43_SHM_SH_UCODESTAT);
2497 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2498 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2499 b43err(dev->wl, "b43_mac_enable(): The firmware "
2500 "should be suspended, but current state is %u\n",
2505 dev->mac_suspended--;
2506 B43_WARN_ON(dev->mac_suspended < 0);
2507 if (dev->mac_suspended == 0) {
2508 b43_write32(dev, B43_MMIO_MACCTL,
2509 b43_read32(dev, B43_MMIO_MACCTL)
2510 | B43_MACCTL_ENABLED);
2511 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2512 B43_IRQ_MAC_SUSPENDED);
2514 b43_read32(dev, B43_MMIO_MACCTL);
2515 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2516 b43_power_saving_ctl_bits(dev, 0);
2520 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2521 void b43_mac_suspend(struct b43_wldev *dev)
2527 B43_WARN_ON(dev->mac_suspended < 0);
2529 if (dev->mac_suspended == 0) {
2530 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2531 b43_write32(dev, B43_MMIO_MACCTL,
2532 b43_read32(dev, B43_MMIO_MACCTL)
2533 & ~B43_MACCTL_ENABLED);
2534 /* force pci to flush the write */
2535 b43_read32(dev, B43_MMIO_MACCTL);
2536 for (i = 35; i; i--) {
2537 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2538 if (tmp & B43_IRQ_MAC_SUSPENDED)
2542 /* Hm, it seems this will take some time. Use msleep(). */
2543 for (i = 40; i; i--) {
2544 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2545 if (tmp & B43_IRQ_MAC_SUSPENDED)
2549 b43err(dev->wl, "MAC suspend failed\n");
2552 dev->mac_suspended++;
2555 static void b43_adjust_opmode(struct b43_wldev *dev)
2557 struct b43_wl *wl = dev->wl;
2561 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2562 /* Reset status to STA infrastructure mode. */
2563 ctl &= ~B43_MACCTL_AP;
2564 ctl &= ~B43_MACCTL_KEEP_CTL;
2565 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2566 ctl &= ~B43_MACCTL_KEEP_BAD;
2567 ctl &= ~B43_MACCTL_PROMISC;
2568 ctl &= ~B43_MACCTL_BEACPROMISC;
2569 ctl |= B43_MACCTL_INFRA;
2571 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2572 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2573 ctl |= B43_MACCTL_AP;
2574 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2575 ctl &= ~B43_MACCTL_INFRA;
2577 if (wl->filter_flags & FIF_CONTROL)
2578 ctl |= B43_MACCTL_KEEP_CTL;
2579 if (wl->filter_flags & FIF_FCSFAIL)
2580 ctl |= B43_MACCTL_KEEP_BAD;
2581 if (wl->filter_flags & FIF_PLCPFAIL)
2582 ctl |= B43_MACCTL_KEEP_BADPLCP;
2583 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2584 ctl |= B43_MACCTL_PROMISC;
2585 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2586 ctl |= B43_MACCTL_BEACPROMISC;
2588 /* Workaround: On old hardware the HW-MAC-address-filter
2589 * doesn't work properly, so always run promisc in filter
2590 * it in software. */
2591 if (dev->dev->id.revision <= 4)
2592 ctl |= B43_MACCTL_PROMISC;
2594 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2597 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2598 if (dev->dev->bus->chip_id == 0x4306 &&
2599 dev->dev->bus->chip_rev == 3)
2604 b43_write16(dev, 0x612, cfp_pretbtt);
2607 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2613 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2616 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2618 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2619 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2622 static void b43_rate_memory_init(struct b43_wldev *dev)
2624 switch (dev->phy.type) {
2628 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2629 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2630 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2631 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2632 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2633 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2634 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2635 if (dev->phy.type == B43_PHYTYPE_A)
2639 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2640 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2641 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2642 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2649 /* Set the default values for the PHY TX Control Words. */
2650 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2654 ctl |= B43_TXH_PHY_ENC_CCK;
2655 ctl |= B43_TXH_PHY_ANT01AUTO;
2656 ctl |= B43_TXH_PHY_TXPWR;
2658 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2659 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2660 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2663 /* Set the TX-Antenna for management frames sent by firmware. */
2664 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2669 ant = b43_antenna_to_phyctl(antenna);
2672 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2673 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2674 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2675 /* For Probe Resposes */
2676 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2677 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2678 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2681 /* This is the opposite of b43_chip_init() */
2682 static void b43_chip_exit(struct b43_wldev *dev)
2685 b43_gpio_cleanup(dev);
2686 /* firmware is released later */
2689 /* Initialize the chip
2690 * http://bcm-specs.sipsolutions.net/ChipInit
2692 static int b43_chip_init(struct b43_wldev *dev)
2694 struct b43_phy *phy = &dev->phy;
2696 u32 value32, macctl;
2699 /* Initialize the MAC control */
2700 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2702 macctl |= B43_MACCTL_GMODE;
2703 macctl |= B43_MACCTL_INFRA;
2704 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2706 err = b43_request_firmware(dev);
2709 err = b43_upload_microcode(dev);
2711 goto out; /* firmware is released later */
2713 err = b43_gpio_init(dev);
2715 goto out; /* firmware is released later */
2717 err = b43_upload_initvals(dev);
2719 goto err_gpio_clean;
2721 /* Turn the Analog on and initialize the PHY. */
2722 phy->ops->switch_analog(dev, 1);
2723 err = b43_phy_init(dev);
2725 goto err_gpio_clean;
2727 /* Disable Interference Mitigation. */
2728 if (phy->ops->interf_mitigation)
2729 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2731 /* Select the antennae */
2732 if (phy->ops->set_rx_antenna)
2733 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2734 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2736 if (phy->type == B43_PHYTYPE_B) {
2737 value16 = b43_read16(dev, 0x005E);
2739 b43_write16(dev, 0x005E, value16);
2741 b43_write32(dev, 0x0100, 0x01000000);
2742 if (dev->dev->id.revision < 5)
2743 b43_write32(dev, 0x010C, 0x01000000);
2745 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2746 & ~B43_MACCTL_INFRA);
2747 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2748 | B43_MACCTL_INFRA);
2750 /* Probe Response Timeout value */
2751 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2752 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2754 /* Initially set the wireless operation mode. */
2755 b43_adjust_opmode(dev);
2757 if (dev->dev->id.revision < 3) {
2758 b43_write16(dev, 0x060E, 0x0000);
2759 b43_write16(dev, 0x0610, 0x8000);
2760 b43_write16(dev, 0x0604, 0x0000);
2761 b43_write16(dev, 0x0606, 0x0200);
2763 b43_write32(dev, 0x0188, 0x80000000);
2764 b43_write32(dev, 0x018C, 0x02000000);
2766 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2767 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2768 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2769 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2770 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2771 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2772 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2774 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2775 value32 |= 0x00100000;
2776 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2778 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2779 dev->dev->bus->chipco.fast_pwrup_delay);
2782 b43dbg(dev->wl, "Chip initialized\n");
2787 b43_gpio_cleanup(dev);
2791 static void b43_periodic_every60sec(struct b43_wldev *dev)
2793 const struct b43_phy_operations *ops = dev->phy.ops;
2795 if (ops->pwork_60sec)
2796 ops->pwork_60sec(dev);
2798 /* Force check the TX power emission now. */
2799 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2802 static void b43_periodic_every30sec(struct b43_wldev *dev)
2804 /* Update device statistics. */
2805 b43_calculate_link_quality(dev);
2808 static void b43_periodic_every15sec(struct b43_wldev *dev)
2810 struct b43_phy *phy = &dev->phy;
2813 if (dev->fw.opensource) {
2814 /* Check if the firmware is still alive.
2815 * It will reset the watchdog counter to 0 in its idle loop. */
2816 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2817 if (unlikely(wdr)) {
2818 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2819 b43_controller_restart(dev, "Firmware watchdog");
2822 b43_shm_write16(dev, B43_SHM_SCRATCH,
2823 B43_WATCHDOG_REG, 1);
2827 if (phy->ops->pwork_15sec)
2828 phy->ops->pwork_15sec(dev);
2830 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2834 static void do_periodic_work(struct b43_wldev *dev)
2838 state = dev->periodic_state;
2840 b43_periodic_every60sec(dev);
2842 b43_periodic_every30sec(dev);
2843 b43_periodic_every15sec(dev);
2846 /* Periodic work locking policy:
2847 * The whole periodic work handler is protected by
2848 * wl->mutex. If another lock is needed somewhere in the
2849 * pwork callchain, it's aquired in-place, where it's needed.
2851 static void b43_periodic_work_handler(struct work_struct *work)
2853 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2854 periodic_work.work);
2855 struct b43_wl *wl = dev->wl;
2856 unsigned long delay;
2858 mutex_lock(&wl->mutex);
2860 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2862 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2865 do_periodic_work(dev);
2867 dev->periodic_state++;
2869 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2870 delay = msecs_to_jiffies(50);
2872 delay = round_jiffies_relative(HZ * 15);
2873 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2875 mutex_unlock(&wl->mutex);
2878 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2880 struct delayed_work *work = &dev->periodic_work;
2882 dev->periodic_state = 0;
2883 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2884 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2887 /* Check if communication with the device works correctly. */
2888 static int b43_validate_chipaccess(struct b43_wldev *dev)
2892 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2894 /* Check for read/write and endianness problems. */
2895 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2896 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2898 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2899 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2902 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2904 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2905 /* The 32bit register shadows the two 16bit registers
2906 * with update sideeffects. Validate this. */
2907 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2908 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2909 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2911 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2914 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2916 v = b43_read32(dev, B43_MMIO_MACCTL);
2917 v |= B43_MACCTL_GMODE;
2918 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2923 b43err(dev->wl, "Failed to validate the chipaccess\n");
2927 static void b43_security_init(struct b43_wldev *dev)
2929 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2930 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2931 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2932 /* KTP is a word address, but we address SHM bytewise.
2933 * So multiply by two.
2936 if (dev->dev->id.revision >= 5) {
2937 /* Number of RCMTA address slots */
2938 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2940 b43_clear_keys(dev);
2943 static int b43_rng_read(struct hwrng *rng, u32 * data)
2945 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2946 unsigned long flags;
2948 /* Don't take wl->mutex here, as it could deadlock with
2949 * hwrng internal locking. It's not needed to take
2950 * wl->mutex here, anyway. */
2952 spin_lock_irqsave(&wl->irq_lock, flags);
2953 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2954 spin_unlock_irqrestore(&wl->irq_lock, flags);
2956 return (sizeof(u16));
2959 static void b43_rng_exit(struct b43_wl *wl)
2961 if (wl->rng_initialized)
2962 hwrng_unregister(&wl->rng);
2965 static int b43_rng_init(struct b43_wl *wl)
2969 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2970 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2971 wl->rng.name = wl->rng_name;
2972 wl->rng.data_read = b43_rng_read;
2973 wl->rng.priv = (unsigned long)wl;
2974 wl->rng_initialized = 1;
2975 err = hwrng_register(&wl->rng);
2977 wl->rng_initialized = 0;
2978 b43err(wl, "Failed to register the random "
2979 "number generator (%d)\n", err);
2985 static int b43_op_tx(struct ieee80211_hw *hw,
2986 struct sk_buff *skb)
2988 struct b43_wl *wl = hw_to_b43_wl(hw);
2989 struct b43_wldev *dev = wl->current_dev;
2990 unsigned long flags;
2993 if (unlikely(skb->len < 2 + 2 + 6)) {
2994 /* Too short, this can't be a valid frame. */
2997 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3001 /* Transmissions on seperate queues can run concurrently. */
3002 read_lock_irqsave(&wl->tx_lock, flags);
3005 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3006 if (b43_using_pio_transfers(dev))
3007 err = b43_pio_tx(dev, skb);
3009 err = b43_dma_tx(dev, skb);
3012 read_unlock_irqrestore(&wl->tx_lock, flags);
3016 return NETDEV_TX_OK;
3019 /* We can not transmit this packet. Drop it. */
3020 dev_kfree_skb_any(skb);
3021 return NETDEV_TX_OK;
3024 /* Locking: wl->irq_lock */
3025 static void b43_qos_params_upload(struct b43_wldev *dev,
3026 const struct ieee80211_tx_queue_params *p,
3029 u16 params[B43_NR_QOSPARAMS];
3033 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3035 memset(¶ms, 0, sizeof(params));
3037 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3038 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3039 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3040 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3041 params[B43_QOSPARAM_AIFS] = p->aifs;
3042 params[B43_QOSPARAM_BSLOTS] = bslots;
3043 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3045 for (i = 0; i < ARRAY_SIZE(params); i++) {
3046 if (i == B43_QOSPARAM_STATUS) {
3047 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3048 shm_offset + (i * 2));
3049 /* Mark the parameters as updated. */
3051 b43_shm_write16(dev, B43_SHM_SHARED,
3052 shm_offset + (i * 2),
3055 b43_shm_write16(dev, B43_SHM_SHARED,
3056 shm_offset + (i * 2),
3062 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3063 static const u16 b43_qos_shm_offsets[] = {
3064 /* [mac80211-queue-nr] = SHM_OFFSET, */
3065 [0] = B43_QOS_VOICE,
3066 [1] = B43_QOS_VIDEO,
3067 [2] = B43_QOS_BESTEFFORT,
3068 [3] = B43_QOS_BACKGROUND,
3071 /* Update all QOS parameters in hardware. */
3072 static void b43_qos_upload_all(struct b43_wldev *dev)
3074 struct b43_wl *wl = dev->wl;
3075 struct b43_qos_params *params;
3078 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3079 ARRAY_SIZE(wl->qos_params));
3081 b43_mac_suspend(dev);
3082 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3083 params = &(wl->qos_params[i]);
3084 b43_qos_params_upload(dev, &(params->p),
3085 b43_qos_shm_offsets[i]);
3087 b43_mac_enable(dev);
3090 static void b43_qos_clear(struct b43_wl *wl)
3092 struct b43_qos_params *params;
3095 /* Initialize QoS parameters to sane defaults. */
3097 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3098 ARRAY_SIZE(wl->qos_params));
3100 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3101 params = &(wl->qos_params[i]);
3103 switch (b43_qos_shm_offsets[i]) {
3107 params->p.cw_min = 0x0001;
3108 params->p.cw_max = 0x0001;
3113 params->p.cw_min = 0x0001;
3114 params->p.cw_max = 0x0001;
3116 case B43_QOS_BESTEFFORT:
3119 params->p.cw_min = 0x0001;
3120 params->p.cw_max = 0x03FF;
3122 case B43_QOS_BACKGROUND:
3125 params->p.cw_min = 0x0001;
3126 params->p.cw_max = 0x03FF;
3134 /* Initialize the core's QOS capabilities */
3135 static void b43_qos_init(struct b43_wldev *dev)
3137 /* Upload the current QOS parameters. */
3138 b43_qos_upload_all(dev);
3140 /* Enable QOS support. */
3141 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3142 b43_write16(dev, B43_MMIO_IFSCTL,
3143 b43_read16(dev, B43_MMIO_IFSCTL)
3144 | B43_MMIO_IFSCTL_USE_EDCF);
3147 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3148 const struct ieee80211_tx_queue_params *params)
3150 struct b43_wl *wl = hw_to_b43_wl(hw);
3151 struct b43_wldev *dev;
3152 unsigned int queue = (unsigned int)_queue;
3155 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3156 /* Queue not available or don't support setting
3157 * params on this queue. Return success to not
3158 * confuse mac80211. */
3161 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3162 ARRAY_SIZE(wl->qos_params));
3164 mutex_lock(&wl->mutex);
3165 dev = wl->current_dev;
3166 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3169 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3170 b43_mac_suspend(dev);
3171 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3172 b43_qos_shm_offsets[queue]);
3173 b43_mac_enable(dev);
3177 mutex_unlock(&wl->mutex);
3182 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3183 struct ieee80211_tx_queue_stats *stats)
3185 struct b43_wl *wl = hw_to_b43_wl(hw);
3186 struct b43_wldev *dev = wl->current_dev;
3187 unsigned long flags;
3192 spin_lock_irqsave(&wl->irq_lock, flags);
3193 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3194 if (b43_using_pio_transfers(dev))
3195 b43_pio_get_tx_stats(dev, stats);
3197 b43_dma_get_tx_stats(dev, stats);
3200 spin_unlock_irqrestore(&wl->irq_lock, flags);
3205 static int b43_op_get_stats(struct ieee80211_hw *hw,
3206 struct ieee80211_low_level_stats *stats)
3208 struct b43_wl *wl = hw_to_b43_wl(hw);
3209 unsigned long flags;
3211 spin_lock_irqsave(&wl->irq_lock, flags);
3212 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3213 spin_unlock_irqrestore(&wl->irq_lock, flags);
3218 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3220 struct ssb_device *sdev = dev->dev;
3223 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3224 tmslow &= ~B43_TMSLOW_GMODE;
3225 tmslow |= B43_TMSLOW_PHYRESET;
3226 tmslow |= SSB_TMSLOW_FGC;
3227 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3230 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3231 tmslow &= ~SSB_TMSLOW_FGC;
3232 tmslow |= B43_TMSLOW_PHYRESET;
3233 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3237 static const char * band_to_string(enum ieee80211_band band)
3240 case IEEE80211_BAND_5GHZ:
3242 case IEEE80211_BAND_2GHZ:
3251 /* Expects wl->mutex locked */
3252 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3254 struct b43_wldev *up_dev = NULL;
3255 struct b43_wldev *down_dev;
3256 struct b43_wldev *d;
3261 /* Find a device and PHY which supports the band. */
3262 list_for_each_entry(d, &wl->devlist, list) {
3263 switch (chan->band) {
3264 case IEEE80211_BAND_5GHZ:
3265 if (d->phy.supports_5ghz) {
3270 case IEEE80211_BAND_2GHZ:
3271 if (d->phy.supports_2ghz) {
3284 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3285 band_to_string(chan->band));
3288 if ((up_dev == wl->current_dev) &&
3289 (!!wl->current_dev->phy.gmode == !!gmode)) {
3290 /* This device is already running. */
3293 b43dbg(wl, "Switching to %s-GHz band\n",
3294 band_to_string(chan->band));
3295 down_dev = wl->current_dev;
3297 prev_status = b43_status(down_dev);
3298 /* Shutdown the currently running core. */
3299 if (prev_status >= B43_STAT_STARTED)
3300 b43_wireless_core_stop(down_dev);
3301 if (prev_status >= B43_STAT_INITIALIZED)
3302 b43_wireless_core_exit(down_dev);
3304 if (down_dev != up_dev) {
3305 /* We switch to a different core, so we put PHY into
3306 * RESET on the old core. */
3307 b43_put_phy_into_reset(down_dev);
3310 /* Now start the new core. */
3311 up_dev->phy.gmode = gmode;
3312 if (prev_status >= B43_STAT_INITIALIZED) {
3313 err = b43_wireless_core_init(up_dev);
3315 b43err(wl, "Fatal: Could not initialize device for "
3316 "selected %s-GHz band\n",
3317 band_to_string(chan->band));
3321 if (prev_status >= B43_STAT_STARTED) {
3322 err = b43_wireless_core_start(up_dev);
3324 b43err(wl, "Fatal: Coult not start device for "
3325 "selected %s-GHz band\n",
3326 band_to_string(chan->band));
3327 b43_wireless_core_exit(up_dev);
3331 B43_WARN_ON(b43_status(up_dev) != prev_status);
3333 wl->current_dev = up_dev;
3337 /* Whoops, failed to init the new core. No core is operating now. */
3338 wl->current_dev = NULL;
3342 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3344 struct b43_wl *wl = hw_to_b43_wl(hw);
3345 struct b43_wldev *dev;
3346 struct b43_phy *phy;
3347 unsigned long flags;
3352 mutex_lock(&wl->mutex);
3354 /* Switch the band (if necessary). This might change the active core. */
3355 err = b43_switch_band(wl, conf->channel);
3357 goto out_unlock_mutex;
3358 dev = wl->current_dev;
3361 /* Disable IRQs while reconfiguring the device.
3362 * This makes it possible to drop the spinlock throughout
3363 * the reconfiguration process. */
3364 spin_lock_irqsave(&wl->irq_lock, flags);
3365 if (b43_status(dev) < B43_STAT_STARTED) {
3366 spin_unlock_irqrestore(&wl->irq_lock, flags);
3367 goto out_unlock_mutex;
3369 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3370 spin_unlock_irqrestore(&wl->irq_lock, flags);
3371 b43_synchronize_irq(dev);
3373 /* Switch to the requested channel.
3374 * The firmware takes care of races with the TX handler. */
3375 if (conf->channel->hw_value != phy->channel)
3376 b43_switch_channel(dev, conf->channel->hw_value);
3378 /* Enable/Disable ShortSlot timing. */
3379 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3381 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3382 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3383 b43_short_slot_timing_enable(dev);
3385 b43_short_slot_timing_disable(dev);
3388 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3390 /* Adjust the desired TX power level. */
3391 if (conf->power_level != 0) {
3392 spin_lock_irqsave(&wl->irq_lock, flags);
3393 if (conf->power_level != phy->desired_txpower) {
3394 phy->desired_txpower = conf->power_level;
3395 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3396 B43_TXPWR_IGNORE_TSSI);
3398 spin_unlock_irqrestore(&wl->irq_lock, flags);
3401 /* Antennas for RX and management frame TX. */
3402 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3403 b43_mgmtframe_txantenna(dev, antenna);
3404 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3405 if (phy->ops->set_rx_antenna)
3406 phy->ops->set_rx_antenna(dev, antenna);
3408 /* Update templates for AP/mesh mode. */
3409 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3410 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3411 b43_set_beacon_int(dev, conf->beacon_int);
3413 if (!!conf->radio_enabled != phy->radio_on) {
3414 if (conf->radio_enabled) {
3415 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
3416 b43info(dev->wl, "Radio turned on by software\n");
3417 if (!dev->radio_hw_enable) {
3418 b43info(dev->wl, "The hardware RF-kill button "
3419 "still turns the radio physically off. "
3420 "Press the button to turn it on.\n");
3423 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
3424 b43info(dev->wl, "Radio turned off by software\n");
3428 spin_lock_irqsave(&wl->irq_lock, flags);
3429 b43_interrupt_enable(dev, savedirqs);
3431 spin_unlock_irqrestore(&wl->irq_lock, flags);
3433 mutex_unlock(&wl->mutex);
3438 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3439 const u8 *local_addr, const u8 *addr,
3440 struct ieee80211_key_conf *key)
3442 struct b43_wl *wl = hw_to_b43_wl(hw);
3443 struct b43_wldev *dev;
3444 unsigned long flags;
3448 DECLARE_MAC_BUF(mac);
3450 if (modparam_nohwcrypt)
3451 return -ENOSPC; /* User disabled HW-crypto */
3453 mutex_lock(&wl->mutex);
3454 spin_lock_irqsave(&wl->irq_lock, flags);
3456 dev = wl->current_dev;
3458 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3461 if (dev->fw.pcm_request_failed) {
3462 /* We don't have firmware for the crypto engine.
3463 * Must use software-crypto. */
3471 if (key->keylen == 5)
3472 algorithm = B43_SEC_ALGO_WEP40;
3474 algorithm = B43_SEC_ALGO_WEP104;
3477 algorithm = B43_SEC_ALGO_TKIP;
3480 algorithm = B43_SEC_ALGO_AES;
3486 index = (u8) (key->keyidx);
3492 if (algorithm == B43_SEC_ALGO_TKIP) {
3493 /* FIXME: No TKIP hardware encryption for now. */
3498 if (is_broadcast_ether_addr(addr)) {
3499 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3500 err = b43_key_write(dev, index, algorithm,
3501 key->key, key->keylen, NULL, key);
3504 * either pairwise key or address is 00:00:00:00:00:00
3505 * for transmit-only keys
3507 err = b43_key_write(dev, -1, algorithm,
3508 key->key, key->keylen, addr, key);
3513 if (algorithm == B43_SEC_ALGO_WEP40 ||
3514 algorithm == B43_SEC_ALGO_WEP104) {
3515 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3518 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3520 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3523 err = b43_key_clear(dev, key->hw_key_idx);
3532 spin_unlock_irqrestore(&wl->irq_lock, flags);
3533 mutex_unlock(&wl->mutex);
3535 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3537 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3538 print_mac(mac, addr));
3543 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3544 unsigned int changed, unsigned int *fflags,
3545 int mc_count, struct dev_addr_list *mc_list)
3547 struct b43_wl *wl = hw_to_b43_wl(hw);
3548 struct b43_wldev *dev = wl->current_dev;
3549 unsigned long flags;
3556 spin_lock_irqsave(&wl->irq_lock, flags);
3557 *fflags &= FIF_PROMISC_IN_BSS |
3563 FIF_BCN_PRBRESP_PROMISC;
3565 changed &= FIF_PROMISC_IN_BSS |
3571 FIF_BCN_PRBRESP_PROMISC;
3573 wl->filter_flags = *fflags;
3575 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3576 b43_adjust_opmode(dev);
3577 spin_unlock_irqrestore(&wl->irq_lock, flags);
3580 static int b43_op_config_interface(struct ieee80211_hw *hw,
3581 struct ieee80211_vif *vif,
3582 struct ieee80211_if_conf *conf)
3584 struct b43_wl *wl = hw_to_b43_wl(hw);
3585 struct b43_wldev *dev = wl->current_dev;
3586 unsigned long flags;
3590 mutex_lock(&wl->mutex);
3591 spin_lock_irqsave(&wl->irq_lock, flags);
3592 B43_WARN_ON(wl->vif != vif);
3594 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3596 memset(wl->bssid, 0, ETH_ALEN);
3597 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3598 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3599 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
3600 B43_WARN_ON(vif->type != wl->if_type);
3601 if (conf->changed & IEEE80211_IFCC_SSID)
3602 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3603 if (conf->changed & IEEE80211_IFCC_BEACON)
3604 b43_update_templates(wl);
3605 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
3606 if (conf->changed & IEEE80211_IFCC_BEACON)
3607 b43_update_templates(wl);
3609 b43_write_mac_bssid_templates(dev);
3611 spin_unlock_irqrestore(&wl->irq_lock, flags);
3612 mutex_unlock(&wl->mutex);
3617 /* Locking: wl->mutex */
3618 static void b43_wireless_core_stop(struct b43_wldev *dev)
3620 struct b43_wl *wl = dev->wl;
3621 unsigned long flags;
3623 if (b43_status(dev) < B43_STAT_STARTED)
3626 /* Disable and sync interrupts. We must do this before than
3627 * setting the status to INITIALIZED, as the interrupt handler
3628 * won't care about IRQs then. */
3629 spin_lock_irqsave(&wl->irq_lock, flags);
3630 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3631 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3632 spin_unlock_irqrestore(&wl->irq_lock, flags);
3633 b43_synchronize_irq(dev);
3635 write_lock_irqsave(&wl->tx_lock, flags);
3636 b43_set_status(dev, B43_STAT_INITIALIZED);
3637 write_unlock_irqrestore(&wl->tx_lock, flags);
3640 mutex_unlock(&wl->mutex);
3641 /* Must unlock as it would otherwise deadlock. No races here.
3642 * Cancel the possibly running self-rearming periodic work. */
3643 cancel_delayed_work_sync(&dev->periodic_work);
3644 mutex_lock(&wl->mutex);
3646 b43_mac_suspend(dev);
3647 free_irq(dev->dev->irq, dev);
3648 b43dbg(wl, "Wireless interface stopped\n");
3651 /* Locking: wl->mutex */
3652 static int b43_wireless_core_start(struct b43_wldev *dev)
3656 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3658 drain_txstatus_queue(dev);
3659 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3660 IRQF_SHARED, KBUILD_MODNAME, dev);
3662 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3666 /* We are ready to run. */
3667 b43_set_status(dev, B43_STAT_STARTED);
3669 /* Start data flow (TX/RX). */
3670 b43_mac_enable(dev);
3671 b43_interrupt_enable(dev, dev->irq_savedstate);
3673 /* Start maintainance work */
3674 b43_periodic_tasks_setup(dev);
3676 b43dbg(dev->wl, "Wireless interface started\n");
3681 /* Get PHY and RADIO versioning numbers */
3682 static int b43_phy_versioning(struct b43_wldev *dev)
3684 struct b43_phy *phy = &dev->phy;
3692 int unsupported = 0;
3694 /* Get PHY versioning */
3695 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3696 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3697 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3698 phy_rev = (tmp & B43_PHYVER_VERSION);
3705 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3713 #ifdef CONFIG_B43_NPHY
3723 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3724 "(Analog %u, Type %u, Revision %u)\n",
3725 analog_type, phy_type, phy_rev);
3728 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3729 analog_type, phy_type, phy_rev);
3731 /* Get RADIO versioning */
3732 if (dev->dev->bus->chip_id == 0x4317) {
3733 if (dev->dev->bus->chip_rev == 0)
3735 else if (dev->dev->bus->chip_rev == 1)
3740 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3741 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3742 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3743 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3745 radio_manuf = (tmp & 0x00000FFF);
3746 radio_ver = (tmp & 0x0FFFF000) >> 12;
3747 radio_rev = (tmp & 0xF0000000) >> 28;
3748 if (radio_manuf != 0x17F /* Broadcom */)
3752 if (radio_ver != 0x2060)
3756 if (radio_manuf != 0x17F)
3760 if ((radio_ver & 0xFFF0) != 0x2050)
3764 if (radio_ver != 0x2050)
3768 if (radio_ver != 0x2055)
3775 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3776 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3777 radio_manuf, radio_ver, radio_rev);
3780 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3781 radio_manuf, radio_ver, radio_rev);
3783 phy->radio_manuf = radio_manuf;
3784 phy->radio_ver = radio_ver;
3785 phy->radio_rev = radio_rev;
3787 phy->analog = analog_type;
3788 phy->type = phy_type;
3794 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3795 struct b43_phy *phy)
3797 phy->hardware_power_control = !!modparam_hwpctl;
3798 phy->next_txpwr_check_time = jiffies;
3799 /* PHY TX errors counter. */
3800 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3803 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3807 /* Assume the radio is enabled. If it's not enabled, the state will
3808 * immediately get fixed on the first periodic work run. */
3809 dev->radio_hw_enable = 1;
3812 memset(&dev->stats, 0, sizeof(dev->stats));
3814 setup_struct_phy_for_init(dev, &dev->phy);
3816 /* IRQ related flags */
3817 dev->irq_reason = 0;
3818 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3819 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3821 dev->mac_suspended = 1;
3823 /* Noise calculation context */
3824 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3827 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3829 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3832 if (!modparam_btcoex)
3834 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3836 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3839 hf = b43_hf_read(dev);
3840 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3841 hf |= B43_HF_BTCOEXALT;
3843 hf |= B43_HF_BTCOEX;
3844 b43_hf_write(dev, hf);
3847 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3849 if (!modparam_btcoex)
3854 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3856 #ifdef CONFIG_SSB_DRIVER_PCICORE
3857 struct ssb_bus *bus = dev->dev->bus;
3860 if (bus->pcicore.dev &&
3861 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3862 bus->pcicore.dev->id.revision <= 5) {
3863 /* IMCFGLO timeouts workaround. */
3864 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3865 tmp &= ~SSB_IMCFGLO_REQTO;
3866 tmp &= ~SSB_IMCFGLO_SERTO;
3867 switch (bus->bustype) {
3868 case SSB_BUSTYPE_PCI:
3869 case SSB_BUSTYPE_PCMCIA:
3872 case SSB_BUSTYPE_SSB:
3876 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3878 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3881 /* Write the short and long frame retry limit values. */
3882 static void b43_set_retry_limits(struct b43_wldev *dev,
3883 unsigned int short_retry,
3884 unsigned int long_retry)
3886 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3887 * the chip-internal counter. */
3888 short_retry = min(short_retry, (unsigned int)0xF);
3889 long_retry = min(long_retry, (unsigned int)0xF);
3891 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3893 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3897 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3901 /* The time value is in microseconds. */
3902 if (dev->phy.type == B43_PHYTYPE_A)
3906 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3908 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3909 pu_delay = max(pu_delay, (u16)2400);
3911 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3914 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3915 static void b43_set_pretbtt(struct b43_wldev *dev)
3919 /* The time value is in microseconds. */
3920 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
3923 if (dev->phy.type == B43_PHYTYPE_A)
3928 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3929 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3932 /* Shutdown a wireless core */
3933 /* Locking: wl->mutex */
3934 static void b43_wireless_core_exit(struct b43_wldev *dev)
3938 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3939 if (b43_status(dev) != B43_STAT_INITIALIZED)
3941 b43_set_status(dev, B43_STAT_UNINIT);
3943 /* Stop the microcode PSM. */
3944 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3945 macctl &= ~B43_MACCTL_PSM_RUN;
3946 macctl |= B43_MACCTL_PSM_JMP0;
3947 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3949 if (!dev->suspend_in_progress) {
3951 b43_rng_exit(dev->wl);
3956 dev->phy.ops->switch_analog(dev, 0);
3957 if (dev->wl->current_beacon) {
3958 dev_kfree_skb_any(dev->wl->current_beacon);
3959 dev->wl->current_beacon = NULL;
3962 ssb_device_disable(dev->dev, 0);
3963 ssb_bus_may_powerdown(dev->dev->bus);
3966 /* Initialize a wireless core */
3967 static int b43_wireless_core_init(struct b43_wldev *dev)
3969 struct b43_wl *wl = dev->wl;
3970 struct ssb_bus *bus = dev->dev->bus;
3971 struct ssb_sprom *sprom = &bus->sprom;
3972 struct b43_phy *phy = &dev->phy;
3977 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3979 err = ssb_bus_powerup(bus, 0);
3982 if (!ssb_device_is_enabled(dev->dev)) {
3983 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3984 b43_wireless_core_reset(dev, tmp);
3987 /* Reset all data structures. */
3988 setup_struct_wldev_for_init(dev);
3989 phy->ops->prepare_structs(dev);
3991 /* Enable IRQ routing to this device. */
3992 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3994 b43_imcfglo_timeouts_workaround(dev);
3995 b43_bluetooth_coext_disable(dev);
3996 if (phy->ops->prepare_hardware) {
3997 err = phy->ops->prepare_hardware(dev);
4001 err = b43_chip_init(dev);
4004 b43_shm_write16(dev, B43_SHM_SHARED,
4005 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4006 hf = b43_hf_read(dev);
4007 if (phy->type == B43_PHYTYPE_G) {
4011 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4012 hf |= B43_HF_OFDMPABOOST;
4013 } else if (phy->type == B43_PHYTYPE_B) {
4015 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4018 b43_hf_write(dev, hf);
4020 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4021 B43_DEFAULT_LONG_RETRY_LIMIT);
4022 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4023 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4025 /* Disable sending probe responses from firmware.
4026 * Setting the MaxTime to one usec will always trigger
4027 * a timeout, so we never send any probe resp.
4028 * A timeout of zero is infinite. */
4029 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4031 b43_rate_memory_init(dev);
4032 b43_set_phytxctl_defaults(dev);
4034 /* Minimum Contention Window */
4035 if (phy->type == B43_PHYTYPE_B) {
4036 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4038 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4040 /* Maximum Contention Window */
4041 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4043 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4044 dev->__using_pio_transfers = 1;
4045 err = b43_pio_init(dev);
4047 dev->__using_pio_transfers = 0;
4048 err = b43_dma_init(dev);
4053 b43_set_synth_pu_delay(dev, 1);
4054 b43_bluetooth_coext_enable(dev);
4056 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4057 b43_upload_card_macaddress(dev);
4058 b43_security_init(dev);
4059 if (!dev->suspend_in_progress)
4062 b43_set_status(dev, B43_STAT_INITIALIZED);
4064 if (!dev->suspend_in_progress)
4072 ssb_bus_may_powerdown(bus);
4073 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4077 static int b43_op_add_interface(struct ieee80211_hw *hw,
4078 struct ieee80211_if_init_conf *conf)
4080 struct b43_wl *wl = hw_to_b43_wl(hw);
4081 struct b43_wldev *dev;
4082 unsigned long flags;
4083 int err = -EOPNOTSUPP;
4085 /* TODO: allow WDS/AP devices to coexist */
4087 if (conf->type != NL80211_IFTYPE_AP &&
4088 conf->type != NL80211_IFTYPE_MESH_POINT &&
4089 conf->type != NL80211_IFTYPE_STATION &&
4090 conf->type != NL80211_IFTYPE_WDS &&
4091 conf->type != NL80211_IFTYPE_ADHOC)
4094 mutex_lock(&wl->mutex);
4096 goto out_mutex_unlock;
4098 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4100 dev = wl->current_dev;
4102 wl->vif = conf->vif;
4103 wl->if_type = conf->type;
4104 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4106 spin_lock_irqsave(&wl->irq_lock, flags);
4107 b43_adjust_opmode(dev);
4108 b43_set_pretbtt(dev);
4109 b43_set_synth_pu_delay(dev, 0);
4110 b43_upload_card_macaddress(dev);
4111 spin_unlock_irqrestore(&wl->irq_lock, flags);
4115 mutex_unlock(&wl->mutex);
4120 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4121 struct ieee80211_if_init_conf *conf)
4123 struct b43_wl *wl = hw_to_b43_wl(hw);
4124 struct b43_wldev *dev = wl->current_dev;
4125 unsigned long flags;
4127 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4129 mutex_lock(&wl->mutex);
4131 B43_WARN_ON(!wl->operating);
4132 B43_WARN_ON(wl->vif != conf->vif);
4137 spin_lock_irqsave(&wl->irq_lock, flags);
4138 b43_adjust_opmode(dev);
4139 memset(wl->mac_addr, 0, ETH_ALEN);
4140 b43_upload_card_macaddress(dev);
4141 spin_unlock_irqrestore(&wl->irq_lock, flags);
4143 mutex_unlock(&wl->mutex);
4146 static int b43_op_start(struct ieee80211_hw *hw)
4148 struct b43_wl *wl = hw_to_b43_wl(hw);
4149 struct b43_wldev *dev = wl->current_dev;
4152 bool do_rfkill_exit = 0;
4154 /* Kill all old instance specific information to make sure
4155 * the card won't use it in the short timeframe between start
4156 * and mac80211 reconfiguring it. */
4157 memset(wl->bssid, 0, ETH_ALEN);
4158 memset(wl->mac_addr, 0, ETH_ALEN);
4159 wl->filter_flags = 0;
4160 wl->radiotap_enabled = 0;
4162 wl->beacon0_uploaded = 0;
4163 wl->beacon1_uploaded = 0;
4164 wl->beacon_templates_virgin = 1;
4166 /* First register RFkill.
4167 * LEDs that are registered later depend on it. */
4168 b43_rfkill_init(dev);
4170 mutex_lock(&wl->mutex);
4172 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4173 err = b43_wireless_core_init(dev);
4176 goto out_mutex_unlock;
4181 if (b43_status(dev) < B43_STAT_STARTED) {
4182 err = b43_wireless_core_start(dev);
4185 b43_wireless_core_exit(dev);
4187 goto out_mutex_unlock;
4192 mutex_unlock(&wl->mutex);
4195 b43_rfkill_exit(dev);
4200 static void b43_op_stop(struct ieee80211_hw *hw)
4202 struct b43_wl *wl = hw_to_b43_wl(hw);
4203 struct b43_wldev *dev = wl->current_dev;
4205 b43_rfkill_exit(dev);
4206 cancel_work_sync(&(wl->beacon_update_trigger));
4208 mutex_lock(&wl->mutex);
4209 if (b43_status(dev) >= B43_STAT_STARTED)
4210 b43_wireless_core_stop(dev);
4211 b43_wireless_core_exit(dev);
4212 mutex_unlock(&wl->mutex);
4214 cancel_work_sync(&(wl->txpower_adjust_work));
4217 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4218 u32 short_retry_limit, u32 long_retry_limit)
4220 struct b43_wl *wl = hw_to_b43_wl(hw);
4221 struct b43_wldev *dev;
4224 mutex_lock(&wl->mutex);
4225 dev = wl->current_dev;
4226 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4230 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4232 mutex_unlock(&wl->mutex);
4237 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4238 struct ieee80211_sta *sta, bool set)
4240 struct b43_wl *wl = hw_to_b43_wl(hw);
4241 unsigned long flags;
4243 spin_lock_irqsave(&wl->irq_lock, flags);
4244 b43_update_templates(wl);
4245 spin_unlock_irqrestore(&wl->irq_lock, flags);
4250 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4251 struct ieee80211_vif *vif,
4252 enum sta_notify_cmd notify_cmd,
4253 struct ieee80211_sta *sta)
4255 struct b43_wl *wl = hw_to_b43_wl(hw);
4257 B43_WARN_ON(!vif || wl->vif != vif);
4260 static const struct ieee80211_ops b43_hw_ops = {
4262 .conf_tx = b43_op_conf_tx,
4263 .add_interface = b43_op_add_interface,
4264 .remove_interface = b43_op_remove_interface,
4265 .config = b43_op_config,
4266 .config_interface = b43_op_config_interface,
4267 .configure_filter = b43_op_configure_filter,
4268 .set_key = b43_op_set_key,
4269 .get_stats = b43_op_get_stats,
4270 .get_tx_stats = b43_op_get_tx_stats,
4271 .start = b43_op_start,
4272 .stop = b43_op_stop,
4273 .set_retry_limit = b43_op_set_retry_limit,
4274 .set_tim = b43_op_beacon_set_tim,
4275 .sta_notify = b43_op_sta_notify,
4278 /* Hard-reset the chip. Do not call this directly.
4279 * Use b43_controller_restart()
4281 static void b43_chip_reset(struct work_struct *work)
4283 struct b43_wldev *dev =
4284 container_of(work, struct b43_wldev, restart_work);
4285 struct b43_wl *wl = dev->wl;
4289 mutex_lock(&wl->mutex);
4291 prev_status = b43_status(dev);
4292 /* Bring the device down... */
4293 if (prev_status >= B43_STAT_STARTED)
4294 b43_wireless_core_stop(dev);
4295 if (prev_status >= B43_STAT_INITIALIZED)
4296 b43_wireless_core_exit(dev);
4298 /* ...and up again. */
4299 if (prev_status >= B43_STAT_INITIALIZED) {
4300 err = b43_wireless_core_init(dev);
4304 if (prev_status >= B43_STAT_STARTED) {
4305 err = b43_wireless_core_start(dev);
4307 b43_wireless_core_exit(dev);
4313 wl->current_dev = NULL; /* Failed to init the dev. */
4314 mutex_unlock(&wl->mutex);
4316 b43err(wl, "Controller restart FAILED\n");
4318 b43info(wl, "Controller restarted\n");
4321 static int b43_setup_bands(struct b43_wldev *dev,
4322 bool have_2ghz_phy, bool have_5ghz_phy)
4324 struct ieee80211_hw *hw = dev->wl->hw;
4327 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4328 if (dev->phy.type == B43_PHYTYPE_N) {
4330 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4333 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4336 dev->phy.supports_2ghz = have_2ghz_phy;
4337 dev->phy.supports_5ghz = have_5ghz_phy;
4342 static void b43_wireless_core_detach(struct b43_wldev *dev)
4344 /* We release firmware that late to not be required to re-request
4345 * is all the time when we reinit the core. */
4346 b43_release_firmware(dev);
4350 static int b43_wireless_core_attach(struct b43_wldev *dev)
4352 struct b43_wl *wl = dev->wl;
4353 struct ssb_bus *bus = dev->dev->bus;
4354 struct pci_dev *pdev = bus->host_pci;
4356 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4359 /* Do NOT do any device initialization here.
4360 * Do it in wireless_core_init() instead.
4361 * This function is for gathering basic information about the HW, only.
4362 * Also some structs may be set up here. But most likely you want to have
4363 * that in core_init(), too.
4366 err = ssb_bus_powerup(bus, 0);
4368 b43err(wl, "Bus powerup failed\n");
4371 /* Get the PHY type. */
4372 if (dev->dev->id.revision >= 5) {
4375 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4376 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4377 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4381 dev->phy.gmode = have_2ghz_phy;
4382 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4383 b43_wireless_core_reset(dev, tmp);
4385 err = b43_phy_versioning(dev);
4388 /* Check if this device supports multiband. */
4390 (pdev->device != 0x4312 &&
4391 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4392 /* No multiband support. */
4395 switch (dev->phy.type) {
4407 if (dev->phy.type == B43_PHYTYPE_A) {
4409 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4413 if (1 /* disable A-PHY */) {
4414 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4415 if (dev->phy.type != B43_PHYTYPE_N) {
4421 err = b43_phy_allocate(dev);
4425 dev->phy.gmode = have_2ghz_phy;
4426 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4427 b43_wireless_core_reset(dev, tmp);
4429 err = b43_validate_chipaccess(dev);
4432 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4436 /* Now set some default "current_dev" */
4437 if (!wl->current_dev)
4438 wl->current_dev = dev;
4439 INIT_WORK(&dev->restart_work, b43_chip_reset);
4441 dev->phy.ops->switch_analog(dev, 0);
4442 ssb_device_disable(dev->dev, 0);
4443 ssb_bus_may_powerdown(bus);
4451 ssb_bus_may_powerdown(bus);
4455 static void b43_one_core_detach(struct ssb_device *dev)
4457 struct b43_wldev *wldev;
4460 /* Do not cancel ieee80211-workqueue based work here.
4461 * See comment in b43_remove(). */
4463 wldev = ssb_get_drvdata(dev);
4465 b43_debugfs_remove_device(wldev);
4466 b43_wireless_core_detach(wldev);
4467 list_del(&wldev->list);
4469 ssb_set_drvdata(dev, NULL);
4473 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4475 struct b43_wldev *wldev;
4476 struct pci_dev *pdev;
4479 if (!list_empty(&wl->devlist)) {
4480 /* We are not the first core on this chip. */
4481 pdev = dev->bus->host_pci;
4482 /* Only special chips support more than one wireless
4483 * core, although some of the other chips have more than
4484 * one wireless core as well. Check for this and
4488 ((pdev->device != 0x4321) &&
4489 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4490 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4495 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4501 b43_set_status(wldev, B43_STAT_UNINIT);
4502 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4503 tasklet_init(&wldev->isr_tasklet,
4504 (void (*)(unsigned long))b43_interrupt_tasklet,
4505 (unsigned long)wldev);
4506 INIT_LIST_HEAD(&wldev->list);
4508 err = b43_wireless_core_attach(wldev);
4510 goto err_kfree_wldev;
4512 list_add(&wldev->list, &wl->devlist);
4514 ssb_set_drvdata(dev, wldev);
4515 b43_debugfs_add_device(wldev);
4525 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4526 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4527 (pdev->device == _device) && \
4528 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4529 (pdev->subsystem_device == _subdevice) )
4531 static void b43_sprom_fixup(struct ssb_bus *bus)
4533 struct pci_dev *pdev;
4535 /* boardflags workarounds */
4536 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4537 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4538 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4539 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4540 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4541 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4542 if (bus->bustype == SSB_BUSTYPE_PCI) {
4543 pdev = bus->host_pci;
4544 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4545 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4546 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4547 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4548 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4549 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4550 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4551 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4555 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4557 struct ieee80211_hw *hw = wl->hw;
4559 ssb_set_devtypedata(dev, NULL);
4560 ieee80211_free_hw(hw);
4563 static int b43_wireless_init(struct ssb_device *dev)
4565 struct ssb_sprom *sprom = &dev->bus->sprom;
4566 struct ieee80211_hw *hw;
4570 b43_sprom_fixup(dev->bus);
4572 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4574 b43err(NULL, "Could not allocate ieee80211 device\n");
4579 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4580 IEEE80211_HW_SIGNAL_DBM |
4581 IEEE80211_HW_NOISE_DBM;
4583 hw->wiphy->interface_modes =
4584 BIT(NL80211_IFTYPE_AP) |
4585 BIT(NL80211_IFTYPE_MESH_POINT) |
4586 BIT(NL80211_IFTYPE_STATION) |
4587 BIT(NL80211_IFTYPE_WDS) |
4588 BIT(NL80211_IFTYPE_ADHOC);
4590 hw->queues = b43_modparam_qos ? 4 : 1;
4591 hw->max_altrates = 1;
4592 SET_IEEE80211_DEV(hw, dev->dev);
4593 if (is_valid_ether_addr(sprom->et1mac))
4594 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4596 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4598 /* Get and initialize struct b43_wl */
4599 wl = hw_to_b43_wl(hw);
4600 memset(wl, 0, sizeof(*wl));
4602 spin_lock_init(&wl->irq_lock);
4603 rwlock_init(&wl->tx_lock);
4604 spin_lock_init(&wl->leds_lock);
4605 spin_lock_init(&wl->shm_lock);
4606 mutex_init(&wl->mutex);
4607 INIT_LIST_HEAD(&wl->devlist);
4608 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4609 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4611 ssb_set_devtypedata(dev, wl);
4612 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4618 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4624 wl = ssb_get_devtypedata(dev);
4626 /* Probing the first core. Must setup common struct b43_wl */
4628 err = b43_wireless_init(dev);
4631 wl = ssb_get_devtypedata(dev);
4634 err = b43_one_core_attach(dev, wl);
4636 goto err_wireless_exit;
4639 err = ieee80211_register_hw(wl->hw);
4641 goto err_one_core_detach;
4647 err_one_core_detach:
4648 b43_one_core_detach(dev);
4651 b43_wireless_exit(dev, wl);
4655 static void b43_remove(struct ssb_device *dev)
4657 struct b43_wl *wl = ssb_get_devtypedata(dev);
4658 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4660 /* We must cancel any work here before unregistering from ieee80211,
4661 * as the ieee80211 unreg will destroy the workqueue. */
4662 cancel_work_sync(&wldev->restart_work);
4665 if (wl->current_dev == wldev)
4666 ieee80211_unregister_hw(wl->hw);
4668 b43_one_core_detach(dev);
4670 if (list_empty(&wl->devlist)) {
4671 /* Last core on the chip unregistered.
4672 * We can destroy common struct b43_wl.
4674 b43_wireless_exit(dev, wl);
4678 /* Perform a hardware reset. This can be called from any context. */
4679 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4681 /* Must avoid requeueing, if we are in shutdown. */
4682 if (b43_status(dev) < B43_STAT_INITIALIZED)
4684 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4685 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4690 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4692 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4693 struct b43_wl *wl = wldev->wl;
4695 b43dbg(wl, "Suspending...\n");
4697 mutex_lock(&wl->mutex);
4698 wldev->suspend_in_progress = true;
4699 wldev->suspend_init_status = b43_status(wldev);
4700 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4701 b43_wireless_core_stop(wldev);
4702 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4703 b43_wireless_core_exit(wldev);
4704 mutex_unlock(&wl->mutex);
4706 b43dbg(wl, "Device suspended.\n");
4711 static int b43_resume(struct ssb_device *dev)
4713 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4714 struct b43_wl *wl = wldev->wl;
4717 b43dbg(wl, "Resuming...\n");
4719 mutex_lock(&wl->mutex);
4720 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4721 err = b43_wireless_core_init(wldev);
4723 b43err(wl, "Resume failed at core init\n");
4727 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4728 err = b43_wireless_core_start(wldev);
4730 b43_leds_exit(wldev);
4731 b43_rng_exit(wldev->wl);
4732 b43_wireless_core_exit(wldev);
4733 b43err(wl, "Resume failed at core start\n");
4737 b43dbg(wl, "Device resumed.\n");
4739 wldev->suspend_in_progress = false;
4740 mutex_unlock(&wl->mutex);
4744 #else /* CONFIG_PM */
4745 # define b43_suspend NULL
4746 # define b43_resume NULL
4747 #endif /* CONFIG_PM */
4749 static struct ssb_driver b43_ssb_driver = {
4750 .name = KBUILD_MODNAME,
4751 .id_table = b43_ssb_tbl,
4753 .remove = b43_remove,
4754 .suspend = b43_suspend,
4755 .resume = b43_resume,
4758 static void b43_print_driverinfo(void)
4760 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4761 *feat_leds = "", *feat_rfkill = "";
4763 #ifdef CONFIG_B43_PCI_AUTOSELECT
4766 #ifdef CONFIG_B43_PCMCIA
4769 #ifdef CONFIG_B43_NPHY
4772 #ifdef CONFIG_B43_LEDS
4775 #ifdef CONFIG_B43_RFKILL
4778 printk(KERN_INFO "Broadcom 43xx driver loaded "
4779 "[ Features: %s%s%s%s%s, Firmware-ID: "
4780 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4781 feat_pci, feat_pcmcia, feat_nphy,
4782 feat_leds, feat_rfkill);
4785 static int __init b43_init(void)
4790 err = b43_pcmcia_init();
4793 err = ssb_driver_register(&b43_ssb_driver);
4795 goto err_pcmcia_exit;
4796 b43_print_driverinfo();
4807 static void __exit b43_exit(void)
4809 ssb_driver_unregister(&b43_ssb_driver);
4814 module_init(b43_init)
4815 module_exit(b43_exit)