git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/qla4xxx/ql4_fw.h

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef _QLA4X_FW_H
   9 #define _QLA4X_FW_H
  10
  11
  12 #define MAX_PRST_DEV_DB_ENTRIES         64
  13 #define MIN_DISC_DEV_DB_ENTRY           MAX_PRST_DEV_DB_ENTRIES
  14 #define MAX_DEV_DB_ENTRIES 512
  15
  16 /*************************************************************************
  17  *
  18  *              ISP 4010 I/O Register Set Structure and Definitions
  19  *
  20  *************************************************************************/
  21
  22 struct port_ctrl_stat_regs {
  23         __le32 ext_hw_conf;     /* 0x50  R/W */
  24         __le32 rsrvd0;          /* 0x54 */
  25         __le32 port_ctrl;       /* 0x58 */
  26         __le32 port_status;     /* 0x5c */
  27         __le32 rsrvd1[32];      /* 0x60-0xdf */
  28         __le32 gp_out;          /* 0xe0 */
  29         __le32 gp_in;           /* 0xe4 */
  30         __le32 rsrvd2[5];       /* 0xe8-0xfb */
  31         __le32 port_err_status; /* 0xfc */
  32 };
  33
  34 struct host_mem_cfg_regs {
  35         __le32 rsrvd0[12];      /* 0x50-0x79 */
  36         __le32 req_q_out;       /* 0x80 */
  37         __le32 rsrvd1[31];      /* 0x84-0xFF */
  38 };
  39
  40 /*  remote register set (access via PCI memory read/write) */
  41 struct isp_reg {
  42 #define MBOX_REG_COUNT 8
  43         __le32 mailbox[MBOX_REG_COUNT];
  44
  45         __le32 flash_address;   /* 0x20 */
  46         __le32 flash_data;
  47         __le32 ctrl_status;
  48
  49         union {
  50                 struct {
  51                         __le32 nvram;
  52                         __le32 reserved1[2]; /* 0x30 */
  53                 } __attribute__ ((packed)) isp4010;
  54                 struct {
  55                         __le32 intr_mask;
  56                         __le32 nvram; /* 0x30 */
  57                         __le32 semaphore;
  58                 } __attribute__ ((packed)) isp4022;
  59         } u1;
  60
  61         __le32 req_q_in;    /* SCSI Request Queue Producer Index */
  62         __le32 rsp_q_out;   /* SCSI Completion Queue Consumer Index */
  63
  64         __le32 reserved2[4];    /* 0x40 */
  65
  66         union {
  67                 struct {
  68                         __le32 ext_hw_conf; /* 0x50 */
  69                         __le32 flow_ctrl;
  70                         __le32 port_ctrl;
  71                         __le32 port_status;
  72
  73                         __le32 reserved3[8]; /* 0x60 */
  74
  75                         __le32 req_q_out; /* 0x80 */
  76
  77                         __le32 reserved4[23]; /* 0x84 */
  78
  79                         __le32 gp_out; /* 0xe0 */
  80                         __le32 gp_in;
  81
  82                         __le32 reserved5[5];
  83
  84                         __le32 port_err_status; /* 0xfc */
  85                 } __attribute__ ((packed)) isp4010;
  86                 struct {
  87                         union {
  88                                 struct port_ctrl_stat_regs p0;
  89                                 struct host_mem_cfg_regs p1;
  90                         };
  91                 } __attribute__ ((packed)) isp4022;
  92         } u2;
  93 };                              /* 256 x100 */
  94
  95
  96 /* Semaphore Defines for 4010 */
  97 #define QL4010_DRVR_SEM_BITS    0x00000030
  98 #define QL4010_GPIO_SEM_BITS    0x000000c0
  99 #define QL4010_SDRAM_SEM_BITS   0x00000300
 100 #define QL4010_PHY_SEM_BITS     0x00000c00
 101 #define QL4010_NVRAM_SEM_BITS   0x00003000
 102 #define QL4010_FLASH_SEM_BITS   0x0000c000
 103
 104 #define QL4010_DRVR_SEM_MASK    0x00300000
 105 #define QL4010_GPIO_SEM_MASK    0x00c00000
 106 #define QL4010_SDRAM_SEM_MASK   0x03000000
 107 #define QL4010_PHY_SEM_MASK     0x0c000000
 108 #define QL4010_NVRAM_SEM_MASK   0x30000000
 109 #define QL4010_FLASH_SEM_MASK   0xc0000000
 110
 111 /* Semaphore Defines for 4022 */
 112 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
 113 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
 114
 115
 116 #define QL4022_DRVR_SEM_MASK    (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
 117 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
 118 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
 119 #define QL4022_NVRAM_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
 120 #define QL4022_FLASH_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
 121
 122
 123
 124 /* Page # defines for 4022 */
 125 #define PORT_CTRL_STAT_PAGE                     0       /* 4022 */
 126 #define HOST_MEM_CFG_PAGE                       1       /* 4022 */
 127 #define LOCAL_RAM_CFG_PAGE                      2       /* 4022 */
 128 #define PROT_STAT_PAGE                          3       /* 4022 */
 129
 130 /* Register Mask - sets corresponding mask bits in the upper word */
 131 static inline uint32_t set_rmask(uint32_t val)
 132 {
 133         return (val & 0xffff) | (val << 16);
 134 }
 135
 136
 137 static inline uint32_t clr_rmask(uint32_t val)
 138 {
 139         return 0 | (val << 16);
 140 }
 141
 142 /*  ctrl_status definitions */
 143 #define CSR_SCSI_PAGE_SELECT                    0x00000003
 144 #define CSR_SCSI_INTR_ENABLE                    0x00000004      /* 4010 */
 145 #define CSR_SCSI_RESET_INTR                     0x00000008
 146 #define CSR_SCSI_COMPLETION_INTR                0x00000010
 147 #define CSR_SCSI_PROCESSOR_INTR                 0x00000020
 148 #define CSR_INTR_RISC                           0x00000040
 149 #define CSR_BOOT_ENABLE                         0x00000080
 150 #define CSR_NET_PAGE_SELECT                     0x00000300      /* 4010 */
 151 #define CSR_FUNC_NUM                            0x00000700      /* 4022 */
 152 #define CSR_NET_RESET_INTR                      0x00000800      /* 4010 */
 153 #define CSR_FORCE_SOFT_RESET                    0x00002000      /* 4022 */
 154 #define CSR_FATAL_ERROR                         0x00004000
 155 #define CSR_SOFT_RESET                          0x00008000
 156 #define ISP_CONTROL_FN_MASK                     CSR_FUNC_NUM
 157 #define ISP_CONTROL_FN0_SCSI                    0x0500
 158 #define ISP_CONTROL_FN1_SCSI                    0x0700
 159
 160 #define INTR_PENDING                            (CSR_SCSI_COMPLETION_INTR |\
 161                                                  CSR_SCSI_PROCESSOR_INTR |\
 162                                                  CSR_SCSI_RESET_INTR)
 163
 164 /* ISP InterruptMask definitions */
 165 #define IMR_SCSI_INTR_ENABLE                    0x00000004      /* 4022 */
 166
 167 /* ISP 4022 nvram definitions */
 168 #define NVR_WRITE_ENABLE                        0x00000010      /* 4022 */
 169
 170 /*  ISP port_status definitions */
 171
 172 /*  ISP Semaphore definitions */
 173
 174 /*  ISP General Purpose Output definitions */
 175 #define GPOR_TOPCAT_RESET                       0x00000004
 176
 177 /*  shadow registers (DMA'd from HA to system memory.  read only) */
 178 struct shadow_regs {
 179         /* SCSI Request Queue Consumer Index */
 180         __le32 req_q_out;       /*  0 x0   R */
 181
 182         /* SCSI Completion Queue Producer Index */
 183         __le32 rsp_q_in;        /*  4 x4   R */
 184 };                /*  8 x8 */
 185
 186
 187 /*  External hardware configuration register */
 188 union external_hw_config_reg {
 189         struct {
 190                 /* FIXME: Do we even need this?  All values are
 191                  * referred to by 16 bit quantities.  Platform and
 192                  * endianess issues. */
 193                 __le32 bReserved0:1;
 194                 __le32 bSDRAMProtectionMethod:2;
 195                 __le32 bSDRAMBanks:1;
 196                 __le32 bSDRAMChipWidth:1;
 197                 __le32 bSDRAMChipSize:2;
 198                 __le32 bParityDisable:1;
 199                 __le32 bExternalMemoryType:1;
 200                 __le32 bFlashBIOSWriteEnable:1;
 201                 __le32 bFlashUpperBankSelect:1;
 202                 __le32 bWriteBurst:2;
 203                 __le32 bReserved1:3;
 204                 __le32 bMask:16;
 205         };
 206         uint32_t Asuint32_t;
 207 };
 208
 209 /*************************************************************************
 210  *
 211  *              Mailbox Commands Structures and Definitions
 212  *
 213  *************************************************************************/
 214
 215 /*  Mailbox command definitions */
 216 #define MBOX_CMD_ABOUT_FW                       0x0009
 217 #define MBOX_CMD_PING                           0x000B
 218 #define MBOX_CMD_LUN_RESET                      0x0016
 219 #define MBOX_CMD_TARGET_WARM_RESET              0x0017
 220 #define MBOX_CMD_GET_MANAGEMENT_DATA            0x001E
 221 #define MBOX_CMD_GET_FW_STATUS                  0x001F
 222 #define MBOX_CMD_SET_ISNS_SERVICE               0x0021
 223 #define ISNS_DISABLE                            0
 224 #define ISNS_ENABLE                             1
 225 #define MBOX_CMD_COPY_FLASH                     0x0024
 226 #define MBOX_CMD_WRITE_FLASH                    0x0025
 227 #define MBOX_CMD_READ_FLASH                     0x0026
 228 #define MBOX_CMD_CLEAR_DATABASE_ENTRY           0x0031
 229 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT         0x0056
 230 #define LOGOUT_OPTION_CLOSE_SESSION             0x01
 231 #define LOGOUT_OPTION_RELOGIN                   0x02
 232 #define MBOX_CMD_EXECUTE_IOCB_A64               0x005A
 233 #define MBOX_CMD_INITIALIZE_FIRMWARE            0x0060
 234 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK         0x0061
 235 #define MBOX_CMD_REQUEST_DATABASE_ENTRY         0x0062
 236 #define MBOX_CMD_SET_DATABASE_ENTRY             0x0063
 237 #define MBOX_CMD_GET_DATABASE_ENTRY             0x0064
 238 #define DDB_DS_UNASSIGNED                       0x00
 239 #define DDB_DS_NO_CONNECTION_ACTIVE             0x01
 240 #define DDB_DS_SESSION_ACTIVE                   0x04
 241 #define DDB_DS_SESSION_FAILED                   0x06
 242 #define DDB_DS_LOGIN_IN_PROCESS                 0x07
 243 #define MBOX_CMD_GET_FW_STATE                   0x0069
 244 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
 245 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS       0x0087
 246 #define MBOX_CMD_SET_ACB                        0x0088
 247 #define MBOX_CMD_GET_ACB                        0x0089
 248 #define MBOX_CMD_DISABLE_ACB                    0x008A
 249 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE        0x008B
 250 #define MBOX_CMD_GET_IPV6_DEST_CACHE            0x008C
 251 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST       0x008D
 252 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST       0x008E
 253 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE        0x0090
 254 #define MBOX_CMD_GET_IP_ADDR_STATE              0x0091
 255 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL           0x0092
 256 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR   0x0093
 257
 258 /* Mailbox 1 */
 259 #define FW_STATE_READY                          0x0000
 260 #define FW_STATE_CONFIG_WAIT                    0x0001
 261 #define FW_STATE_WAIT_LOGIN                     0x0002
 262 #define FW_STATE_ERROR                          0x0004
 263 #define FW_STATE_DHCP_IN_PROGRESS               0x0008
 264
 265 /* Mailbox 3 */
 266 #define FW_ADDSTATE_OPTICAL_MEDIA               0x0001
 267 #define FW_ADDSTATE_DHCP_ENABLED                0x0002
 268 #define FW_ADDSTATE_LINK_UP                     0x0010
 269 #define FW_ADDSTATE_ISNS_SVC_ENABLED            0x0020
 270 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS    0x006B
 271 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN           0x0074
 272 #define MBOX_CMD_GET_CRASH_RECORD               0x0076  /* 4010 only */
 273 #define MBOX_CMD_GET_CONN_EVENT_LOG             0x0077
 274
 275 /*  Mailbox status definitions */
 276 #define MBOX_COMPLETION_STATUS                  4
 277 #define MBOX_STS_BUSY                           0x0007
 278 #define MBOX_STS_INTERMEDIATE_COMPLETION        0x1000
 279 #define MBOX_STS_COMMAND_COMPLETE               0x4000
 280 #define MBOX_STS_COMMAND_ERROR                  0x4005
 281
 282 #define MBOX_ASYNC_EVENT_STATUS                 8
 283 #define MBOX_ASTS_SYSTEM_ERROR                  0x8002
 284 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR        0x8003
 285 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR       0x8004
 286 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM      0x8005
 287 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED     0x8006
 288 #define MBOX_ASTS_LINK_UP                       0x8010
 289 #define MBOX_ASTS_LINK_DOWN                     0x8011
 290 #define MBOX_ASTS_DATABASE_CHANGED              0x8014
 291 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED      0x8015
 292 #define MBOX_ASTS_SELF_TEST_FAILED              0x8016
 293 #define MBOX_ASTS_LOGIN_FAILED                  0x8017
 294 #define MBOX_ASTS_DNS                           0x8018
 295 #define MBOX_ASTS_HEARTBEAT                     0x8019
 296 #define MBOX_ASTS_NVRAM_INVALID                 0x801A
 297 #define MBOX_ASTS_MAC_ADDRESS_CHANGED           0x801B
 298 #define MBOX_ASTS_IP_ADDRESS_CHANGED            0x801C
 299 #define MBOX_ASTS_DHCP_LEASE_EXPIRED            0x801D
 300 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED           0x801F
 301 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
 302 #define MBOX_ASTS_DUPLICATE_IP                  0x8025
 303 #define MBOX_ASTS_ARP_COMPLETE                  0x8026
 304 #define MBOX_ASTS_SUBNET_STATE_CHANGE           0x8027
 305 #define MBOX_ASTS_RESPONSE_QUEUE_FULL           0x8028
 306 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED         0x8029
 307 #define MBOX_ASTS_IPV6_PREFIX_EXPIRED           0x802B
 308 #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED        0x802C
 309 #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED       0x802D
 310 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD         0x802E
 311
 312 #define ISNS_EVENT_DATA_RECEIVED                0x0000
 313 #define ISNS_EVENT_CONNECTION_OPENED            0x0001
 314 #define ISNS_EVENT_CONNECTION_FAILED            0x0002
 315 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR      0x8022
 316 #define MBOX_ASTS_SUBNET_STATE_CHANGE           0x8027
 317
 318 /*************************************************************************/
 319
 320 /* Host Adapter Initialization Control Block (from host) */
 321 struct addr_ctrl_blk {
 322         uint8_t version;        /* 00 */
 323         uint8_t control;        /* 01 */
 324
 325         uint16_t fw_options;    /* 02-03 */
 326 #define  FWOPT_HEARTBEAT_ENABLE           0x1000
 327 #define  FWOPT_SESSION_MODE               0x0040
 328 #define  FWOPT_INITIATOR_MODE             0x0020
 329 #define  FWOPT_TARGET_MODE                0x0010
 330
 331         uint16_t exec_throttle; /* 04-05 */
 332         uint8_t zio_count;      /* 06 */
 333         uint8_t res0;   /* 07 */
 334         uint16_t eth_mtu_size;  /* 08-09 */
 335         uint16_t add_fw_options;        /* 0A-0B */
 336
 337         uint8_t hb_interval;    /* 0C */
 338         uint8_t inst_num; /* 0D */
 339         uint16_t res1;          /* 0E-0F */
 340         uint16_t rqq_consumer_idx;      /* 10-11 */
 341         uint16_t compq_producer_idx;    /* 12-13 */
 342         uint16_t rqq_len;       /* 14-15 */
 343         uint16_t compq_len;     /* 16-17 */
 344         uint32_t rqq_addr_lo;   /* 18-1B */
 345         uint32_t rqq_addr_hi;   /* 1C-1F */
 346         uint32_t compq_addr_lo; /* 20-23 */
 347         uint32_t compq_addr_hi; /* 24-27 */
 348         uint32_t shdwreg_addr_lo;       /* 28-2B */
 349         uint32_t shdwreg_addr_hi;       /* 2C-2F */
 350
 351         uint16_t iscsi_opts;    /* 30-31 */
 352         uint16_t ipv4_tcp_opts; /* 32-33 */
 353         uint16_t ipv4_ip_opts;  /* 34-35 */
 354
 355         uint16_t iscsi_max_pdu_size;    /* 36-37 */
 356         uint8_t ipv4_tos;       /* 38 */
 357         uint8_t ipv4_ttl;       /* 39 */
 358         uint8_t acb_version;    /* 3A */
 359         uint8_t res2;   /* 3B */
 360         uint16_t def_timeout;   /* 3C-3D */
 361         uint16_t iscsi_fburst_len;      /* 3E-3F */
 362         uint16_t iscsi_def_time2wait;   /* 40-41 */
 363         uint16_t iscsi_def_time2retain; /* 42-43 */
 364         uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
 365         uint16_t conn_ka_timeout;       /* 46-47 */
 366         uint16_t ipv4_port;     /* 48-49 */
 367         uint16_t iscsi_max_burst_len;   /* 4A-4B */
 368         uint32_t res5;          /* 4C-4F */
 369         uint8_t ipv4_addr[4];   /* 50-53 */
 370         uint16_t ipv4_vlan_tag; /* 54-55 */
 371         uint8_t ipv4_addr_state;        /* 56 */
 372         uint8_t ipv4_cacheid;   /* 57 */
 373         uint8_t res6[8];        /* 58-5F */
 374         uint8_t ipv4_subnet[4]; /* 60-63 */
 375         uint8_t res7[12];       /* 64-6F */
 376         uint8_t ipv4_gw_addr[4];        /* 70-73 */
 377         uint8_t res8[0xc];      /* 74-7F */
 378         uint8_t pri_dns_srvr_ip[4];/* 80-83 */
 379         uint8_t sec_dns_srvr_ip[4];/* 84-87 */
 380         uint16_t min_eph_port;  /* 88-89 */
 381         uint16_t max_eph_port;  /* 8A-8B */
 382         uint8_t res9[4];        /* 8C-8F */
 383         uint8_t iscsi_alias[32];/* 90-AF */
 384         uint8_t res9_1[0x16];   /* B0-C5 */
 385         uint16_t tgt_portal_grp;/* C6-C7 */
 386         uint8_t abort_timer;    /* C8    */
 387         uint8_t ipv4_tcp_wsf;   /* C9    */
 388         uint8_t res10[6];       /* CA-CF */
 389         uint8_t ipv4_sec_ip_addr[4];    /* D0-D3 */
 390         uint8_t ipv4_dhcp_vid_len;      /* D4 */
 391         uint8_t ipv4_dhcp_vid[11];      /* D5-DF */
 392         uint8_t res11[20];      /* E0-F3 */
 393         uint8_t ipv4_dhcp_alt_cid_len;  /* F4 */
 394         uint8_t ipv4_dhcp_alt_cid[11];  /* F5-FF */
 395         uint8_t iscsi_name[224];        /* 100-1DF */
 396         uint8_t res12[32];      /* 1E0-1FF */
 397         uint32_t cookie;        /* 200-203 */
 398         uint16_t ipv6_port;     /* 204-205 */
 399         uint16_t ipv6_opts;     /* 206-207 */
 400         uint16_t ipv6_addtl_opts;       /* 208-209 */
 401         uint16_t ipv6_tcp_opts; /* 20A-20B */
 402         uint8_t ipv6_tcp_wsf;   /* 20C */
 403         uint16_t ipv6_flow_lbl; /* 20D-20F */
 404         uint8_t ipv6_gw_addr[16];       /* 210-21F */
 405         uint16_t ipv6_vlan_tag; /* 220-221 */
 406         uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
 407         uint8_t ipv6_addr0_state;       /* 223 */
 408         uint8_t ipv6_addr1_state;       /* 224 */
 409         uint8_t ipv6_gw_state;  /* 225 */
 410         uint8_t ipv6_traffic_class;     /* 226 */
 411         uint8_t ipv6_hop_limit; /* 227 */
 412         uint8_t ipv6_if_id[8];  /* 228-22F */
 413         uint8_t ipv6_addr0[16]; /* 230-23F */
 414         uint8_t ipv6_addr1[16]; /* 240-24F */
 415         uint32_t ipv6_nd_reach_time;    /* 250-253 */
 416         uint32_t ipv6_nd_rexmit_timer;  /* 254-257 */
 417         uint32_t ipv6_nd_stale_timeout; /* 258-25B */
 418         uint8_t ipv6_dup_addr_detect_count;     /* 25C */
 419         uint8_t ipv6_cache_id;  /* 25D */
 420         uint8_t res13[18];      /* 25E-26F */
 421         uint32_t ipv6_gw_advrt_mtu;     /* 270-273 */
 422         uint8_t res14[140];     /* 274-2FF */
 423 };
 424
 425 struct init_fw_ctrl_blk {
 426         struct addr_ctrl_blk pri;
 427         struct addr_ctrl_blk sec;
 428 };
 429
 430 /*************************************************************************/
 431
 432 struct dev_db_entry {
 433         uint16_t options;       /* 00-01 */
 434 #define DDB_OPT_DISC_SESSION  0x10
 435 #define DDB_OPT_TARGET        0x02 /* device is a target */
 436
 437         uint16_t exec_throttle; /* 02-03 */
 438         uint16_t exec_count;    /* 04-05 */
 439         uint16_t res0;  /* 06-07 */
 440         uint16_t iscsi_options; /* 08-09 */
 441         uint16_t tcp_options;   /* 0A-0B */
 442         uint16_t ip_options;    /* 0C-0D */
 443         uint16_t iscsi_max_rcv_data_seg_len;    /* 0E-0F */
 444         uint32_t res1;  /* 10-13 */
 445         uint16_t iscsi_max_snd_data_seg_len;    /* 14-15 */
 446         uint16_t iscsi_first_burst_len; /* 16-17 */
 447         uint16_t iscsi_def_time2wait;   /* 18-19 */
 448         uint16_t iscsi_def_time2retain; /* 1A-1B */
 449         uint16_t iscsi_max_outsnd_r2t;  /* 1C-1D */
 450         uint16_t ka_timeout;    /* 1E-1F */
 451         uint8_t isid[6];        /* 20-25 big-endian, must be converted
 452                                  * to little-endian */
 453         uint16_t tsid;          /* 26-27 */
 454         uint16_t port;  /* 28-29 */
 455         uint16_t iscsi_max_burst_len;   /* 2A-2B */
 456         uint16_t def_timeout;   /* 2C-2D */
 457         uint16_t res2;  /* 2E-2F */
 458         uint8_t ip_addr[0x10];  /* 30-3F */
 459         uint8_t iscsi_alias[0x20];      /* 40-5F */
 460         uint8_t tgt_addr[0x20]; /* 60-7F */
 461         uint16_t mss;   /* 80-81 */
 462         uint16_t res3;  /* 82-83 */
 463         uint16_t lcl_port;      /* 84-85 */
 464         uint8_t ipv4_tos;       /* 86 */
 465         uint16_t ipv6_flow_lbl; /* 87-89 */
 466         uint8_t res4[0x36];     /* 8A-BF */
 467         uint8_t iscsi_name[0xE0];       /* C0-19F : xxzzy Make this a
 468                                          * pointer to a string so we
 469                                          * don't have to reserve soooo
 470                                          * much RAM */
 471         uint8_t ipv6_addr[0x10];/* 1A0-1AF */
 472         uint8_t res5[0x10];     /* 1B0-1BF */
 473         uint16_t ddb_link;      /* 1C0-1C1 */
 474         uint16_t chap_tbl_idx;  /* 1C2-1C3 */
 475         uint16_t tgt_portal_grp; /* 1C4-1C5 */
 476         uint8_t tcp_xmt_wsf;    /* 1C6 */
 477         uint8_t tcp_rcv_wsf;    /* 1C7 */
 478         uint32_t stat_sn;       /* 1C8-1CB */
 479         uint32_t exp_stat_sn;   /* 1CC-1CF */
 480         uint8_t res6[0x30];     /* 1D0-1FF */
 481 };
 482
 483 /*************************************************************************/
 484
 485 /* Flash definitions */
 486
 487 #define FLASH_OFFSET_SYS_INFO   0x02000000
 488 #define FLASH_DEFAULTBLOCKSIZE  0x20000
 489 #define FLASH_EOF_OFFSET        (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
 490                                                             * for EOF
 491                                                             * signature */
 492
 493 struct sys_info_phys_addr {
 494         uint8_t address[6];     /* 00-05 */
 495         uint8_t filler[2];      /* 06-07 */
 496 };
 497
 498 struct flash_sys_info {
 499         uint32_t cookie;        /* 00-03 */
 500         uint32_t physAddrCount; /* 04-07 */
 501         struct sys_info_phys_addr physAddr[4]; /* 08-27 */
 502         uint8_t vendorId[128];  /* 28-A7 */
 503         uint8_t productId[128]; /* A8-127 */
 504         uint32_t serialNumber;  /* 128-12B */
 505
 506         /*  PCI Configuration values */
 507         uint32_t pciDeviceVendor;       /* 12C-12F */
 508         uint32_t pciDeviceId;   /* 130-133 */
 509         uint32_t pciSubsysVendor;       /* 134-137 */
 510         uint32_t pciSubsysId;   /* 138-13B */
 511
 512         /*  This validates version 1. */
 513         uint32_t crumbs;        /* 13C-13F */
 514
 515         uint32_t enterpriseNumber;      /* 140-143 */
 516
 517         uint32_t mtu;           /* 144-147 */
 518         uint32_t reserved0;     /* 148-14b */
 519         uint32_t crumbs2;       /* 14c-14f */
 520         uint8_t acSerialNumber[16];     /* 150-15f */
 521         uint32_t crumbs3;       /* 160-16f */
 522
 523         /* Leave this last in the struct so it is declared invalid if
 524          * any new items are added.
 525          */
 526         uint32_t reserved1[39]; /* 170-1ff */
 527 };      /* 200 */
 528
 529 struct crash_record {
 530         uint16_t fw_major_version;      /* 00 - 01 */
 531         uint16_t fw_minor_version;      /* 02 - 03 */
 532         uint16_t fw_patch_version;      /* 04 - 05 */
 533         uint16_t fw_build_version;      /* 06 - 07 */
 534
 535         uint8_t build_date[16]; /* 08 - 17 */
 536         uint8_t build_time[16]; /* 18 - 27 */
 537         uint8_t build_user[16]; /* 28 - 37 */
 538         uint8_t card_serial_num[16];    /* 38 - 47 */
 539
 540         uint32_t time_of_crash_in_secs; /* 48 - 4B */
 541         uint32_t time_of_crash_in_ms;   /* 4C - 4F */
 542
 543         uint16_t out_RISC_sd_num_frames;        /* 50 - 51 */
 544         uint16_t OAP_sd_num_words;      /* 52 - 53 */
 545         uint16_t IAP_sd_num_frames;     /* 54 - 55 */
 546         uint16_t in_RISC_sd_num_words;  /* 56 - 57 */
 547
 548         uint8_t reserved1[28];  /* 58 - 7F */
 549
 550         uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
 551         uint8_t in_RISC_reg_dump[256];  /*180 -27F */
 552         uint8_t in_out_RISC_stack_dump[0];      /*280 - ??? */
 553 };
 554
 555 struct conn_event_log_entry {
 556 #define MAX_CONN_EVENT_LOG_ENTRIES      100
 557         uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
 558         uint32_t timestamp_ms;  /* 04 - 07 milliseconds since boot */
 559         uint16_t device_index;  /* 08 - 09  */
 560         uint16_t fw_conn_state; /* 0A - 0B  */
 561         uint8_t event_type;     /* 0C - 0C  */
 562         uint8_t error_code;     /* 0D - 0D  */
 563         uint16_t error_code_detail;     /* 0E - 0F  */
 564         uint8_t num_consecutive_events; /* 10 - 10  */
 565         uint8_t rsvd[3];        /* 11 - 13  */
 566 };
 567
 568 /*************************************************************************
 569  *
 570  *                              IOCB Commands Structures and Definitions
 571  *
 572  *************************************************************************/
 573 #define IOCB_MAX_CDB_LEN            16  /* Bytes in a CBD */
 574 #define IOCB_MAX_SENSEDATA_LEN      32  /* Bytes of sense data */
 575
 576 /* IOCB header structure */
 577 struct qla4_header {
 578         uint8_t entryType;
 579 #define ET_STATUS                0x03
 580 #define ET_MARKER                0x04
 581 #define ET_CONT_T1               0x0A
 582 #define ET_STATUS_CONTINUATION   0x10
 583 #define ET_CMND_T3               0x19
 584 #define ET_PASSTHRU0             0x3A
 585 #define ET_PASSTHRU_STATUS       0x3C
 586
 587         uint8_t entryStatus;
 588         uint8_t systemDefined;
 589         uint8_t entryCount;
 590
 591         /* SyetemDefined definition */
 592 };
 593
 594 /* Generic queue entry structure*/
 595 struct queue_entry {
 596         uint8_t data[60];
 597         uint32_t signature;
 598
 599 };
 600
 601 /* 64 bit addressing segment counts*/
 602
 603 #define COMMAND_SEG_A64   1
 604 #define CONTINUE_SEG_A64  5
 605
 606 /* 64 bit addressing segment definition*/
 607
 608 struct data_seg_a64 {
 609         struct {
 610                 uint32_t addrLow;
 611                 uint32_t addrHigh;
 612
 613         } base;
 614
 615         uint32_t count;
 616
 617 };
 618
 619 /* Command Type 3 entry structure*/
 620
 621 struct command_t3_entry {
 622         struct qla4_header hdr; /* 00-03 */
 623
 624         uint32_t handle;        /* 04-07 */
 625         uint16_t target;        /* 08-09 */
 626         uint16_t connection_id; /* 0A-0B */
 627
 628         uint8_t control_flags;  /* 0C */
 629
 630         /* data direction  (bits 5-6) */
 631 #define CF_WRITE                0x20
 632 #define CF_READ                 0x40
 633 #define CF_NO_DATA              0x00
 634
 635         /* task attributes (bits 2-0) */
 636 #define CF_HEAD_TAG             0x03
 637 #define CF_ORDERED_TAG          0x02
 638 #define CF_SIMPLE_TAG           0x01
 639
 640         /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
 641          * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
 642          * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
 643          * PROPERLY.
 644          */
 645         uint8_t state_flags;    /* 0D */
 646         uint8_t cmdRefNum;      /* 0E */
 647         uint8_t reserved1;      /* 0F */
 648         uint8_t cdb[IOCB_MAX_CDB_LEN];  /* 10-1F */
 649         struct scsi_lun lun;    /* FCP LUN (BE). */
 650         uint32_t cmdSeqNum;     /* 28-2B */
 651         uint16_t timeout;       /* 2C-2D */
 652         uint16_t dataSegCnt;    /* 2E-2F */
 653         uint32_t ttlByteCnt;    /* 30-33 */
 654         struct data_seg_a64 dataseg[COMMAND_SEG_A64];   /* 34-3F */
 655
 656 };
 657
 658
 659 /* Continuation Type 1 entry structure*/
 660 struct continuation_t1_entry {
 661         struct qla4_header hdr;
 662
 663         struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
 664
 665 };
 666
 667 /* Parameterize for 64 or 32 bits */
 668 #define COMMAND_SEG     COMMAND_SEG_A64
 669 #define CONTINUE_SEG    CONTINUE_SEG_A64
 670
 671 #define ET_COMMAND      ET_CMND_T3
 672 #define ET_CONTINUE     ET_CONT_T1
 673
 674 /* Marker entry structure*/
 675 struct qla4_marker_entry {
 676         struct qla4_header hdr; /* 00-03 */
 677
 678         uint32_t system_defined; /* 04-07 */
 679         uint16_t target;        /* 08-09 */
 680         uint16_t modifier;      /* 0A-0B */
 681 #define MM_LUN_RESET            0
 682 #define MM_TGT_WARM_RESET       1
 683
 684         uint16_t flags;         /* 0C-0D */
 685         uint16_t reserved1;     /* 0E-0F */
 686         struct scsi_lun lun;    /* FCP LUN (BE). */
 687         uint64_t reserved2;     /* 18-1F */
 688         uint64_t reserved3;     /* 20-27 */
 689         uint64_t reserved4;     /* 28-2F */
 690         uint64_t reserved5;     /* 30-37 */
 691         uint64_t reserved6;     /* 38-3F */
 692 };
 693
 694 /* Status entry structure*/
 695 struct status_entry {
 696         struct qla4_header hdr; /* 00-03 */
 697
 698         uint32_t handle;        /* 04-07 */
 699
 700         uint8_t scsiStatus;     /* 08 */
 701 #define SCSI_CHECK_CONDITION              0x02
 702
 703         uint8_t iscsiFlags;     /* 09 */
 704 #define ISCSI_FLAG_RESIDUAL_UNDER         0x02
 705 #define ISCSI_FLAG_RESIDUAL_OVER          0x04
 706
 707         uint8_t iscsiResponse;  /* 0A */
 708
 709         uint8_t completionStatus;       /* 0B */
 710 #define SCS_COMPLETE                      0x00
 711 #define SCS_INCOMPLETE                    0x01
 712 #define SCS_RESET_OCCURRED                0x04
 713 #define SCS_ABORTED                       0x05
 714 #define SCS_TIMEOUT                       0x06
 715 #define SCS_DATA_OVERRUN                  0x07
 716 #define SCS_DATA_UNDERRUN                 0x15
 717 #define SCS_QUEUE_FULL                    0x1C
 718 #define SCS_DEVICE_UNAVAILABLE            0x28
 719 #define SCS_DEVICE_LOGGED_OUT             0x29
 720
 721         uint8_t reserved1;      /* 0C */
 722
 723         /* state_flags MUST be at the same location as state_flags in
 724          * the Command_T3/4_Entry */
 725         uint8_t state_flags;    /* 0D */
 726
 727         uint16_t senseDataByteCnt;      /* 0E-0F */
 728         uint32_t residualByteCnt;       /* 10-13 */
 729         uint32_t bidiResidualByteCnt;   /* 14-17 */
 730         uint32_t expSeqNum;     /* 18-1B */
 731         uint32_t maxCmdSeqNum;  /* 1C-1F */
 732         uint8_t senseData[IOCB_MAX_SENSEDATA_LEN];      /* 20-3F */
 733
 734 };
 735
 736 struct passthru0 {
 737         struct qla4_header hdr;                /* 00-03 */
 738         uint32_t handle;        /* 04-07 */
 739         uint16_t target;        /* 08-09 */
 740         uint16_t connectionID;  /* 0A-0B */
 741 #define ISNS_DEFAULT_SERVER_CONN_ID     ((uint16_t)0x8000)
 742
 743         uint16_t controlFlags;  /* 0C-0D */
 744 #define PT_FLAG_ETHERNET_FRAME          0x8000
 745 #define PT_FLAG_ISNS_PDU                0x8000
 746 #define PT_FLAG_SEND_BUFFER             0x0200
 747 #define PT_FLAG_WAIT_4_RESPONSE         0x0100
 748
 749         uint16_t timeout;       /* 0E-0F */
 750 #define PT_DEFAULT_TIMEOUT              30 /* seconds */
 751
 752         struct data_seg_a64 outDataSeg64;       /* 10-1B */
 753         uint32_t res1;          /* 1C-1F */
 754         struct data_seg_a64 inDataSeg64;        /* 20-2B */
 755         uint8_t res2[20];       /* 2C-3F */
 756 };
 757
 758 struct passthru_status {
 759         struct qla4_header hdr;                /* 00-03 */
 760         uint32_t handle;        /* 04-07 */
 761         uint16_t target;        /* 08-09 */
 762         uint16_t connectionID;  /* 0A-0B */
 763
 764         uint8_t completionStatus;       /* 0C */
 765 #define PASSTHRU_STATUS_COMPLETE                0x01
 766
 767         uint8_t residualFlags;  /* 0D */
 768
 769         uint16_t timeout;       /* 0E-0F */
 770         uint16_t portNumber;    /* 10-11 */
 771         uint8_t res1[10];       /* 12-1B */
 772         uint32_t outResidual;   /* 1C-1F */
 773         uint8_t res2[12];       /* 20-2B */
 774         uint32_t inResidual;    /* 2C-2F */
 775         uint8_t res4[16];       /* 30-3F */
 776 };
 777
 778 #endif /*  _QLA4X_FW_H */