git.oblomov.eu Git - linux-2.6/blob - drivers/video/imsttfb.c

   1 /*
   2  *  drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
   3  *
   4  *  This file is derived from the powermac console "imstt" driver:
   5  *  Copyright (C) 1997 Sigurdur Asgeirsson
   6  *  With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
   7  *  Modified by Danilo Beuche 1998
   8  *  Some register values added by Damien Doligez, INRIA Rocquencourt
   9  *  Various cleanups by Paul Mundt (lethal@chaoticdreams.org)
  10  *
  11  *  This file was written by Ryan Nielsen (ran@krazynet.com)
  12  *  Most of the frame buffer device stuff was copied from atyfb.c
  13  *
  14  *  This file is subject to the terms and conditions of the GNU General Public
  15  *  License. See the file COPYING in the main directory of this archive for
  16  *  more details.
  17  */
  18
  19 #include <linux/config.h>
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/mm.h>
  25 #include <linux/tty.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/fb.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <asm/io.h>
  34 #include <asm/uaccess.h>
  35
  36 #if defined(CONFIG_PPC)
  37 #include <linux/nvram.h>
  38 #include <asm/prom.h>
  39 #include <asm/pci-bridge.h>
  40 #include "macmodes.h"
  41 #endif
  42
  43 #ifndef __powerpc__
  44 #define eieio()         /* Enforce In-order Execution of I/O */
  45 #endif
  46
  47 /* TwinTurbo (Cosmo) registers */
  48 enum {
  49         S1SA    =  0, /* 0x00 */
  50         S2SA    =  1, /* 0x04 */
  51         SP      =  2, /* 0x08 */
  52         DSA     =  3, /* 0x0C */
  53         CNT     =  4, /* 0x10 */
  54         DP_OCTL =  5, /* 0x14 */
  55         CLR     =  6, /* 0x18 */
  56         BI      =  8, /* 0x20 */
  57         MBC     =  9, /* 0x24 */
  58         BLTCTL  = 10, /* 0x28 */
  59
  60         /* Scan Timing Generator Registers */
  61         HES     = 12, /* 0x30 */
  62         HEB     = 13, /* 0x34 */
  63         HSB     = 14, /* 0x38 */
  64         HT      = 15, /* 0x3C */
  65         VES     = 16, /* 0x40 */
  66         VEB     = 17, /* 0x44 */
  67         VSB     = 18, /* 0x48 */
  68         VT      = 19, /* 0x4C */
  69         HCIV    = 20, /* 0x50 */
  70         VCIV    = 21, /* 0x54 */
  71         TCDR    = 22, /* 0x58 */
  72         VIL     = 23, /* 0x5C */
  73         STGCTL  = 24, /* 0x60 */
  74
  75         /* Screen Refresh Generator Registers */
  76         SSR     = 25, /* 0x64 */
  77         HRIR    = 26, /* 0x68 */
  78         SPR     = 27, /* 0x6C */
  79         CMR     = 28, /* 0x70 */
  80         SRGCTL  = 29, /* 0x74 */
  81
  82         /* RAM Refresh Generator Registers */
  83         RRCIV   = 30, /* 0x78 */
  84         RRSC    = 31, /* 0x7C */
  85         RRCR    = 34, /* 0x88 */
  86
  87         /* System Registers */
  88         GIOE    = 32, /* 0x80 */
  89         GIO     = 33, /* 0x84 */
  90         SCR     = 35, /* 0x8C */
  91         SSTATUS = 36, /* 0x90 */
  92         PRC     = 37, /* 0x94 */
  93
  94 #if 0
  95         /* PCI Registers */
  96         DVID    = 0x00000000L,
  97         SC      = 0x00000004L,
  98         CCR     = 0x00000008L,
  99         OG      = 0x0000000CL,
 100         BARM    = 0x00000010L,
 101         BARER   = 0x00000030L,
 102 #endif
 103 };
 104
 105 /* IBM 624 RAMDAC Direct Registers */
 106 enum {
 107         PADDRW  = 0x00,
 108         PDATA   = 0x04,
 109         PPMASK  = 0x08,
 110         PADDRR  = 0x0c,
 111         PIDXLO  = 0x10,
 112         PIDXHI  = 0x14,
 113         PIDXDATA= 0x18,
 114         PIDXCTL = 0x1c
 115 };
 116
 117 /* IBM 624 RAMDAC Indirect Registers */
 118 enum {
 119         CLKCTL          = 0x02, /* (0x01) Miscellaneous Clock Control */
 120         SYNCCTL         = 0x03, /* (0x00) Sync Control */
 121         HSYNCPOS        = 0x04, /* (0x00) Horizontal Sync Position */
 122         PWRMNGMT        = 0x05, /* (0x00) Power Management */
 123         DACOP           = 0x06, /* (0x02) DAC Operation */
 124         PALETCTL        = 0x07, /* (0x00) Palette Control */
 125         SYSCLKCTL       = 0x08, /* (0x01) System Clock Control */
 126         PIXFMT          = 0x0a, /* () Pixel Format  [bpp >> 3 + 2] */
 127         BPP8            = 0x0b, /* () 8 Bits/Pixel Control */
 128         BPP16           = 0x0c, /* () 16 Bits/Pixel Control  [bit 1=1 for 565] */
 129         BPP24           = 0x0d, /* () 24 Bits/Pixel Control */
 130         BPP32           = 0x0e, /* () 32 Bits/Pixel Control */
 131         PIXCTL1         = 0x10, /* (0x05) Pixel PLL Control 1 */
 132         PIXCTL2         = 0x11, /* (0x00) Pixel PLL Control 2 */
 133         SYSCLKN         = 0x15, /* () System Clock N (System PLL Reference Divider) */
 134         SYSCLKM         = 0x16, /* () System Clock M (System PLL VCO Divider) */
 135         SYSCLKP         = 0x17, /* () System Clock P */
 136         SYSCLKC         = 0x18, /* () System Clock C */
 137         /*
 138          * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
 139          * c is charge pump bias which depends on the VCO frequency
 140          */
 141         PIXM0           = 0x20, /* () Pixel M 0 */
 142         PIXN0           = 0x21, /* () Pixel N 0 */
 143         PIXP0           = 0x22, /* () Pixel P 0 */
 144         PIXC0           = 0x23, /* () Pixel C 0 */
 145         CURSCTL         = 0x30, /* (0x00) Cursor Control */
 146         CURSXLO         = 0x31, /* () Cursor X position, low 8 bits */
 147         CURSXHI         = 0x32, /* () Cursor X position, high 8 bits */
 148         CURSYLO         = 0x33, /* () Cursor Y position, low 8 bits */
 149         CURSYHI         = 0x34, /* () Cursor Y position, high 8 bits */
 150         CURSHOTX        = 0x35, /* () Cursor Hot Spot X */
 151         CURSHOTY        = 0x36, /* () Cursor Hot Spot Y */
 152         CURSACCTL       = 0x37, /* () Advanced Cursor Control Enable */
 153         CURSACATTR      = 0x38, /* () Advanced Cursor Attribute */
 154         CURS1R          = 0x40, /* () Cursor 1 Red */
 155         CURS1G          = 0x41, /* () Cursor 1 Green */
 156         CURS1B          = 0x42, /* () Cursor 1 Blue */
 157         CURS2R          = 0x43, /* () Cursor 2 Red */
 158         CURS2G          = 0x44, /* () Cursor 2 Green */
 159         CURS2B          = 0x45, /* () Cursor 2 Blue */
 160         CURS3R          = 0x46, /* () Cursor 3 Red */
 161         CURS3G          = 0x47, /* () Cursor 3 Green */
 162         CURS3B          = 0x48, /* () Cursor 3 Blue */
 163         BORDR           = 0x60, /* () Border Color Red */
 164         BORDG           = 0x61, /* () Border Color Green */
 165         BORDB           = 0x62, /* () Border Color Blue */
 166         MISCTL1         = 0x70, /* (0x00) Miscellaneous Control 1 */
 167         MISCTL2         = 0x71, /* (0x00) Miscellaneous Control 2 */
 168         MISCTL3         = 0x72, /* (0x00) Miscellaneous Control 3 */
 169         KEYCTL          = 0x78  /* (0x00) Key Control/DB Operation */
 170 };
 171
 172 /* TI TVP 3030 RAMDAC Direct Registers */
 173 enum {
 174         TVPADDRW = 0x00,        /* 0  Palette/Cursor RAM Write Address/Index */
 175         TVPPDATA = 0x04,        /* 1  Palette Data RAM Data */
 176         TVPPMASK = 0x08,        /* 2  Pixel Read-Mask */
 177         TVPPADRR = 0x0c,        /* 3  Palette/Cursor RAM Read Address */
 178         TVPCADRW = 0x10,        /* 4  Cursor/Overscan Color Write Address */
 179         TVPCDATA = 0x14,        /* 5  Cursor/Overscan Color Data */
 180                                 /* 6  reserved */
 181         TVPCADRR = 0x1c,        /* 7  Cursor/Overscan Color Read Address */
 182                                 /* 8  reserved */
 183         TVPDCCTL = 0x24,        /* 9  Direct Cursor Control */
 184         TVPIDATA = 0x28,        /* 10 Index Data */
 185         TVPCRDAT = 0x2c,        /* 11 Cursor RAM Data */
 186         TVPCXPOL = 0x30,        /* 12 Cursor-Position X LSB */
 187         TVPCXPOH = 0x34,        /* 13 Cursor-Position X MSB */
 188         TVPCYPOL = 0x38,        /* 14 Cursor-Position Y LSB */
 189         TVPCYPOH = 0x3c,        /* 15 Cursor-Position Y MSB */
 190 };
 191
 192 /* TI TVP 3030 RAMDAC Indirect Registers */
 193 enum {
 194         TVPIRREV = 0x01,        /* Silicon Revision [RO] */
 195         TVPIRICC = 0x06,        /* Indirect Cursor Control      (0x00) */
 196         TVPIRBRC = 0x07,        /* Byte Router Control  (0xe4) */
 197         TVPIRLAC = 0x0f,        /* Latch Control                (0x06) */
 198         TVPIRTCC = 0x18,        /* True Color Control   (0x80) */
 199         TVPIRMXC = 0x19,        /* Multiplex Control            (0x98) */
 200         TVPIRCLS = 0x1a,        /* Clock Selection              (0x07) */
 201         TVPIRPPG = 0x1c,        /* Palette Page         (0x00) */
 202         TVPIRGEC = 0x1d,        /* General Control              (0x00) */
 203         TVPIRMIC = 0x1e,        /* Miscellaneous Control        (0x00) */
 204         TVPIRPLA = 0x2c,        /* PLL Address */
 205         TVPIRPPD = 0x2d,        /* Pixel Clock PLL Data */
 206         TVPIRMPD = 0x2e,        /* Memory Clock PLL Data */
 207         TVPIRLPD = 0x2f,        /* Loop Clock PLL Data */
 208         TVPIRCKL = 0x30,        /* Color-Key Overlay Low */
 209         TVPIRCKH = 0x31,        /* Color-Key Overlay High */
 210         TVPIRCRL = 0x32,        /* Color-Key Red Low */
 211         TVPIRCRH = 0x33,        /* Color-Key Red High */
 212         TVPIRCGL = 0x34,        /* Color-Key Green Low */
 213         TVPIRCGH = 0x35,        /* Color-Key Green High */
 214         TVPIRCBL = 0x36,        /* Color-Key Blue Low */
 215         TVPIRCBH = 0x37,        /* Color-Key Blue High */
 216         TVPIRCKC = 0x38,        /* Color-Key Control            (0x00) */
 217         TVPIRMLC = 0x39,        /* MCLK/Loop Clock Control      (0x18) */
 218         TVPIRSEN = 0x3a,        /* Sense Test                   (0x00) */
 219         TVPIRTMD = 0x3b,        /* Test Mode Data */
 220         TVPIRRML = 0x3c,        /* CRC Remainder LSB [RO] */
 221         TVPIRRMM = 0x3d,        /* CRC Remainder MSB [RO] */
 222         TVPIRRMS = 0x3e,        /* CRC  Bit Select [WO] */
 223         TVPIRDID = 0x3f,        /* Device ID [RO]               (0x30) */
 224         TVPIRRES = 0xff         /* Software Reset [WO] */
 225 };
 226
 227 struct initvalues {
 228         __u8 addr, value;
 229 };
 230
 231 static struct initvalues ibm_initregs[] __devinitdata = {
 232         { CLKCTL,       0x21 },
 233         { SYNCCTL,      0x00 },
 234         { HSYNCPOS,     0x00 },
 235         { PWRMNGMT,     0x00 },
 236         { DACOP,        0x02 },
 237         { PALETCTL,     0x00 },
 238         { SYSCLKCTL,    0x01 },
 239
 240         /*
 241          * Note that colors in X are correct only if all video data is
 242          * passed through the palette in the DAC.  That is, "indirect
 243          * color" must be configured.  This is the case for the IBM DAC
 244          * used in the 2MB and 4MB cards, at least.
 245          */
 246         { BPP8,         0x00 },
 247         { BPP16,        0x01 },
 248         { BPP24,        0x00 },
 249         { BPP32,        0x00 },
 250
 251         { PIXCTL1,      0x05 },
 252         { PIXCTL2,      0x00 },
 253         { SYSCLKN,      0x08 },
 254         { SYSCLKM,      0x4f },
 255         { SYSCLKP,      0x00 },
 256         { SYSCLKC,      0x00 },
 257         { CURSCTL,      0x00 },
 258         { CURSACCTL,    0x01 },
 259         { CURSACATTR,   0xa8 },
 260         { CURS1R,       0xff },
 261         { CURS1G,       0xff },
 262         { CURS1B,       0xff },
 263         { CURS2R,       0xff },
 264         { CURS2G,       0xff },
 265         { CURS2B,       0xff },
 266         { CURS3R,       0xff },
 267         { CURS3G,       0xff },
 268         { CURS3B,       0xff },
 269         { BORDR,        0xff },
 270         { BORDG,        0xff },
 271         { BORDB,        0xff },
 272         { MISCTL1,      0x01 },
 273         { MISCTL2,      0x45 },
 274         { MISCTL3,      0x00 },
 275         { KEYCTL,       0x00 }
 276 };
 277
 278 static struct initvalues tvp_initregs[] __devinitdata = {
 279         { TVPIRICC,     0x00 },
 280         { TVPIRBRC,     0xe4 },
 281         { TVPIRLAC,     0x06 },
 282         { TVPIRTCC,     0x80 },
 283         { TVPIRMXC,     0x4d },
 284         { TVPIRCLS,     0x05 },
 285         { TVPIRPPG,     0x00 },
 286         { TVPIRGEC,     0x00 },
 287         { TVPIRMIC,     0x08 },
 288         { TVPIRCKL,     0xff },
 289         { TVPIRCKH,     0xff },
 290         { TVPIRCRL,     0xff },
 291         { TVPIRCRH,     0xff },
 292         { TVPIRCGL,     0xff },
 293         { TVPIRCGH,     0xff },
 294         { TVPIRCBL,     0xff },
 295         { TVPIRCBH,     0xff },
 296         { TVPIRCKC,     0x00 },
 297         { TVPIRPLA,     0x00 },
 298         { TVPIRPPD,     0xc0 },
 299         { TVPIRPPD,     0xd5 },
 300         { TVPIRPPD,     0xea },
 301         { TVPIRPLA,     0x00 },
 302         { TVPIRMPD,     0xb9 },
 303         { TVPIRMPD,     0x3a },
 304         { TVPIRMPD,     0xb1 },
 305         { TVPIRPLA,     0x00 },
 306         { TVPIRLPD,     0xc1 },
 307         { TVPIRLPD,     0x3d },
 308         { TVPIRLPD,     0xf3 },
 309 };
 310
 311 struct imstt_regvals {
 312         __u32 pitch;
 313         __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
 314         __u8 pclk_m, pclk_n, pclk_p;
 315         /* Values of the tvp which change depending on colormode x resolution */
 316         __u8 mlc[3];    /* Memory Loop Config 0x39 */
 317         __u8 lckl_p[3]; /* P value of LCKL PLL */
 318 };
 319
 320 struct imstt_par {
 321         struct imstt_regvals init;
 322         __u32 __iomem *dc_regs;
 323         unsigned long cmap_regs_phys;
 324         __u8 *cmap_regs;
 325         __u32 ramdac;
 326         __u32 palette[16];
 327 };
 328
 329 enum {
 330         IBM = 0,
 331         TVP = 1
 332 };
 333
 334 #define USE_NV_MODES            1
 335 #define INIT_BPP                8
 336 #define INIT_XRES               640
 337 #define INIT_YRES               480
 338
 339 static int inverse = 0;
 340 static char fontname[40] __initdata = { 0 };
 341 #if defined(CONFIG_PPC)
 342 static signed char init_vmode __devinitdata = -1, init_cmode __devinitdata = -1;
 343 #endif
 344
 345 static struct imstt_regvals tvp_reg_init_2 = {
 346         512,
 347         0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
 348         0xec, 0x2a, 0xf3,
 349         { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
 350 };
 351
 352 static struct imstt_regvals tvp_reg_init_6 = {
 353         640,
 354         0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
 355         0xef, 0x2e, 0xb2,
 356         { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
 357 };
 358
 359 static struct imstt_regvals tvp_reg_init_12 = {
 360         800,
 361         0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
 362         0xf6, 0x2e, 0xf2,
 363         { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
 364 };
 365
 366 static struct imstt_regvals tvp_reg_init_13 = {
 367         832,
 368         0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
 369         0xfe, 0x3e, 0xf1,
 370         { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
 371 };
 372
 373 static struct imstt_regvals tvp_reg_init_17 = {
 374         1024,
 375         0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
 376         0xfc, 0x3a, 0xf1,
 377         { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
 378 };
 379
 380 static struct imstt_regvals tvp_reg_init_18 = {
 381         1152,
 382         0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
 383         0xfd, 0x3a, 0xf1,
 384         { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
 385 };
 386
 387 static struct imstt_regvals tvp_reg_init_19 = {
 388         1280,
 389         0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
 390         0xf7, 0x36, 0xf0,
 391         { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
 392 };
 393
 394 static struct imstt_regvals tvp_reg_init_20 = {
 395         1280,
 396         0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
 397         0xf0, 0x2d, 0xf0,
 398         { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
 399 };
 400
 401 /*
 402  * PCI driver prototypes
 403  */
 404 static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 405 static void imsttfb_remove(struct pci_dev *pdev);
 406
 407 /*
 408  * Register access
 409  */
 410 static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex)
 411 {
 412 #ifdef __powerpc__
 413         return in_le32(base + regindex);
 414 #else
 415         return readl(base + regindex);
 416 #endif
 417 }
 418
 419 static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val)
 420 {
 421 #ifdef __powerpc__
 422         out_le32(base + regindex, val);
 423 #else
 424         writel(val, base + regindex);
 425 #endif
 426 }
 427
 428 static __u32
 429 getclkMHz(struct imstt_par *par)
 430 {
 431         __u32 clk_m, clk_n, clk_p;
 432
 433         clk_m = par->init.pclk_m;
 434         clk_n = par->init.pclk_n;
 435         clk_p = par->init.pclk_p;
 436
 437         return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
 438 }
 439
 440 static void
 441 setclkMHz(struct imstt_par *par, __u32 MHz)
 442 {
 443         __u32 clk_m, clk_n, clk_p, x, stage, spilled;
 444
 445         clk_m = clk_n = clk_p = 0;
 446         stage = spilled = 0;
 447         for (;;) {
 448                 switch (stage) {
 449                         case 0:
 450                                 clk_m++;
 451                                 break;
 452                         case 1:
 453                                 clk_n++;
 454                                 break;
 455                 }
 456                 x = 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
 457                 if (x == MHz)
 458                         break;
 459                 if (x > MHz) {
 460                         spilled = 1;
 461                         stage = 1;
 462                 } else if (spilled && x < MHz) {
 463                         stage = 0;
 464                 }
 465         }
 466
 467         par->init.pclk_m = clk_m;
 468         par->init.pclk_n = clk_n;
 469         par->init.pclk_p = clk_p;
 470 }
 471
 472 static struct imstt_regvals *
 473 compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres)
 474 {
 475         struct imstt_regvals *init = &par->init;
 476         __u32 MHz, hes, heb, veb, htp, vtp;
 477
 478         switch (xres) {
 479                 case 640:
 480                         hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
 481                         MHz = 30 /* .25 */ ;
 482                         break;
 483                 case 832:
 484                         hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
 485                         MHz = 57 /* .27_ */ ;
 486                         break;
 487                 case 1024:
 488                         hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
 489                         MHz = 80;
 490                         break;
 491                 case 1152:
 492                         hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
 493                         MHz = 101 /* .6_ */ ;
 494                         break;
 495                 case 1280:
 496                         hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
 497                         MHz = yres == 960 ? 126 : 135;
 498                         break;
 499                 case 1600:
 500                         hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
 501                         MHz = 200;
 502                         break;
 503                 default:
 504                         return NULL;
 505         }
 506
 507         setclkMHz(par, MHz);
 508
 509         init->hes = hes;
 510         init->heb = heb;
 511         init->hsb = init->heb + (xres >> 3);
 512         init->ht = init->hsb + htp;
 513         init->ves = 0x0003;
 514         init->veb = veb;
 515         init->vsb = init->veb + yres;
 516         init->vt = init->vsb + vtp;
 517         init->vil = init->vsb;
 518
 519         init->pitch = xres;
 520         return init;
 521 }
 522
 523 static struct imstt_regvals *
 524 compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres)
 525 {
 526         struct imstt_regvals *init;
 527
 528         switch (xres) {
 529                 case 512:
 530                         init = &tvp_reg_init_2;
 531                         break;
 532                 case 640:
 533                         init = &tvp_reg_init_6;
 534                         break;
 535                 case 800:
 536                         init = &tvp_reg_init_12;
 537                         break;
 538                 case 832:
 539                         init = &tvp_reg_init_13;
 540                         break;
 541                 case 1024:
 542                         init = &tvp_reg_init_17;
 543                         break;
 544                 case 1152:
 545                         init = &tvp_reg_init_18;
 546                         break;
 547                 case 1280:
 548                         init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
 549                         break;
 550                 default:
 551                         return NULL;
 552         }
 553         par->init = *init;
 554         return init;
 555 }
 556
 557 static struct imstt_regvals *
 558 compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres)
 559 {
 560         if (par->ramdac == IBM)
 561                 return compute_imstt_regvals_ibm(par, xres, yres);
 562         else
 563                 return compute_imstt_regvals_tvp(par, xres, yres);
 564 }
 565
 566 static void
 567 set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp)
 568 {
 569         struct imstt_regvals *init = &par->init;
 570         __u8 pformat = (bpp >> 3) + 2;
 571
 572         par->cmap_regs[PIDXHI] = 0;             eieio();
 573         par->cmap_regs[PIDXLO] = PIXM0;         eieio();
 574         par->cmap_regs[PIDXDATA] = init->pclk_m;eieio();
 575         par->cmap_regs[PIDXLO] = PIXN0;         eieio();
 576         par->cmap_regs[PIDXDATA] = init->pclk_n;eieio();
 577         par->cmap_regs[PIDXLO] = PIXP0;         eieio();
 578         par->cmap_regs[PIDXDATA] = init->pclk_p;eieio();
 579         par->cmap_regs[PIDXLO] = PIXC0;         eieio();
 580         par->cmap_regs[PIDXDATA] = 0x02;        eieio();
 581
 582         par->cmap_regs[PIDXLO] = PIXFMT;        eieio();
 583         par->cmap_regs[PIDXDATA] = pformat;     eieio();
 584 }
 585
 586 static void
 587 set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp)
 588 {
 589         struct imstt_regvals *init = &par->init;
 590         __u8 tcc, mxc, lckl_n, mic;
 591         __u8 mlc, lckl_p;
 592
 593         switch (bpp) {
 594                 default:
 595                 case 8:
 596                         tcc = 0x80;
 597                         mxc = 0x4d;
 598                         lckl_n = 0xc1;
 599                         mlc = init->mlc[0];
 600                         lckl_p = init->lckl_p[0];
 601                         break;
 602                 case 16:
 603                         tcc = 0x44;
 604                         mxc = 0x55;
 605                         lckl_n = 0xe1;
 606                         mlc = init->mlc[1];
 607                         lckl_p = init->lckl_p[1];
 608                         break;
 609                 case 24:
 610                         tcc = 0x5e;
 611                         mxc = 0x5d;
 612                         lckl_n = 0xf1;
 613                         mlc = init->mlc[2];
 614                         lckl_p = init->lckl_p[2];
 615                         break;
 616                 case 32:
 617                         tcc = 0x46;
 618                         mxc = 0x5d;
 619                         lckl_n = 0xf1;
 620                         mlc = init->mlc[2];
 621                         lckl_p = init->lckl_p[2];
 622                         break;
 623         }
 624         mic = 0x08;
 625
 626         par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
 627         par->cmap_regs[TVPIDATA] = 0x00;                eieio();
 628         par->cmap_regs[TVPADDRW] = TVPIRPPD;            eieio();
 629         par->cmap_regs[TVPIDATA] = init->pclk_m;        eieio();
 630         par->cmap_regs[TVPADDRW] = TVPIRPPD;            eieio();
 631         par->cmap_regs[TVPIDATA] = init->pclk_n;        eieio();
 632         par->cmap_regs[TVPADDRW] = TVPIRPPD;            eieio();
 633         par->cmap_regs[TVPIDATA] = init->pclk_p;        eieio();
 634
 635         par->cmap_regs[TVPADDRW] = TVPIRTCC;            eieio();
 636         par->cmap_regs[TVPIDATA] = tcc;                 eieio();
 637         par->cmap_regs[TVPADDRW] = TVPIRMXC;            eieio();
 638         par->cmap_regs[TVPIDATA] = mxc;                 eieio();
 639         par->cmap_regs[TVPADDRW] = TVPIRMIC;            eieio();
 640         par->cmap_regs[TVPIDATA] = mic;                 eieio();
 641
 642         par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
 643         par->cmap_regs[TVPIDATA] = 0x00;                eieio();
 644         par->cmap_regs[TVPADDRW] = TVPIRLPD;            eieio();
 645         par->cmap_regs[TVPIDATA] = lckl_n;              eieio();
 646
 647         par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
 648         par->cmap_regs[TVPIDATA] = 0x15;                eieio();
 649         par->cmap_regs[TVPADDRW] = TVPIRMLC;            eieio();
 650         par->cmap_regs[TVPIDATA] = mlc;                 eieio();
 651
 652         par->cmap_regs[TVPADDRW] = TVPIRPLA;            eieio();
 653         par->cmap_regs[TVPIDATA] = 0x2a;                eieio();
 654         par->cmap_regs[TVPADDRW] = TVPIRLPD;            eieio();
 655         par->cmap_regs[TVPIDATA] = lckl_p;              eieio();
 656 }
 657
 658 static void
 659 set_imstt_regvals (struct fb_info *info, u_int bpp)
 660 {
 661         struct imstt_par *par = info->par;
 662         struct imstt_regvals *init = &par->init;
 663         __u32 ctl, pitch, byteswap, scr;
 664
 665         if (par->ramdac == IBM)
 666                 set_imstt_regvals_ibm(par, bpp);
 667         else
 668                 set_imstt_regvals_tvp(par, bpp);
 669
 670   /*
 671    * From what I (jsk) can gather poking around with MacsBug,
 672    * bits 8 and 9 in the SCR register control endianness
 673    * correction (byte swapping).  These bits must be set according
 674    * to the color depth as follows:
 675    *     Color depth    Bit 9   Bit 8
 676    *     ==========     =====   =====
 677    *        8bpp          0       0
 678    *       16bpp          0       1
 679    *       32bpp          1       1
 680    */
 681         switch (bpp) {
 682                 default:
 683                 case 8:
 684                         ctl = 0x17b1;
 685                         pitch = init->pitch >> 2;
 686                         byteswap = 0x000;
 687                         break;
 688                 case 16:
 689                         ctl = 0x17b3;
 690                         pitch = init->pitch >> 1;
 691                         byteswap = 0x100;
 692                         break;
 693                 case 24:
 694                         ctl = 0x17b9;
 695                         pitch = init->pitch - (init->pitch >> 2);
 696                         byteswap = 0x200;
 697                         break;
 698                 case 32:
 699                         ctl = 0x17b5;
 700                         pitch = init->pitch;
 701                         byteswap = 0x300;
 702                         break;
 703         }
 704         if (par->ramdac == TVP)
 705                 ctl -= 0x30;
 706
 707         write_reg_le32(par->dc_regs, HES, init->hes);
 708         write_reg_le32(par->dc_regs, HEB, init->heb);
 709         write_reg_le32(par->dc_regs, HSB, init->hsb);
 710         write_reg_le32(par->dc_regs, HT, init->ht);
 711         write_reg_le32(par->dc_regs, VES, init->ves);
 712         write_reg_le32(par->dc_regs, VEB, init->veb);
 713         write_reg_le32(par->dc_regs, VSB, init->vsb);
 714         write_reg_le32(par->dc_regs, VT, init->vt);
 715         write_reg_le32(par->dc_regs, VIL, init->vil);
 716         write_reg_le32(par->dc_regs, HCIV, 1);
 717         write_reg_le32(par->dc_regs, VCIV, 1);
 718         write_reg_le32(par->dc_regs, TCDR, 4);
 719         write_reg_le32(par->dc_regs, RRCIV, 1);
 720         write_reg_le32(par->dc_regs, RRSC, 0x980);
 721         write_reg_le32(par->dc_regs, RRCR, 0x11);
 722
 723         if (par->ramdac == IBM) {
 724                 write_reg_le32(par->dc_regs, HRIR, 0x0100);
 725                 write_reg_le32(par->dc_regs, CMR, 0x00ff);
 726                 write_reg_le32(par->dc_regs, SRGCTL, 0x0073);
 727         } else {
 728                 write_reg_le32(par->dc_regs, HRIR, 0x0200);
 729                 write_reg_le32(par->dc_regs, CMR, 0x01ff);
 730                 write_reg_le32(par->dc_regs, SRGCTL, 0x0003);
 731         }
 732
 733         switch (info->fix.smem_len) {
 734                 case 0x200000:
 735                         scr = 0x059d | byteswap;
 736                         break;
 737                 /* case 0x400000:
 738                    case 0x800000: */
 739                 default:
 740                         pitch >>= 1;
 741                         scr = 0x150dd | byteswap;
 742                         break;
 743         }
 744
 745         write_reg_le32(par->dc_regs, SCR, scr);
 746         write_reg_le32(par->dc_regs, SPR, pitch);
 747         write_reg_le32(par->dc_regs, STGCTL, ctl);
 748 }
 749
 750 static inline void
 751 set_offset (struct fb_var_screeninfo *var, struct fb_info *info)
 752 {
 753         struct imstt_par *par = info->par;
 754         __u32 off = var->yoffset * (info->fix.line_length >> 3)
 755                     + ((var->xoffset * (var->bits_per_pixel >> 3)) >> 3);
 756         write_reg_le32(par->dc_regs, SSR, off);
 757 }
 758
 759 static inline void
 760 set_555 (struct imstt_par *par)
 761 {
 762         if (par->ramdac == IBM) {
 763                 par->cmap_regs[PIDXHI] = 0;             eieio();
 764                 par->cmap_regs[PIDXLO] = BPP16;         eieio();
 765                 par->cmap_regs[PIDXDATA] = 0x01;        eieio();
 766         } else {
 767                 par->cmap_regs[TVPADDRW] = TVPIRTCC;    eieio();
 768                 par->cmap_regs[TVPIDATA] = 0x44;        eieio();
 769         }
 770 }
 771
 772 static inline void
 773 set_565 (struct imstt_par *par)
 774 {
 775         if (par->ramdac == IBM) {
 776                 par->cmap_regs[PIDXHI] = 0;             eieio();
 777                 par->cmap_regs[PIDXLO] = BPP16;         eieio();
 778                 par->cmap_regs[PIDXDATA] = 0x03;        eieio();
 779         } else {
 780                 par->cmap_regs[TVPADDRW] = TVPIRTCC;    eieio();
 781                 par->cmap_regs[TVPIDATA] = 0x45;        eieio();
 782         }
 783 }
 784
 785 static int
 786 imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 787 {
 788         if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
 789             && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
 790             || var->xres_virtual < var->xres || var->yres_virtual < var->yres
 791             || var->nonstd
 792             || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 793                 return -EINVAL;
 794
 795         if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len
 796             || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len)
 797                 return -EINVAL;
 798
 799         switch (var->bits_per_pixel) {
 800                 case 8:
 801                         var->red.offset = 0;
 802                         var->red.length = 8;
 803                         var->green.offset = 0;
 804                         var->green.length = 8;
 805                         var->blue.offset = 0;
 806                         var->blue.length = 8;
 807                         var->transp.offset = 0;
 808                         var->transp.length = 0;
 809                         break;
 810                 case 16:        /* RGB 555 or 565 */
 811                         if (var->green.length != 6)
 812                                 var->red.offset = 10;
 813                         var->red.length = 5;
 814                         var->green.offset = 5;
 815                         if (var->green.length != 6)
 816                                 var->green.length = 5;
 817                         var->blue.offset = 0;
 818                         var->blue.length = 5;
 819                         var->transp.offset = 0;
 820                         var->transp.length = 0;
 821                         break;
 822                 case 24:        /* RGB 888 */
 823                         var->red.offset = 16;
 824                         var->red.length = 8;
 825                         var->green.offset = 8;
 826                         var->green.length = 8;
 827                         var->blue.offset = 0;
 828                         var->blue.length = 8;
 829                         var->transp.offset = 0;
 830                         var->transp.length = 0;
 831                         break;
 832                 case 32:        /* RGBA 8888 */
 833                         var->red.offset = 16;
 834                         var->red.length = 8;
 835                         var->green.offset = 8;
 836                         var->green.length = 8;
 837                         var->blue.offset = 0;
 838                         var->blue.length = 8;
 839                         var->transp.offset = 24;
 840                         var->transp.length = 8;
 841                         break;
 842         }
 843
 844         if (var->yres == var->yres_virtual) {
 845                 __u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2));
 846                 var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual;
 847                 if (var->yres_virtual < var->yres)
 848                         var->yres_virtual = var->yres;
 849         }
 850
 851         var->red.msb_right = 0;
 852         var->green.msb_right = 0;
 853         var->blue.msb_right = 0;
 854         var->transp.msb_right = 0;
 855         var->height = -1;
 856         var->width = -1;
 857         var->vmode = FB_VMODE_NONINTERLACED;
 858         var->left_margin = var->right_margin = 16;
 859         var->upper_margin = var->lower_margin = 16;
 860         var->hsync_len = var->vsync_len = 8;
 861         return 0;
 862 }
 863
 864 static int
 865 imsttfb_set_par(struct fb_info *info)
 866 {
 867         struct imstt_par *par = info->par;
 868
 869         if (!compute_imstt_regvals(par, info->var.xres, info->var.yres))
 870                 return -EINVAL;
 871
 872         if (info->var.green.length == 6)
 873                 set_565(par);
 874         else
 875                 set_555(par);
 876         set_imstt_regvals(info, info->var.bits_per_pixel);
 877         info->var.pixclock = 1000000 / getclkMHz(par);
 878         return 0;
 879 }
 880
 881 static int
 882 imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
 883                    u_int transp, struct fb_info *info)
 884 {
 885         struct imstt_par *par = info->par;
 886         u_int bpp = info->var.bits_per_pixel;
 887
 888         if (regno > 255)
 889                 return 1;
 890
 891         red >>= 8;
 892         green >>= 8;
 893         blue >>= 8;
 894
 895         /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
 896         if (0 && bpp == 16)     /* screws up X */
 897                 par->cmap_regs[PADDRW] = regno << 3;
 898         else
 899                 par->cmap_regs[PADDRW] = regno;
 900         eieio();
 901
 902         par->cmap_regs[PDATA] = red;    eieio();
 903         par->cmap_regs[PDATA] = green;  eieio();
 904         par->cmap_regs[PDATA] = blue;   eieio();
 905
 906         if (regno < 16)
 907                 switch (bpp) {
 908                         case 16:
 909                                 par->palette[regno] =
 910                                         (regno << (info->var.green.length ==
 911                                         5 ? 10 : 11)) | (regno << 5) | regno;
 912                                 break;
 913                         case 24:
 914                                 par->palette[regno] =
 915                                         (regno << 16) | (regno << 8) | regno;
 916                                 break;
 917                         case 32: {
 918                                 int i = (regno << 8) | regno;
 919                                 par->palette[regno] = (i << 16) |i;
 920                                 break;
 921                         }
 922                 }
 923         return 0;
 924 }
 925
 926 static int
 927 imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 928 {
 929         if (var->xoffset + info->var.xres > info->var.xres_virtual
 930             || var->yoffset + info->var.yres > info->var.yres_virtual)
 931                 return -EINVAL;
 932
 933         info->var.xoffset = var->xoffset;
 934         info->var.yoffset = var->yoffset;
 935         set_offset(var, info);
 936         return 0;
 937 }
 938
 939 static int
 940 imsttfb_blank(int blank, struct fb_info *info)
 941 {
 942         struct imstt_par *par = info->par;
 943         __u32 ctrl;
 944
 945         ctrl = read_reg_le32(par->dc_regs, STGCTL);
 946         if (blank > 0) {
 947                 switch (blank) {
 948                 case FB_BLANK_NORMAL:
 949                 case FB_BLANK_POWERDOWN:
 950                         ctrl &= ~0x00000380;
 951                         if (par->ramdac == IBM) {
 952                                 par->cmap_regs[PIDXHI] = 0;             eieio();
 953                                 par->cmap_regs[PIDXLO] = MISCTL2;       eieio();
 954                                 par->cmap_regs[PIDXDATA] = 0x55;        eieio();
 955                                 par->cmap_regs[PIDXLO] = MISCTL1;       eieio();
 956                                 par->cmap_regs[PIDXDATA] = 0x11;        eieio();
 957                                 par->cmap_regs[PIDXLO] = SYNCCTL;       eieio();
 958                                 par->cmap_regs[PIDXDATA] = 0x0f;        eieio();
 959                                 par->cmap_regs[PIDXLO] = PWRMNGMT;      eieio();
 960                                 par->cmap_regs[PIDXDATA] = 0x1f;        eieio();
 961                                 par->cmap_regs[PIDXLO] = CLKCTL;        eieio();
 962                                 par->cmap_regs[PIDXDATA] = 0xc0;
 963                         }
 964                         break;
 965                 case FB_BLANK_VSYNC_SUSPEND:
 966                         ctrl &= ~0x00000020;
 967                         break;
 968                 case FB_BLANK_HSYNC_SUSPEND:
 969                         ctrl &= ~0x00000010;
 970                         break;
 971                 }
 972         } else {
 973                 if (par->ramdac == IBM) {
 974                         ctrl |= 0x000017b0;
 975                         par->cmap_regs[PIDXHI] = 0;             eieio();
 976                         par->cmap_regs[PIDXLO] = CLKCTL;        eieio();
 977                         par->cmap_regs[PIDXDATA] = 0x01;        eieio();
 978                         par->cmap_regs[PIDXLO] = PWRMNGMT;      eieio();
 979                         par->cmap_regs[PIDXDATA] = 0x00;        eieio();
 980                         par->cmap_regs[PIDXLO] = SYNCCTL;       eieio();
 981                         par->cmap_regs[PIDXDATA] = 0x00;        eieio();
 982                         par->cmap_regs[PIDXLO] = MISCTL1;       eieio();
 983                         par->cmap_regs[PIDXDATA] = 0x01;        eieio();
 984                         par->cmap_regs[PIDXLO] = MISCTL2;       eieio();
 985                         par->cmap_regs[PIDXDATA] = 0x45;        eieio();
 986                 } else
 987                         ctrl |= 0x00001780;
 988         }
 989         write_reg_le32(par->dc_regs, STGCTL, ctrl);
 990         return 0;
 991 }
 992
 993 static void
 994 imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 995 {
 996         struct imstt_par *par = info->par;
 997         __u32 Bpp, line_pitch, bgc, dx, dy, width, height;
 998
 999         bgc = rect->color;
1000         bgc |= (bgc << 8);
1001         bgc |= (bgc << 16);
1002
1003         Bpp = info->var.bits_per_pixel >> 3,
1004         line_pitch = info->fix.line_length;
1005
1006         dy = rect->dy * line_pitch;
1007         dx = rect->dx * Bpp;
1008         height = rect->height;
1009         height--;
1010         width = rect->width * Bpp;
1011         width--;
1012
1013         if (rect->rop == ROP_COPY) {
1014                 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1015                 write_reg_le32(par->dc_regs, DSA, dy + dx);
1016                 write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1017                 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1018                 write_reg_le32(par->dc_regs, BI, 0xffffffff);
1019                 write_reg_le32(par->dc_regs, MBC, 0xffffffff);
1020                 write_reg_le32(par->dc_regs, CLR, bgc);
1021                 write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */
1022                 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1023                 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1024         } else {
1025                 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1026                 write_reg_le32(par->dc_regs, DSA, dy + dx);
1027                 write_reg_le32(par->dc_regs, S1SA, dy + dx);
1028                 write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1029                 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1030                 write_reg_le32(par->dc_regs, SP, line_pitch);
1031                 write_reg_le32(par->dc_regs, BLTCTL, 0x40005);
1032                 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1033                 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1034         }
1035 }
1036
1037 static void
1038 imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1039 {
1040         struct imstt_par *par = info->par;
1041         __u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl;
1042         __u32 cnt, bltctl, sx, sy, dx, dy, height, width;
1043
1044         Bpp = info->var.bits_per_pixel >> 3,
1045
1046         sx = area->sx * Bpp;
1047         sy = area->sy;
1048         dx = area->dx * Bpp;
1049         dy = area->dy;
1050         height = area->height;
1051         height--;
1052         width = area->width * Bpp;
1053         width--;
1054
1055         line_pitch = info->fix.line_length;
1056         bltctl = 0x05;
1057         sp = line_pitch << 16;
1058         cnt = height << 16;
1059
1060         if (sy < dy) {
1061                 sy += height;
1062                 dy += height;
1063                 sp |= -(line_pitch) & 0xffff;
1064                 dp_octl = -(line_pitch) & 0xffff;
1065         } else {
1066                 sp |= line_pitch;
1067                 dp_octl = line_pitch;
1068         }
1069         if (sx < dx) {
1070                 sx += width;
1071                 dx += width;
1072                 bltctl |= 0x80;
1073                 cnt |= -(width) & 0xffff;
1074         } else {
1075                 cnt |= width;
1076         }
1077         fb_offset_old = sy * line_pitch + sx;
1078         fb_offset_new = dy * line_pitch + dx;
1079
1080         while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1081         write_reg_le32(par->dc_regs, S1SA, fb_offset_old);
1082         write_reg_le32(par->dc_regs, SP, sp);
1083         write_reg_le32(par->dc_regs, DSA, fb_offset_new);
1084         write_reg_le32(par->dc_regs, CNT, cnt);
1085         write_reg_le32(par->dc_regs, DP_OCTL, dp_octl);
1086         write_reg_le32(par->dc_regs, BLTCTL, bltctl);
1087         while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1088         while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1089 }
1090
1091 #if 0
1092 static int
1093 imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc)
1094 {
1095         u_int x, y;
1096
1097         if (width > 32 || height > 32)
1098                 return -EINVAL;
1099
1100         if (par->ramdac == IBM) {
1101                 par->cmap_regs[PIDXHI] = 1;     eieio();
1102                 for (x = 0; x < 0x100; x++) {
1103                         par->cmap_regs[PIDXLO] = x;             eieio();
1104                         par->cmap_regs[PIDXDATA] = 0x00;        eieio();
1105                 }
1106                 par->cmap_regs[PIDXHI] = 1;     eieio();
1107                 for (y = 0; y < height; y++)
1108                         for (x = 0; x < width >> 2; x++) {
1109                                 par->cmap_regs[PIDXLO] = x + y * 8;     eieio();
1110                                 par->cmap_regs[PIDXDATA] = 0xff;        eieio();
1111                         }
1112                 par->cmap_regs[PIDXHI] = 0;             eieio();
1113                 par->cmap_regs[PIDXLO] = CURS1R;        eieio();
1114                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1115                 par->cmap_regs[PIDXLO] = CURS1G;        eieio();
1116                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1117                 par->cmap_regs[PIDXLO] = CURS1B;        eieio();
1118                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1119                 par->cmap_regs[PIDXLO] = CURS2R;        eieio();
1120                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1121                 par->cmap_regs[PIDXLO] = CURS2G;        eieio();
1122                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1123                 par->cmap_regs[PIDXLO] = CURS2B;        eieio();
1124                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1125                 par->cmap_regs[PIDXLO] = CURS3R;        eieio();
1126                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1127                 par->cmap_regs[PIDXLO] = CURS3G;        eieio();
1128                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1129                 par->cmap_regs[PIDXLO] = CURS3B;        eieio();
1130                 par->cmap_regs[PIDXDATA] = fgc;         eieio();
1131         } else {
1132                 par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1133                 par->cmap_regs[TVPIDATA] &= 0x03;       eieio();
1134                 par->cmap_regs[TVPADDRW] = 0;           eieio();
1135                 for (x = 0; x < 0x200; x++) {
1136                         par->cmap_regs[TVPCRDAT] = 0x00;        eieio();
1137                 }
1138                 for (x = 0; x < 0x200; x++) {
1139                         par->cmap_regs[TVPCRDAT] = 0xff;        eieio();
1140                 }
1141                 par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1142                 par->cmap_regs[TVPIDATA] &= 0x03;       eieio();
1143                 for (y = 0; y < height; y++)
1144                         for (x = 0; x < width >> 3; x++) {
1145                                 par->cmap_regs[TVPADDRW] = x + y * 8;   eieio();
1146                                 par->cmap_regs[TVPCRDAT] = 0xff;                eieio();
1147                         }
1148                 par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1149                 par->cmap_regs[TVPIDATA] |= 0x08;       eieio();
1150                 for (y = 0; y < height; y++)
1151                         for (x = 0; x < width >> 3; x++) {
1152                                 par->cmap_regs[TVPADDRW] = x + y * 8;   eieio();
1153                                 par->cmap_regs[TVPCRDAT] = 0xff;                eieio();
1154                         }
1155                 par->cmap_regs[TVPCADRW] = 0x00;        eieio();
1156                 for (x = 0; x < 12; x++)
1157                         par->cmap_regs[TVPCDATA] = fgc; eieio();
1158         }
1159         return 1;
1160 }
1161
1162 static void
1163 imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on)
1164 {
1165         if (par->ramdac == IBM) {
1166                 par->cmap_regs[PIDXHI] = 0;     eieio();
1167                 if (!on) {
1168                         par->cmap_regs[PIDXLO] = CURSCTL;       eieio();
1169                         par->cmap_regs[PIDXDATA] = 0x00;        eieio();
1170                 } else {
1171                         par->cmap_regs[PIDXLO] = CURSXHI;       eieio();
1172                         par->cmap_regs[PIDXDATA] = d->dx >> 8;  eieio();
1173                         par->cmap_regs[PIDXLO] = CURSXLO;       eieio();
1174                         par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio();
1175                         par->cmap_regs[PIDXLO] = CURSYHI;       eieio();
1176                         par->cmap_regs[PIDXDATA] = d->dy >> 8;  eieio();
1177                         par->cmap_regs[PIDXLO] = CURSYLO;       eieio();
1178                         par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio();
1179                         par->cmap_regs[PIDXLO] = CURSCTL;       eieio();
1180                         par->cmap_regs[PIDXDATA] = 0x02;        eieio();
1181                 }
1182         } else {
1183                 if (!on) {
1184                         par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1185                         par->cmap_regs[TVPIDATA] = 0x00;        eieio();
1186                 } else {
1187                         __u16 x = d->dx + 0x40, y = d->dy + 0x40;
1188
1189                         par->cmap_regs[TVPCXPOH] = x >> 8;      eieio();
1190                         par->cmap_regs[TVPCXPOL] = x & 0xff;    eieio();
1191                         par->cmap_regs[TVPCYPOH] = y >> 8;      eieio();
1192                         par->cmap_regs[TVPCYPOL] = y & 0xff;    eieio();
1193                         par->cmap_regs[TVPADDRW] = TVPIRICC;    eieio();
1194                         par->cmap_regs[TVPIDATA] = 0x02;        eieio();
1195                 }
1196         }
1197 }
1198
1199 static int
1200 imsttfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1201 {
1202         struct imstt_par *par = info->par;
1203         u32 flags = cursor->set, fg, bg, xx, yy;
1204
1205         if (cursor->dest == NULL && cursor->rop == ROP_XOR)
1206                 return 1;
1207
1208         imstt_set_cursor(info, cursor, 0);
1209
1210         if (flags & FB_CUR_SETPOS) {
1211                 xx = cursor->image.dx - info->var.xoffset;
1212                 yy = cursor->image.dy - info->var.yoffset;
1213         }
1214
1215         if (flags & FB_CUR_SETSIZE) {
1216         }
1217
1218         if (flags & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
1219                 int fg_idx = cursor->image.fg_color;
1220                 int width = (cursor->image.width+7)/8;
1221                 u8 *dat = (u8 *) cursor->image.data;
1222                 u8 *dst = (u8 *) cursor->dest;
1223                 u8 *msk = (u8 *) cursor->mask;
1224
1225                 switch (cursor->rop) {
1226                 case ROP_XOR:
1227                         for (i = 0; i < cursor->image.height; i++) {
1228                                 for (j = 0; j < width; j++) {
1229                                         d_idx = i * MAX_CURS/8  + j;
1230                                         data[d_idx] =  byte_rev[dat[s_idx] ^
1231                                                                 dst[s_idx]];
1232                                         mask[d_idx] = byte_rev[msk[s_idx]];
1233                                         s_idx++;
1234                                 }
1235                         }
1236                         break;
1237                 case ROP_COPY:
1238                 default:
1239                         for (i = 0; i < cursor->image.height; i++) {
1240                                 for (j = 0; j < width; j++) {
1241                                         d_idx = i * MAX_CURS/8 + j;
1242                                         data[d_idx] = byte_rev[dat[s_idx]];
1243                                         mask[d_idx] = byte_rev[msk[s_idx]];
1244                                         s_idx++;
1245                                 }
1246                         }
1247                         break;
1248                 }
1249
1250                 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1251                      ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1252                      ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1253
1254                 imsttfb_load_cursor_image(par, xx, yy, fgc);
1255         }
1256         if (cursor->enable)
1257                 imstt_set_cursor(info, cursor, 1);
1258         return 0;
1259 }
1260 #endif
1261
1262 #define FBIMSTT_SETREG          0x545401
1263 #define FBIMSTT_GETREG          0x545402
1264 #define FBIMSTT_SETCMAPREG      0x545403
1265 #define FBIMSTT_GETCMAPREG      0x545404
1266 #define FBIMSTT_SETIDXREG       0x545405
1267 #define FBIMSTT_GETIDXREG       0x545406
1268
1269 static int
1270 imsttfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1271 {
1272         struct imstt_par *par = info->par;
1273         void __user *argp = (void __user *)arg;
1274         __u32 reg[2];
1275         __u8 idx[2];
1276
1277         switch (cmd) {
1278                 case FBIMSTT_SETREG:
1279                         if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1280                                 return -EFAULT;
1281                         write_reg_le32(par->dc_regs, reg[0], reg[1]);
1282                         return 0;
1283                 case FBIMSTT_GETREG:
1284                         if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1285                                 return -EFAULT;
1286                         reg[1] = read_reg_le32(par->dc_regs, reg[0]);
1287                         if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
1288                                 return -EFAULT;
1289                         return 0;
1290                 case FBIMSTT_SETCMAPREG:
1291                         if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1292                                 return -EFAULT;
1293                         write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]);
1294                         return 0;
1295                 case FBIMSTT_GETCMAPREG:
1296                         if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1297                                 return -EFAULT;
1298                         reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]);
1299                         if (copy_to_user((void __user *)(arg + 4), &reg[1], 4))
1300                                 return -EFAULT;
1301                         return 0;
1302                 case FBIMSTT_SETIDXREG:
1303                         if (copy_from_user(idx, argp, 2))
1304                                 return -EFAULT;
1305                         par->cmap_regs[PIDXHI] = 0;             eieio();
1306                         par->cmap_regs[PIDXLO] = idx[0];        eieio();
1307                         par->cmap_regs[PIDXDATA] = idx[1];      eieio();
1308                         return 0;
1309                 case FBIMSTT_GETIDXREG:
1310                         if (copy_from_user(idx, argp, 1))
1311                                 return -EFAULT;
1312                         par->cmap_regs[PIDXHI] = 0;             eieio();
1313                         par->cmap_regs[PIDXLO] = idx[0];        eieio();
1314                         idx[1] = par->cmap_regs[PIDXDATA];
1315                         if (copy_to_user((void __user *)(arg + 1), &idx[1], 1))
1316                                 return -EFAULT;
1317                         return 0;
1318                 default:
1319                         return -ENOIOCTLCMD;
1320         }
1321 }
1322
1323 static struct pci_device_id imsttfb_pci_tbl[] = {
1324         { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128,
1325           PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM },
1326         { PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D,
1327           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP },
1328         { 0, }
1329 };
1330
1331 MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl);
1332
1333 static struct pci_driver imsttfb_pci_driver = {
1334         .name =         "imsttfb",
1335         .id_table =     imsttfb_pci_tbl,
1336         .probe =        imsttfb_probe,
1337         .remove =       __devexit_p(imsttfb_remove),
1338 };
1339
1340 static struct fb_ops imsttfb_ops = {
1341         .owner          = THIS_MODULE,
1342         .fb_check_var   = imsttfb_check_var,
1343         .fb_set_par     = imsttfb_set_par,
1344         .fb_setcolreg   = imsttfb_setcolreg,
1345         .fb_pan_display = imsttfb_pan_display,
1346         .fb_blank       = imsttfb_blank,
1347         .fb_fillrect    = imsttfb_fillrect,
1348         .fb_copyarea    = imsttfb_copyarea,
1349         .fb_imageblit   = cfb_imageblit,
1350         .fb_ioctl       = imsttfb_ioctl,
1351 };
1352
1353 static void __devinit
1354 init_imstt(struct fb_info *info)
1355 {
1356         struct imstt_par *par = info->par;
1357         __u32 i, tmp, *ip, *end;
1358
1359         tmp = read_reg_le32(par->dc_regs, PRC);
1360         if (par->ramdac == IBM)
1361                 info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000;
1362         else
1363                 info->fix.smem_len = 0x800000;
1364
1365         ip = (__u32 *)info->screen_base;
1366         end = (__u32 *)(info->screen_base + info->fix.smem_len);
1367         while (ip < end)
1368                 *ip++ = 0;
1369
1370         /* initialize the card */
1371         tmp = read_reg_le32(par->dc_regs, STGCTL);
1372         write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
1373         write_reg_le32(par->dc_regs, SSR, 0);
1374
1375         /* set default values for DAC registers */
1376         if (par->ramdac == IBM) {
1377                 par->cmap_regs[PPMASK] = 0xff;  eieio();
1378                 par->cmap_regs[PIDXHI] = 0;     eieio();
1379                 for (i = 0; i < sizeof(ibm_initregs) / sizeof(*ibm_initregs); i++) {
1380                         par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;  eieio();
1381                         par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;       eieio();
1382                 }
1383         } else {
1384                 for (i = 0; i < sizeof(tvp_initregs) / sizeof(*tvp_initregs); i++) {
1385                         par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;        eieio();
1386                         par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;       eieio();
1387                 }
1388         }
1389
1390 #if USE_NV_MODES && defined(CONFIG_PPC)
1391         {
1392                 int vmode = init_vmode, cmode = init_cmode;
1393
1394                 if (vmode == -1) {
1395                         vmode = nvram_read_byte(NV_VMODE);
1396                         if (vmode <= 0 || vmode > VMODE_MAX)
1397                                 vmode = VMODE_640_480_67;
1398                 }
1399                 if (cmode == -1) {
1400                         cmode = nvram_read_byte(NV_CMODE);
1401                         if (cmode < CMODE_8 || cmode > CMODE_32)
1402                                 cmode = CMODE_8;
1403                 }
1404                 if (mac_vmode_to_var(vmode, cmode, &info->var)) {
1405                         info->var.xres = info->var.xres_virtual = INIT_XRES;
1406                         info->var.yres = info->var.yres_virtual = INIT_YRES;
1407                         info->var.bits_per_pixel = INIT_BPP;
1408                 }
1409         }
1410 #else
1411         info->var.xres = info->var.xres_virtual = INIT_XRES;
1412         info->var.yres = info->var.yres_virtual = INIT_YRES;
1413         info->var.bits_per_pixel = INIT_BPP;
1414 #endif
1415
1416         if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len
1417             || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) {
1418                 printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
1419                 framebuffer_release(info);
1420                 return;
1421         }
1422
1423         sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP");
1424         info->fix.mmio_len = 0x1000;
1425         info->fix.accel = FB_ACCEL_IMS_TWINTURBO;
1426         info->fix.type = FB_TYPE_PACKED_PIXELS;
1427         info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1428                                                         : FB_VISUAL_DIRECTCOLOR;
1429         info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3);
1430         info->fix.xpanstep = 8;
1431         info->fix.ypanstep = 1;
1432         info->fix.ywrapstep = 0;
1433
1434         info->var.accel_flags = FB_ACCELF_TEXT;
1435
1436 //      if (par->ramdac == IBM)
1437 //              imstt_cursor_init(info);
1438         if (info->var.green.length == 6)
1439                 set_565(par);
1440         else
1441                 set_555(par);
1442         set_imstt_regvals(info, info->var.bits_per_pixel);
1443
1444         info->var.pixclock = 1000000 / getclkMHz(par);
1445
1446         info->fbops = &imsttfb_ops;
1447         info->flags = FBINFO_DEFAULT |
1448                       FBINFO_HWACCEL_COPYAREA |
1449                       FBINFO_HWACCEL_FILLRECT |
1450                       FBINFO_HWACCEL_YPAN;
1451
1452         fb_alloc_cmap(&info->cmap, 0, 0);
1453
1454         if (register_framebuffer(info) < 0) {
1455                 framebuffer_release(info);
1456                 return;
1457         }
1458
1459         tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
1460         printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
1461                 info->node, info->fix.id, info->fix.smem_len >> 20, tmp);
1462 }
1463
1464 static int __devinit
1465 imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1466 {
1467         unsigned long addr, size;
1468         struct imstt_par *par;
1469         struct fb_info *info;
1470 #ifdef CONFIG_PPC_OF
1471         struct device_node *dp;
1472
1473         dp = pci_device_to_OF_node(pdev);
1474         if(dp)
1475                 printk(KERN_INFO "%s: OF name %s\n",__FUNCTION__, dp->name);
1476         else
1477                 printk(KERN_ERR "imsttfb: no OF node for pci device\n");
1478 #endif /* CONFIG_PPC_OF */
1479
1480         info = framebuffer_alloc(sizeof(struct imstt_par), &pdev->dev);
1481
1482         if (!info) {
1483                 printk(KERN_ERR "imsttfb: Can't allocate memory\n");
1484                 return -ENOMEM;
1485         }
1486
1487         par = info->par;
1488
1489         addr = pci_resource_start (pdev, 0);
1490         size = pci_resource_len (pdev, 0);
1491
1492         if (!request_mem_region(addr, size, "imsttfb")) {
1493                 printk(KERN_ERR "imsttfb: Can't reserve memory region\n");
1494                 framebuffer_release(info);
1495                 return -ENODEV;
1496         }
1497
1498         switch (pdev->device) {
1499                 case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */
1500                         par->ramdac = IBM;
1501 #ifdef CONFIG_PPC_OF
1502                         if (dp && ((strcmp(dp->name, "IMS,tt128mb8") == 0) ||
1503                                    (strcmp(dp->name, "IMS,tt128mb8A") == 0)))
1504                                 par->ramdac = TVP;
1505 #endif /* CONFIG_PPC_OF */
1506                         break;
1507                 case PCI_DEVICE_ID_IMS_TT3D:  /* IMS,tt3d */
1508                         par->ramdac = TVP;
1509                         break;
1510                 default:
1511                         printk(KERN_INFO "imsttfb: Device 0x%x unknown, "
1512                                          "contact maintainer.\n", pdev->device);
1513                         return -ENODEV;
1514         }
1515
1516         info->fix.smem_start = addr;
1517         info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ?
1518                                             0x400000 : 0x800000);
1519         info->fix.mmio_start = addr + 0x800000;
1520         par->dc_regs = ioremap(addr + 0x800000, 0x1000);
1521         par->cmap_regs_phys = addr + 0x840000;
1522         par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1523         info->pseudo_palette = par->palette;
1524         init_imstt(info);
1525
1526         pci_set_drvdata(pdev, info);
1527         return 0;
1528 }
1529
1530 static void __devexit
1531 imsttfb_remove(struct pci_dev *pdev)
1532 {
1533         struct fb_info *info = pci_get_drvdata(pdev);
1534         struct imstt_par *par = info->par;
1535         int size = pci_resource_len(pdev, 0);
1536
1537         unregister_framebuffer(info);
1538         iounmap(par->cmap_regs);
1539         iounmap(par->dc_regs);
1540         iounmap(info->screen_base);
1541         release_mem_region(info->fix.smem_start, size);
1542         framebuffer_release(info);
1543 }
1544
1545 #ifndef MODULE
1546 static int __init
1547 imsttfb_setup(char *options)
1548 {
1549         char *this_opt;
1550
1551         if (!options || !*options)
1552                 return 0;
1553
1554         while ((this_opt = strsep(&options, ",")) != NULL) {
1555                 if (!strncmp(this_opt, "font:", 5)) {
1556                         char *p;
1557                         int i;
1558
1559                         p = this_opt + 5;
1560                         for (i = 0; i < sizeof(fontname) - 1; i++)
1561                                 if (!*p || *p == ' ' || *p == ',')
1562                                         break;
1563                         memcpy(fontname, this_opt + 5, i);
1564                         fontname[i] = 0;
1565                 } else if (!strncmp(this_opt, "inverse", 7)) {
1566                         inverse = 1;
1567                         fb_invert_cmaps();
1568                 }
1569 #if defined(CONFIG_PPC)
1570                 else if (!strncmp(this_opt, "vmode:", 6)) {
1571                         int vmode = simple_strtoul(this_opt+6, NULL, 0);
1572                         if (vmode > 0 && vmode <= VMODE_MAX)
1573                                 init_vmode = vmode;
1574                 } else if (!strncmp(this_opt, "cmode:", 6)) {
1575                         int cmode = simple_strtoul(this_opt+6, NULL, 0);
1576                         switch (cmode) {
1577                                 case CMODE_8:
1578                                 case 8:
1579                                         init_cmode = CMODE_8;
1580                                         break;
1581                                 case CMODE_16:
1582                                 case 15:
1583                                 case 16:
1584                                         init_cmode = CMODE_16;
1585                                         break;
1586                                 case CMODE_32:
1587                                 case 24:
1588                                 case 32:
1589                                         init_cmode = CMODE_32;
1590                                         break;
1591                         }
1592                 }
1593 #endif
1594         }
1595         return 0;
1596 }
1597
1598 #endif /* MODULE */
1599
1600 static int __init imsttfb_init(void)
1601 {
1602 #ifndef MODULE
1603         char *option = NULL;
1604
1605         if (fb_get_options("imsttfb", &option))
1606                 return -ENODEV;
1607
1608         imsttfb_setup(option);
1609 #endif
1610         return pci_register_driver(&imsttfb_pci_driver);
1611 }
1612
1613 static void __exit imsttfb_exit(void)
1614 {
1615         pci_unregister_driver(&imsttfb_pci_driver);
1616 }
1617
1618 MODULE_LICENSE("GPL");
1619
1620 module_init(imsttfb_init);
1621 module_exit(imsttfb_exit);
1622