[MTD NAND] s3c24x0 board: Fix clock handling, ensure proper initialisation.
[linux-2.6] / drivers / mtd / nand / s3c2410.c
1 /* linux/drivers/mtd/nand/s3c2410.c
2  *
3  * Copyright (c) 2004,2005 Simtec Electronics
4  *      http://www.simtec.co.uk/products/SWLINUX/
5  *      Ben Dooks <ben@simtec.co.uk>
6  *
7  * Samsung S3C2410/S3C240 NAND driver
8  *
9  * Changelog:
10  *      21-Sep-2004  BJD  Initial version
11  *      23-Sep-2004  BJD  Mulitple device support
12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
14  *      18-Feb-2005  BJD  Fix sparse errors
15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
16  *      02-May-2005  BJD  Fixed s3c2440 support
17  *      02-May-2005  BJD  Reduced hwcontrol decode
18  *      20-Jun-2005  BJD  Updated s3c2440 support, fixed timing bug
19  *      08-Jul-2005  BJD  Fix OOPS when no platform data supplied
20  *      20-Oct-2005  BJD  Fix timing calculation bug
21  *      14-Jan-2006  BJD  Allow clock to be stopped when idle
22  *
23  * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
24  *
25  * This program is free software; you can redistribute it and/or modify
26  * it under the terms of the GNU General Public License as published by
27  * the Free Software Foundation; either version 2 of the License, or
28  * (at your option) any later version.
29  *
30  * This program is distributed in the hope that it will be useful,
31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
33  * GNU General Public License for more details.
34  *
35  * You should have received a copy of the GNU General Public License
36  * along with this program; if not, write to the Free Software
37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
38 */
39
40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
41 #define DEBUG
42 #endif
43
44 #include <linux/module.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/string.h>
49 #include <linux/ioport.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
52 #include <linux/err.h>
53 #include <linux/slab.h>
54 #include <linux/clk.h>
55
56 #include <linux/mtd/mtd.h>
57 #include <linux/mtd/nand.h>
58 #include <linux/mtd/nand_ecc.h>
59 #include <linux/mtd/partitions.h>
60
61 #include <asm/io.h>
62
63 #include <asm/arch/regs-nand.h>
64 #include <asm/arch/nand.h>
65
66 #define PFX "s3c2410-nand: "
67
68 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
69 static int hardware_ecc = 1;
70 #else
71 static int hardware_ecc = 0;
72 #endif
73
74 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
75 static int clock_stop = 1;
76 #else
77 static const int clock_stop = 0;
78 #endif
79
80
81 /* new oob placement block for use with hardware ecc generation
82  */
83
84 static struct nand_ecclayout nand_hw_eccoob = {
85         .eccbytes = 3,
86         .eccpos = {0, 1, 2},
87         .oobfree = {{8, 8}}
88 };
89
90 /* controller and mtd information */
91
92 struct s3c2410_nand_info;
93
94 struct s3c2410_nand_mtd {
95         struct mtd_info                 mtd;
96         struct nand_chip                chip;
97         struct s3c2410_nand_set         *set;
98         struct s3c2410_nand_info        *info;
99         int                             scan_res;
100 };
101
102 /* overview of the s3c2410 nand state */
103
104 struct s3c2410_nand_info {
105         /* mtd info */
106         struct nand_hw_control          controller;
107         struct s3c2410_nand_mtd         *mtds;
108         struct s3c2410_platform_nand    *platform;
109
110         /* device info */
111         struct device                   *device;
112         struct resource                 *area;
113         struct clk                      *clk;
114         void __iomem                    *regs;
115         int                             mtd_count;
116
117         unsigned char                   is_s3c2440;
118 };
119
120 /* conversion functions */
121
122 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
123 {
124         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
125 }
126
127 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
128 {
129         return s3c2410_nand_mtd_toours(mtd)->info;
130 }
131
132 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
133 {
134         return platform_get_drvdata(dev);
135 }
136
137 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
138 {
139         return dev->dev.platform_data;
140 }
141
142 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
143 {
144         return clock_stop;
145 }
146
147 /* timing calculations */
148
149 #define NS_IN_KHZ 1000000
150
151 static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
152 {
153         int result;
154
155         result = (wanted * clk) / NS_IN_KHZ;
156         result++;
157
158         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
159
160         if (result > max) {
161                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
162                 return -1;
163         }
164
165         if (result < 1)
166                 result = 1;
167
168         return result;
169 }
170
171 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
172
173 /* controller setup */
174
175 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, struct platform_device *pdev)
176 {
177         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
178         unsigned long clkrate = clk_get_rate(info->clk);
179         int tacls, twrph0, twrph1;
180         unsigned long cfg;
181
182         /* calculate the timing information for the controller */
183
184         clkrate /= 1000;        /* turn clock into kHz for ease of use */
185
186         if (plat != NULL) {
187                 tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4);
188                 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
189                 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
190         } else {
191                 /* default timings */
192                 tacls = 4;
193                 twrph0 = 8;
194                 twrph1 = 8;
195         }
196
197         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
198                 printk(KERN_ERR PFX "cannot get timings suitable for board\n");
199                 return -EINVAL;
200         }
201
202         printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
203                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
204
205         if (!info->is_s3c2440) {
206                 cfg = S3C2410_NFCONF_EN;
207                 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
208                 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
209                 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
210         } else {
211                 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
212                 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
213                 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
214
215                 /* enable the controller and de-assert nFCE */
216
217                 writel(S3C2440_NFCONT_ENABLE | S3C2440_NFCONT_ENABLE,
218                        info->regs + S3C2440_NFCONT);
219         }
220
221         pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
222
223         writel(cfg, info->regs + S3C2410_NFCONF);
224         return 0;
225 }
226
227 /* select chip */
228
229 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
230 {
231         struct s3c2410_nand_info *info;
232         struct s3c2410_nand_mtd *nmtd;
233         struct nand_chip *this = mtd->priv;
234         void __iomem *reg;
235         unsigned long cur;
236         unsigned long bit;
237
238         nmtd = this->priv;
239         info = nmtd->info;
240
241         bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE;
242         reg = info->regs + ((info->is_s3c2440) ? S3C2440_NFCONT : S3C2410_NFCONF);
243
244         if (chip != -1 && allow_clk_stop(info))
245                 clk_enable(info->clk);
246
247         cur = readl(reg);
248
249         if (chip == -1) {
250                 cur |= bit;
251         } else {
252                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
253                         printk(KERN_ERR PFX "chip %d out of range\n", chip);
254                         return;
255                 }
256
257                 if (info->platform != NULL) {
258                         if (info->platform->select_chip != NULL)
259                                 (info->platform->select_chip) (nmtd->set, chip);
260                 }
261
262                 cur &= ~bit;
263         }
264
265         writel(cur, reg);
266
267         if (chip == -1 && allow_clk_stop(info))
268                 clk_disable(info->clk);
269 }
270
271 /* command and control functions
272  *
273  * Note, these all use tglx's method of changing the IO_ADDR_W field
274  * to make the code simpler, and use the nand layer's code to issue the
275  * command and address sequences via the proper IO ports.
276  *
277 */
278
279 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
280                                    unsigned int ctrl)
281 {
282         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
283         struct nand_chip *chip = mtd->priv;
284
285         if (cmd == NAND_CMD_NONE)
286                 return;
287
288         if (ctrl & NAND_CLE)
289                 writeb(cmd, info->regs + S3C2410_NFCMD);
290         else
291                 writeb(cmd, info->regs + S3C2410_NFADDR);
292 }
293
294 /* command and control functions */
295
296 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
297                                    unsigned int ctrl)
298 {
299         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
300         struct nand_chip *chip = mtd->priv;
301
302         if (cmd == NAND_CMD_NONE)
303                 return;
304
305         if (ctrl & NAND_CLE)
306                 writeb(cmd, info->regs + S3C2440_NFCMD);
307         else
308                 writeb(cmd, info->regs + S3C2440_NFADDR);
309 }
310
311 /* s3c2410_nand_devready()
312  *
313  * returns 0 if the nand is busy, 1 if it is ready
314 */
315
316 static int s3c2410_nand_devready(struct mtd_info *mtd)
317 {
318         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
319
320         if (info->is_s3c2440)
321                 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
322         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
323 }
324
325 /* ECC handling functions */
326
327 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
328 {
329         pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", mtd, dat, read_ecc, calc_ecc);
330
331         pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
332                  read_ecc[0], read_ecc[1], read_ecc[2], calc_ecc[0], calc_ecc[1], calc_ecc[2]);
333
334         if (read_ecc[0] == calc_ecc[0] && read_ecc[1] == calc_ecc[1] && read_ecc[2] == calc_ecc[2])
335                 return 0;
336
337         /* we curently have no method for correcting the error */
338
339         return -1;
340 }
341
342 /* ECC functions
343  *
344  * These allow the s3c2410 and s3c2440 to use the controller's ECC
345  * generator block to ECC the data as it passes through]
346 */
347
348 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
349 {
350         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
351         unsigned long ctrl;
352
353         ctrl = readl(info->regs + S3C2410_NFCONF);
354         ctrl |= S3C2410_NFCONF_INITECC;
355         writel(ctrl, info->regs + S3C2410_NFCONF);
356 }
357
358 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
359 {
360         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
361         unsigned long ctrl;
362
363         ctrl = readl(info->regs + S3C2440_NFCONT);
364         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
365 }
366
367 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
368 {
369         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
370
371         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
372         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
373         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
374
375         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
376
377         return 0;
378 }
379
380 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
381 {
382         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
383         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
384
385         ecc_code[0] = ecc;
386         ecc_code[1] = ecc >> 8;
387         ecc_code[2] = ecc >> 16;
388
389         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
390
391         return 0;
392 }
393
394 /* over-ride the standard functions for a little more speed. We can
395  * use read/write block to move the data buffers to/from the controller
396 */
397
398 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
399 {
400         struct nand_chip *this = mtd->priv;
401         readsb(this->IO_ADDR_R, buf, len);
402 }
403
404 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
405 {
406         struct nand_chip *this = mtd->priv;
407         writesb(this->IO_ADDR_W, buf, len);
408 }
409
410 /* device management functions */
411
412 static int s3c2410_nand_remove(struct platform_device *pdev)
413 {
414         struct s3c2410_nand_info *info = to_nand_info(pdev);
415
416         platform_set_drvdata(pdev, NULL);
417
418         if (info == NULL)
419                 return 0;
420
421         /* first thing we need to do is release all our mtds
422          * and their partitions, then go through freeing the
423          * resources used
424          */
425
426         if (info->mtds != NULL) {
427                 struct s3c2410_nand_mtd *ptr = info->mtds;
428                 int mtdno;
429
430                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
431                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
432                         nand_release(&ptr->mtd);
433                 }
434
435                 kfree(info->mtds);
436         }
437
438         /* free the common resources */
439
440         if (info->clk != NULL && !IS_ERR(info->clk)) {
441                 if (!allow_clk_stop(info))
442                         clk_disable(info->clk);
443                 clk_put(info->clk);
444         }
445
446         if (info->regs != NULL) {
447                 iounmap(info->regs);
448                 info->regs = NULL;
449         }
450
451         if (info->area != NULL) {
452                 release_resource(info->area);
453                 kfree(info->area);
454                 info->area = NULL;
455         }
456
457         kfree(info);
458
459         return 0;
460 }
461
462 #ifdef CONFIG_MTD_PARTITIONS
463 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
464                                       struct s3c2410_nand_mtd *mtd,
465                                       struct s3c2410_nand_set *set)
466 {
467         if (set == NULL)
468                 return add_mtd_device(&mtd->mtd);
469
470         if (set->nr_partitions > 0 && set->partitions != NULL) {
471                 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
472         }
473
474         return add_mtd_device(&mtd->mtd);
475 }
476 #else
477 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
478                                       struct s3c2410_nand_mtd *mtd,
479                                       struct s3c2410_nand_set *set)
480 {
481         return add_mtd_device(&mtd->mtd);
482 }
483 #endif
484
485 /* s3c2410_nand_init_chip
486  *
487  * init a single instance of an chip
488 */
489
490 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
491                                    struct s3c2410_nand_mtd *nmtd,
492                                    struct s3c2410_nand_set *set)
493 {
494         struct nand_chip *chip = &nmtd->chip;
495
496         chip->IO_ADDR_R    = info->regs + S3C2410_NFDATA;
497         chip->IO_ADDR_W    = info->regs + S3C2410_NFDATA;
498         chip->cmd_ctrl     = s3c2410_nand_hwcontrol;
499         chip->dev_ready    = s3c2410_nand_devready;
500         chip->write_buf    = s3c2410_nand_write_buf;
501         chip->read_buf     = s3c2410_nand_read_buf;
502         chip->select_chip  = s3c2410_nand_select_chip;
503         chip->chip_delay   = 50;
504         chip->priv         = nmtd;
505         chip->options      = 0;
506         chip->controller   = &info->controller;
507
508         if (info->is_s3c2440) {
509                 chip->IO_ADDR_R  = info->regs + S3C2440_NFDATA;
510                 chip->IO_ADDR_W  = info->regs + S3C2440_NFDATA;
511                 chip->cmd_ctrl   = s3c2440_nand_hwcontrol;
512         }
513
514         nmtd->info         = info;
515         nmtd->mtd.priv     = chip;
516         nmtd->mtd.owner    = THIS_MODULE;
517         nmtd->set          = set;
518
519         if (hardware_ecc) {
520                 chip->ecc.correct   = s3c2410_nand_correct_data;
521                 chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
522                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
523                 chip->ecc.mode      = NAND_ECC_HW;
524                 chip->ecc.size      = 512;
525                 chip->ecc.bytes     = 3;
526                 chip->ecc.layout    = &nand_hw_eccoob;
527
528                 if (info->is_s3c2440) {
529                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
530                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
531                 }
532         } else {
533                 chip->ecc.mode      = NAND_ECC_SOFT;
534         }
535 }
536
537 /* s3c2410_nand_probe
538  *
539  * called by device layer when it finds a device matching
540  * one our driver can handled. This code checks to see if
541  * it can allocate all necessary resources then calls the
542  * nand layer to look for devices
543 */
544
545 static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440)
546 {
547         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
548         struct s3c2410_nand_info *info;
549         struct s3c2410_nand_mtd *nmtd;
550         struct s3c2410_nand_set *sets;
551         struct resource *res;
552         int err = 0;
553         int size;
554         int nr_sets;
555         int setno;
556
557         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
558
559         info = kmalloc(sizeof(*info), GFP_KERNEL);
560         if (info == NULL) {
561                 dev_err(&pdev->dev, "no memory for flash info\n");
562                 err = -ENOMEM;
563                 goto exit_error;
564         }
565
566         memzero(info, sizeof(*info));
567         platform_set_drvdata(pdev, info);
568
569         spin_lock_init(&info->controller.lock);
570         init_waitqueue_head(&info->controller.wq);
571
572         /* get the clock source and enable it */
573
574         info->clk = clk_get(&pdev->dev, "nand");
575         if (IS_ERR(info->clk)) {
576                 dev_err(&pdev->dev, "failed to get clock");
577                 err = -ENOENT;
578                 goto exit_error;
579         }
580
581         clk_enable(info->clk);
582
583         /* allocate and map the resource */
584
585         /* currently we assume we have the one resource */
586         res  = pdev->resource;
587         size = res->end - res->start + 1;
588
589         info->area = request_mem_region(res->start, size, pdev->name);
590
591         if (info->area == NULL) {
592                 dev_err(&pdev->dev, "cannot reserve register region\n");
593                 err = -ENOENT;
594                 goto exit_error;
595         }
596
597         info->device     = &pdev->dev;
598         info->platform   = plat;
599         info->regs       = ioremap(res->start, size);
600         info->is_s3c2440 = is_s3c2440;
601
602         if (info->regs == NULL) {
603                 dev_err(&pdev->dev, "cannot reserve register region\n");
604                 err = -EIO;
605                 goto exit_error;
606         }
607
608         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
609
610         /* initialise the hardware */
611
612         err = s3c2410_nand_inithw(info, pdev);
613         if (err != 0)
614                 goto exit_error;
615
616         sets = (plat != NULL) ? plat->sets : NULL;
617         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
618
619         info->mtd_count = nr_sets;
620
621         /* allocate our information */
622
623         size = nr_sets * sizeof(*info->mtds);
624         info->mtds = kmalloc(size, GFP_KERNEL);
625         if (info->mtds == NULL) {
626                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
627                 err = -ENOMEM;
628                 goto exit_error;
629         }
630
631         memzero(info->mtds, size);
632
633         /* initialise all possible chips */
634
635         nmtd = info->mtds;
636
637         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
638                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
639
640                 s3c2410_nand_init_chip(info, nmtd, sets);
641
642                 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
643
644                 if (nmtd->scan_res == 0) {
645                         s3c2410_nand_add_partition(info, nmtd, sets);
646                 }
647
648                 if (sets != NULL)
649                         sets++;
650         }
651
652         if (allow_clk_stop(info)) {
653                 dev_info(&pdev->dev, "clock idle support enabled\n");
654                 clk_disable(info->clk);
655         }
656
657         pr_debug("initialised ok\n");
658         return 0;
659
660  exit_error:
661         s3c2410_nand_remove(pdev);
662
663         if (err == 0)
664                 err = -EINVAL;
665         return err;
666 }
667
668 /* PM Support */
669 #ifdef CONFIG_PM
670
671 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
672 {
673         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
674
675         if (info) {
676                 if (!allow_clk_stop(info))
677                         clk_disable(info->clk);
678         }
679
680         return 0;
681 }
682
683 static int s3c24xx_nand_resume(struct platform_device *dev)
684 {
685         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
686
687         if (info) {
688                 clk_enable(info->clk);
689                 s3c2410_nand_inithw(info, dev);
690
691                 if (allow_clk_stop(info))
692                         clk_disable(info->clk);
693         }
694
695         return 0;
696 }
697
698 #else
699 #define s3c24xx_nand_suspend NULL
700 #define s3c24xx_nand_resume NULL
701 #endif
702
703 /* driver device registration */
704
705 static int s3c2410_nand_probe(struct platform_device *dev)
706 {
707         return s3c24xx_nand_probe(dev, 0);
708 }
709
710 static int s3c2440_nand_probe(struct platform_device *dev)
711 {
712         return s3c24xx_nand_probe(dev, 1);
713 }
714
715 static struct platform_driver s3c2410_nand_driver = {
716         .probe          = s3c2410_nand_probe,
717         .remove         = s3c2410_nand_remove,
718         .suspend        = s3c24xx_nand_suspend,
719         .resume         = s3c24xx_nand_resume,
720         .driver         = {
721                 .name   = "s3c2410-nand",
722                 .owner  = THIS_MODULE,
723         },
724 };
725
726 static struct platform_driver s3c2440_nand_driver = {
727         .probe          = s3c2440_nand_probe,
728         .remove         = s3c2410_nand_remove,
729         .suspend        = s3c24xx_nand_suspend,
730         .resume         = s3c24xx_nand_resume,
731         .driver         = {
732                 .name   = "s3c2440-nand",
733                 .owner  = THIS_MODULE,
734         },
735 };
736
737 static int __init s3c2410_nand_init(void)
738 {
739         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
740
741         platform_driver_register(&s3c2440_nand_driver);
742         return platform_driver_register(&s3c2410_nand_driver);
743 }
744
745 static void __exit s3c2410_nand_exit(void)
746 {
747         platform_driver_unregister(&s3c2440_nand_driver);
748         platform_driver_unregister(&s3c2410_nand_driver);
749 }
750
751 module_init(s3c2410_nand_init);
752 module_exit(s3c2410_nand_exit);
753
754 MODULE_LICENSE("GPL");
755 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
756 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");