git.oblomov.eu Git - linux-2.6/blob - drivers/usb/host/ehci-sched.c

   1 /*
   2  * Copyright (c) 2001-2004 by David Brownell
   3  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* this file is part of ehci-hcd.c */
  21
  22 /*-------------------------------------------------------------------------*/
  23
  24 /*
  25  * EHCI scheduled transaction support:  interrupt, iso, split iso
  26  * These are called "periodic" transactions in the EHCI spec.
  27  *
  28  * Note that for interrupt transfers, the QH/QTD manipulation is shared
  29  * with the "asynchronous" transaction support (control/bulk transfers).
  30  * The only real difference is in how interrupt transfers are scheduled.
  31  *
  32  * For ISO, we make an "iso_stream" head to serve the same role as a QH.
  33  * It keeps track of every ITD (or SITD) that's linked, and holds enough
  34  * pre-calculated schedule data to make appending to the queue be quick.
  35  */
  36
  37 static int ehci_get_frame (struct usb_hcd *hcd);
  38
  39 /*-------------------------------------------------------------------------*/
  40
  41 /*
  42  * periodic_next_shadow - return "next" pointer on shadow list
  43  * @periodic: host pointer to qh/itd/sitd
  44  * @tag: hardware tag for type of this record
  45  */
  46 static union ehci_shadow *
  47 periodic_next_shadow (union ehci_shadow *periodic, __le32 tag)
  48 {
  49         switch (tag) {
  50         case Q_TYPE_QH:
  51                 return &periodic->qh->qh_next;
  52         case Q_TYPE_FSTN:
  53                 return &periodic->fstn->fstn_next;
  54         case Q_TYPE_ITD:
  55                 return &periodic->itd->itd_next;
  56         // case Q_TYPE_SITD:
  57         default:
  58                 return &periodic->sitd->sitd_next;
  59         }
  60 }
  61
  62 /* caller must hold ehci->lock */
  63 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
  64 {
  65         union ehci_shadow       *prev_p = &ehci->pshadow [frame];
  66         __le32                  *hw_p = &ehci->periodic [frame];
  67         union ehci_shadow       here = *prev_p;
  68
  69         /* find predecessor of "ptr"; hw and shadow lists are in sync */
  70         while (here.ptr && here.ptr != ptr) {
  71                 prev_p = periodic_next_shadow (prev_p, Q_NEXT_TYPE (*hw_p));
  72                 hw_p = here.hw_next;
  73                 here = *prev_p;
  74         }
  75         /* an interrupt entry (at list end) could have been shared */
  76         if (!here.ptr)
  77                 return;
  78
  79         /* update shadow and hardware lists ... the old "next" pointers
  80          * from ptr may still be in use, the caller updates them.
  81          */
  82         *prev_p = *periodic_next_shadow (&here, Q_NEXT_TYPE (*hw_p));
  83         *hw_p = *here.hw_next;
  84 }
  85
  86 /* how many of the uframe's 125 usecs are allocated? */
  87 static unsigned short
  88 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
  89 {
  90         __le32                  *hw_p = &ehci->periodic [frame];
  91         union ehci_shadow       *q = &ehci->pshadow [frame];
  92         unsigned                usecs = 0;
  93
  94         while (q->ptr) {
  95                 switch (Q_NEXT_TYPE (*hw_p)) {
  96                 case Q_TYPE_QH:
  97                         /* is it in the S-mask? */
  98                         if (q->qh->hw_info2 & cpu_to_le32 (1 << uframe))
  99                                 usecs += q->qh->usecs;
 100                         /* ... or C-mask? */
 101                         if (q->qh->hw_info2 & cpu_to_le32 (1 << (8 + uframe)))
 102                                 usecs += q->qh->c_usecs;
 103                         hw_p = &q->qh->hw_next;
 104                         q = &q->qh->qh_next;
 105                         break;
 106                 // case Q_TYPE_FSTN:
 107                 default:
 108                         /* for "save place" FSTNs, count the relevant INTR
 109                          * bandwidth from the previous frame
 110                          */
 111                         if (q->fstn->hw_prev != EHCI_LIST_END) {
 112                                 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
 113                         }
 114                         hw_p = &q->fstn->hw_next;
 115                         q = &q->fstn->fstn_next;
 116                         break;
 117                 case Q_TYPE_ITD:
 118                         usecs += q->itd->usecs [uframe];
 119                         hw_p = &q->itd->hw_next;
 120                         q = &q->itd->itd_next;
 121                         break;
 122                 case Q_TYPE_SITD:
 123                         /* is it in the S-mask?  (count SPLIT, DATA) */
 124                         if (q->sitd->hw_uframe & cpu_to_le32 (1 << uframe)) {
 125                                 if (q->sitd->hw_fullspeed_ep &
 126                                                 __constant_cpu_to_le32 (1<<31))
 127                                         usecs += q->sitd->stream->usecs;
 128                                 else    /* worst case for OUT start-split */
 129                                         usecs += HS_USECS_ISO (188);
 130                         }
 131
 132                         /* ... C-mask?  (count CSPLIT, DATA) */
 133                         if (q->sitd->hw_uframe &
 134                                         cpu_to_le32 (1 << (8 + uframe))) {
 135                                 /* worst case for IN complete-split */
 136                                 usecs += q->sitd->stream->c_usecs;
 137                         }
 138
 139                         hw_p = &q->sitd->hw_next;
 140                         q = &q->sitd->sitd_next;
 141                         break;
 142                 }
 143         }
 144 #ifdef  DEBUG
 145         if (usecs > 100)
 146                 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
 147                         frame * 8 + uframe, usecs);
 148 #endif
 149         return usecs;
 150 }
 151
 152 /*-------------------------------------------------------------------------*/
 153
 154 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
 155 {
 156         if (!dev1->tt || !dev2->tt)
 157                 return 0;
 158         if (dev1->tt != dev2->tt)
 159                 return 0;
 160         if (dev1->tt->multi)
 161                 return dev1->ttport == dev2->ttport;
 162         else
 163                 return 1;
 164 }
 165
 166 /* return true iff the device's transaction translator is available
 167  * for a periodic transfer starting at the specified frame, using
 168  * all the uframes in the mask.
 169  */
 170 static int tt_no_collision (
 171         struct ehci_hcd         *ehci,
 172         unsigned                period,
 173         struct usb_device       *dev,
 174         unsigned                frame,
 175         u32                     uf_mask
 176 )
 177 {
 178         if (period == 0)        /* error */
 179                 return 0;
 180
 181         /* note bandwidth wastage:  split never follows csplit
 182          * (different dev or endpoint) until the next uframe.
 183          * calling convention doesn't make that distinction.
 184          */
 185         for (; frame < ehci->periodic_size; frame += period) {
 186                 union ehci_shadow       here;
 187                 __le32                  type;
 188
 189                 here = ehci->pshadow [frame];
 190                 type = Q_NEXT_TYPE (ehci->periodic [frame]);
 191                 while (here.ptr) {
 192                         switch (type) {
 193                         case Q_TYPE_ITD:
 194                                 type = Q_NEXT_TYPE (here.itd->hw_next);
 195                                 here = here.itd->itd_next;
 196                                 continue;
 197                         case Q_TYPE_QH:
 198                                 if (same_tt (dev, here.qh->dev)) {
 199                                         u32             mask;
 200
 201                                         mask = le32_to_cpu (here.qh->hw_info2);
 202                                         /* "knows" no gap is needed */
 203                                         mask |= mask >> 8;
 204                                         if (mask & uf_mask)
 205                                                 break;
 206                                 }
 207                                 type = Q_NEXT_TYPE (here.qh->hw_next);
 208                                 here = here.qh->qh_next;
 209                                 continue;
 210                         case Q_TYPE_SITD:
 211                                 if (same_tt (dev, here.sitd->urb->dev)) {
 212                                         u16             mask;
 213
 214                                         mask = le32_to_cpu (here.sitd
 215                                                                 ->hw_uframe);
 216                                         /* FIXME assumes no gap for IN! */
 217                                         mask |= mask >> 8;
 218                                         if (mask & uf_mask)
 219                                                 break;
 220                                 }
 221                                 type = Q_NEXT_TYPE (here.sitd->hw_next);
 222                                 here = here.sitd->sitd_next;
 223                                 continue;
 224                         // case Q_TYPE_FSTN:
 225                         default:
 226                                 ehci_dbg (ehci,
 227                                         "periodic frame %d bogus type %d\n",
 228                                         frame, type);
 229                         }
 230
 231                         /* collision or error */
 232                         return 0;
 233                 }
 234         }
 235
 236         /* no collision */
 237         return 1;
 238 }
 239
 240 /*-------------------------------------------------------------------------*/
 241
 242 static int enable_periodic (struct ehci_hcd *ehci)
 243 {
 244         u32     cmd;
 245         int     status;
 246
 247         /* did clearing PSE did take effect yet?
 248          * takes effect only at frame boundaries...
 249          */
 250         status = handshake (&ehci->regs->status, STS_PSS, 0, 9 * 125);
 251         if (status != 0) {
 252                 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 253                 return status;
 254         }
 255
 256         cmd = readl (&ehci->regs->command) | CMD_PSE;
 257         writel (cmd, &ehci->regs->command);
 258         /* posted write ... PSS happens later */
 259         ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
 260
 261         /* make sure ehci_work scans these */
 262         ehci->next_uframe = readl (&ehci->regs->frame_index)
 263                                 % (ehci->periodic_size << 3);
 264         return 0;
 265 }
 266
 267 static int disable_periodic (struct ehci_hcd *ehci)
 268 {
 269         u32     cmd;
 270         int     status;
 271
 272         /* did setting PSE not take effect yet?
 273          * takes effect only at frame boundaries...
 274          */
 275         status = handshake (&ehci->regs->status, STS_PSS, STS_PSS, 9 * 125);
 276         if (status != 0) {
 277                 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 278                 return status;
 279         }
 280
 281         cmd = readl (&ehci->regs->command) & ~CMD_PSE;
 282         writel (cmd, &ehci->regs->command);
 283         /* posted write ... */
 284
 285         ehci->next_uframe = -1;
 286         return 0;
 287 }
 288
 289 /*-------------------------------------------------------------------------*/
 290
 291 /* periodic schedule slots have iso tds (normal or split) first, then a
 292  * sparse tree for active interrupt transfers.
 293  *
 294  * this just links in a qh; caller guarantees uframe masks are set right.
 295  * no FSTN support (yet; ehci 0.96+)
 296  */
 297 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 298 {
 299         unsigned        i;
 300         unsigned        period = qh->period;
 301
 302         dev_dbg (&qh->dev->dev,
 303                 "link qh%d-%04x/%p start %d [%d/%d us]\n",
 304                 period, le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
 305                 qh, qh->start, qh->usecs, qh->c_usecs);
 306
 307         /* high bandwidth, or otherwise every microframe */
 308         if (period == 0)
 309                 period = 1;
 310
 311         for (i = qh->start; i < ehci->periodic_size; i += period) {
 312                 union ehci_shadow       *prev = &ehci->pshadow [i];
 313                 __le32                  *hw_p = &ehci->periodic [i];
 314                 union ehci_shadow       here = *prev;
 315                 __le32                  type = 0;
 316
 317                 /* skip the iso nodes at list head */
 318                 while (here.ptr) {
 319                         type = Q_NEXT_TYPE (*hw_p);
 320                         if (type == Q_TYPE_QH)
 321                                 break;
 322                         prev = periodic_next_shadow (prev, type);
 323                         hw_p = &here.qh->hw_next;
 324                         here = *prev;
 325                 }
 326
 327                 /* sorting each branch by period (slow-->fast)
 328                  * enables sharing interior tree nodes
 329                  */
 330                 while (here.ptr && qh != here.qh) {
 331                         if (qh->period > here.qh->period)
 332                                 break;
 333                         prev = &here.qh->qh_next;
 334                         hw_p = &here.qh->hw_next;
 335                         here = *prev;
 336                 }
 337                 /* link in this qh, unless some earlier pass did that */
 338                 if (qh != here.qh) {
 339                         qh->qh_next = here;
 340                         if (here.qh)
 341                                 qh->hw_next = *hw_p;
 342                         wmb ();
 343                         prev->qh = qh;
 344                         *hw_p = QH_NEXT (qh->qh_dma);
 345                 }
 346         }
 347         qh->qh_state = QH_STATE_LINKED;
 348         qh_get (qh);
 349
 350         /* update per-qh bandwidth for usbfs */
 351         ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
 352                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 353                 : (qh->usecs * 8);
 354
 355         /* maybe enable periodic schedule processing */
 356         if (!ehci->periodic_sched++)
 357                 return enable_periodic (ehci);
 358
 359         return 0;
 360 }
 361
 362 static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 363 {
 364         unsigned        i;
 365         unsigned        period;
 366
 367         // FIXME:
 368         // IF this isn't high speed
 369         //   and this qh is active in the current uframe
 370         //   (and overlay token SplitXstate is false?)
 371         // THEN
 372         //   qh->hw_info1 |= __constant_cpu_to_le32 (1 << 7 /* "ignore" */);
 373
 374         /* high bandwidth, or otherwise part of every microframe */
 375         if ((period = qh->period) == 0)
 376                 period = 1;
 377
 378         for (i = qh->start; i < ehci->periodic_size; i += period)
 379                 periodic_unlink (ehci, i, qh);
 380
 381         /* update per-qh bandwidth for usbfs */
 382         ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
 383                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 384                 : (qh->usecs * 8);
 385
 386         dev_dbg (&qh->dev->dev,
 387                 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
 388                 qh->period,
 389                 le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
 390                 qh, qh->start, qh->usecs, qh->c_usecs);
 391
 392         /* qh->qh_next still "live" to HC */
 393         qh->qh_state = QH_STATE_UNLINK;
 394         qh->qh_next.ptr = NULL;
 395         qh_put (qh);
 396
 397         /* maybe turn off periodic schedule */
 398         ehci->periodic_sched--;
 399         if (!ehci->periodic_sched)
 400                 (void) disable_periodic (ehci);
 401 }
 402
 403 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 404 {
 405         unsigned        wait;
 406
 407         qh_unlink_periodic (ehci, qh);
 408
 409         /* simple/paranoid:  always delay, expecting the HC needs to read
 410          * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
 411          * expect khubd to clean up after any CSPLITs we won't issue.
 412          * active high speed queues may need bigger delays...
 413          */
 414         if (list_empty (&qh->qtd_list)
 415                         || (__constant_cpu_to_le32 (QH_CMASK)
 416                                         & qh->hw_info2) != 0)
 417                 wait = 2;
 418         else
 419                 wait = 55;      /* worst case: 3 * 1024 */
 420
 421         udelay (wait);
 422         qh->qh_state = QH_STATE_IDLE;
 423         qh->hw_next = EHCI_LIST_END;
 424         wmb ();
 425 }
 426
 427 /*-------------------------------------------------------------------------*/
 428
 429 static int check_period (
 430         struct ehci_hcd *ehci,
 431         unsigned        frame,
 432         unsigned        uframe,
 433         unsigned        period,
 434         unsigned        usecs
 435 ) {
 436         int             claimed;
 437
 438         /* complete split running into next frame?
 439          * given FSTN support, we could sometimes check...
 440          */
 441         if (uframe >= 8)
 442                 return 0;
 443
 444         /*
 445          * 80% periodic == 100 usec/uframe available
 446          * convert "usecs we need" to "max already claimed"
 447          */
 448         usecs = 100 - usecs;
 449
 450         /* we "know" 2 and 4 uframe intervals were rejected; so
 451          * for period 0, check _every_ microframe in the schedule.
 452          */
 453         if (unlikely (period == 0)) {
 454                 do {
 455                         for (uframe = 0; uframe < 7; uframe++) {
 456                                 claimed = periodic_usecs (ehci, frame, uframe);
 457                                 if (claimed > usecs)
 458                                         return 0;
 459                         }
 460                 } while ((frame += 1) < ehci->periodic_size);
 461
 462         /* just check the specified uframe, at that period */
 463         } else {
 464                 do {
 465                         claimed = periodic_usecs (ehci, frame, uframe);
 466                         if (claimed > usecs)
 467                                 return 0;
 468                 } while ((frame += period) < ehci->periodic_size);
 469         }
 470
 471         // success!
 472         return 1;
 473 }
 474
 475 static int check_intr_schedule (
 476         struct ehci_hcd         *ehci,
 477         unsigned                frame,
 478         unsigned                uframe,
 479         const struct ehci_qh    *qh,
 480         __le32                  *c_maskp
 481 )
 482 {
 483         int             retval = -ENOSPC;
 484         u8              mask;
 485
 486         if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
 487                 goto done;
 488
 489         if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
 490                 goto done;
 491         if (!qh->c_usecs) {
 492                 retval = 0;
 493                 *c_maskp = 0;
 494                 goto done;
 495         }
 496
 497         /* Make sure this tt's buffer is also available for CSPLITs.
 498          * We pessimize a bit; probably the typical full speed case
 499          * doesn't need the second CSPLIT.
 500          *
 501          * NOTE:  both SPLIT and CSPLIT could be checked in just
 502          * one smart pass...
 503          */
 504         mask = 0x03 << (uframe + qh->gap_uf);
 505         *c_maskp = cpu_to_le32 (mask << 8);
 506
 507         mask |= 1 << uframe;
 508         if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
 509                 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
 510                                         qh->period, qh->c_usecs))
 511                         goto done;
 512                 if (!check_period (ehci, frame, uframe + qh->gap_uf,
 513                                         qh->period, qh->c_usecs))
 514                         goto done;
 515                 retval = 0;
 516         }
 517 done:
 518         return retval;
 519 }
 520
 521 /* "first fit" scheduling policy used the first time through,
 522  * or when the previous schedule slot can't be re-used.
 523  */
 524 static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 525 {
 526         int             status;
 527         unsigned        uframe;
 528         __le32          c_mask;
 529         unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
 530
 531         qh_refresh(ehci, qh);
 532         qh->hw_next = EHCI_LIST_END;
 533         frame = qh->start;
 534
 535         /* reuse the previous schedule slots, if we can */
 536         if (frame < qh->period) {
 537                 uframe = ffs (le32_to_cpup (&qh->hw_info2) & QH_SMASK);
 538                 status = check_intr_schedule (ehci, frame, --uframe,
 539                                 qh, &c_mask);
 540         } else {
 541                 uframe = 0;
 542                 c_mask = 0;
 543                 status = -ENOSPC;
 544         }
 545
 546         /* else scan the schedule to find a group of slots such that all
 547          * uframes have enough periodic bandwidth available.
 548          */
 549         if (status) {
 550                 /* "normal" case, uframing flexible except with splits */
 551                 if (qh->period) {
 552                         frame = qh->period - 1;
 553                         do {
 554                                 for (uframe = 0; uframe < 8; uframe++) {
 555                                         status = check_intr_schedule (ehci,
 556                                                         frame, uframe, qh,
 557                                                         &c_mask);
 558                                         if (status == 0)
 559                                                 break;
 560                                 }
 561                         } while (status && frame--);
 562
 563                 /* qh->period == 0 means every uframe */
 564                 } else {
 565                         frame = 0;
 566                         status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
 567                 }
 568                 if (status)
 569                         goto done;
 570                 qh->start = frame;
 571
 572                 /* reset S-frame and (maybe) C-frame masks */
 573                 qh->hw_info2 &= __constant_cpu_to_le32(~(QH_CMASK | QH_SMASK));
 574                 qh->hw_info2 |= qh->period
 575                         ? cpu_to_le32 (1 << uframe)
 576                         : __constant_cpu_to_le32 (QH_SMASK);
 577                 qh->hw_info2 |= c_mask;
 578         } else
 579                 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
 580
 581         /* stuff into the periodic schedule */
 582         status = qh_link_periodic (ehci, qh);
 583 done:
 584         return status;
 585 }
 586
 587 static int intr_submit (
 588         struct ehci_hcd         *ehci,
 589         struct usb_host_endpoint *ep,
 590         struct urb              *urb,
 591         struct list_head        *qtd_list,
 592         gfp_t                   mem_flags
 593 ) {
 594         unsigned                epnum;
 595         unsigned long           flags;
 596         struct ehci_qh          *qh;
 597         int                     status = 0;
 598         struct list_head        empty;
 599
 600         /* get endpoint and transfer/schedule data */
 601         epnum = ep->desc.bEndpointAddress;
 602
 603         spin_lock_irqsave (&ehci->lock, flags);
 604
 605         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
 606                                &ehci_to_hcd(ehci)->flags))) {
 607                 status = -ESHUTDOWN;
 608                 goto done;
 609         }
 610
 611         /* get qh and force any scheduling errors */
 612         INIT_LIST_HEAD (&empty);
 613         qh = qh_append_tds (ehci, urb, &empty, epnum, &ep->hcpriv);
 614         if (qh == NULL) {
 615                 status = -ENOMEM;
 616                 goto done;
 617         }
 618         if (qh->qh_state == QH_STATE_IDLE) {
 619                 if ((status = qh_schedule (ehci, qh)) != 0)
 620                         goto done;
 621         }
 622
 623         /* then queue the urb's tds to the qh */
 624         qh = qh_append_tds (ehci, urb, qtd_list, epnum, &ep->hcpriv);
 625         BUG_ON (qh == NULL);
 626
 627         /* ... update usbfs periodic stats */
 628         ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
 629
 630 done:
 631         spin_unlock_irqrestore (&ehci->lock, flags);
 632         if (status)
 633                 qtd_list_free (ehci, urb, qtd_list);
 634
 635         return status;
 636 }
 637
 638 /*-------------------------------------------------------------------------*/
 639
 640 /* ehci_iso_stream ops work with both ITD and SITD */
 641
 642 static struct ehci_iso_stream *
 643 iso_stream_alloc (gfp_t mem_flags)
 644 {
 645         struct ehci_iso_stream *stream;
 646
 647         stream = kzalloc(sizeof *stream, mem_flags);
 648         if (likely (stream != NULL)) {
 649                 INIT_LIST_HEAD(&stream->td_list);
 650                 INIT_LIST_HEAD(&stream->free_list);
 651                 stream->next_uframe = -1;
 652                 stream->refcount = 1;
 653         }
 654         return stream;
 655 }
 656
 657 static void
 658 iso_stream_init (
 659         struct ehci_hcd         *ehci,
 660         struct ehci_iso_stream  *stream,
 661         struct usb_device       *dev,
 662         int                     pipe,
 663         unsigned                interval
 664 )
 665 {
 666         static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
 667
 668         u32                     buf1;
 669         unsigned                epnum, maxp;
 670         int                     is_input;
 671         long                    bandwidth;
 672
 673         /*
 674          * this might be a "high bandwidth" highspeed endpoint,
 675          * as encoded in the ep descriptor's wMaxPacket field
 676          */
 677         epnum = usb_pipeendpoint (pipe);
 678         is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
 679         maxp = usb_maxpacket(dev, pipe, !is_input);
 680         if (is_input) {
 681                 buf1 = (1 << 11);
 682         } else {
 683                 buf1 = 0;
 684         }
 685
 686         /* knows about ITD vs SITD */
 687         if (dev->speed == USB_SPEED_HIGH) {
 688                 unsigned multi = hb_mult(maxp);
 689
 690                 stream->highspeed = 1;
 691
 692                 maxp = max_packet(maxp);
 693                 buf1 |= maxp;
 694                 maxp *= multi;
 695
 696                 stream->buf0 = cpu_to_le32 ((epnum << 8) | dev->devnum);
 697                 stream->buf1 = cpu_to_le32 (buf1);
 698                 stream->buf2 = cpu_to_le32 (multi);
 699
 700                 /* usbfs wants to report the average usecs per frame tied up
 701                  * when transfers on this endpoint are scheduled ...
 702                  */
 703                 stream->usecs = HS_USECS_ISO (maxp);
 704                 bandwidth = stream->usecs * 8;
 705                 bandwidth /= 1 << (interval - 1);
 706
 707         } else {
 708                 u32             addr;
 709                 int             think_time;
 710
 711                 addr = dev->ttport << 24;
 712                 if (!ehci_is_TDI(ehci)
 713                                 || (dev->tt->hub !=
 714                                         ehci_to_hcd(ehci)->self.root_hub))
 715                         addr |= dev->tt->hub->devnum << 16;
 716                 addr |= epnum << 8;
 717                 addr |= dev->devnum;
 718                 stream->usecs = HS_USECS_ISO (maxp);
 719                 think_time = dev->tt ? dev->tt->think_time : 0;
 720                 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
 721                                 dev->speed, is_input, 1, maxp));
 722                 if (is_input) {
 723                         u32     tmp;
 724
 725                         addr |= 1 << 31;
 726                         stream->c_usecs = stream->usecs;
 727                         stream->usecs = HS_USECS_ISO (1);
 728                         stream->raw_mask = 1;
 729
 730                         /* pessimistic c-mask */
 731                         tmp = usb_calc_bus_time (USB_SPEED_FULL, 1, 0, maxp)
 732                                         / (125 * 1000);
 733                         stream->raw_mask |= 3 << (tmp + 9);
 734                 } else
 735                         stream->raw_mask = smask_out [maxp / 188];
 736                 bandwidth = stream->usecs + stream->c_usecs;
 737                 bandwidth /= 1 << (interval + 2);
 738
 739                 /* stream->splits gets created from raw_mask later */
 740                 stream->address = cpu_to_le32 (addr);
 741         }
 742         stream->bandwidth = bandwidth;
 743
 744         stream->udev = dev;
 745
 746         stream->bEndpointAddress = is_input | epnum;
 747         stream->interval = interval;
 748         stream->maxp = maxp;
 749 }
 750
 751 static void
 752 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
 753 {
 754         stream->refcount--;
 755
 756         /* free whenever just a dev->ep reference remains.
 757          * not like a QH -- no persistent state (toggle, halt)
 758          */
 759         if (stream->refcount == 1) {
 760                 int             is_in;
 761
 762                 // BUG_ON (!list_empty(&stream->td_list));
 763
 764                 while (!list_empty (&stream->free_list)) {
 765                         struct list_head        *entry;
 766
 767                         entry = stream->free_list.next;
 768                         list_del (entry);
 769
 770                         /* knows about ITD vs SITD */
 771                         if (stream->highspeed) {
 772                                 struct ehci_itd         *itd;
 773
 774                                 itd = list_entry (entry, struct ehci_itd,
 775                                                 itd_list);
 776                                 dma_pool_free (ehci->itd_pool, itd,
 777                                                 itd->itd_dma);
 778                         } else {
 779                                 struct ehci_sitd        *sitd;
 780
 781                                 sitd = list_entry (entry, struct ehci_sitd,
 782                                                 sitd_list);
 783                                 dma_pool_free (ehci->sitd_pool, sitd,
 784                                                 sitd->sitd_dma);
 785                         }
 786                 }
 787
 788                 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
 789                 stream->bEndpointAddress &= 0x0f;
 790                 stream->ep->hcpriv = NULL;
 791
 792                 if (stream->rescheduled) {
 793                         ehci_info (ehci, "ep%d%s-iso rescheduled "
 794                                 "%lu times in %lu seconds\n",
 795                                 stream->bEndpointAddress, is_in ? "in" : "out",
 796                                 stream->rescheduled,
 797                                 ((jiffies - stream->start)/HZ)
 798                                 );
 799                 }
 800
 801                 kfree(stream);
 802         }
 803 }
 804
 805 static inline struct ehci_iso_stream *
 806 iso_stream_get (struct ehci_iso_stream *stream)
 807 {
 808         if (likely (stream != NULL))
 809                 stream->refcount++;
 810         return stream;
 811 }
 812
 813 static struct ehci_iso_stream *
 814 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
 815 {
 816         unsigned                epnum;
 817         struct ehci_iso_stream  *stream;
 818         struct usb_host_endpoint *ep;
 819         unsigned long           flags;
 820
 821         epnum = usb_pipeendpoint (urb->pipe);
 822         if (usb_pipein(urb->pipe))
 823                 ep = urb->dev->ep_in[epnum];
 824         else
 825                 ep = urb->dev->ep_out[epnum];
 826
 827         spin_lock_irqsave (&ehci->lock, flags);
 828         stream = ep->hcpriv;
 829
 830         if (unlikely (stream == NULL)) {
 831                 stream = iso_stream_alloc(GFP_ATOMIC);
 832                 if (likely (stream != NULL)) {
 833                         /* dev->ep owns the initial refcount */
 834                         ep->hcpriv = stream;
 835                         stream->ep = ep;
 836                         iso_stream_init(ehci, stream, urb->dev, urb->pipe,
 837                                         urb->interval);
 838                 }
 839
 840         /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
 841         } else if (unlikely (stream->hw_info1 != 0)) {
 842                 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
 843                         urb->dev->devpath, epnum,
 844                         usb_pipein(urb->pipe) ? "in" : "out");
 845                 stream = NULL;
 846         }
 847
 848         /* caller guarantees an eventual matching iso_stream_put */
 849         stream = iso_stream_get (stream);
 850
 851         spin_unlock_irqrestore (&ehci->lock, flags);
 852         return stream;
 853 }
 854
 855 /*-------------------------------------------------------------------------*/
 856
 857 /* ehci_iso_sched ops can be ITD-only or SITD-only */
 858
 859 static struct ehci_iso_sched *
 860 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
 861 {
 862         struct ehci_iso_sched   *iso_sched;
 863         int                     size = sizeof *iso_sched;
 864
 865         size += packets * sizeof (struct ehci_iso_packet);
 866         iso_sched = kmalloc (size, mem_flags);
 867         if (likely (iso_sched != NULL)) {
 868                 memset(iso_sched, 0, size);
 869                 INIT_LIST_HEAD (&iso_sched->td_list);
 870         }
 871         return iso_sched;
 872 }
 873
 874 static inline void
 875 itd_sched_init (
 876         struct ehci_iso_sched   *iso_sched,
 877         struct ehci_iso_stream  *stream,
 878         struct urb              *urb
 879 )
 880 {
 881         unsigned        i;
 882         dma_addr_t      dma = urb->transfer_dma;
 883
 884         /* how many uframes are needed for these transfers */
 885         iso_sched->span = urb->number_of_packets * stream->interval;
 886
 887         /* figure out per-uframe itd fields that we'll need later
 888          * when we fit new itds into the schedule.
 889          */
 890         for (i = 0; i < urb->number_of_packets; i++) {
 891                 struct ehci_iso_packet  *uframe = &iso_sched->packet [i];
 892                 unsigned                length;
 893                 dma_addr_t              buf;
 894                 u32                     trans;
 895
 896                 length = urb->iso_frame_desc [i].length;
 897                 buf = dma + urb->iso_frame_desc [i].offset;
 898
 899                 trans = EHCI_ISOC_ACTIVE;
 900                 trans |= buf & 0x0fff;
 901                 if (unlikely (((i + 1) == urb->number_of_packets))
 902                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
 903                         trans |= EHCI_ITD_IOC;
 904                 trans |= length << 16;
 905                 uframe->transaction = cpu_to_le32 (trans);
 906
 907                 /* might need to cross a buffer page within a uframe */
 908                 uframe->bufp = (buf & ~(u64)0x0fff);
 909                 buf += length;
 910                 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
 911                         uframe->cross = 1;
 912         }
 913 }
 914
 915 static void
 916 iso_sched_free (
 917         struct ehci_iso_stream  *stream,
 918         struct ehci_iso_sched   *iso_sched
 919 )
 920 {
 921         if (!iso_sched)
 922                 return;
 923         // caller must hold ehci->lock!
 924         list_splice (&iso_sched->td_list, &stream->free_list);
 925         kfree (iso_sched);
 926 }
 927
 928 static int
 929 itd_urb_transaction (
 930         struct ehci_iso_stream  *stream,
 931         struct ehci_hcd         *ehci,
 932         struct urb              *urb,
 933         gfp_t                   mem_flags
 934 )
 935 {
 936         struct ehci_itd         *itd;
 937         dma_addr_t              itd_dma;
 938         int                     i;
 939         unsigned                num_itds;
 940         struct ehci_iso_sched   *sched;
 941         unsigned long           flags;
 942
 943         sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
 944         if (unlikely (sched == NULL))
 945                 return -ENOMEM;
 946
 947         itd_sched_init (sched, stream, urb);
 948
 949         if (urb->interval < 8)
 950                 num_itds = 1 + (sched->span + 7) / 8;
 951         else
 952                 num_itds = urb->number_of_packets;
 953
 954         /* allocate/init ITDs */
 955         spin_lock_irqsave (&ehci->lock, flags);
 956         for (i = 0; i < num_itds; i++) {
 957
 958                 /* free_list.next might be cache-hot ... but maybe
 959                  * the HC caches it too. avoid that issue for now.
 960                  */
 961
 962                 /* prefer previously-allocated itds */
 963                 if (likely (!list_empty(&stream->free_list))) {
 964                         itd = list_entry (stream->free_list.prev,
 965                                          struct ehci_itd, itd_list);
 966                         list_del (&itd->itd_list);
 967                         itd_dma = itd->itd_dma;
 968                 } else
 969                         itd = NULL;
 970
 971                 if (!itd) {
 972                         spin_unlock_irqrestore (&ehci->lock, flags);
 973                         itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
 974                                         &itd_dma);
 975                         spin_lock_irqsave (&ehci->lock, flags);
 976                 }
 977
 978                 if (unlikely (NULL == itd)) {
 979                         iso_sched_free (stream, sched);
 980                         spin_unlock_irqrestore (&ehci->lock, flags);
 981                         return -ENOMEM;
 982                 }
 983                 memset (itd, 0, sizeof *itd);
 984                 itd->itd_dma = itd_dma;
 985                 list_add (&itd->itd_list, &sched->td_list);
 986         }
 987         spin_unlock_irqrestore (&ehci->lock, flags);
 988
 989         /* temporarily store schedule info in hcpriv */
 990         urb->hcpriv = sched;
 991         urb->error_count = 0;
 992         return 0;
 993 }
 994
 995 /*-------------------------------------------------------------------------*/
 996
 997 static inline int
 998 itd_slot_ok (
 999         struct ehci_hcd         *ehci,
1000         u32                     mod,
1001         u32                     uframe,
1002         u8                      usecs,
1003         u32                     period
1004 )
1005 {
1006         uframe %= period;
1007         do {
1008                 /* can't commit more than 80% periodic == 100 usec */
1009                 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1010                                 > (100 - usecs))
1011                         return 0;
1012
1013                 /* we know urb->interval is 2^N uframes */
1014                 uframe += period;
1015         } while (uframe < mod);
1016         return 1;
1017 }
1018
1019 static inline int
1020 sitd_slot_ok (
1021         struct ehci_hcd         *ehci,
1022         u32                     mod,
1023         struct ehci_iso_stream  *stream,
1024         u32                     uframe,
1025         struct ehci_iso_sched   *sched,
1026         u32                     period_uframes
1027 )
1028 {
1029         u32                     mask, tmp;
1030         u32                     frame, uf;
1031
1032         mask = stream->raw_mask << (uframe & 7);
1033
1034         /* for IN, don't wrap CSPLIT into the next frame */
1035         if (mask & ~0xffff)
1036                 return 0;
1037
1038         /* this multi-pass logic is simple, but performance may
1039          * suffer when the schedule data isn't cached.
1040          */
1041
1042         /* check bandwidth */
1043         uframe %= period_uframes;
1044         do {
1045                 u32             max_used;
1046
1047                 frame = uframe >> 3;
1048                 uf = uframe & 7;
1049
1050                 /* tt must be idle for start(s), any gap, and csplit.
1051                  * assume scheduling slop leaves 10+% for control/bulk.
1052                  */
1053                 if (!tt_no_collision (ehci, period_uframes << 3,
1054                                 stream->udev, frame, mask))
1055                         return 0;
1056
1057                 /* check starts (OUT uses more than one) */
1058                 max_used = 100 - stream->usecs;
1059                 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1060                         if (periodic_usecs (ehci, frame, uf) > max_used)
1061                                 return 0;
1062                 }
1063
1064                 /* for IN, check CSPLIT */
1065                 if (stream->c_usecs) {
1066                         uf = uframe & 7;
1067                         max_used = 100 - stream->c_usecs;
1068                         do {
1069                                 tmp = 1 << uf;
1070                                 tmp <<= 8;
1071                                 if ((stream->raw_mask & tmp) == 0)
1072                                         continue;
1073                                 if (periodic_usecs (ehci, frame, uf)
1074                                                 > max_used)
1075                                         return 0;
1076                         } while (++uf < 8);
1077                 }
1078
1079                 /* we know urb->interval is 2^N uframes */
1080                 uframe += period_uframes;
1081         } while (uframe < mod);
1082
1083         stream->splits = cpu_to_le32(stream->raw_mask << (uframe & 7));
1084         return 1;
1085 }
1086
1087 /*
1088  * This scheduler plans almost as far into the future as it has actual
1089  * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
1090  * "as small as possible" to be cache-friendlier.)  That limits the size
1091  * transfers you can stream reliably; avoid more than 64 msec per urb.
1092  * Also avoid queue depths of less than ehci's worst irq latency (affected
1093  * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1094  * and other factors); or more than about 230 msec total (for portability,
1095  * given EHCI_TUNE_FLS and the slop).  Or, write a smarter scheduler!
1096  */
1097
1098 #define SCHEDULE_SLOP   10      /* frames */
1099
1100 static int
1101 iso_stream_schedule (
1102         struct ehci_hcd         *ehci,
1103         struct urb              *urb,
1104         struct ehci_iso_stream  *stream
1105 )
1106 {
1107         u32                     now, start, max, period;
1108         int                     status;
1109         unsigned                mod = ehci->periodic_size << 3;
1110         struct ehci_iso_sched   *sched = urb->hcpriv;
1111
1112         if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1113                 ehci_dbg (ehci, "iso request %p too long\n", urb);
1114                 status = -EFBIG;
1115                 goto fail;
1116         }
1117
1118         if ((stream->depth + sched->span) > mod) {
1119                 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1120                         urb, stream->depth, sched->span, mod);
1121                 status = -EFBIG;
1122                 goto fail;
1123         }
1124
1125         now = readl (&ehci->regs->frame_index) % mod;
1126
1127         /* when's the last uframe this urb could start? */
1128         max = now + mod;
1129
1130         /* typical case: reuse current schedule. stream is still active,
1131          * and no gaps from host falling behind (irq delays etc)
1132          */
1133         if (likely (!list_empty (&stream->td_list))) {
1134                 start = stream->next_uframe;
1135                 if (start < now)
1136                         start += mod;
1137                 if (likely ((start + sched->span) < max))
1138                         goto ready;
1139                 /* else fell behind; someday, try to reschedule */
1140                 status = -EL2NSYNC;
1141                 goto fail;
1142         }
1143
1144         /* need to schedule; when's the next (u)frame we could start?
1145          * this is bigger than ehci->i_thresh allows; scheduling itself
1146          * isn't free, the slop should handle reasonably slow cpus.  it
1147          * can also help high bandwidth if the dma and irq loads don't
1148          * jump until after the queue is primed.
1149          */
1150         start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1151         start %= mod;
1152         stream->next_uframe = start;
1153
1154         /* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
1155
1156         period = urb->interval;
1157         if (!stream->highspeed)
1158                 period <<= 3;
1159
1160         /* find a uframe slot with enough bandwidth */
1161         for (; start < (stream->next_uframe + period); start++) {
1162                 int             enough_space;
1163
1164                 /* check schedule: enough space? */
1165                 if (stream->highspeed)
1166                         enough_space = itd_slot_ok (ehci, mod, start,
1167                                         stream->usecs, period);
1168                 else {
1169                         if ((start % 8) >= 6)
1170                                 continue;
1171                         enough_space = sitd_slot_ok (ehci, mod, stream,
1172                                         start, sched, period);
1173                 }
1174
1175                 /* schedule it here if there's enough bandwidth */
1176                 if (enough_space) {
1177                         stream->next_uframe = start % mod;
1178                         goto ready;
1179                 }
1180         }
1181
1182         /* no room in the schedule */
1183         ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1184                 list_empty (&stream->td_list) ? "" : "re",
1185                 urb, now, max);
1186         status = -ENOSPC;
1187
1188 fail:
1189         iso_sched_free (stream, sched);
1190         urb->hcpriv = NULL;
1191         return status;
1192
1193 ready:
1194         /* report high speed start in uframes; full speed, in frames */
1195         urb->start_frame = stream->next_uframe;
1196         if (!stream->highspeed)
1197                 urb->start_frame >>= 3;
1198         return 0;
1199 }
1200
1201 /*-------------------------------------------------------------------------*/
1202
1203 static inline void
1204 itd_init (struct ehci_iso_stream *stream, struct ehci_itd *itd)
1205 {
1206         int i;
1207
1208         /* it's been recently zeroed */
1209         itd->hw_next = EHCI_LIST_END;
1210         itd->hw_bufp [0] = stream->buf0;
1211         itd->hw_bufp [1] = stream->buf1;
1212         itd->hw_bufp [2] = stream->buf2;
1213
1214         for (i = 0; i < 8; i++)
1215                 itd->index[i] = -1;
1216
1217         /* All other fields are filled when scheduling */
1218 }
1219
1220 static inline void
1221 itd_patch (
1222         struct ehci_itd         *itd,
1223         struct ehci_iso_sched   *iso_sched,
1224         unsigned                index,
1225         u16                     uframe
1226 )
1227 {
1228         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1229         unsigned                pg = itd->pg;
1230
1231         // BUG_ON (pg == 6 && uf->cross);
1232
1233         uframe &= 0x07;
1234         itd->index [uframe] = index;
1235
1236         itd->hw_transaction [uframe] = uf->transaction;
1237         itd->hw_transaction [uframe] |= cpu_to_le32 (pg << 12);
1238         itd->hw_bufp [pg] |= cpu_to_le32 (uf->bufp & ~(u32)0);
1239         itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(uf->bufp >> 32));
1240
1241         /* iso_frame_desc[].offset must be strictly increasing */
1242         if (unlikely (uf->cross)) {
1243                 u64     bufp = uf->bufp + 4096;
1244                 itd->pg = ++pg;
1245                 itd->hw_bufp [pg] |= cpu_to_le32 (bufp & ~(u32)0);
1246                 itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(bufp >> 32));
1247         }
1248 }
1249
1250 static inline void
1251 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1252 {
1253         /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1254         itd->itd_next = ehci->pshadow [frame];
1255         itd->hw_next = ehci->periodic [frame];
1256         ehci->pshadow [frame].itd = itd;
1257         itd->frame = frame;
1258         wmb ();
1259         ehci->periodic [frame] = cpu_to_le32 (itd->itd_dma) | Q_TYPE_ITD;
1260 }
1261
1262 /* fit urb's itds into the selected schedule slot; activate as needed */
1263 static int
1264 itd_link_urb (
1265         struct ehci_hcd         *ehci,
1266         struct urb              *urb,
1267         unsigned                mod,
1268         struct ehci_iso_stream  *stream
1269 )
1270 {
1271         int                     packet;
1272         unsigned                next_uframe, uframe, frame;
1273         struct ehci_iso_sched   *iso_sched = urb->hcpriv;
1274         struct ehci_itd         *itd;
1275
1276         next_uframe = stream->next_uframe % mod;
1277
1278         if (unlikely (list_empty(&stream->td_list))) {
1279                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1280                                 += stream->bandwidth;
1281                 ehci_vdbg (ehci,
1282                         "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1283                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1284                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1285                         urb->interval,
1286                         next_uframe >> 3, next_uframe & 0x7);
1287                 stream->start = jiffies;
1288         }
1289         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1290
1291         /* fill iTDs uframe by uframe */
1292         for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1293                 if (itd == NULL) {
1294                         /* ASSERT:  we have all necessary itds */
1295                         // BUG_ON (list_empty (&iso_sched->td_list));
1296
1297                         /* ASSERT:  no itds for this endpoint in this uframe */
1298
1299                         itd = list_entry (iso_sched->td_list.next,
1300                                         struct ehci_itd, itd_list);
1301                         list_move_tail (&itd->itd_list, &stream->td_list);
1302                         itd->stream = iso_stream_get (stream);
1303                         itd->urb = usb_get_urb (urb);
1304                         itd_init (stream, itd);
1305                 }
1306
1307                 uframe = next_uframe & 0x07;
1308                 frame = next_uframe >> 3;
1309
1310                 itd->usecs [uframe] = stream->usecs;
1311                 itd_patch (itd, iso_sched, packet, uframe);
1312
1313                 next_uframe += stream->interval;
1314                 stream->depth += stream->interval;
1315                 next_uframe %= mod;
1316                 packet++;
1317
1318                 /* link completed itds into the schedule */
1319                 if (((next_uframe >> 3) != frame)
1320                                 || packet == urb->number_of_packets) {
1321                         itd_link (ehci, frame % ehci->periodic_size, itd);
1322                         itd = NULL;
1323                 }
1324         }
1325         stream->next_uframe = next_uframe;
1326
1327         /* don't need that schedule data any more */
1328         iso_sched_free (stream, iso_sched);
1329         urb->hcpriv = NULL;
1330
1331         timer_action (ehci, TIMER_IO_WATCHDOG);
1332         if (unlikely (!ehci->periodic_sched++))
1333                 return enable_periodic (ehci);
1334         return 0;
1335 }
1336
1337 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1338
1339 static unsigned
1340 itd_complete (
1341         struct ehci_hcd *ehci,
1342         struct ehci_itd *itd,
1343         struct pt_regs  *regs
1344 ) {
1345         struct urb                              *urb = itd->urb;
1346         struct usb_iso_packet_descriptor        *desc;
1347         u32                                     t;
1348         unsigned                                uframe;
1349         int                                     urb_index = -1;
1350         struct ehci_iso_stream                  *stream = itd->stream;
1351         struct usb_device                       *dev;
1352
1353         /* for each uframe with a packet */
1354         for (uframe = 0; uframe < 8; uframe++) {
1355                 if (likely (itd->index[uframe] == -1))
1356                         continue;
1357                 urb_index = itd->index[uframe];
1358                 desc = &urb->iso_frame_desc [urb_index];
1359
1360                 t = le32_to_cpup (&itd->hw_transaction [uframe]);
1361                 itd->hw_transaction [uframe] = 0;
1362                 stream->depth -= stream->interval;
1363
1364                 /* report transfer status */
1365                 if (unlikely (t & ISO_ERRS)) {
1366                         urb->error_count++;
1367                         if (t & EHCI_ISOC_BUF_ERR)
1368                                 desc->status = usb_pipein (urb->pipe)
1369                                         ? -ENOSR  /* hc couldn't read */
1370                                         : -ECOMM; /* hc couldn't write */
1371                         else if (t & EHCI_ISOC_BABBLE)
1372                                 desc->status = -EOVERFLOW;
1373                         else /* (t & EHCI_ISOC_XACTERR) */
1374                                 desc->status = -EPROTO;
1375
1376                         /* HC need not update length with this error */
1377                         if (!(t & EHCI_ISOC_BABBLE))
1378                                 desc->actual_length = EHCI_ITD_LENGTH (t);
1379                 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1380                         desc->status = 0;
1381                         desc->actual_length = EHCI_ITD_LENGTH (t);
1382                 }
1383         }
1384
1385         usb_put_urb (urb);
1386         itd->urb = NULL;
1387         itd->stream = NULL;
1388         list_move (&itd->itd_list, &stream->free_list);
1389         iso_stream_put (ehci, stream);
1390
1391         /* handle completion now? */
1392         if (likely ((urb_index + 1) != urb->number_of_packets))
1393                 return 0;
1394
1395         /* ASSERT: it's really the last itd for this urb
1396         list_for_each_entry (itd, &stream->td_list, itd_list)
1397                 BUG_ON (itd->urb == urb);
1398          */
1399
1400         /* give urb back to the driver ... can be out-of-order */
1401         dev = usb_get_dev (urb->dev);
1402         ehci_urb_done (ehci, urb, regs);
1403         urb = NULL;
1404
1405         /* defer stopping schedule; completion can submit */
1406         ehci->periodic_sched--;
1407         if (unlikely (!ehci->periodic_sched))
1408                 (void) disable_periodic (ehci);
1409         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1410
1411         if (unlikely (list_empty (&stream->td_list))) {
1412                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1413                                 -= stream->bandwidth;
1414                 ehci_vdbg (ehci,
1415                         "deschedule devp %s ep%d%s-iso\n",
1416                         dev->devpath, stream->bEndpointAddress & 0x0f,
1417                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1418         }
1419         iso_stream_put (ehci, stream);
1420         usb_put_dev (dev);
1421
1422         return 1;
1423 }
1424
1425 /*-------------------------------------------------------------------------*/
1426
1427 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1428         gfp_t mem_flags)
1429 {
1430         int                     status = -EINVAL;
1431         unsigned long           flags;
1432         struct ehci_iso_stream  *stream;
1433
1434         /* Get iso_stream head */
1435         stream = iso_stream_find (ehci, urb);
1436         if (unlikely (stream == NULL)) {
1437                 ehci_dbg (ehci, "can't get iso stream\n");
1438                 return -ENOMEM;
1439         }
1440         if (unlikely (urb->interval != stream->interval)) {
1441                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1442                         stream->interval, urb->interval);
1443                 goto done;
1444         }
1445
1446 #ifdef EHCI_URB_TRACE
1447         ehci_dbg (ehci,
1448                 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1449                 __FUNCTION__, urb->dev->devpath, urb,
1450                 usb_pipeendpoint (urb->pipe),
1451                 usb_pipein (urb->pipe) ? "in" : "out",
1452                 urb->transfer_buffer_length,
1453                 urb->number_of_packets, urb->interval,
1454                 stream);
1455 #endif
1456
1457         /* allocate ITDs w/o locking anything */
1458         status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1459         if (unlikely (status < 0)) {
1460                 ehci_dbg (ehci, "can't init itds\n");
1461                 goto done;
1462         }
1463
1464         /* schedule ... need to lock */
1465         spin_lock_irqsave (&ehci->lock, flags);
1466         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1467                                &ehci_to_hcd(ehci)->flags)))
1468                 status = -ESHUTDOWN;
1469         else
1470                 status = iso_stream_schedule (ehci, urb, stream);
1471         if (likely (status == 0))
1472                 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1473         spin_unlock_irqrestore (&ehci->lock, flags);
1474
1475 done:
1476         if (unlikely (status < 0))
1477                 iso_stream_put (ehci, stream);
1478         return status;
1479 }
1480
1481 #ifdef CONFIG_USB_EHCI_SPLIT_ISO
1482
1483 /*-------------------------------------------------------------------------*/
1484
1485 /*
1486  * "Split ISO TDs" ... used for USB 1.1 devices going through the
1487  * TTs in USB 2.0 hubs.  These need microframe scheduling.
1488  */
1489
1490 static inline void
1491 sitd_sched_init (
1492         struct ehci_iso_sched   *iso_sched,
1493         struct ehci_iso_stream  *stream,
1494         struct urb              *urb
1495 )
1496 {
1497         unsigned        i;
1498         dma_addr_t      dma = urb->transfer_dma;
1499
1500         /* how many frames are needed for these transfers */
1501         iso_sched->span = urb->number_of_packets * stream->interval;
1502
1503         /* figure out per-frame sitd fields that we'll need later
1504          * when we fit new sitds into the schedule.
1505          */
1506         for (i = 0; i < urb->number_of_packets; i++) {
1507                 struct ehci_iso_packet  *packet = &iso_sched->packet [i];
1508                 unsigned                length;
1509                 dma_addr_t              buf;
1510                 u32                     trans;
1511
1512                 length = urb->iso_frame_desc [i].length & 0x03ff;
1513                 buf = dma + urb->iso_frame_desc [i].offset;
1514
1515                 trans = SITD_STS_ACTIVE;
1516                 if (((i + 1) == urb->number_of_packets)
1517                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1518                         trans |= SITD_IOC;
1519                 trans |= length << 16;
1520                 packet->transaction = cpu_to_le32 (trans);
1521
1522                 /* might need to cross a buffer page within a td */
1523                 packet->bufp = buf;
1524                 packet->buf1 = (buf + length) & ~0x0fff;
1525                 if (packet->buf1 != (buf & ~(u64)0x0fff))
1526                         packet->cross = 1;
1527
1528                 /* OUT uses multiple start-splits */
1529                 if (stream->bEndpointAddress & USB_DIR_IN)
1530                         continue;
1531                 length = (length + 187) / 188;
1532                 if (length > 1) /* BEGIN vs ALL */
1533                         length |= 1 << 3;
1534                 packet->buf1 |= length;
1535         }
1536 }
1537
1538 static int
1539 sitd_urb_transaction (
1540         struct ehci_iso_stream  *stream,
1541         struct ehci_hcd         *ehci,
1542         struct urb              *urb,
1543         gfp_t                   mem_flags
1544 )
1545 {
1546         struct ehci_sitd        *sitd;
1547         dma_addr_t              sitd_dma;
1548         int                     i;
1549         struct ehci_iso_sched   *iso_sched;
1550         unsigned long           flags;
1551
1552         iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1553         if (iso_sched == NULL)
1554                 return -ENOMEM;
1555
1556         sitd_sched_init (iso_sched, stream, urb);
1557
1558         /* allocate/init sITDs */
1559         spin_lock_irqsave (&ehci->lock, flags);
1560         for (i = 0; i < urb->number_of_packets; i++) {
1561
1562                 /* NOTE:  for now, we don't try to handle wraparound cases
1563                  * for IN (using sitd->hw_backpointer, like a FSTN), which
1564                  * means we never need two sitds for full speed packets.
1565                  */
1566
1567                 /* free_list.next might be cache-hot ... but maybe
1568                  * the HC caches it too. avoid that issue for now.
1569                  */
1570
1571                 /* prefer previously-allocated sitds */
1572                 if (!list_empty(&stream->free_list)) {
1573                         sitd = list_entry (stream->free_list.prev,
1574                                          struct ehci_sitd, sitd_list);
1575                         list_del (&sitd->sitd_list);
1576                         sitd_dma = sitd->sitd_dma;
1577                 } else
1578                         sitd = NULL;
1579
1580                 if (!sitd) {
1581                         spin_unlock_irqrestore (&ehci->lock, flags);
1582                         sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1583                                         &sitd_dma);
1584                         spin_lock_irqsave (&ehci->lock, flags);
1585                 }
1586
1587                 if (!sitd) {
1588                         iso_sched_free (stream, iso_sched);
1589                         spin_unlock_irqrestore (&ehci->lock, flags);
1590                         return -ENOMEM;
1591                 }
1592                 memset (sitd, 0, sizeof *sitd);
1593                 sitd->sitd_dma = sitd_dma;
1594                 list_add (&sitd->sitd_list, &iso_sched->td_list);
1595         }
1596
1597         /* temporarily store schedule info in hcpriv */
1598         urb->hcpriv = iso_sched;
1599         urb->error_count = 0;
1600
1601         spin_unlock_irqrestore (&ehci->lock, flags);
1602         return 0;
1603 }
1604
1605 /*-------------------------------------------------------------------------*/
1606
1607 static inline void
1608 sitd_patch (
1609         struct ehci_iso_stream  *stream,
1610         struct ehci_sitd        *sitd,
1611         struct ehci_iso_sched   *iso_sched,
1612         unsigned                index
1613 )
1614 {
1615         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1616         u64                     bufp = uf->bufp;
1617
1618         sitd->hw_next = EHCI_LIST_END;
1619         sitd->hw_fullspeed_ep = stream->address;
1620         sitd->hw_uframe = stream->splits;
1621         sitd->hw_results = uf->transaction;
1622         sitd->hw_backpointer = EHCI_LIST_END;
1623
1624         bufp = uf->bufp;
1625         sitd->hw_buf [0] = cpu_to_le32 (bufp);
1626         sitd->hw_buf_hi [0] = cpu_to_le32 (bufp >> 32);
1627
1628         sitd->hw_buf [1] = cpu_to_le32 (uf->buf1);
1629         if (uf->cross)
1630                 bufp += 4096;
1631         sitd->hw_buf_hi [1] = cpu_to_le32 (bufp >> 32);
1632         sitd->index = index;
1633 }
1634
1635 static inline void
1636 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1637 {
1638         /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1639         sitd->sitd_next = ehci->pshadow [frame];
1640         sitd->hw_next = ehci->periodic [frame];
1641         ehci->pshadow [frame].sitd = sitd;
1642         sitd->frame = frame;
1643         wmb ();
1644         ehci->periodic [frame] = cpu_to_le32 (sitd->sitd_dma) | Q_TYPE_SITD;
1645 }
1646
1647 /* fit urb's sitds into the selected schedule slot; activate as needed */
1648 static int
1649 sitd_link_urb (
1650         struct ehci_hcd         *ehci,
1651         struct urb              *urb,
1652         unsigned                mod,
1653         struct ehci_iso_stream  *stream
1654 )
1655 {
1656         int                     packet;
1657         unsigned                next_uframe;
1658         struct ehci_iso_sched   *sched = urb->hcpriv;
1659         struct ehci_sitd        *sitd;
1660
1661         next_uframe = stream->next_uframe;
1662
1663         if (list_empty(&stream->td_list)) {
1664                 /* usbfs ignores TT bandwidth */
1665                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1666                                 += stream->bandwidth;
1667                 ehci_vdbg (ehci,
1668                         "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1669                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1670                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1671                         (next_uframe >> 3) % ehci->periodic_size,
1672                         stream->interval, le32_to_cpu (stream->splits));
1673                 stream->start = jiffies;
1674         }
1675         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1676
1677         /* fill sITDs frame by frame */
1678         for (packet = 0, sitd = NULL;
1679                         packet < urb->number_of_packets;
1680                         packet++) {
1681
1682                 /* ASSERT:  we have all necessary sitds */
1683                 BUG_ON (list_empty (&sched->td_list));
1684
1685                 /* ASSERT:  no itds for this endpoint in this frame */
1686
1687                 sitd = list_entry (sched->td_list.next,
1688                                 struct ehci_sitd, sitd_list);
1689                 list_move_tail (&sitd->sitd_list, &stream->td_list);
1690                 sitd->stream = iso_stream_get (stream);
1691                 sitd->urb = usb_get_urb (urb);
1692
1693                 sitd_patch (stream, sitd, sched, packet);
1694                 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1695                                 sitd);
1696
1697                 next_uframe += stream->interval << 3;
1698                 stream->depth += stream->interval << 3;
1699         }
1700         stream->next_uframe = next_uframe % mod;
1701
1702         /* don't need that schedule data any more */
1703         iso_sched_free (stream, sched);
1704         urb->hcpriv = NULL;
1705
1706         timer_action (ehci, TIMER_IO_WATCHDOG);
1707         if (!ehci->periodic_sched++)
1708                 return enable_periodic (ehci);
1709         return 0;
1710 }
1711
1712 /*-------------------------------------------------------------------------*/
1713
1714 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
1715                                 | SITD_STS_XACT | SITD_STS_MMF)
1716
1717 static unsigned
1718 sitd_complete (
1719         struct ehci_hcd         *ehci,
1720         struct ehci_sitd        *sitd,
1721         struct pt_regs          *regs
1722 ) {
1723         struct urb                              *urb = sitd->urb;
1724         struct usb_iso_packet_descriptor        *desc;
1725         u32                                     t;
1726         int                                     urb_index = -1;
1727         struct ehci_iso_stream                  *stream = sitd->stream;
1728         struct usb_device                       *dev;
1729
1730         urb_index = sitd->index;
1731         desc = &urb->iso_frame_desc [urb_index];
1732         t = le32_to_cpup (&sitd->hw_results);
1733
1734         /* report transfer status */
1735         if (t & SITD_ERRS) {
1736                 urb->error_count++;
1737                 if (t & SITD_STS_DBE)
1738                         desc->status = usb_pipein (urb->pipe)
1739                                 ? -ENOSR  /* hc couldn't read */
1740                                 : -ECOMM; /* hc couldn't write */
1741                 else if (t & SITD_STS_BABBLE)
1742                         desc->status = -EOVERFLOW;
1743                 else /* XACT, MMF, etc */
1744                         desc->status = -EPROTO;
1745         } else {
1746                 desc->status = 0;
1747                 desc->actual_length = desc->length - SITD_LENGTH (t);
1748         }
1749
1750         usb_put_urb (urb);
1751         sitd->urb = NULL;
1752         sitd->stream = NULL;
1753         list_move (&sitd->sitd_list, &stream->free_list);
1754         stream->depth -= stream->interval << 3;
1755         iso_stream_put (ehci, stream);
1756
1757         /* handle completion now? */
1758         if ((urb_index + 1) != urb->number_of_packets)
1759                 return 0;
1760
1761         /* ASSERT: it's really the last sitd for this urb
1762         list_for_each_entry (sitd, &stream->td_list, sitd_list)
1763                 BUG_ON (sitd->urb == urb);
1764          */
1765
1766         /* give urb back to the driver */
1767         dev = usb_get_dev (urb->dev);
1768         ehci_urb_done (ehci, urb, regs);
1769         urb = NULL;
1770
1771         /* defer stopping schedule; completion can submit */
1772         ehci->periodic_sched--;
1773         if (!ehci->periodic_sched)
1774                 (void) disable_periodic (ehci);
1775         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1776
1777         if (list_empty (&stream->td_list)) {
1778                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1779                                 -= stream->bandwidth;
1780                 ehci_vdbg (ehci,
1781                         "deschedule devp %s ep%d%s-iso\n",
1782                         dev->devpath, stream->bEndpointAddress & 0x0f,
1783                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1784         }
1785         iso_stream_put (ehci, stream);
1786         usb_put_dev (dev);
1787
1788         return 1;
1789 }
1790
1791
1792 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
1793         gfp_t mem_flags)
1794 {
1795         int                     status = -EINVAL;
1796         unsigned long           flags;
1797         struct ehci_iso_stream  *stream;
1798
1799         /* Get iso_stream head */
1800         stream = iso_stream_find (ehci, urb);
1801         if (stream == NULL) {
1802                 ehci_dbg (ehci, "can't get iso stream\n");
1803                 return -ENOMEM;
1804         }
1805         if (urb->interval != stream->interval) {
1806                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1807                         stream->interval, urb->interval);
1808                 goto done;
1809         }
1810
1811 #ifdef EHCI_URB_TRACE
1812         ehci_dbg (ehci,
1813                 "submit %p dev%s ep%d%s-iso len %d\n",
1814                 urb, urb->dev->devpath,
1815                 usb_pipeendpoint (urb->pipe),
1816                 usb_pipein (urb->pipe) ? "in" : "out",
1817                 urb->transfer_buffer_length);
1818 #endif
1819
1820         /* allocate SITDs */
1821         status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
1822         if (status < 0) {
1823                 ehci_dbg (ehci, "can't init sitds\n");
1824                 goto done;
1825         }
1826
1827         /* schedule ... need to lock */
1828         spin_lock_irqsave (&ehci->lock, flags);
1829         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1830                                &ehci_to_hcd(ehci)->flags)))
1831                 status = -ESHUTDOWN;
1832         else
1833                 status = iso_stream_schedule (ehci, urb, stream);
1834         if (status == 0)
1835                 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1836         spin_unlock_irqrestore (&ehci->lock, flags);
1837
1838 done:
1839         if (status < 0)
1840                 iso_stream_put (ehci, stream);
1841         return status;
1842 }
1843
1844 #else
1845
1846 static inline int
1847 sitd_submit (struct ehci_hcd *ehci, struct urb *urb, gfp_t mem_flags)
1848 {
1849         ehci_dbg (ehci, "split iso support is disabled\n");
1850         return -ENOSYS;
1851 }
1852
1853 static inline unsigned
1854 sitd_complete (
1855         struct ehci_hcd         *ehci,
1856         struct ehci_sitd        *sitd,
1857         struct pt_regs          *regs
1858 ) {
1859         ehci_err (ehci, "sitd_complete %p?\n", sitd);
1860         return 0;
1861 }
1862
1863 #endif /* USB_EHCI_SPLIT_ISO */
1864
1865 /*-------------------------------------------------------------------------*/
1866
1867 static void
1868 scan_periodic (struct ehci_hcd *ehci, struct pt_regs *regs)
1869 {
1870         unsigned        frame, clock, now_uframe, mod;
1871         unsigned        modified;
1872
1873         mod = ehci->periodic_size << 3;
1874
1875         /*
1876          * When running, scan from last scan point up to "now"
1877          * else clean up by scanning everything that's left.
1878          * Touches as few pages as possible:  cache-friendly.
1879          */
1880         now_uframe = ehci->next_uframe;
1881         if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
1882                 clock = readl (&ehci->regs->frame_index);
1883         else
1884                 clock = now_uframe + mod - 1;
1885         clock %= mod;
1886
1887         for (;;) {
1888                 union ehci_shadow       q, *q_p;
1889                 __le32                  type, *hw_p;
1890                 unsigned                uframes;
1891
1892                 /* don't scan past the live uframe */
1893                 frame = now_uframe >> 3;
1894                 if (frame == (clock >> 3))
1895                         uframes = now_uframe & 0x07;
1896                 else {
1897                         /* safe to scan the whole frame at once */
1898                         now_uframe |= 0x07;
1899                         uframes = 8;
1900                 }
1901
1902 restart:
1903                 /* scan each element in frame's queue for completions */
1904                 q_p = &ehci->pshadow [frame];
1905                 hw_p = &ehci->periodic [frame];
1906                 q.ptr = q_p->ptr;
1907                 type = Q_NEXT_TYPE (*hw_p);
1908                 modified = 0;
1909
1910                 while (q.ptr != NULL) {
1911                         unsigned                uf;
1912                         union ehci_shadow       temp;
1913                         int                     live;
1914
1915                         live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
1916                         switch (type) {
1917                         case Q_TYPE_QH:
1918                                 /* handle any completions */
1919                                 temp.qh = qh_get (q.qh);
1920                                 type = Q_NEXT_TYPE (q.qh->hw_next);
1921                                 q = q.qh->qh_next;
1922                                 modified = qh_completions (ehci, temp.qh, regs);
1923                                 if (unlikely (list_empty (&temp.qh->qtd_list)))
1924                                         intr_deschedule (ehci, temp.qh);
1925                                 qh_put (temp.qh);
1926                                 break;
1927                         case Q_TYPE_FSTN:
1928                                 /* for "save place" FSTNs, look at QH entries
1929                                  * in the previous frame for completions.
1930                                  */
1931                                 if (q.fstn->hw_prev != EHCI_LIST_END) {
1932                                         dbg ("ignoring completions from FSTNs");
1933                                 }
1934                                 type = Q_NEXT_TYPE (q.fstn->hw_next);
1935                                 q = q.fstn->fstn_next;
1936                                 break;
1937                         case Q_TYPE_ITD:
1938                                 /* skip itds for later in the frame */
1939                                 rmb ();
1940                                 for (uf = live ? uframes : 8; uf < 8; uf++) {
1941                                         if (0 == (q.itd->hw_transaction [uf]
1942                                                         & ITD_ACTIVE))
1943                                                 continue;
1944                                         q_p = &q.itd->itd_next;
1945                                         hw_p = &q.itd->hw_next;
1946                                         type = Q_NEXT_TYPE (q.itd->hw_next);
1947                                         q = *q_p;
1948                                         break;
1949                                 }
1950                                 if (uf != 8)
1951                                         break;
1952
1953                                 /* this one's ready ... HC won't cache the
1954                                  * pointer for much longer, if at all.
1955                                  */
1956                                 *q_p = q.itd->itd_next;
1957                                 *hw_p = q.itd->hw_next;
1958                                 type = Q_NEXT_TYPE (q.itd->hw_next);
1959                                 wmb();
1960                                 modified = itd_complete (ehci, q.itd, regs);
1961                                 q = *q_p;
1962                                 break;
1963                         case Q_TYPE_SITD:
1964                                 if ((q.sitd->hw_results & SITD_ACTIVE)
1965                                                 && live) {
1966                                         q_p = &q.sitd->sitd_next;
1967                                         hw_p = &q.sitd->hw_next;
1968                                         type = Q_NEXT_TYPE (q.sitd->hw_next);
1969                                         q = *q_p;
1970                                         break;
1971                                 }
1972                                 *q_p = q.sitd->sitd_next;
1973                                 *hw_p = q.sitd->hw_next;
1974                                 type = Q_NEXT_TYPE (q.sitd->hw_next);
1975                                 wmb();
1976                                 modified = sitd_complete (ehci, q.sitd, regs);
1977                                 q = *q_p;
1978                                 break;
1979                         default:
1980                                 dbg ("corrupt type %d frame %d shadow %p",
1981                                         type, frame, q.ptr);
1982                                 // BUG ();
1983                                 q.ptr = NULL;
1984                         }
1985
1986                         /* assume completion callbacks modify the queue */
1987                         if (unlikely (modified))
1988                                 goto restart;
1989                 }
1990
1991                 /* stop when we catch up to the HC */
1992
1993                 // FIXME:  this assumes we won't get lapped when
1994                 // latencies climb; that should be rare, but...
1995                 // detect it, and just go all the way around.
1996                 // FLR might help detect this case, so long as latencies
1997                 // don't exceed periodic_size msec (default 1.024 sec).
1998
1999                 // FIXME:  likewise assumes HC doesn't halt mid-scan
2000
2001                 if (now_uframe == clock) {
2002                         unsigned        now;
2003
2004                         if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2005                                 break;
2006                         ehci->next_uframe = now_uframe;
2007                         now = readl (&ehci->regs->frame_index) % mod;
2008                         if (now_uframe == now)
2009                                 break;
2010
2011                         /* rescan the rest of this frame, then ... */
2012                         clock = now;
2013                 } else {
2014                         now_uframe++;
2015                         now_uframe %= mod;
2016                 }
2017         }
2018 }