3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
39 #ifndef _LANGUAGE_ASSEMBLY
41 #include <linux/delay.h>
42 #include <linux/types.h>
45 /* cpu pipeline flush */
46 void static inline au_sync(void)
48 __asm__ volatile ("sync");
51 void static inline au_sync_udelay(int us)
53 __asm__ volatile ("sync");
57 void static inline au_sync_delay(int ms)
59 __asm__ volatile ("sync");
63 void static inline au_writeb(u8 val, unsigned long reg)
65 *(volatile u8 *)(reg) = val;
68 void static inline au_writew(u16 val, unsigned long reg)
70 *(volatile u16 *)(reg) = val;
73 void static inline au_writel(u32 val, unsigned long reg)
75 *(volatile u32 *)(reg) = val;
78 static inline u8 au_readb(unsigned long reg)
80 return (*(volatile u8 *)reg);
83 static inline u16 au_readw(unsigned long reg)
85 return (*(volatile u16 *)reg);
88 static inline u32 au_readl(unsigned long reg)
90 return (*(volatile u32 *)reg);
94 /* arch/mips/au1000/common/clocks.c */
95 extern void set_au1x00_speed(unsigned int new_freq);
96 extern unsigned int get_au1x00_speed(void);
97 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
98 extern unsigned long get_au1x00_uart_baud_base(void);
99 extern void set_au1x00_lcd_clock(void);
100 extern unsigned int get_au1x00_lcd_clock(void);
103 * Every board describes its IRQ mapping with this table.
105 typedef struct au1xxx_irqmap {
112 * init_IRQ looks for a table with this name.
114 extern au1xxx_irq_map_t au1xxx_irq_map[];
116 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
119 /* no CP0 timer irq */
120 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
122 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
126 * SDRAM Register Offsets
128 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
129 #define MEM_SDMODE0 (0x0000)
130 #define MEM_SDMODE1 (0x0004)
131 #define MEM_SDMODE2 (0x0008)
132 #define MEM_SDADDR0 (0x000C)
133 #define MEM_SDADDR1 (0x0010)
134 #define MEM_SDADDR2 (0x0014)
135 #define MEM_SDREFCFG (0x0018)
136 #define MEM_SDPRECMD (0x001C)
137 #define MEM_SDAUTOREF (0x0020)
138 #define MEM_SDWRMD0 (0x0024)
139 #define MEM_SDWRMD1 (0x0028)
140 #define MEM_SDWRMD2 (0x002C)
141 #define MEM_SDSLEEP (0x0030)
142 #define MEM_SDSMCKE (0x0034)
145 * MEM_SDMODE register content definitions
147 #define MEM_SDMODE_F (1<<22)
148 #define MEM_SDMODE_SR (1<<21)
149 #define MEM_SDMODE_BS (1<<20)
150 #define MEM_SDMODE_RS (3<<18)
151 #define MEM_SDMODE_CS (7<<15)
152 #define MEM_SDMODE_TRAS (15<<11)
153 #define MEM_SDMODE_TMRD (3<<9)
154 #define MEM_SDMODE_TWR (3<<7)
155 #define MEM_SDMODE_TRP (3<<5)
156 #define MEM_SDMODE_TRCD (3<<3)
157 #define MEM_SDMODE_TCL (7<<0)
159 #define MEM_SDMODE_BS_2Bank (0<<20)
160 #define MEM_SDMODE_BS_4Bank (1<<20)
161 #define MEM_SDMODE_RS_11Row (0<<18)
162 #define MEM_SDMODE_RS_12Row (1<<18)
163 #define MEM_SDMODE_RS_13Row (2<<18)
164 #define MEM_SDMODE_RS_N(N) ((N)<<18)
165 #define MEM_SDMODE_CS_7Col (0<<15)
166 #define MEM_SDMODE_CS_8Col (1<<15)
167 #define MEM_SDMODE_CS_9Col (2<<15)
168 #define MEM_SDMODE_CS_10Col (3<<15)
169 #define MEM_SDMODE_CS_11Col (4<<15)
170 #define MEM_SDMODE_CS_N(N) ((N)<<15)
171 #define MEM_SDMODE_TRAS_N(N) ((N)<<11)
172 #define MEM_SDMODE_TMRD_N(N) ((N)<<9)
173 #define MEM_SDMODE_TWR_N(N) ((N)<<7)
174 #define MEM_SDMODE_TRP_N(N) ((N)<<5)
175 #define MEM_SDMODE_TRCD_N(N) ((N)<<3)
176 #define MEM_SDMODE_TCL_N(N) ((N)<<0)
179 * MEM_SDADDR register contents definitions
181 #define MEM_SDADDR_E (1<<20)
182 #define MEM_SDADDR_CSBA (0x03FF<<10)
183 #define MEM_SDADDR_CSMASK (0x03FF<<0)
184 #define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
185 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
188 * MEM_SDREFCFG register content definitions
190 #define MEM_SDREFCFG_TRC (15<<28)
191 #define MEM_SDREFCFG_TRPM (3<<26)
192 #define MEM_SDREFCFG_E (1<<25)
193 #define MEM_SDREFCFG_RE (0x1ffffff<<0)
194 #define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
195 #define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
196 #define MEM_SDREFCFG_REF_N(N) (N)
199 /***********************************************************************/
202 * Au1550 SDRAM Register Offsets
205 /***********************************************************************/
207 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
208 #define MEM_SDMODE0 (0x0800)
209 #define MEM_SDMODE1 (0x0808)
210 #define MEM_SDMODE2 (0x0810)
211 #define MEM_SDADDR0 (0x0820)
212 #define MEM_SDADDR1 (0x0828)
213 #define MEM_SDADDR2 (0x0830)
214 #define MEM_SDCONFIGA (0x0840)
215 #define MEM_SDCONFIGB (0x0848)
216 #define MEM_SDSTAT (0x0850)
217 #define MEM_SDERRADDR (0x0858)
218 #define MEM_SDSTRIDE0 (0x0860)
219 #define MEM_SDSTRIDE1 (0x0868)
220 #define MEM_SDSTRIDE2 (0x0870)
221 #define MEM_SDWRMD0 (0x0880)
222 #define MEM_SDWRMD1 (0x0888)
223 #define MEM_SDWRMD2 (0x0890)
224 #define MEM_SDPRECMD (0x08C0)
225 #define MEM_SDAUTOREF (0x08C8)
226 #define MEM_SDSREF (0x08D0)
227 #define MEM_SDSLEEP MEM_SDSREF
232 * Physical base addresses for integrated peripherals
235 #ifdef CONFIG_SOC_AU1000
236 #define MEM_PHYS_ADDR 0x14000000
237 #define STATIC_MEM_PHYS_ADDR 0x14001000
238 #define DMA0_PHYS_ADDR 0x14002000
239 #define DMA1_PHYS_ADDR 0x14002100
240 #define DMA2_PHYS_ADDR 0x14002200
241 #define DMA3_PHYS_ADDR 0x14002300
242 #define DMA4_PHYS_ADDR 0x14002400
243 #define DMA5_PHYS_ADDR 0x14002500
244 #define DMA6_PHYS_ADDR 0x14002600
245 #define DMA7_PHYS_ADDR 0x14002700
246 #define IC0_PHYS_ADDR 0x10400000
247 #define IC1_PHYS_ADDR 0x11800000
248 #define AC97_PHYS_ADDR 0x10000000
249 #define USBH_PHYS_ADDR 0x10100000
250 #define USBD_PHYS_ADDR 0x10200000
251 #define IRDA_PHYS_ADDR 0x10300000
252 #define MAC0_PHYS_ADDR 0x10500000
253 #define MAC1_PHYS_ADDR 0x10510000
254 #define MACEN_PHYS_ADDR 0x10520000
255 #define MACDMA0_PHYS_ADDR 0x14004000
256 #define MACDMA1_PHYS_ADDR 0x14004200
257 #define I2S_PHYS_ADDR 0x11000000
258 #define UART0_PHYS_ADDR 0x11100000
259 #define UART1_PHYS_ADDR 0x11200000
260 #define UART2_PHYS_ADDR 0x11300000
261 #define UART3_PHYS_ADDR 0x11400000
262 #define SSI0_PHYS_ADDR 0x11600000
263 #define SSI1_PHYS_ADDR 0x11680000
264 #define SYS_PHYS_ADDR 0x11900000
265 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
266 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
267 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
270 /********************************************************************/
272 #ifdef CONFIG_SOC_AU1500
273 #define MEM_PHYS_ADDR 0x14000000
274 #define STATIC_MEM_PHYS_ADDR 0x14001000
275 #define DMA0_PHYS_ADDR 0x14002000
276 #define DMA1_PHYS_ADDR 0x14002100
277 #define DMA2_PHYS_ADDR 0x14002200
278 #define DMA3_PHYS_ADDR 0x14002300
279 #define DMA4_PHYS_ADDR 0x14002400
280 #define DMA5_PHYS_ADDR 0x14002500
281 #define DMA6_PHYS_ADDR 0x14002600
282 #define DMA7_PHYS_ADDR 0x14002700
283 #define IC0_PHYS_ADDR 0x10400000
284 #define IC1_PHYS_ADDR 0x11800000
285 #define AC97_PHYS_ADDR 0x10000000
286 #define USBH_PHYS_ADDR 0x10100000
287 #define USBD_PHYS_ADDR 0x10200000
288 #define PCI_PHYS_ADDR 0x14005000
289 #define MAC0_PHYS_ADDR 0x11500000
290 #define MAC1_PHYS_ADDR 0x11510000
291 #define MACEN_PHYS_ADDR 0x11520000
292 #define MACDMA0_PHYS_ADDR 0x14004000
293 #define MACDMA1_PHYS_ADDR 0x14004200
294 #define I2S_PHYS_ADDR 0x11000000
295 #define UART0_PHYS_ADDR 0x11100000
296 #define UART3_PHYS_ADDR 0x11400000
297 #define GPIO2_PHYS_ADDR 0x11700000
298 #define SYS_PHYS_ADDR 0x11900000
299 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
300 #define PCI_IO_PHYS_ADDR 0x500000000ULL
301 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
302 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
303 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
304 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
305 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
308 /********************************************************************/
310 #ifdef CONFIG_SOC_AU1100
311 #define MEM_PHYS_ADDR 0x14000000
312 #define STATIC_MEM_PHYS_ADDR 0x14001000
313 #define DMA0_PHYS_ADDR 0x14002000
314 #define DMA1_PHYS_ADDR 0x14002100
315 #define DMA2_PHYS_ADDR 0x14002200
316 #define DMA3_PHYS_ADDR 0x14002300
317 #define DMA4_PHYS_ADDR 0x14002400
318 #define DMA5_PHYS_ADDR 0x14002500
319 #define DMA6_PHYS_ADDR 0x14002600
320 #define DMA7_PHYS_ADDR 0x14002700
321 #define IC0_PHYS_ADDR 0x10400000
322 #define SD0_PHYS_ADDR 0x10600000
323 #define SD1_PHYS_ADDR 0x10680000
324 #define IC1_PHYS_ADDR 0x11800000
325 #define AC97_PHYS_ADDR 0x10000000
326 #define USBH_PHYS_ADDR 0x10100000
327 #define USBD_PHYS_ADDR 0x10200000
328 #define IRDA_PHYS_ADDR 0x10300000
329 #define MAC0_PHYS_ADDR 0x10500000
330 #define MACEN_PHYS_ADDR 0x10520000
331 #define MACDMA0_PHYS_ADDR 0x14004000
332 #define MACDMA1_PHYS_ADDR 0x14004200
333 #define I2S_PHYS_ADDR 0x11000000
334 #define UART0_PHYS_ADDR 0x11100000
335 #define UART1_PHYS_ADDR 0x11200000
336 #define UART3_PHYS_ADDR 0x11400000
337 #define SSI0_PHYS_ADDR 0x11600000
338 #define SSI1_PHYS_ADDR 0x11680000
339 #define GPIO2_PHYS_ADDR 0x11700000
340 #define SYS_PHYS_ADDR 0x11900000
341 #define LCD_PHYS_ADDR 0x15000000
342 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
343 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
344 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
347 /***********************************************************************/
349 #ifdef CONFIG_SOC_AU1550
350 #define MEM_PHYS_ADDR 0x14000000
351 #define STATIC_MEM_PHYS_ADDR 0x14001000
352 #define IC0_PHYS_ADDR 0x10400000
353 #define IC1_PHYS_ADDR 0x11800000
354 #define USBH_PHYS_ADDR 0x14020000
355 #define USBD_PHYS_ADDR 0x10200000
356 #define PCI_PHYS_ADDR 0x14005000
357 #define MAC0_PHYS_ADDR 0x10500000
358 #define MAC1_PHYS_ADDR 0x10510000
359 #define MACEN_PHYS_ADDR 0x10520000
360 #define MACDMA0_PHYS_ADDR 0x14004000
361 #define MACDMA1_PHYS_ADDR 0x14004200
362 #define UART0_PHYS_ADDR 0x11100000
363 #define UART1_PHYS_ADDR 0x11200000
364 #define UART3_PHYS_ADDR 0x11400000
365 #define GPIO2_PHYS_ADDR 0x11700000
366 #define SYS_PHYS_ADDR 0x11900000
367 #define DDMA_PHYS_ADDR 0x14002000
368 #define PE_PHYS_ADDR 0x14008000
369 #define PSC0_PHYS_ADDR 0x11A00000
370 #define PSC1_PHYS_ADDR 0x11B00000
371 #define PSC2_PHYS_ADDR 0x10A00000
372 #define PSC3_PHYS_ADDR 0x10B00000
373 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
374 #define PCI_IO_PHYS_ADDR 0x500000000ULL
375 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
376 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
377 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
378 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
379 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
382 /***********************************************************************/
384 #ifdef CONFIG_SOC_AU1200
385 #define MEM_PHYS_ADDR 0x14000000
386 #define STATIC_MEM_PHYS_ADDR 0x14001000
387 #define AES_PHYS_ADDR 0x10300000
388 #define CIM_PHYS_ADDR 0x14004000
389 #define IC0_PHYS_ADDR 0x10400000
390 #define IC1_PHYS_ADDR 0x11800000
391 #define USBM_PHYS_ADDR 0x14020000
392 #define USBH_PHYS_ADDR 0x14020100
393 #define UART0_PHYS_ADDR 0x11100000
394 #define UART1_PHYS_ADDR 0x11200000
395 #define GPIO2_PHYS_ADDR 0x11700000
396 #define SYS_PHYS_ADDR 0x11900000
397 #define DDMA_PHYS_ADDR 0x14002000
398 #define PSC0_PHYS_ADDR 0x11A00000
399 #define PSC1_PHYS_ADDR 0x11B00000
400 #define SD0_PHYS_ADDR 0x10600000
401 #define SD1_PHYS_ADDR 0x10680000
402 #define LCD_PHYS_ADDR 0x15000000
403 #define SWCNT_PHYS_ADDR 0x1110010C
404 #define MAEFE_PHYS_ADDR 0x14012000
405 #define MAEBE_PHYS_ADDR 0x14010000
406 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
407 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
408 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
412 /* Static Bus Controller */
413 #define MEM_STCFG0 0xB4001000
414 #define MEM_STTIME0 0xB4001004
415 #define MEM_STADDR0 0xB4001008
417 #define MEM_STCFG1 0xB4001010
418 #define MEM_STTIME1 0xB4001014
419 #define MEM_STADDR1 0xB4001018
421 #define MEM_STCFG2 0xB4001020
422 #define MEM_STTIME2 0xB4001024
423 #define MEM_STADDR2 0xB4001028
425 #define MEM_STCFG3 0xB4001030
426 #define MEM_STTIME3 0xB4001034
427 #define MEM_STADDR3 0xB4001038
429 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
430 #define MEM_STNDCTL 0xB4001100
431 #define MEM_STSTAT 0xB4001104
433 #define MEM_STNAND_CMD (0x0)
434 #define MEM_STNAND_ADDR (0x4)
435 #define MEM_STNAND_DATA (0x20)
438 /* Interrupt Controller 0 */
439 #define IC0_CFG0RD 0xB0400040
440 #define IC0_CFG0SET 0xB0400040
441 #define IC0_CFG0CLR 0xB0400044
443 #define IC0_CFG1RD 0xB0400048
444 #define IC0_CFG1SET 0xB0400048
445 #define IC0_CFG1CLR 0xB040004C
447 #define IC0_CFG2RD 0xB0400050
448 #define IC0_CFG2SET 0xB0400050
449 #define IC0_CFG2CLR 0xB0400054
451 #define IC0_REQ0INT 0xB0400054
452 #define IC0_SRCRD 0xB0400058
453 #define IC0_SRCSET 0xB0400058
454 #define IC0_SRCCLR 0xB040005C
455 #define IC0_REQ1INT 0xB040005C
457 #define IC0_ASSIGNRD 0xB0400060
458 #define IC0_ASSIGNSET 0xB0400060
459 #define IC0_ASSIGNCLR 0xB0400064
461 #define IC0_WAKERD 0xB0400068
462 #define IC0_WAKESET 0xB0400068
463 #define IC0_WAKECLR 0xB040006C
465 #define IC0_MASKRD 0xB0400070
466 #define IC0_MASKSET 0xB0400070
467 #define IC0_MASKCLR 0xB0400074
469 #define IC0_RISINGRD 0xB0400078
470 #define IC0_RISINGCLR 0xB0400078
471 #define IC0_FALLINGRD 0xB040007C
472 #define IC0_FALLINGCLR 0xB040007C
474 #define IC0_TESTBIT 0xB0400080
476 /* Interrupt Controller 1 */
477 #define IC1_CFG0RD 0xB1800040
478 #define IC1_CFG0SET 0xB1800040
479 #define IC1_CFG0CLR 0xB1800044
481 #define IC1_CFG1RD 0xB1800048
482 #define IC1_CFG1SET 0xB1800048
483 #define IC1_CFG1CLR 0xB180004C
485 #define IC1_CFG2RD 0xB1800050
486 #define IC1_CFG2SET 0xB1800050
487 #define IC1_CFG2CLR 0xB1800054
489 #define IC1_REQ0INT 0xB1800054
490 #define IC1_SRCRD 0xB1800058
491 #define IC1_SRCSET 0xB1800058
492 #define IC1_SRCCLR 0xB180005C
493 #define IC1_REQ1INT 0xB180005C
495 #define IC1_ASSIGNRD 0xB1800060
496 #define IC1_ASSIGNSET 0xB1800060
497 #define IC1_ASSIGNCLR 0xB1800064
499 #define IC1_WAKERD 0xB1800068
500 #define IC1_WAKESET 0xB1800068
501 #define IC1_WAKECLR 0xB180006C
503 #define IC1_MASKRD 0xB1800070
504 #define IC1_MASKSET 0xB1800070
505 #define IC1_MASKCLR 0xB1800074
507 #define IC1_RISINGRD 0xB1800078
508 #define IC1_RISINGCLR 0xB1800078
509 #define IC1_FALLINGRD 0xB180007C
510 #define IC1_FALLINGCLR 0xB180007C
512 #define IC1_TESTBIT 0xB1800080
514 /* Interrupt Configuration Modes */
515 #define INTC_INT_DISABLED 0
516 #define INTC_INT_RISE_EDGE 0x1
517 #define INTC_INT_FALL_EDGE 0x2
518 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
519 #define INTC_INT_HIGH_LEVEL 0x5
520 #define INTC_INT_LOW_LEVEL 0x6
521 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
523 /* Interrupt Numbers */
525 #ifdef CONFIG_SOC_AU1000
526 #define AU1000_UART0_INT 0
527 #define AU1000_UART1_INT 1 /* au1000 */
528 #define AU1000_UART2_INT 2 /* au1000 */
529 #define AU1000_UART3_INT 3
530 #define AU1000_SSI0_INT 4 /* au1000 */
531 #define AU1000_SSI1_INT 5 /* au1000 */
532 #define AU1000_DMA_INT_BASE 6
533 #define AU1000_TOY_INT 14
534 #define AU1000_TOY_MATCH0_INT 15
535 #define AU1000_TOY_MATCH1_INT 16
536 #define AU1000_TOY_MATCH2_INT 17
537 #define AU1000_RTC_INT 18
538 #define AU1000_RTC_MATCH0_INT 19
539 #define AU1000_RTC_MATCH1_INT 20
540 #define AU1000_RTC_MATCH2_INT 21
541 #define AU1000_IRDA_TX_INT 22 /* au1000 */
542 #define AU1000_IRDA_RX_INT 23 /* au1000 */
543 #define AU1000_USB_DEV_REQ_INT 24
544 #define AU1000_USB_DEV_SUS_INT 25
545 #define AU1000_USB_HOST_INT 26
546 #define AU1000_ACSYNC_INT 27
547 #define AU1000_MAC0_DMA_INT 28
548 #define AU1000_MAC1_DMA_INT 29
549 #define AU1000_I2S_UO_INT 30 /* au1000 */
550 #define AU1000_AC97C_INT 31
551 #define AU1000_GPIO_0 32
552 #define AU1000_GPIO_1 33
553 #define AU1000_GPIO_2 34
554 #define AU1000_GPIO_3 35
555 #define AU1000_GPIO_4 36
556 #define AU1000_GPIO_5 37
557 #define AU1000_GPIO_6 38
558 #define AU1000_GPIO_7 39
559 #define AU1000_GPIO_8 40
560 #define AU1000_GPIO_9 41
561 #define AU1000_GPIO_10 42
562 #define AU1000_GPIO_11 43
563 #define AU1000_GPIO_12 44
564 #define AU1000_GPIO_13 45
565 #define AU1000_GPIO_14 46
566 #define AU1000_GPIO_15 47
567 #define AU1000_GPIO_16 48
568 #define AU1000_GPIO_17 49
569 #define AU1000_GPIO_18 50
570 #define AU1000_GPIO_19 51
571 #define AU1000_GPIO_20 52
572 #define AU1000_GPIO_21 53
573 #define AU1000_GPIO_22 54
574 #define AU1000_GPIO_23 55
575 #define AU1000_GPIO_24 56
576 #define AU1000_GPIO_25 57
577 #define AU1000_GPIO_26 58
578 #define AU1000_GPIO_27 59
579 #define AU1000_GPIO_28 60
580 #define AU1000_GPIO_29 61
581 #define AU1000_GPIO_30 62
582 #define AU1000_GPIO_31 63
584 #define UART0_ADDR 0xB1100000
585 #define UART1_ADDR 0xB1200000
586 #define UART2_ADDR 0xB1300000
587 #define UART3_ADDR 0xB1400000
589 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
590 #define USB_HOST_CONFIG 0xB017fffc
592 #define AU1000_ETH0_BASE 0xB0500000
593 #define AU1000_ETH1_BASE 0xB0510000
594 #define AU1000_MAC0_ENABLE 0xB0520000
595 #define AU1000_MAC1_ENABLE 0xB0520004
596 #define NUM_ETH_INTERFACES 2
597 #endif /* CONFIG_SOC_AU1000 */
600 #ifdef CONFIG_SOC_AU1500
601 #define AU1500_UART0_INT 0
602 #define AU1000_PCI_INTA 1 /* au1500 */
603 #define AU1000_PCI_INTB 2 /* au1500 */
604 #define AU1500_UART3_INT 3
605 #define AU1000_PCI_INTC 4 /* au1500 */
606 #define AU1000_PCI_INTD 5 /* au1500 */
607 #define AU1000_DMA_INT_BASE 6
608 #define AU1000_TOY_INT 14
609 #define AU1000_TOY_MATCH0_INT 15
610 #define AU1000_TOY_MATCH1_INT 16
611 #define AU1000_TOY_MATCH2_INT 17
612 #define AU1000_RTC_INT 18
613 #define AU1000_RTC_MATCH0_INT 19
614 #define AU1000_RTC_MATCH1_INT 20
615 #define AU1000_RTC_MATCH2_INT 21
616 #define AU1500_PCI_ERR_INT 22
617 #define AU1000_USB_DEV_REQ_INT 24
618 #define AU1000_USB_DEV_SUS_INT 25
619 #define AU1000_USB_HOST_INT 26
620 #define AU1000_ACSYNC_INT 27
621 #define AU1500_MAC0_DMA_INT 28
622 #define AU1500_MAC1_DMA_INT 29
623 #define AU1000_AC97C_INT 31
624 #define AU1000_GPIO_0 32
625 #define AU1000_GPIO_1 33
626 #define AU1000_GPIO_2 34
627 #define AU1000_GPIO_3 35
628 #define AU1000_GPIO_4 36
629 #define AU1000_GPIO_5 37
630 #define AU1000_GPIO_6 38
631 #define AU1000_GPIO_7 39
632 #define AU1000_GPIO_8 40
633 #define AU1000_GPIO_9 41
634 #define AU1000_GPIO_10 42
635 #define AU1000_GPIO_11 43
636 #define AU1000_GPIO_12 44
637 #define AU1000_GPIO_13 45
638 #define AU1000_GPIO_14 46
639 #define AU1000_GPIO_15 47
640 #define AU1500_GPIO_200 48
641 #define AU1500_GPIO_201 49
642 #define AU1500_GPIO_202 50
643 #define AU1500_GPIO_203 51
644 #define AU1500_GPIO_20 52
645 #define AU1500_GPIO_204 53
646 #define AU1500_GPIO_205 54
647 #define AU1500_GPIO_23 55
648 #define AU1500_GPIO_24 56
649 #define AU1500_GPIO_25 57
650 #define AU1500_GPIO_26 58
651 #define AU1500_GPIO_27 59
652 #define AU1500_GPIO_28 60
653 #define AU1500_GPIO_206 61
654 #define AU1500_GPIO_207 62
655 #define AU1500_GPIO_208_215 63
658 #define INTA AU1000_PCI_INTA
659 #define INTB AU1000_PCI_INTB
660 #define INTC AU1000_PCI_INTC
661 #define INTD AU1000_PCI_INTD
663 #define UART0_ADDR 0xB1100000
664 #define UART3_ADDR 0xB1400000
666 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
667 #define USB_HOST_CONFIG 0xB017fffc
669 #define AU1500_ETH0_BASE 0xB1500000
670 #define AU1500_ETH1_BASE 0xB1510000
671 #define AU1500_MAC0_ENABLE 0xB1520000
672 #define AU1500_MAC1_ENABLE 0xB1520004
673 #define NUM_ETH_INTERFACES 2
674 #endif /* CONFIG_SOC_AU1500 */
677 #ifdef CONFIG_SOC_AU1100
678 #define AU1100_UART0_INT 0
679 #define AU1100_UART1_INT 1
680 #define AU1100_SD_INT 2
681 #define AU1100_UART3_INT 3
682 #define AU1000_SSI0_INT 4
683 #define AU1000_SSI1_INT 5
684 #define AU1000_DMA_INT_BASE 6
685 #define AU1000_TOY_INT 14
686 #define AU1000_TOY_MATCH0_INT 15
687 #define AU1000_TOY_MATCH1_INT 16
688 #define AU1000_TOY_MATCH2_INT 17
689 #define AU1000_RTC_INT 18
690 #define AU1000_RTC_MATCH0_INT 19
691 #define AU1000_RTC_MATCH1_INT 20
692 #define AU1000_RTC_MATCH2_INT 21
693 #define AU1000_IRDA_TX_INT 22
694 #define AU1000_IRDA_RX_INT 23
695 #define AU1000_USB_DEV_REQ_INT 24
696 #define AU1000_USB_DEV_SUS_INT 25
697 #define AU1000_USB_HOST_INT 26
698 #define AU1000_ACSYNC_INT 27
699 #define AU1100_MAC0_DMA_INT 28
700 #define AU1100_GPIO_208_215 29
701 #define AU1100_LCD_INT 30
702 #define AU1000_AC97C_INT 31
703 #define AU1000_GPIO_0 32
704 #define AU1000_GPIO_1 33
705 #define AU1000_GPIO_2 34
706 #define AU1000_GPIO_3 35
707 #define AU1000_GPIO_4 36
708 #define AU1000_GPIO_5 37
709 #define AU1000_GPIO_6 38
710 #define AU1000_GPIO_7 39
711 #define AU1000_GPIO_8 40
712 #define AU1000_GPIO_9 41
713 #define AU1000_GPIO_10 42
714 #define AU1000_GPIO_11 43
715 #define AU1000_GPIO_12 44
716 #define AU1000_GPIO_13 45
717 #define AU1000_GPIO_14 46
718 #define AU1000_GPIO_15 47
719 #define AU1000_GPIO_16 48
720 #define AU1000_GPIO_17 49
721 #define AU1000_GPIO_18 50
722 #define AU1000_GPIO_19 51
723 #define AU1000_GPIO_20 52
724 #define AU1000_GPIO_21 53
725 #define AU1000_GPIO_22 54
726 #define AU1000_GPIO_23 55
727 #define AU1000_GPIO_24 56
728 #define AU1000_GPIO_25 57
729 #define AU1000_GPIO_26 58
730 #define AU1000_GPIO_27 59
731 #define AU1000_GPIO_28 60
732 #define AU1000_GPIO_29 61
733 #define AU1000_GPIO_30 62
734 #define AU1000_GPIO_31 63
736 #define UART0_ADDR 0xB1100000
737 #define UART1_ADDR 0xB1200000
738 #define UART3_ADDR 0xB1400000
740 #define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
741 #define USB_HOST_CONFIG 0xB017fffc
743 #define AU1100_ETH0_BASE 0xB0500000
744 #define AU1100_MAC0_ENABLE 0xB0520000
745 #define NUM_ETH_INTERFACES 1
746 #endif /* CONFIG_SOC_AU1100 */
748 #ifdef CONFIG_SOC_AU1550
749 #define AU1550_UART0_INT 0
750 #define AU1550_PCI_INTA 1
751 #define AU1550_PCI_INTB 2
752 #define AU1550_DDMA_INT 3
753 #define AU1550_CRYPTO_INT 4
754 #define AU1550_PCI_INTC 5
755 #define AU1550_PCI_INTD 6
756 #define AU1550_PCI_RST_INT 7
757 #define AU1550_UART1_INT 8
758 #define AU1550_UART3_INT 9
759 #define AU1550_PSC0_INT 10
760 #define AU1550_PSC1_INT 11
761 #define AU1550_PSC2_INT 12
762 #define AU1550_PSC3_INT 13
763 #define AU1000_TOY_INT 14
764 #define AU1000_TOY_MATCH0_INT 15
765 #define AU1000_TOY_MATCH1_INT 16
766 #define AU1000_TOY_MATCH2_INT 17
767 #define AU1000_RTC_INT 18
768 #define AU1000_RTC_MATCH0_INT 19
769 #define AU1000_RTC_MATCH1_INT 20
770 #define AU1000_RTC_MATCH2_INT 21
771 #define AU1550_NAND_INT 23
772 #define AU1550_USB_DEV_REQ_INT 24
773 #define AU1550_USB_DEV_SUS_INT 25
774 #define AU1550_USB_HOST_INT 26
775 #define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT
776 #define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT
777 #define AU1000_USB_HOST_INT AU1550_USB_HOST_INT
778 #define AU1550_MAC0_DMA_INT 27
779 #define AU1550_MAC1_DMA_INT 28
780 #define AU1000_GPIO_0 32
781 #define AU1000_GPIO_1 33
782 #define AU1000_GPIO_2 34
783 #define AU1000_GPIO_3 35
784 #define AU1000_GPIO_4 36
785 #define AU1000_GPIO_5 37
786 #define AU1000_GPIO_6 38
787 #define AU1000_GPIO_7 39
788 #define AU1000_GPIO_8 40
789 #define AU1000_GPIO_9 41
790 #define AU1000_GPIO_10 42
791 #define AU1000_GPIO_11 43
792 #define AU1000_GPIO_12 44
793 #define AU1000_GPIO_13 45
794 #define AU1000_GPIO_14 46
795 #define AU1000_GPIO_15 47
796 #define AU1550_GPIO_200 48
797 #define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205
798 #define AU1500_GPIO_16 50
799 #define AU1500_GPIO_17 51
800 #define AU1500_GPIO_20 52
801 #define AU1500_GPIO_21 53
802 #define AU1500_GPIO_22 54
803 #define AU1500_GPIO_23 55
804 #define AU1500_GPIO_24 56
805 #define AU1500_GPIO_25 57
806 #define AU1500_GPIO_26 58
807 #define AU1500_GPIO_27 59
808 #define AU1500_GPIO_28 60
809 #define AU1500_GPIO_206 61
810 #define AU1500_GPIO_207 62
811 #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
814 #define INTA AU1550_PCI_INTA
815 #define INTB AU1550_PCI_INTB
816 #define INTC AU1550_PCI_INTC
817 #define INTD AU1550_PCI_INTD
819 #define UART0_ADDR 0xB1100000
820 #define UART1_ADDR 0xB1200000
821 #define UART3_ADDR 0xB1400000
823 #define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
824 #define USB_OHCI_LEN 0x00060000
825 #define USB_HOST_CONFIG 0xB4027ffc
827 #define AU1550_ETH0_BASE 0xB0500000
828 #define AU1550_ETH1_BASE 0xB0510000
829 #define AU1550_MAC0_ENABLE 0xB0520000
830 #define AU1550_MAC1_ENABLE 0xB0520004
831 #define NUM_ETH_INTERFACES 2
832 #endif /* CONFIG_SOC_AU1550 */
834 #ifdef CONFIG_SOC_AU1200
835 #define AU1200_UART0_INT 0
836 #define AU1200_SWT_INT 1
837 #define AU1200_SD_INT 2
838 #define AU1200_DDMA_INT 3
839 #define AU1200_MAE_BE_INT 4
840 #define AU1200_GPIO_200 5
841 #define AU1200_GPIO_201 6
842 #define AU1200_GPIO_202 7
843 #define AU1200_UART1_INT 8
844 #define AU1200_MAE_FE_INT 9
845 #define AU1200_PSC0_INT 10
846 #define AU1200_PSC1_INT 11
847 #define AU1200_AES_INT 12
848 #define AU1200_CAMERA_INT 13
849 #define AU1000_TOY_INT 14
850 #define AU1000_TOY_MATCH0_INT 15
851 #define AU1000_TOY_MATCH1_INT 16
852 #define AU1000_TOY_MATCH2_INT 17
853 #define AU1000_RTC_INT 18
854 #define AU1000_RTC_MATCH0_INT 19
855 #define AU1000_RTC_MATCH1_INT 20
856 #define AU1000_RTC_MATCH2_INT 21
857 #define AU1200_NAND_INT 23
858 #define AU1200_GPIO_204 24
859 #define AU1200_GPIO_205 25
860 #define AU1200_GPIO_206 26
861 #define AU1200_GPIO_207 27
862 #define AU1200_GPIO_208_215 28 // Logical OR of 208:215
863 #define AU1200_USB_INT 29
864 #define AU1000_USB_HOST_INT AU1200_USB_INT
865 #define AU1200_LCD_INT 30
866 #define AU1200_MAE_BOTH_INT 31
867 #define AU1000_GPIO_0 32
868 #define AU1000_GPIO_1 33
869 #define AU1000_GPIO_2 34
870 #define AU1000_GPIO_3 35
871 #define AU1000_GPIO_4 36
872 #define AU1000_GPIO_5 37
873 #define AU1000_GPIO_6 38
874 #define AU1000_GPIO_7 39
875 #define AU1000_GPIO_8 40
876 #define AU1000_GPIO_9 41
877 #define AU1000_GPIO_10 42
878 #define AU1000_GPIO_11 43
879 #define AU1000_GPIO_12 44
880 #define AU1000_GPIO_13 45
881 #define AU1000_GPIO_14 46
882 #define AU1000_GPIO_15 47
883 #define AU1000_GPIO_16 48
884 #define AU1000_GPIO_17 49
885 #define AU1000_GPIO_18 50
886 #define AU1000_GPIO_19 51
887 #define AU1000_GPIO_20 52
888 #define AU1000_GPIO_21 53
889 #define AU1000_GPIO_22 54
890 #define AU1000_GPIO_23 55
891 #define AU1000_GPIO_24 56
892 #define AU1000_GPIO_25 57
893 #define AU1000_GPIO_26 58
894 #define AU1000_GPIO_27 59
895 #define AU1000_GPIO_28 60
896 #define AU1000_GPIO_29 61
897 #define AU1000_GPIO_30 62
898 #define AU1000_GPIO_31 63
900 #define UART0_ADDR 0xB1100000
901 #define UART1_ADDR 0xB1200000
903 #define USB_UOC_BASE 0x14020020
904 #define USB_UOC_LEN 0x20
905 #define USB_OHCI_BASE 0x14020100
906 #define USB_OHCI_LEN 0x100
907 #define USB_EHCI_BASE 0x14020200
908 #define USB_EHCI_LEN 0x100
909 #define USB_UDC_BASE 0x14022000
910 #define USB_UDC_LEN 0x2000
911 #define USB_MSR_BASE 0xB4020000
912 #define USB_MSR_MCFG 4
913 #define USBMSRMCFG_OMEMEN 0
914 #define USBMSRMCFG_OBMEN 1
915 #define USBMSRMCFG_EMEMEN 2
916 #define USBMSRMCFG_EBMEN 3
917 #define USBMSRMCFG_DMEMEN 4
918 #define USBMSRMCFG_DBMEN 5
919 #define USBMSRMCFG_GMEMEN 6
920 #define USBMSRMCFG_OHCCLKEN 16
921 #define USBMSRMCFG_EHCCLKEN 17
922 #define USBMSRMCFG_UDCCLKEN 18
923 #define USBMSRMCFG_PHYPLLEN 19
924 #define USBMSRMCFG_RDCOMB 30
925 #define USBMSRMCFG_PFEN 31
927 #endif /* CONFIG_SOC_AU1200 */
929 #define AU1000_LAST_INTC0_INT 31
930 #define AU1000_LAST_INTC1_INT 63
931 #define AU1000_MAX_INTR 63
932 #define INTX 0xFF /* not valid */
934 /* Programmable Counters 0 and 1 */
935 #define SYS_BASE 0xB1900000
936 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
937 # define SYS_CNTRL_E1S (1<<23)
938 # define SYS_CNTRL_T1S (1<<20)
939 # define SYS_CNTRL_M21 (1<<19)
940 # define SYS_CNTRL_M11 (1<<18)
941 # define SYS_CNTRL_M01 (1<<17)
942 # define SYS_CNTRL_C1S (1<<16)
943 # define SYS_CNTRL_BP (1<<14)
944 # define SYS_CNTRL_EN1 (1<<13)
945 # define SYS_CNTRL_BT1 (1<<12)
946 # define SYS_CNTRL_EN0 (1<<11)
947 # define SYS_CNTRL_BT0 (1<<10)
948 # define SYS_CNTRL_E0 (1<<8)
949 # define SYS_CNTRL_E0S (1<<7)
950 # define SYS_CNTRL_32S (1<<5)
951 # define SYS_CNTRL_T0S (1<<4)
952 # define SYS_CNTRL_M20 (1<<3)
953 # define SYS_CNTRL_M10 (1<<2)
954 # define SYS_CNTRL_M00 (1<<1)
955 # define SYS_CNTRL_C0S (1<<0)
957 /* Programmable Counter 0 Registers */
958 #define SYS_TOYTRIM (SYS_BASE + 0)
959 #define SYS_TOYWRITE (SYS_BASE + 4)
960 #define SYS_TOYMATCH0 (SYS_BASE + 8)
961 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
962 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
963 #define SYS_TOYREAD (SYS_BASE + 0x40)
965 /* Programmable Counter 1 Registers */
966 #define SYS_RTCTRIM (SYS_BASE + 0x44)
967 #define SYS_RTCWRITE (SYS_BASE + 0x48)
968 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
969 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
970 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
971 #define SYS_RTCREAD (SYS_BASE + 0x58)
974 #define I2S_DATA 0xB1000000
975 # define I2S_DATA_MASK (0xffffff)
976 #define I2S_CONFIG 0xB1000004
977 # define I2S_CONFIG_XU (1<<25)
978 # define I2S_CONFIG_XO (1<<24)
979 # define I2S_CONFIG_RU (1<<23)
980 # define I2S_CONFIG_RO (1<<22)
981 # define I2S_CONFIG_TR (1<<21)
982 # define I2S_CONFIG_TE (1<<20)
983 # define I2S_CONFIG_TF (1<<19)
984 # define I2S_CONFIG_RR (1<<18)
985 # define I2S_CONFIG_RE (1<<17)
986 # define I2S_CONFIG_RF (1<<16)
987 # define I2S_CONFIG_PD (1<<11)
988 # define I2S_CONFIG_LB (1<<10)
989 # define I2S_CONFIG_IC (1<<9)
990 # define I2S_CONFIG_FM_BIT 7
991 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
992 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
993 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
994 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
995 # define I2S_CONFIG_TN (1<<6)
996 # define I2S_CONFIG_RN (1<<5)
997 # define I2S_CONFIG_SZ_BIT 0
998 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1000 #define I2S_CONTROL 0xB1000008
1001 # define I2S_CONTROL_D (1<<1)
1002 # define I2S_CONTROL_CE (1<<0)
1004 /* USB Host Controller */
1005 #ifndef USB_OHCI_LEN
1006 #define USB_OHCI_LEN 0x00100000
1009 #ifndef CONFIG_SOC_AU1200
1011 /* USB Device Controller */
1012 #define USBD_EP0RD 0xB0200000
1013 #define USBD_EP0WR 0xB0200004
1014 #define USBD_EP2WR 0xB0200008
1015 #define USBD_EP3WR 0xB020000C
1016 #define USBD_EP4RD 0xB0200010
1017 #define USBD_EP5RD 0xB0200014
1018 #define USBD_INTEN 0xB0200018
1019 #define USBD_INTSTAT 0xB020001C
1020 # define USBDEV_INT_SOF (1<<12)
1021 # define USBDEV_INT_HF_BIT 6
1022 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1023 # define USBDEV_INT_CMPLT_BIT 0
1024 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1025 #define USBD_CONFIG 0xB0200020
1026 #define USBD_EP0CS 0xB0200024
1027 #define USBD_EP2CS 0xB0200028
1028 #define USBD_EP3CS 0xB020002C
1029 #define USBD_EP4CS 0xB0200030
1030 #define USBD_EP5CS 0xB0200034
1031 # define USBDEV_CS_SU (1<<14)
1032 # define USBDEV_CS_NAK (1<<13)
1033 # define USBDEV_CS_ACK (1<<12)
1034 # define USBDEV_CS_BUSY (1<<11)
1035 # define USBDEV_CS_TSIZE_BIT 1
1036 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1037 # define USBDEV_CS_STALL (1<<0)
1038 #define USBD_EP0RDSTAT 0xB0200040
1039 #define USBD_EP0WRSTAT 0xB0200044
1040 #define USBD_EP2WRSTAT 0xB0200048
1041 #define USBD_EP3WRSTAT 0xB020004C
1042 #define USBD_EP4RDSTAT 0xB0200050
1043 #define USBD_EP5RDSTAT 0xB0200054
1044 # define USBDEV_FSTAT_FLUSH (1<<6)
1045 # define USBDEV_FSTAT_UF (1<<5)
1046 # define USBDEV_FSTAT_OF (1<<4)
1047 # define USBDEV_FSTAT_FCNT_BIT 0
1048 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1049 #define USBD_ENABLE 0xB0200058
1050 # define USBDEV_ENABLE (1<<1)
1051 # define USBDEV_CE (1<<0)
1053 #endif /* !CONFIG_SOC_AU1200 */
1055 /* Ethernet Controllers */
1057 /* 4 byte offsets from AU1000_ETH_BASE */
1058 #define MAC_CONTROL 0x0
1059 # define MAC_RX_ENABLE (1<<2)
1060 # define MAC_TX_ENABLE (1<<3)
1061 # define MAC_DEF_CHECK (1<<5)
1062 # define MAC_SET_BL(X) (((X)&0x3)<<6)
1063 # define MAC_AUTO_PAD (1<<8)
1064 # define MAC_DISABLE_RETRY (1<<10)
1065 # define MAC_DISABLE_BCAST (1<<11)
1066 # define MAC_LATE_COL (1<<12)
1067 # define MAC_HASH_MODE (1<<13)
1068 # define MAC_HASH_ONLY (1<<15)
1069 # define MAC_PASS_ALL (1<<16)
1070 # define MAC_INVERSE_FILTER (1<<17)
1071 # define MAC_PROMISCUOUS (1<<18)
1072 # define MAC_PASS_ALL_MULTI (1<<19)
1073 # define MAC_FULL_DUPLEX (1<<20)
1074 # define MAC_NORMAL_MODE 0
1075 # define MAC_INT_LOOPBACK (1<<21)
1076 # define MAC_EXT_LOOPBACK (1<<22)
1077 # define MAC_DISABLE_RX_OWN (1<<23)
1078 # define MAC_BIG_ENDIAN (1<<30)
1079 # define MAC_RX_ALL (1<<31)
1080 #define MAC_ADDRESS_HIGH 0x4
1081 #define MAC_ADDRESS_LOW 0x8
1082 #define MAC_MCAST_HIGH 0xC
1083 #define MAC_MCAST_LOW 0x10
1084 #define MAC_MII_CNTRL 0x14
1085 # define MAC_MII_BUSY (1<<0)
1086 # define MAC_MII_READ 0
1087 # define MAC_MII_WRITE (1<<1)
1088 # define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
1089 # define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
1090 #define MAC_MII_DATA 0x18
1091 #define MAC_FLOW_CNTRL 0x1C
1092 # define MAC_FLOW_CNTRL_BUSY (1<<0)
1093 # define MAC_FLOW_CNTRL_ENABLE (1<<1)
1094 # define MAC_PASS_CONTROL (1<<2)
1095 # define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
1096 #define MAC_VLAN1_TAG 0x20
1097 #define MAC_VLAN2_TAG 0x24
1099 /* Ethernet Controller Enable */
1101 # define MAC_EN_CLOCK_ENABLE (1<<0)
1102 # define MAC_EN_RESET0 (1<<1)
1103 # define MAC_EN_TOSS (0<<2)
1104 # define MAC_EN_CACHEABLE (1<<3)
1105 # define MAC_EN_RESET1 (1<<4)
1106 # define MAC_EN_RESET2 (1<<5)
1107 # define MAC_DMA_RESET (1<<6)
1109 /* Ethernet Controller DMA Channels */
1111 #define MAC0_TX_DMA_ADDR 0xB4004000
1112 #define MAC1_TX_DMA_ADDR 0xB4004200
1113 /* offsets from MAC_TX_RING_ADDR address */
1114 #define MAC_TX_BUFF0_STATUS 0x0
1115 # define TX_FRAME_ABORTED (1<<0)
1116 # define TX_JAB_TIMEOUT (1<<1)
1117 # define TX_NO_CARRIER (1<<2)
1118 # define TX_LOSS_CARRIER (1<<3)
1119 # define TX_EXC_DEF (1<<4)
1120 # define TX_LATE_COLL_ABORT (1<<5)
1121 # define TX_EXC_COLL (1<<6)
1122 # define TX_UNDERRUN (1<<7)
1123 # define TX_DEFERRED (1<<8)
1124 # define TX_LATE_COLL (1<<9)
1125 # define TX_COLL_CNT_MASK (0xF<<10)
1126 # define TX_PKT_RETRY (1<<31)
1127 #define MAC_TX_BUFF0_ADDR 0x4
1128 # define TX_DMA_ENABLE (1<<0)
1129 # define TX_T_DONE (1<<1)
1130 # define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1131 #define MAC_TX_BUFF0_LEN 0x8
1132 #define MAC_TX_BUFF1_STATUS 0x10
1133 #define MAC_TX_BUFF1_ADDR 0x14
1134 #define MAC_TX_BUFF1_LEN 0x18
1135 #define MAC_TX_BUFF2_STATUS 0x20
1136 #define MAC_TX_BUFF2_ADDR 0x24
1137 #define MAC_TX_BUFF2_LEN 0x28
1138 #define MAC_TX_BUFF3_STATUS 0x30
1139 #define MAC_TX_BUFF3_ADDR 0x34
1140 #define MAC_TX_BUFF3_LEN 0x38
1142 #define MAC0_RX_DMA_ADDR 0xB4004100
1143 #define MAC1_RX_DMA_ADDR 0xB4004300
1144 /* offsets from MAC_RX_RING_ADDR */
1145 #define MAC_RX_BUFF0_STATUS 0x0
1146 # define RX_FRAME_LEN_MASK 0x3fff
1147 # define RX_WDOG_TIMER (1<<14)
1148 # define RX_RUNT (1<<15)
1149 # define RX_OVERLEN (1<<16)
1150 # define RX_COLL (1<<17)
1151 # define RX_ETHER (1<<18)
1152 # define RX_MII_ERROR (1<<19)
1153 # define RX_DRIBBLING (1<<20)
1154 # define RX_CRC_ERROR (1<<21)
1155 # define RX_VLAN1 (1<<22)
1156 # define RX_VLAN2 (1<<23)
1157 # define RX_LEN_ERROR (1<<24)
1158 # define RX_CNTRL_FRAME (1<<25)
1159 # define RX_U_CNTRL_FRAME (1<<26)
1160 # define RX_MCAST_FRAME (1<<27)
1161 # define RX_BCAST_FRAME (1<<28)
1162 # define RX_FILTER_FAIL (1<<29)
1163 # define RX_PACKET_FILTER (1<<30)
1164 # define RX_MISSED_FRAME (1<<31)
1166 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1167 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1168 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1169 #define MAC_RX_BUFF0_ADDR 0x4
1170 # define RX_DMA_ENABLE (1<<0)
1171 # define RX_T_DONE (1<<1)
1172 # define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1173 # define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
1174 #define MAC_RX_BUFF1_STATUS 0x10
1175 #define MAC_RX_BUFF1_ADDR 0x14
1176 #define MAC_RX_BUFF2_STATUS 0x20
1177 #define MAC_RX_BUFF2_ADDR 0x24
1178 #define MAC_RX_BUFF3_STATUS 0x30
1179 #define MAC_RX_BUFF3_ADDR 0x34
1183 #define UART_BASE UART0_ADDR
1184 #ifdef CONFIG_SOC_AU1200
1185 #define UART_DEBUG_BASE UART1_ADDR
1187 #define UART_DEBUG_BASE UART3_ADDR
1190 #define UART_RX 0 /* Receive buffer */
1191 #define UART_TX 4 /* Transmit buffer */
1192 #define UART_IER 8 /* Interrupt Enable Register */
1193 #define UART_IIR 0xC /* Interrupt ID Register */
1194 #define UART_FCR 0x10 /* FIFO Control Register */
1195 #define UART_LCR 0x14 /* Line Control Register */
1196 #define UART_MCR 0x18 /* Modem Control Register */
1197 #define UART_LSR 0x1C /* Line Status Register */
1198 #define UART_MSR 0x20 /* Modem Status Register */
1199 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1200 #define UART_MOD_CNTRL 0x100 /* Module Control */
1202 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1203 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1204 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1205 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1206 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1207 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1208 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1209 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1210 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1211 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1212 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1213 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1214 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1217 * These are the definitions for the Line Control Register
1219 #define UART_LCR_SBC 0x40 /* Set break control */
1220 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1221 #define UART_LCR_EPAR 0x10 /* Even parity select */
1222 #define UART_LCR_PARITY 0x08 /* Parity Enable */
1223 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1224 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1225 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1226 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1227 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1230 * These are the definitions for the Line Status Register
1232 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1233 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1234 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1235 #define UART_LSR_FE 0x08 /* Frame error indicator */
1236 #define UART_LSR_PE 0x04 /* Parity error indicator */
1237 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1238 #define UART_LSR_DR 0x01 /* Receiver data ready */
1241 * These are the definitions for the Interrupt Identification Register
1243 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1244 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1245 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1246 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1247 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1248 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1251 * These are the definitions for the Interrupt Enable Register
1253 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1254 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1255 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1256 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1259 * These are the definitions for the Modem Control Register
1261 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1262 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1263 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1264 #define UART_MCR_RTS 0x02 /* RTS complement */
1265 #define UART_MCR_DTR 0x01 /* DTR complement */
1268 * These are the definitions for the Modem Status Register
1270 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1271 #define UART_MSR_RI 0x40 /* Ring Indicator */
1272 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1273 #define UART_MSR_CTS 0x10 /* Clear to Send */
1274 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1275 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1276 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1277 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1278 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1283 #define SSI0_STATUS 0xB1600000
1284 # define SSI_STATUS_BF (1<<4)
1285 # define SSI_STATUS_OF (1<<3)
1286 # define SSI_STATUS_UF (1<<2)
1287 # define SSI_STATUS_D (1<<1)
1288 # define SSI_STATUS_B (1<<0)
1289 #define SSI0_INT 0xB1600004
1290 # define SSI_INT_OI (1<<3)
1291 # define SSI_INT_UI (1<<2)
1292 # define SSI_INT_DI (1<<1)
1293 #define SSI0_INT_ENABLE 0xB1600008
1294 # define SSI_INTE_OIE (1<<3)
1295 # define SSI_INTE_UIE (1<<2)
1296 # define SSI_INTE_DIE (1<<1)
1297 #define SSI0_CONFIG 0xB1600020
1298 # define SSI_CONFIG_AO (1<<24)
1299 # define SSI_CONFIG_DO (1<<23)
1300 # define SSI_CONFIG_ALEN_BIT 20
1301 # define SSI_CONFIG_ALEN_MASK (0x7<<20)
1302 # define SSI_CONFIG_DLEN_BIT 16
1303 # define SSI_CONFIG_DLEN_MASK (0x7<<16)
1304 # define SSI_CONFIG_DD (1<<11)
1305 # define SSI_CONFIG_AD (1<<10)
1306 # define SSI_CONFIG_BM_BIT 8
1307 # define SSI_CONFIG_BM_MASK (0x3<<8)
1308 # define SSI_CONFIG_CE (1<<7)
1309 # define SSI_CONFIG_DP (1<<6)
1310 # define SSI_CONFIG_DL (1<<5)
1311 # define SSI_CONFIG_EP (1<<4)
1312 #define SSI0_ADATA 0xB1600024
1313 # define SSI_AD_D (1<<24)
1314 # define SSI_AD_ADDR_BIT 16
1315 # define SSI_AD_ADDR_MASK (0xff<<16)
1316 # define SSI_AD_DATA_BIT 0
1317 # define SSI_AD_DATA_MASK (0xfff<<0)
1318 #define SSI0_CLKDIV 0xB1600028
1319 #define SSI0_CONTROL 0xB1600100
1320 # define SSI_CONTROL_CD (1<<1)
1321 # define SSI_CONTROL_E (1<<0)
1324 #define SSI1_STATUS 0xB1680000
1325 #define SSI1_INT 0xB1680004
1326 #define SSI1_INT_ENABLE 0xB1680008
1327 #define SSI1_CONFIG 0xB1680020
1328 #define SSI1_ADATA 0xB1680024
1329 #define SSI1_CLKDIV 0xB1680028
1330 #define SSI1_ENABLE 0xB1680100
1333 * Register content definitions
1335 #define SSI_STATUS_BF (1<<4)
1336 #define SSI_STATUS_OF (1<<3)
1337 #define SSI_STATUS_UF (1<<2)
1338 #define SSI_STATUS_D (1<<1)
1339 #define SSI_STATUS_B (1<<0)
1342 #define SSI_INT_OI (1<<3)
1343 #define SSI_INT_UI (1<<2)
1344 #define SSI_INT_DI (1<<1)
1347 #define SSI_INTEN_OIE (1<<3)
1348 #define SSI_INTEN_UIE (1<<2)
1349 #define SSI_INTEN_DIE (1<<1)
1351 #define SSI_CONFIG_AO (1<<24)
1352 #define SSI_CONFIG_DO (1<<23)
1353 #define SSI_CONFIG_ALEN (7<<20)
1354 #define SSI_CONFIG_DLEN (15<<16)
1355 #define SSI_CONFIG_DD (1<<11)
1356 #define SSI_CONFIG_AD (1<<10)
1357 #define SSI_CONFIG_BM (3<<8)
1358 #define SSI_CONFIG_CE (1<<7)
1359 #define SSI_CONFIG_DP (1<<6)
1360 #define SSI_CONFIG_DL (1<<5)
1361 #define SSI_CONFIG_EP (1<<4)
1362 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
1363 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
1364 #define SSI_CONFIG_BM_HI (0<<8)
1365 #define SSI_CONFIG_BM_LO (1<<8)
1366 #define SSI_CONFIG_BM_CY (2<<8)
1368 #define SSI_ADATA_D (1<<24)
1369 #define SSI_ADATA_ADDR (0xFF<<16)
1370 #define SSI_ADATA_DATA (0x0FFF)
1371 #define SSI_ADATA_ADDR_N(N) (N<<16)
1373 #define SSI_ENABLE_CD (1<<1)
1374 #define SSI_ENABLE_E (1<<0)
1377 /* IrDA Controller */
1378 #define IRDA_BASE 0xB0300000
1379 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
1380 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
1381 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
1382 #define IR_RING_SIZE (IRDA_BASE+0x0C)
1383 #define IR_RING_PROMPT (IRDA_BASE+0x10)
1384 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1385 #define IR_INT_CLEAR (IRDA_BASE+0x18)
1386 #define IR_CONFIG_1 (IRDA_BASE+0x20)
1387 # define IR_RX_INVERT_LED (1<<0)
1388 # define IR_TX_INVERT_LED (1<<1)
1389 # define IR_ST (1<<2)
1390 # define IR_SF (1<<3)
1391 # define IR_SIR (1<<4)
1392 # define IR_MIR (1<<5)
1393 # define IR_FIR (1<<6)
1394 # define IR_16CRC (1<<7)
1395 # define IR_TD (1<<8)
1396 # define IR_RX_ALL (1<<9)
1397 # define IR_DMA_ENABLE (1<<10)
1398 # define IR_RX_ENABLE (1<<11)
1399 # define IR_TX_ENABLE (1<<12)
1400 # define IR_LOOPBACK (1<<14)
1401 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1402 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1403 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
1404 #define IR_ENABLE (IRDA_BASE+0x28)
1405 # define IR_RX_STATUS (1<<9)
1406 # define IR_TX_STATUS (1<<10)
1407 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1408 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1409 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1410 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1411 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
1412 # define IR_MODE_INV (1<<0)
1413 # define IR_ONE_PIN (1<<1)
1414 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1417 #define SYS_PINFUNC 0xB190002C
1418 # define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1419 # define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1420 # define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1421 # define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1422 # define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1423 # define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1424 # define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1425 # define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1426 # define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1427 # define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1428 # define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1429 # define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1430 # define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1431 # define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1432 # define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1433 # define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1436 # define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1437 # define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1438 # define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1439 # define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1441 /* Au1550 Only. Redefines lots of pins */
1442 # define SYS_PF_PSC2_MASK (7 << 17)
1443 # define SYS_PF_PSC2_AC97 (0)
1444 # define SYS_PF_PSC2_SPI (0)
1445 # define SYS_PF_PSC2_I2S (1 << 17)
1446 # define SYS_PF_PSC2_SMBUS (3 << 17)
1447 # define SYS_PF_PSC2_GPIO (7 << 17)
1448 # define SYS_PF_PSC3_MASK (7 << 20)
1449 # define SYS_PF_PSC3_AC97 (0)
1450 # define SYS_PF_PSC3_SPI (0)
1451 # define SYS_PF_PSC3_I2S (1 << 20)
1452 # define SYS_PF_PSC3_SMBUS (3 << 20)
1453 # define SYS_PF_PSC3_GPIO (7 << 20)
1454 # define SYS_PF_PSC1_S1 (1 << 1)
1455 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1458 #ifdef CONFIG_SOC_AU1200
1459 #define SYS_PINFUNC_DMA (1<<31)
1460 #define SYS_PINFUNC_S0A (1<<30)
1461 #define SYS_PINFUNC_S1A (1<<29)
1462 #define SYS_PINFUNC_LP0 (1<<28)
1463 #define SYS_PINFUNC_LP1 (1<<27)
1464 #define SYS_PINFUNC_LD16 (1<<26)
1465 #define SYS_PINFUNC_LD8 (1<<25)
1466 #define SYS_PINFUNC_LD1 (1<<24)
1467 #define SYS_PINFUNC_LD0 (1<<23)
1468 #define SYS_PINFUNC_P1A (3<<21)
1469 #define SYS_PINFUNC_P1B (1<<20)
1470 #define SYS_PINFUNC_FS3 (1<<19)
1471 #define SYS_PINFUNC_P0A (3<<17)
1472 #define SYS_PINFUNC_CS (1<<16)
1473 #define SYS_PINFUNC_CIM (1<<15)
1474 #define SYS_PINFUNC_P1C (1<<14)
1475 #define SYS_PINFUNC_U1T (1<<12)
1476 #define SYS_PINFUNC_U1R (1<<11)
1477 #define SYS_PINFUNC_EX1 (1<<10)
1478 #define SYS_PINFUNC_EX0 (1<<9)
1479 #define SYS_PINFUNC_U0R (1<<8)
1480 #define SYS_PINFUNC_MC (1<<7)
1481 #define SYS_PINFUNC_S0B (1<<6)
1482 #define SYS_PINFUNC_S0C (1<<5)
1483 #define SYS_PINFUNC_P0B (1<<4)
1484 #define SYS_PINFUNC_U0T (1<<3)
1485 #define SYS_PINFUNC_S1B (1<<2)
1488 #define SYS_TRIOUTRD 0xB1900100
1489 #define SYS_TRIOUTCLR 0xB1900100
1490 #define SYS_OUTPUTRD 0xB1900108
1491 #define SYS_OUTPUTSET 0xB1900108
1492 #define SYS_OUTPUTCLR 0xB190010C
1493 #define SYS_PINSTATERD 0xB1900110
1494 #define SYS_PININPUTEN 0xB1900110
1496 /* GPIO2, Au1500, Au1550 only */
1497 #define GPIO2_BASE 0xB1700000
1498 #define GPIO2_DIR (GPIO2_BASE + 0)
1499 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1500 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1501 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1502 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1504 /* Power Management */
1505 #define SYS_SCRATCH0 0xB1900018
1506 #define SYS_SCRATCH1 0xB190001C
1507 #define SYS_WAKEMSK 0xB1900034
1508 #define SYS_ENDIAN 0xB1900038
1509 #define SYS_POWERCTRL 0xB190003C
1510 #define SYS_WAKESRC 0xB190005C
1511 #define SYS_SLPPWR 0xB1900078
1512 #define SYS_SLEEP 0xB190007C
1514 /* Clock Controller */
1515 #define SYS_FREQCTRL0 0xB1900020
1516 # define SYS_FC_FRDIV2_BIT 22
1517 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1518 # define SYS_FC_FE2 (1<<21)
1519 # define SYS_FC_FS2 (1<<20)
1520 # define SYS_FC_FRDIV1_BIT 12
1521 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1522 # define SYS_FC_FE1 (1<<11)
1523 # define SYS_FC_FS1 (1<<10)
1524 # define SYS_FC_FRDIV0_BIT 2
1525 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1526 # define SYS_FC_FE0 (1<<1)
1527 # define SYS_FC_FS0 (1<<0)
1528 #define SYS_FREQCTRL1 0xB1900024
1529 # define SYS_FC_FRDIV5_BIT 22
1530 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1531 # define SYS_FC_FE5 (1<<21)
1532 # define SYS_FC_FS5 (1<<20)
1533 # define SYS_FC_FRDIV4_BIT 12
1534 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1535 # define SYS_FC_FE4 (1<<11)
1536 # define SYS_FC_FS4 (1<<10)
1537 # define SYS_FC_FRDIV3_BIT 2
1538 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1539 # define SYS_FC_FE3 (1<<1)
1540 # define SYS_FC_FS3 (1<<0)
1541 #define SYS_CLKSRC 0xB1900028
1542 # define SYS_CS_ME1_BIT 27
1543 # define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1544 # define SYS_CS_DE1 (1<<26)
1545 # define SYS_CS_CE1 (1<<25)
1546 # define SYS_CS_ME0_BIT 22
1547 # define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1548 # define SYS_CS_DE0 (1<<21)
1549 # define SYS_CS_CE0 (1<<20)
1550 # define SYS_CS_MI2_BIT 17
1551 # define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1552 # define SYS_CS_DI2 (1<<16)
1553 # define SYS_CS_CI2 (1<<15)
1554 #ifdef CONFIG_SOC_AU1100
1555 # define SYS_CS_ML_BIT 7
1556 # define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
1557 # define SYS_CS_DL (1<<6)
1558 # define SYS_CS_CL (1<<5)
1560 # define SYS_CS_MUH_BIT 12
1561 # define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1562 # define SYS_CS_DUH (1<<11)
1563 # define SYS_CS_CUH (1<<10)
1564 # define SYS_CS_MUD_BIT 7
1565 # define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1566 # define SYS_CS_DUD (1<<6)
1567 # define SYS_CS_CUD (1<<5)
1569 # define SYS_CS_MIR_BIT 2
1570 # define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1571 # define SYS_CS_DIR (1<<1)
1572 # define SYS_CS_CIR (1<<0)
1574 # define SYS_CS_MUX_AUX 0x1
1575 # define SYS_CS_MUX_FQ0 0x2
1576 # define SYS_CS_MUX_FQ1 0x3
1577 # define SYS_CS_MUX_FQ2 0x4
1578 # define SYS_CS_MUX_FQ3 0x5
1579 # define SYS_CS_MUX_FQ4 0x6
1580 # define SYS_CS_MUX_FQ5 0x7
1581 #define SYS_CPUPLL 0xB1900060
1582 #define SYS_AUXPLL 0xB1900064
1584 /* AC97 Controller */
1585 #define AC97C_CONFIG 0xB0000000
1586 # define AC97C_RECV_SLOTS_BIT 13
1587 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1588 # define AC97C_XMIT_SLOTS_BIT 3
1589 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1590 # define AC97C_SG (1<<2)
1591 # define AC97C_SYNC (1<<1)
1592 # define AC97C_RESET (1<<0)
1593 #define AC97C_STATUS 0xB0000004
1594 # define AC97C_XU (1<<11)
1595 # define AC97C_XO (1<<10)
1596 # define AC97C_RU (1<<9)
1597 # define AC97C_RO (1<<8)
1598 # define AC97C_READY (1<<7)
1599 # define AC97C_CP (1<<6)
1600 # define AC97C_TR (1<<5)
1601 # define AC97C_TE (1<<4)
1602 # define AC97C_TF (1<<3)
1603 # define AC97C_RR (1<<2)
1604 # define AC97C_RE (1<<1)
1605 # define AC97C_RF (1<<0)
1606 #define AC97C_DATA 0xB0000008
1607 #define AC97C_CMD 0xB000000C
1608 # define AC97C_WD_BIT 16
1609 # define AC97C_READ (1<<7)
1610 # define AC97C_INDEX_MASK 0x7f
1611 #define AC97C_CNTRL 0xB0000010
1612 # define AC97C_RS (1<<1)
1613 # define AC97C_CE (1<<0)
1616 /* Secure Digital (SD) Controller */
1617 #define SD0_XMIT_FIFO 0xB0600000
1618 #define SD0_RECV_FIFO 0xB0600004
1619 #define SD1_XMIT_FIFO 0xB0680000
1620 #define SD1_RECV_FIFO 0xB0680004
1622 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1623 /* Au1500 PCI Controller */
1624 #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1625 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1626 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1627 # define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1628 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1629 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1630 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1631 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1632 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1633 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1634 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1635 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1636 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1637 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1638 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1639 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1641 #define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
1643 /* All of our structures, like pci resource, have 32 bit members.
1644 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1645 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1646 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1647 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1648 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1649 * ourselves and then adjust the device's resources.
1651 #define Au1500_EXT_CFG 0x600000000ULL
1652 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1653 #define Au1500_PCI_IO_START 0x500000000ULL
1654 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1655 #define Au1500_PCI_MEM_START 0x440000000ULL
1656 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1658 #define PCI_IO_START (Au1500_PCI_IO_START + 0x1000)
1659 #define PCI_IO_END (Au1500_PCI_IO_END)
1660 #define PCI_MEM_START (Au1500_PCI_MEM_START)
1661 #define PCI_MEM_END (Au1500_PCI_MEM_END)
1662 #define PCI_FIRST_DEVFN (0<<3)
1663 #define PCI_LAST_DEVFN (19<<3)
1665 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1666 #define IOPORT_RESOURCE_END 0xffffffff
1667 #define IOMEM_RESOURCE_START 0x10000000
1668 #define IOMEM_RESOURCE_END 0xffffffff
1671 * Borrowed from the PPC arch:
1672 * The following macro is used to lookup irqs in a standard table
1673 * format for those PPC systems that do not already have PCI
1674 * interrupts properly routed.
1676 /* FIXME - double check this from asm-ppc/pci-bridge.h */
1677 #define PCI_IRQ_TABLE_LOOKUP \
1678 ({ long _ctl_ = -1; \
1679 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
1680 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
1684 #else /* Au1000 and Au1100 and Au1200 */
1686 /* don't allow any legacy ports probing */
1687 #define IOPORT_RESOURCE_START 0x10000000
1688 #define IOPORT_RESOURCE_END 0xffffffff
1689 #define IOMEM_RESOURCE_START 0x10000000
1690 #define IOMEM_RESOURCE_END 0xffffffff
1692 #define PCI_IO_START 0
1693 #define PCI_IO_END 0
1694 #define PCI_MEM_START 0
1695 #define PCI_MEM_END 0
1696 #define PCI_FIRST_DEVFN 0
1697 #define PCI_LAST_DEVFN 0
1701 #ifndef _LANGUAGE_ASSEMBLY
1702 typedef volatile struct
1704 /* 0x0000 */ u32 toytrim;
1705 /* 0x0004 */ u32 toywrite;
1706 /* 0x0008 */ u32 toymatch0;
1707 /* 0x000C */ u32 toymatch1;
1708 /* 0x0010 */ u32 toymatch2;
1709 /* 0x0014 */ u32 cntrctrl;
1710 /* 0x0018 */ u32 scratch0;
1711 /* 0x001C */ u32 scratch1;
1712 /* 0x0020 */ u32 freqctrl0;
1713 /* 0x0024 */ u32 freqctrl1;
1714 /* 0x0028 */ u32 clksrc;
1715 /* 0x002C */ u32 pinfunc;
1716 /* 0x0030 */ u32 reserved0;
1717 /* 0x0034 */ u32 wakemsk;
1718 /* 0x0038 */ u32 endian;
1719 /* 0x003C */ u32 powerctrl;
1720 /* 0x0040 */ u32 toyread;
1721 /* 0x0044 */ u32 rtctrim;
1722 /* 0x0048 */ u32 rtcwrite;
1723 /* 0x004C */ u32 rtcmatch0;
1724 /* 0x0050 */ u32 rtcmatch1;
1725 /* 0x0054 */ u32 rtcmatch2;
1726 /* 0x0058 */ u32 rtcread;
1727 /* 0x005C */ u32 wakesrc;
1728 /* 0x0060 */ u32 cpupll;
1729 /* 0x0064 */ u32 auxpll;
1730 /* 0x0068 */ u32 reserved1;
1731 /* 0x006C */ u32 reserved2;
1732 /* 0x0070 */ u32 reserved3;
1733 /* 0x0074 */ u32 reserved4;
1734 /* 0x0078 */ u32 slppwr;
1735 /* 0x007C */ u32 sleep;
1736 /* 0x0080 */ u32 reserved5[32];
1737 /* 0x0100 */ u32 trioutrd;
1738 #define trioutclr trioutrd
1739 /* 0x0104 */ u32 reserved6;
1740 /* 0x0108 */ u32 outputrd;
1741 #define outputset outputrd
1742 /* 0x010C */ u32 outputclr;
1743 /* 0x0110 */ u32 pinstaterd;
1744 #define pininputen pinstaterd
1748 static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1751 /* Processor information base on prid.
1752 * Copied from PowerPC.
1754 #ifndef _LANGUAGE_ASSEMBLY
1756 /* CPU is matched via (PRID & prid_mask) == prid_value */
1757 unsigned int prid_mask;
1758 unsigned int prid_value;
1761 unsigned char cpu_od; /* Set Config[OD] */
1762 unsigned char cpu_bclk; /* Enable BCLK switching */
1765 extern struct cpu_spec cpu_specs[];
1766 extern struct cpu_spec *cur_cpu_spec[];