2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/timer.h>
30 #include <linux/list.h>
31 #include <linux/interrupt.h>
32 #include <linux/reboot.h>
33 #include <linux/usb.h>
34 #include <linux/moduleparam.h>
35 #include <linux/dma-mapping.h>
37 #include "../core/hcd.h"
39 #include <asm/byteorder.h>
42 #include <asm/system.h>
43 #include <asm/unaligned.h>
45 #include <asm/firmware.h>
49 /*-------------------------------------------------------------------------*/
52 * EHCI hc_driver implementation ... experimental, incomplete.
53 * Based on the final 1.0 register interface specification.
55 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
56 * First was PCMCIA, like ISA; then CardBus, which is PCI.
57 * Next comes "CardBay", using USB 2.0 signals.
59 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
60 * Special thanks to Intel and VIA for providing host controllers to
61 * test this driver on, and Cypress (including In-System Design) for
62 * providing early devices for those host controllers to talk to!
66 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
67 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
68 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
69 * <sojkam@centrum.cz>, updates by DB).
71 * 2002-11-29 Correct handling for hw async_next register.
72 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
73 * only scheduling is different, no arbitrary limitations.
74 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
75 * clean up HC run state handshaking.
76 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
77 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
78 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
79 * 2002-05-07 Some error path cleanups to report better errors; wmb();
80 * use non-CVS version id; better iso bandwidth claim.
81 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
82 * errors in submit path. Bugfixes to interrupt scheduling/processing.
83 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
84 * more checking to generic hcd framework (db). Make it work with
85 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
86 * 2002-01-14 Minor cleanup; version synch.
87 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
88 * 2002-01-04 Control/Bulk queuing behaves.
90 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
91 * 2001-June Works with usb-storage and NEC EHCI on 2.4
94 #define DRIVER_VERSION "10 Dec 2004"
95 #define DRIVER_AUTHOR "David Brownell"
96 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
98 static const char hcd_name [] = "ehci_hcd";
101 #undef EHCI_VERBOSE_DEBUG
102 #undef EHCI_URB_TRACE
108 /* magic numbers that can affect system performance */
109 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
110 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
111 #define EHCI_TUNE_RL_TT 0
112 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
113 #define EHCI_TUNE_MULT_TT 1
114 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
116 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
117 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
118 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
119 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
121 /* Initial IRQ latency: faster than hw default */
122 static int log2_irq_thresh = 0; // 0 to 6
123 module_param (log2_irq_thresh, int, S_IRUGO);
124 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
126 /* initial park setting: slower than hw default */
127 static unsigned park = 0;
128 module_param (park, uint, S_IRUGO);
129 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
131 /* for flakey hardware, ignore overcurrent indicators */
132 static int ignore_oc = 0;
133 module_param (ignore_oc, bool, S_IRUGO);
134 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
136 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
138 /*-------------------------------------------------------------------------*/
141 #include "ehci-dbg.c"
143 /*-------------------------------------------------------------------------*/
146 * handshake - spin reading hc until handshake completes or fails
147 * @ptr: address of hc register to be read
148 * @mask: bits to look at in result of read
149 * @done: value of those bits when handshake succeeds
150 * @usec: timeout in microseconds
152 * Returns negative errno, or zero on success
154 * Success happens when the "mask" bits have the specified value (hardware
155 * handshake done). There are two failure modes: "usec" have passed (major
156 * hardware flakeout), or the register reads as all-ones (hardware removed).
158 * That last failure should_only happen in cases like physical cardbus eject
159 * before driver shutdown. But it also seems to be caused by bugs in cardbus
160 * bridge shutdown: shutting down the bridge before the devices using it.
162 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
163 u32 mask, u32 done, int usec)
168 result = ehci_readl(ehci, ptr);
169 if (result == ~(u32)0) /* card removed */
180 /* force HC to halt state from unknown (EHCI spec section 2.3) */
181 static int ehci_halt (struct ehci_hcd *ehci)
183 u32 temp = ehci_readl(ehci, &ehci->regs->status);
185 /* disable any irqs left enabled by previous code */
186 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
188 if ((temp & STS_HALT) != 0)
191 temp = ehci_readl(ehci, &ehci->regs->command);
193 ehci_writel(ehci, temp, &ehci->regs->command);
194 return handshake (ehci, &ehci->regs->status,
195 STS_HALT, STS_HALT, 16 * 125);
198 /* put TDI/ARC silicon into EHCI mode */
199 static void tdi_reset (struct ehci_hcd *ehci)
201 u32 __iomem *reg_ptr;
204 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
205 tmp = ehci_readl(ehci, reg_ptr);
206 tmp |= USBMODE_CM_HC;
207 /* The default byte access to MMR space is LE after
208 * controller reset. Set the required endian mode
209 * for transfer buffers to match the host microprocessor
211 if (ehci_big_endian_mmio(ehci))
213 ehci_writel(ehci, tmp, reg_ptr);
216 /* reset a non-running (STS_HALT == 1) controller */
217 static int ehci_reset (struct ehci_hcd *ehci)
220 u32 command = ehci_readl(ehci, &ehci->regs->command);
222 command |= CMD_RESET;
223 dbg_cmd (ehci, "reset", command);
224 ehci_writel(ehci, command, &ehci->regs->command);
225 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
226 ehci->next_statechange = jiffies;
227 retval = handshake (ehci, &ehci->regs->command,
228 CMD_RESET, 0, 250 * 1000);
233 if (ehci_is_TDI(ehci))
239 /* idle the controller (from running) */
240 static void ehci_quiesce (struct ehci_hcd *ehci)
245 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
249 /* wait for any schedule enables/disables to take effect */
250 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
251 temp &= STS_ASS | STS_PSS;
252 if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS,
253 temp, 16 * 125) != 0) {
254 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
258 /* then disable anything that's still active */
259 temp = ehci_readl(ehci, &ehci->regs->command);
260 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
261 ehci_writel(ehci, temp, &ehci->regs->command);
263 /* hardware can take 16 microframes to turn off ... */
264 if (handshake (ehci, &ehci->regs->status, STS_ASS | STS_PSS,
266 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
271 /*-------------------------------------------------------------------------*/
273 static void ehci_work(struct ehci_hcd *ehci);
275 #include "ehci-hub.c"
276 #include "ehci-mem.c"
278 #include "ehci-sched.c"
280 /*-------------------------------------------------------------------------*/
282 #ifdef CONFIG_CPU_FREQ
284 #include <linux/cpufreq.h>
286 static void ehci_cpufreq_pause (struct ehci_hcd *ehci)
290 spin_lock_irqsave(&ehci->lock, flags);
291 if (!ehci->cpufreq_changing++)
292 qh_inactivate_split_intr_qhs(ehci);
293 spin_unlock_irqrestore(&ehci->lock, flags);
296 static void ehci_cpufreq_unpause (struct ehci_hcd *ehci)
300 spin_lock_irqsave(&ehci->lock, flags);
301 if (!--ehci->cpufreq_changing)
302 qh_reactivate_split_intr_qhs(ehci);
303 spin_unlock_irqrestore(&ehci->lock, flags);
307 * ehci_cpufreq_notifier is needed to avoid MMF errors that occur when
308 * EHCI controllers that don't cache many uframes get delayed trying to
309 * read main memory during CPU frequency transitions. This can cause
310 * split interrupt transactions to not be completed in the required uframe.
311 * This has been observed on the Broadcom/ServerWorks HT1000 controller.
313 static int ehci_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
316 struct ehci_hcd *ehci = container_of(nb, struct ehci_hcd,
320 case CPUFREQ_PRECHANGE:
321 ehci_cpufreq_pause(ehci);
323 case CPUFREQ_POSTCHANGE:
324 ehci_cpufreq_unpause(ehci);
332 /*-------------------------------------------------------------------------*/
334 static void ehci_watchdog (unsigned long param)
336 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
339 spin_lock_irqsave (&ehci->lock, flags);
341 /* lost IAA irqs wedge things badly; seen with a vt8235 */
343 u32 status = ehci_readl(ehci, &ehci->regs->status);
344 if (status & STS_IAA) {
345 ehci_vdbg (ehci, "lost IAA\n");
346 COUNT (ehci->stats.lost_iaa);
347 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
348 ehci->reclaim_ready = 1;
352 /* stop async processing after it's idled a bit */
353 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
354 start_unlink_async (ehci, ehci->async);
356 /* ehci could run by timer, without IRQs ... */
359 spin_unlock_irqrestore (&ehci->lock, flags);
362 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
363 * The firmware seems to think that powering off is a wakeup event!
364 * This routine turns off remote wakeup and everything else, on all ports.
366 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
368 int port = HCS_N_PORTS(ehci->hcs_params);
371 ehci_writel(ehci, PORT_RWC_BITS,
372 &ehci->regs->port_status[port]);
375 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
376 * This forcibly disables dma and IRQs, helping kexec and other cases
377 * where the next system software may expect clean state.
380 ehci_shutdown (struct usb_hcd *hcd)
382 struct ehci_hcd *ehci;
384 ehci = hcd_to_ehci (hcd);
385 (void) ehci_halt (ehci);
386 ehci_turn_off_all_ports(ehci);
388 /* make BIOS/etc use companion controller during reboot */
389 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
391 /* unblock posted writes */
392 ehci_readl(ehci, &ehci->regs->configured_flag);
395 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
399 if (!HCS_PPC (ehci->hcs_params))
402 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
403 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
404 (void) ehci_hub_control(ehci_to_hcd(ehci),
405 is_on ? SetPortFeature : ClearPortFeature,
408 /* Flush those writes */
409 ehci_readl(ehci, &ehci->regs->command);
413 /*-------------------------------------------------------------------------*/
416 * ehci_work is called from some interrupts, timers, and so on.
417 * it calls driver completion functions, after dropping ehci->lock.
419 static void ehci_work (struct ehci_hcd *ehci)
421 timer_action_done (ehci, TIMER_IO_WATCHDOG);
422 if (ehci->reclaim_ready)
423 end_unlink_async (ehci);
425 /* another CPU may drop ehci->lock during a schedule scan while
426 * it reports urb completions. this flag guards against bogus
427 * attempts at re-entrant schedule scanning.
433 if (ehci->next_uframe != -1)
434 scan_periodic (ehci);
437 /* the IO watchdog guards against hardware or driver bugs that
438 * misplace IRQs, and should let us run completely without IRQs.
439 * such lossage has been observed on both VT6202 and VT8235.
441 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
442 (ehci->async->qh_next.ptr != NULL ||
443 ehci->periodic_sched != 0))
444 timer_action (ehci, TIMER_IO_WATCHDOG);
447 static void ehci_stop (struct usb_hcd *hcd)
449 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
451 ehci_dbg (ehci, "stop\n");
453 /* Turn off port power on all root hub ports. */
454 ehci_port_power (ehci, 0);
456 /* no more interrupts ... */
457 del_timer_sync (&ehci->watchdog);
459 spin_lock_irq(&ehci->lock);
460 if (HC_IS_RUNNING (hcd->state))
464 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
465 spin_unlock_irq(&ehci->lock);
467 #ifdef CONFIG_CPU_FREQ
468 cpufreq_unregister_notifier(&ehci->cpufreq_transition,
469 CPUFREQ_TRANSITION_NOTIFIER);
471 /* let companion controllers work when we aren't */
472 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
474 remove_companion_file(ehci);
475 remove_debug_files (ehci);
477 /* root hub is shut down separately (first, when possible) */
478 spin_lock_irq (&ehci->lock);
481 spin_unlock_irq (&ehci->lock);
482 ehci_mem_cleanup (ehci);
485 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
486 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
487 ehci->stats.lost_iaa);
488 ehci_dbg (ehci, "complete %ld unlink %ld\n",
489 ehci->stats.complete, ehci->stats.unlink);
492 dbg_status (ehci, "ehci_stop completed",
493 ehci_readl(ehci, &ehci->regs->status));
496 /* one-time init, only for memory state */
497 static int ehci_init(struct usb_hcd *hcd)
499 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
504 spin_lock_init(&ehci->lock);
506 init_timer(&ehci->watchdog);
507 ehci->watchdog.function = ehci_watchdog;
508 ehci->watchdog.data = (unsigned long) ehci;
511 * hw default: 1K periodic list heads, one per frame.
512 * periodic_size can shrink by USBCMD update if hcc_params allows.
514 ehci->periodic_size = DEFAULT_I_TDPS;
515 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
518 /* controllers may cache some of the periodic schedule ... */
519 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
520 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
522 else // N microframes cached
523 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
525 ehci->reclaim = NULL;
526 ehci->reclaim_ready = 0;
527 ehci->next_uframe = -1;
530 * dedicate a qh for the async ring head, since we couldn't unlink
531 * a 'real' qh without stopping the async schedule [4.8]. use it
532 * as the 'reclamation list head' too.
533 * its dummy is used in hw_alt_next of many tds, to prevent the qh
534 * from automatically advancing to the next td after short reads.
536 ehci->async->qh_next.qh = NULL;
537 ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
538 ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
539 ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
540 ehci->async->hw_qtd_next = EHCI_LIST_END(ehci);
541 ehci->async->qh_state = QH_STATE_LINKED;
542 ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
544 /* clear interrupt enables, set irq latency */
545 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
547 temp = 1 << (16 + log2_irq_thresh);
548 if (HCC_CANPARK(hcc_params)) {
549 /* HW default park == 3, on hardware that supports it (like
550 * NVidia and ALI silicon), maximizes throughput on the async
551 * schedule by avoiding QH fetches between transfers.
553 * With fast usb storage devices and NForce2, "park" seems to
554 * make problems: throughput reduction (!), data errors...
557 park = min(park, (unsigned) 3);
561 ehci_dbg(ehci, "park %d\n", park);
563 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
564 /* periodic schedule size can be smaller than default */
566 temp |= (EHCI_TUNE_FLS << 2);
567 switch (EHCI_TUNE_FLS) {
568 case 0: ehci->periodic_size = 1024; break;
569 case 1: ehci->periodic_size = 512; break;
570 case 2: ehci->periodic_size = 256; break;
574 ehci->command = temp;
576 #ifdef CONFIG_CPU_FREQ
577 INIT_LIST_HEAD(&ehci->split_intr_qhs);
579 * If the EHCI controller caches enough uframes, this probably
580 * isn't needed unless there are so many low/full speed devices
581 * that the controller's can't cache it all.
583 ehci->cpufreq_transition.notifier_call = ehci_cpufreq_notifier;
584 cpufreq_register_notifier(&ehci->cpufreq_transition,
585 CPUFREQ_TRANSITION_NOTIFIER);
590 /* start HC running; it's halted, ehci_init() has been run (once) */
591 static int ehci_run (struct usb_hcd *hcd)
593 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
598 hcd->uses_new_polling = 1;
601 /* EHCI spec section 4.1 */
602 if ((retval = ehci_reset(ehci)) != 0) {
603 ehci_mem_cleanup(ehci);
606 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
607 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
610 * hcc_params controls whether ehci->regs->segment must (!!!)
611 * be used; it constrains QH/ITD/SITD and QTD locations.
612 * pci_pool consistent memory always uses segment zero.
613 * streaming mappings for I/O buffers, like pci_map_single(),
614 * can return segments above 4GB, if the device allows.
616 * NOTE: the dma mask is visible through dma_supported(), so
617 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
618 * Scsi_Host.highmem_io, and so forth. It's readonly to all
619 * host side drivers though.
621 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
622 if (HCC_64BIT_ADDR(hcc_params)) {
623 ehci_writel(ehci, 0, &ehci->regs->segment);
625 // this is deeply broken on almost all architectures
626 if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
627 ehci_info(ehci, "enabled 64bit DMA\n");
632 // Philips, Intel, and maybe others need CMD_RUN before the
633 // root hub will detect new devices (why?); NEC doesn't
634 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
635 ehci->command |= CMD_RUN;
636 ehci_writel(ehci, ehci->command, &ehci->regs->command);
637 dbg_cmd (ehci, "init", ehci->command);
640 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
641 * are explicitly handed to companion controller(s), so no TT is
642 * involved with the root hub. (Except where one is integrated,
643 * and there's no companion controller unless maybe for USB OTG.)
645 hcd->state = HC_STATE_RUNNING;
646 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
647 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
649 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
651 "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
652 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
653 temp >> 8, temp & 0xff, DRIVER_VERSION,
654 ignore_oc ? ", overcurrent ignored" : "");
656 ehci_writel(ehci, INTR_MASK,
657 &ehci->regs->intr_enable); /* Turn On Interrupts */
659 /* GRR this is run-once init(), being done every time the HC starts.
660 * So long as they're part of class devices, we can't do it init()
661 * since the class device isn't created that early.
663 create_debug_files(ehci);
664 create_companion_file(ehci);
669 /*-------------------------------------------------------------------------*/
671 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
673 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
674 u32 status, pcd_status = 0;
677 spin_lock (&ehci->lock);
679 status = ehci_readl(ehci, &ehci->regs->status);
681 /* e.g. cardbus physical eject */
682 if (status == ~(u32) 0) {
683 ehci_dbg (ehci, "device removed\n");
688 if (!status) { /* irq sharing? */
689 spin_unlock(&ehci->lock);
693 /* clear (just) interrupts */
694 ehci_writel(ehci, status, &ehci->regs->status);
695 ehci_readl(ehci, &ehci->regs->command); /* unblock posted write */
698 #ifdef EHCI_VERBOSE_DEBUG
699 /* unrequested/ignored: Frame List Rollover */
700 dbg_status (ehci, "irq", status);
703 /* INT, ERR, and IAA interrupt rates can be throttled */
705 /* normal [4.15.1.2] or error [4.15.1.1] completion */
706 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
707 if (likely ((status & STS_ERR) == 0))
708 COUNT (ehci->stats.normal);
710 COUNT (ehci->stats.error);
714 /* complete the unlinking of some qh [4.15.2.3] */
715 if (status & STS_IAA) {
716 COUNT (ehci->stats.reclaim);
717 ehci->reclaim_ready = 1;
721 /* remote wakeup [4.3.1] */
722 if (status & STS_PCD) {
723 unsigned i = HCS_N_PORTS (ehci->hcs_params);
726 /* resume root hub? */
727 if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN))
728 usb_hcd_resume_root_hub(hcd);
731 int pstatus = ehci_readl(ehci,
732 &ehci->regs->port_status [i]);
734 if (pstatus & PORT_OWNER)
736 if (!(pstatus & PORT_RESUME)
737 || ehci->reset_done [i] != 0)
740 /* start 20 msec resume signaling from this port,
741 * and make khubd collect PORT_STAT_C_SUSPEND to
742 * stop that signaling.
744 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
745 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
746 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
750 /* PCI errors [4.15.2.4] */
751 if (unlikely ((status & STS_FATAL) != 0)) {
752 /* bogus "fatal" IRQs appear on some chips... why? */
753 status = ehci_readl(ehci, &ehci->regs->status);
754 dbg_cmd (ehci, "fatal", ehci_readl(ehci,
755 &ehci->regs->command));
756 dbg_status (ehci, "fatal", status);
757 if (status & STS_HALT) {
758 ehci_err (ehci, "fatal error\n");
761 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
762 /* generic layer kills/unlinks all urbs, then
763 * uses ehci_stop to clean up the rest
771 spin_unlock (&ehci->lock);
772 if (pcd_status & STS_PCD)
773 usb_hcd_poll_rh_status(hcd);
777 /*-------------------------------------------------------------------------*/
780 * non-error returns are a promise to giveback() the urb later
781 * we drop ownership so next owner (or urb unlink) can get it
783 * urb + dev is in hcd.self.controller.urb_list
784 * we're queueing TDs onto software and hardware lists
786 * hcd-specific init for hcpriv hasn't been done yet
788 * NOTE: control, bulk, and interrupt share the same code to append TDs
789 * to a (possibly active) QH, and the same QH scanning code.
791 static int ehci_urb_enqueue (
793 struct usb_host_endpoint *ep,
797 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
798 struct list_head qtd_list;
800 INIT_LIST_HEAD (&qtd_list);
802 switch (usb_pipetype (urb->pipe)) {
803 // case PIPE_CONTROL:
806 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
808 return submit_async (ehci, ep, urb, &qtd_list, mem_flags);
811 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
813 return intr_submit (ehci, ep, urb, &qtd_list, mem_flags);
815 case PIPE_ISOCHRONOUS:
816 if (urb->dev->speed == USB_SPEED_HIGH)
817 return itd_submit (ehci, urb, mem_flags);
819 return sitd_submit (ehci, urb, mem_flags);
823 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
825 /* if we need to use IAA and it's busy, defer */
826 if (qh->qh_state == QH_STATE_LINKED
828 && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) {
829 struct ehci_qh *last;
831 for (last = ehci->reclaim;
833 last = last->reclaim)
835 qh->qh_state = QH_STATE_UNLINK_WAIT;
838 /* bypass IAA if the hc can't care */
839 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim)
840 end_unlink_async (ehci);
842 /* something else might have unlinked the qh by now */
843 if (qh->qh_state == QH_STATE_LINKED)
844 start_unlink_async (ehci, qh);
847 /* remove from hardware lists
848 * completions normally happen asynchronously
851 static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
853 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
857 spin_lock_irqsave (&ehci->lock, flags);
858 switch (usb_pipetype (urb->pipe)) {
859 // case PIPE_CONTROL:
862 qh = (struct ehci_qh *) urb->hcpriv;
865 unlink_async (ehci, qh);
869 qh = (struct ehci_qh *) urb->hcpriv;
872 switch (qh->qh_state) {
873 case QH_STATE_LINKED:
874 intr_deschedule (ehci, qh);
877 qh_completions (ehci, qh);
880 ehci_dbg (ehci, "bogus qh %p state %d\n",
885 /* reschedule QH iff another request is queued */
886 if (!list_empty (&qh->qtd_list)
887 && HC_IS_RUNNING (hcd->state)) {
890 status = qh_schedule (ehci, qh);
891 spin_unlock_irqrestore (&ehci->lock, flags);
894 // shouldn't happen often, but ...
895 // FIXME kill those tds' urbs
896 err ("can't reschedule qh %p, err %d",
903 case PIPE_ISOCHRONOUS:
906 // wait till next completion, do it then.
907 // completion irqs can wait up to 1024 msec,
911 spin_unlock_irqrestore (&ehci->lock, flags);
915 /*-------------------------------------------------------------------------*/
917 // bulk qh holds the data toggle
920 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
922 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
924 struct ehci_qh *qh, *tmp;
926 /* ASSERT: any requests/urbs are being unlinked */
927 /* ASSERT: nobody can be submitting urbs for this any more */
930 spin_lock_irqsave (&ehci->lock, flags);
935 /* endpoints can be iso streams. for now, we don't
936 * accelerate iso completions ... so spin a while.
938 if (qh->hw_info1 == 0) {
939 ehci_vdbg (ehci, "iso delay\n");
943 if (!HC_IS_RUNNING (hcd->state))
944 qh->qh_state = QH_STATE_IDLE;
945 switch (qh->qh_state) {
946 case QH_STATE_LINKED:
947 for (tmp = ehci->async->qh_next.qh;
949 tmp = tmp->qh_next.qh)
951 /* periodic qh self-unlinks on empty */
954 unlink_async (ehci, qh);
956 case QH_STATE_UNLINK: /* wait for hw to finish? */
958 spin_unlock_irqrestore (&ehci->lock, flags);
959 schedule_timeout_uninterruptible(1);
961 case QH_STATE_IDLE: /* fully unlinked */
962 if (list_empty (&qh->qtd_list)) {
966 /* else FALL THROUGH */
969 /* caller was supposed to have unlinked any requests;
970 * that's not our job. just leak this memory.
972 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
973 qh, ep->desc.bEndpointAddress, qh->qh_state,
974 list_empty (&qh->qtd_list) ? "" : "(has tds)");
979 spin_unlock_irqrestore (&ehci->lock, flags);
983 static int ehci_get_frame (struct usb_hcd *hcd)
985 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
986 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
990 /*-------------------------------------------------------------------------*/
992 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
994 MODULE_DESCRIPTION (DRIVER_INFO);
995 MODULE_AUTHOR (DRIVER_AUTHOR);
996 MODULE_LICENSE ("GPL");
999 #include "ehci-pci.c"
1000 #define PCI_DRIVER ehci_pci_driver
1003 #ifdef CONFIG_USB_EHCI_FSL
1004 #include "ehci-fsl.c"
1005 #define PLATFORM_DRIVER ehci_fsl_driver
1008 #ifdef CONFIG_SOC_AU1200
1009 #include "ehci-au1xxx.c"
1010 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1013 #ifdef CONFIG_PPC_PS3
1014 #include "ehci-ps3.c"
1015 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_sb_driver
1018 #ifdef CONFIG_440EPX
1019 #include "ehci-ppc-soc.c"
1020 #define PLATFORM_DRIVER ehci_ppc_soc_driver
1023 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1024 !defined(PS3_SYSTEM_BUS_DRIVER)
1025 #error "missing bus glue for ehci-hcd"
1028 static int __init ehci_hcd_init(void)
1032 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1034 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1035 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1037 #ifdef PLATFORM_DRIVER
1038 retval = platform_driver_register(&PLATFORM_DRIVER);
1044 retval = pci_register_driver(&PCI_DRIVER);
1046 #ifdef PLATFORM_DRIVER
1047 platform_driver_unregister(&PLATFORM_DRIVER);
1053 #ifdef PS3_SYSTEM_BUS_DRIVER
1054 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
1055 retval = ps3_system_bus_driver_register(
1056 &PS3_SYSTEM_BUS_DRIVER);
1058 #ifdef PLATFORM_DRIVER
1059 platform_driver_unregister(&PLATFORM_DRIVER);
1062 pci_unregister_driver(&PCI_DRIVER);
1071 module_init(ehci_hcd_init);
1073 static void __exit ehci_hcd_cleanup(void)
1075 #ifdef PLATFORM_DRIVER
1076 platform_driver_unregister(&PLATFORM_DRIVER);
1079 pci_unregister_driver(&PCI_DRIVER);
1081 #ifdef PS3_SYSTEM_BUS_DRIVER
1082 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1083 ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1086 module_exit(ehci_hcd_cleanup);