1 #include <linux/init.h>
2 #include <linux/bitops.h>
3 #include <linux/delay.h>
7 #include <asm/processor-cyrix.h>
8 #include <asm/processor-flags.h>
10 #include <asm/pci-direct.h>
16 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
18 static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
20 unsigned char ccr2, ccr3;
23 /* we test for DEVID by checking whether CCR3 is writable */
24 local_irq_save(flags);
25 ccr3 = getCx86(CX86_CCR3);
26 setCx86(CX86_CCR3, ccr3 ^ 0x80);
27 getCx86(0xc0); /* dummy to change bus */
29 if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
30 ccr2 = getCx86(CX86_CCR2);
31 setCx86(CX86_CCR2, ccr2 ^ 0x04);
32 getCx86(0xc0); /* dummy */
34 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
36 else { /* Cx486S A step */
37 setCx86(CX86_CCR2, ccr2);
41 setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
43 /* read DIR0 and DIR1 CPU registers */
44 *dir0 = getCx86(CX86_DIR0);
45 *dir1 = getCx86(CX86_DIR1);
47 local_irq_restore(flags);
51 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
52 * order to identify the Cyrix CPU model after we're out of setup.c
54 * Actually since bugs.h doesn't even reference this perhaps someone should
55 * fix the documentation ???
57 static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
59 static char Cx86_model[][9] __cpuinitdata = {
60 "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
63 static char Cx486_name[][5] __cpuinitdata = {
64 "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
67 static char Cx486S_name[][4] __cpuinitdata = {
68 "S", "S2", "Se", "S2e"
70 static char Cx486D_name[][4] __cpuinitdata = {
71 "DX", "DX2", "?", "?", "?", "DX4"
73 static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
74 static char cyrix_model_mult1[] __cpuinitdata = "12??43";
75 static char cyrix_model_mult2[] __cpuinitdata = "12233445";
78 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
79 * BIOSes for compatibility with DOS games. This makes the udelay loop
80 * work correctly, and improves performance.
82 * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
85 static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
89 if (Cx86_dir0_msb == 3) {
90 unsigned char ccr3, ccr5;
92 local_irq_save(flags);
93 ccr3 = getCx86(CX86_CCR3);
94 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
95 ccr5 = getCx86(CX86_CCR5);
97 setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
98 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
99 local_irq_restore(flags);
101 if (ccr5 & 2) { /* possible wrong calibration done */
102 printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
104 c->loops_per_jiffy = loops_per_jiffy;
110 static void __cpuinit set_cx86_reorder(void)
114 printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
115 ccr3 = getCx86(CX86_CCR3);
116 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
118 /* Load/Store Serialize to mem access disable (=reorder it) */
119 setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
120 /* set load/store serialize from 1GB to 4GB */
122 setCx86(CX86_CCR3, ccr3);
125 static void __cpuinit set_cx86_memwb(void)
127 printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
129 /* CCR2 bit 2: unlock NW bit */
130 setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
131 /* set 'Not Write-through' */
132 write_cr0(read_cr0() | X86_CR0_NW);
133 /* CCR2 bit 2: lock NW bit and set WT1 */
134 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
138 * Configure later MediaGX and/or Geode processor.
141 static void __cpuinit geode_configure(void)
145 local_irq_save(flags);
147 /* Suspend on halt power saving and enable #SUSP pin */
148 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
150 ccr3 = getCx86(CX86_CCR3);
151 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
154 /* FPU fast, DTE cache, Mem bypass */
155 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
156 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
161 local_irq_restore(flags);
165 static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
167 unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
168 char *buf = c->x86_model_id;
169 const char *p = NULL;
172 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
173 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
175 clear_cpu_cap(c, 0*32+31);
177 /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
178 if (test_cpu_cap(c, 1*32+24)) {
179 clear_cpu_cap(c, 1*32+24);
180 set_cpu_cap(c, X86_FEATURE_CXMMX);
183 do_cyrix_devid(&dir0, &dir1);
187 Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */
188 dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
190 /* common case step number/rev -- exceptions handled below */
191 c->x86_model = (dir1 >> 4) + 1;
192 c->x86_mask = dir1 & 0xf;
194 /* Now cook; the original recipe is by Channing Corn, from Cyrix.
195 * We do the same thing for each generation: we work out
196 * the model, multiplier and stepping. Black magic included,
197 * to make the silicon step/rev numbers match the printed ones.
203 case 0: /* Cx486SLC/DLC/SRx/DRx */
204 p = Cx486_name[dir0_lsn & 7];
207 case 1: /* Cx486S/DX/DX2/DX4 */
208 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
209 : Cx486S_name[dir0_lsn & 3];
213 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
217 case 3: /* 6x86/6x86L */
219 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
220 if (dir1 > 0x21) { /* 686L */
226 /* Emulate MTRRs using Cyrix's ARRs. */
227 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
228 /* 6x86's contain this bug */
232 case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
237 * It isn't really a PCI quirk directly, but the cure is the
238 * same. The MediaGX has deep magic SMM stuff that handles the
239 * SB emulation. It throws away the fifo on disable_dma() which
240 * is wrong and ruins the audio.
242 * Bug2: VSA1 has a wrap bug so that using maximum sized DMA
243 * causes bad things. According to NatSemi VSA2 has another
244 * bug to do with 'hlt'. I've not seen any boards using VSA2
245 * and X doesn't seem to support it either so who cares 8).
246 * VSA1 we work around however.
249 printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
250 isa_dma_bridge_buggy = 2;
252 /* We do this before the PCI layer is running. However we
253 are safe here as we know the bridge must be a Cyrix
254 companion and must be present */
255 vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
256 device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
259 * The 5510/5520 companion chips have a funky PIT.
261 if (vendor == PCI_VENDOR_ID_CYRIX &&
262 (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520))
263 mark_tsc_unstable("cyrix 5510/5520 detected");
266 c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */
268 /* GXm supports extended cpuid levels 'ala' AMD */
269 if (c->cpuid_level == 2) {
270 /* Enable cxMMX extensions (GX1 Datasheet 54) */
271 setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
274 * GXm : 0x30 ... 0x5f GXm datasheet 51
275 * GXlv: 0x6x GXlv datasheet 54
277 * GX1 : 0x8x GX1 datasheet 56
279 if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f))
281 get_model_name(c); /* get CPU marketing name */
283 } else { /* MediaGX */
284 Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
286 c->x86_model = (dir1 & 0x20) ? 1 : 2;
290 case 5: /* 6x86MX/M II */
292 dir0_msn++; /* M II */
293 /* Enable MMX extensions (App note 108) */
294 setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
296 c->coma_bug = 1; /* 6x86MX, it has the bug. */
298 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
299 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
301 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
303 /* Emulate MTRRs using Cyrix's ARRs. */
304 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
307 case 0xf: /* Cyrix 486 without DEVID registers */
309 case 0xd: /* either a 486SLC or DLC w/o DEVID */
311 p = Cx486_name[(c->hard_math) ? 1 : 0];
314 case 0xe: /* a 486S A step */
321 default: /* unknown (shouldn't happen, we know everyone ;-) */
325 strcpy(buf, Cx86_model[dir0_msn & 7]);
332 * Handle National Semiconductor branded processors
334 static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
337 * There may be GX1 processors in the wild that are branded
340 * This function only handles the GX processor, and kicks every
341 * thing else to the Cyrix init function above - that should
342 * cover any processors that might have been branded differently
343 * after NSC acquired Cyrix.
345 * If this breaks your GX1 horribly, please e-mail
346 * info-linux@ldcmail.amd.com to tell us.
349 /* Handle the GX (Formally known as the GX2) */
351 if (c->x86 == 5 && c->x86_model == 5)
352 display_cacheinfo(c);
358 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
359 * by the fact that they preserve the flags across the division of 5/2.
360 * PII and PPro exhibit this behavior too, but they have cpuid available.
364 * Perform the Cyrix 5/2 test. A Cyrix won't change
365 * the flags, while other 486 chips will.
367 static inline int test_cyrix_52div(void)
371 __asm__ __volatile__(
372 "sahf\n\t" /* clear flags (%eax = 0x0005) */
373 "div %b2\n\t" /* divide 5 by 2 */
374 "lahf" /* store flags into %ah */
379 /* AH is 0x02 on Cyrix after the divide.. */
380 return (unsigned char) (test >> 8) == 0x02;
383 static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
385 /* Detect Cyrix with disabled CPUID */
386 if (c->x86 == 4 && test_cyrix_52div()) {
387 unsigned char dir0, dir1;
389 strcpy(c->x86_vendor_id, "CyrixInstead");
390 c->x86_vendor = X86_VENDOR_CYRIX;
392 /* Actually enable cpuid on the older cyrix */
394 /* Retrieve CPU revisions */
396 do_cyrix_devid(&dir0, &dir1);
400 /* Check it is an affected model */
402 if (dir0 == 5 || dir0 == 3) {
405 printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
406 local_irq_save(flags);
407 ccr3 = getCx86(CX86_CCR3);
408 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
409 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80); /* enable cpuid */
410 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
411 local_irq_restore(flags);
416 static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
418 .c_ident = { "CyrixInstead" },
419 .c_init = init_cyrix,
420 .c_identify = cyrix_identify,
423 cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev);
425 static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
427 .c_ident = { "Geode by NSC" },
431 cpu_vendor_dev_register(X86_VENDOR_NSC, &nsc_cpu_dev);