Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6] / drivers / gpu / drm / radeon / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5  * Copyright 2007 Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *    Kevin E. Martin <martin@valinux.com>
29  *    Gareth Hughes <gareth@valinux.com>
30  */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
36 #include "r300_reg.h"
37
38 #include "radeon_microcode.h"
39
40 #define RADEON_FIFO_DEBUG       0
41
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
43 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
44
45 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
46 {
47         u32 ret;
48         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
49         ret = RADEON_READ(R520_MC_IND_DATA);
50         RADEON_WRITE(R520_MC_IND_INDEX, 0);
51         return ret;
52 }
53
54 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
55 {
56         u32 ret;
57         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
58         ret = RADEON_READ(RS480_NB_MC_DATA);
59         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
60         return ret;
61 }
62
63 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
64 {
65         u32 ret;
66         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
67         ret = RADEON_READ(RS690_MC_DATA);
68         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
69         return ret;
70 }
71
72 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73 {
74         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
75                 return RS690_READ_MCIND(dev_priv, addr);
76         else
77                 return RS480_READ_MCIND(dev_priv, addr);
78 }
79
80 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
81 {
82
83         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
84                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
85         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
86                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
87         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
88                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
89         else
90                 return RADEON_READ(RADEON_MC_FB_LOCATION);
91 }
92
93 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
94 {
95         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
96                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
97         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
98                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
99         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
100                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
101         else
102                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
103 }
104
105 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
106 {
107         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
108                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
109         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
110                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
111         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
112                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
113         else
114                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
115 }
116
117 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
118 {
119         u32 agp_base_hi = upper_32_bits(agp_base);
120         u32 agp_base_lo = agp_base & 0xffffffff;
121
122         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
123                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
124                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
125         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
126                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
127                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
128         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
129                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
130                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
131         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
132                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
133                 RADEON_WRITE(RS480_AGP_BASE_2, 0);
134         } else {
135                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
136                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
137                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
138         }
139 }
140
141 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
142 {
143         drm_radeon_private_t *dev_priv = dev->dev_private;
144
145         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
146         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
147 }
148
149 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
150 {
151         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
152         return RADEON_READ(RADEON_PCIE_DATA);
153 }
154
155 #if RADEON_FIFO_DEBUG
156 static void radeon_status(drm_radeon_private_t * dev_priv)
157 {
158         printk("%s:\n", __func__);
159         printk("RBBM_STATUS = 0x%08x\n",
160                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
161         printk("CP_RB_RTPR = 0x%08x\n",
162                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
163         printk("CP_RB_WTPR = 0x%08x\n",
164                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
165         printk("AIC_CNTL = 0x%08x\n",
166                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
167         printk("AIC_STAT = 0x%08x\n",
168                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
169         printk("AIC_PT_BASE = 0x%08x\n",
170                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
171         printk("TLB_ADDR = 0x%08x\n",
172                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
173         printk("TLB_DATA = 0x%08x\n",
174                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
175 }
176 #endif
177
178 /* ================================================================
179  * Engine, FIFO control
180  */
181
182 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
183 {
184         u32 tmp;
185         int i;
186
187         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
188
189         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
190                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
191                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
192                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
193
194                 for (i = 0; i < dev_priv->usec_timeout; i++) {
195                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
196                               & RADEON_RB3D_DC_BUSY)) {
197                                 return 0;
198                         }
199                         DRM_UDELAY(1);
200                 }
201         } else {
202                 /* don't flush or purge cache here or lockup */
203                 return 0;
204         }
205
206 #if RADEON_FIFO_DEBUG
207         DRM_ERROR("failed!\n");
208         radeon_status(dev_priv);
209 #endif
210         return -EBUSY;
211 }
212
213 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
214 {
215         int i;
216
217         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
218
219         for (i = 0; i < dev_priv->usec_timeout; i++) {
220                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
221                              & RADEON_RBBM_FIFOCNT_MASK);
222                 if (slots >= entries)
223                         return 0;
224                 DRM_UDELAY(1);
225         }
226         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
227                  RADEON_READ(RADEON_RBBM_STATUS),
228                  RADEON_READ(R300_VAP_CNTL_STATUS));
229
230 #if RADEON_FIFO_DEBUG
231         DRM_ERROR("failed!\n");
232         radeon_status(dev_priv);
233 #endif
234         return -EBUSY;
235 }
236
237 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
238 {
239         int i, ret;
240
241         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
242
243         ret = radeon_do_wait_for_fifo(dev_priv, 64);
244         if (ret)
245                 return ret;
246
247         for (i = 0; i < dev_priv->usec_timeout; i++) {
248                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
249                       & RADEON_RBBM_ACTIVE)) {
250                         radeon_do_pixcache_flush(dev_priv);
251                         return 0;
252                 }
253                 DRM_UDELAY(1);
254         }
255         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
256                  RADEON_READ(RADEON_RBBM_STATUS),
257                  RADEON_READ(R300_VAP_CNTL_STATUS));
258
259 #if RADEON_FIFO_DEBUG
260         DRM_ERROR("failed!\n");
261         radeon_status(dev_priv);
262 #endif
263         return -EBUSY;
264 }
265
266 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
267 {
268         uint32_t gb_tile_config, gb_pipe_sel = 0;
269
270         /* RS4xx/RS6xx/R4xx/R5xx */
271         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
272                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
273                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
274         } else {
275                 /* R3xx */
276                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
277                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
278                         dev_priv->num_gb_pipes = 2;
279                 } else {
280                         /* R3Vxx */
281                         dev_priv->num_gb_pipes = 1;
282                 }
283         }
284         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
285
286         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
287
288         switch (dev_priv->num_gb_pipes) {
289         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
290         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
291         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
292         default:
293         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
294         }
295
296         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
297                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
298                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
299         }
300         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
301         radeon_do_wait_for_idle(dev_priv);
302         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
303         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
304                                                R300_DC_AUTOFLUSH_ENABLE |
305                                                R300_DC_DC_DISABLE_IGNORE_PE));
306
307
308 }
309
310 /* ================================================================
311  * CP control, initialization
312  */
313
314 /* Load the microcode for the CP */
315 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
316 {
317         int i;
318         DRM_DEBUG("\n");
319
320         radeon_do_wait_for_idle(dev_priv);
321
322         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
323         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
324             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
325             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
326             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
327             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
328                 DRM_INFO("Loading R100 Microcode\n");
329                 for (i = 0; i < 256; i++) {
330                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
331                                      R100_cp_microcode[i][1]);
332                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
333                                      R100_cp_microcode[i][0]);
334                 }
335         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
336                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
337                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
338                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
339                 DRM_INFO("Loading R200 Microcode\n");
340                 for (i = 0; i < 256; i++) {
341                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
342                                      R200_cp_microcode[i][1]);
343                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
344                                      R200_cp_microcode[i][0]);
345                 }
346         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
347                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
348                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
349                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
350                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
351                 DRM_INFO("Loading R300 Microcode\n");
352                 for (i = 0; i < 256; i++) {
353                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
354                                      R300_cp_microcode[i][1]);
355                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
356                                      R300_cp_microcode[i][0]);
357                 }
358         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
359                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
360                 DRM_INFO("Loading R400 Microcode\n");
361                 for (i = 0; i < 256; i++) {
362                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
363                                      R420_cp_microcode[i][1]);
364                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
365                                      R420_cp_microcode[i][0]);
366                 }
367         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
368                 DRM_INFO("Loading RS690 Microcode\n");
369                 for (i = 0; i < 256; i++) {
370                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
371                                      RS690_cp_microcode[i][1]);
372                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
373                                      RS690_cp_microcode[i][0]);
374                 }
375         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
376                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
377                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
378                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
379                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
380                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
381                 DRM_INFO("Loading R500 Microcode\n");
382                 for (i = 0; i < 256; i++) {
383                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
384                                      R520_cp_microcode[i][1]);
385                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
386                                      R520_cp_microcode[i][0]);
387                 }
388         }
389 }
390
391 /* Flush any pending commands to the CP.  This should only be used just
392  * prior to a wait for idle, as it informs the engine that the command
393  * stream is ending.
394  */
395 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
396 {
397         DRM_DEBUG("\n");
398 #if 0
399         u32 tmp;
400
401         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
402         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
403 #endif
404 }
405
406 /* Wait for the CP to go idle.
407  */
408 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
409 {
410         RING_LOCALS;
411         DRM_DEBUG("\n");
412
413         BEGIN_RING(6);
414
415         RADEON_PURGE_CACHE();
416         RADEON_PURGE_ZCACHE();
417         RADEON_WAIT_UNTIL_IDLE();
418
419         ADVANCE_RING();
420         COMMIT_RING();
421
422         return radeon_do_wait_for_idle(dev_priv);
423 }
424
425 /* Start the Command Processor.
426  */
427 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
428 {
429         RING_LOCALS;
430         DRM_DEBUG("\n");
431
432         radeon_do_wait_for_idle(dev_priv);
433
434         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
435
436         dev_priv->cp_running = 1;
437
438         BEGIN_RING(8);
439         /* isync can only be written through cp on r5xx write it here */
440         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
441         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
442                  RADEON_ISYNC_ANY3D_IDLE2D |
443                  RADEON_ISYNC_WAIT_IDLEGUI |
444                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
445         RADEON_PURGE_CACHE();
446         RADEON_PURGE_ZCACHE();
447         RADEON_WAIT_UNTIL_IDLE();
448         ADVANCE_RING();
449         COMMIT_RING();
450
451         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
452 }
453
454 /* Reset the Command Processor.  This will not flush any pending
455  * commands, so you must wait for the CP command stream to complete
456  * before calling this routine.
457  */
458 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
459 {
460         u32 cur_read_ptr;
461         DRM_DEBUG("\n");
462
463         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
464         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
465         SET_RING_HEAD(dev_priv, cur_read_ptr);
466         dev_priv->ring.tail = cur_read_ptr;
467 }
468
469 /* Stop the Command Processor.  This will not flush any pending
470  * commands, so you must flush the command stream and wait for the CP
471  * to go idle before calling this routine.
472  */
473 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
474 {
475         DRM_DEBUG("\n");
476
477         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
478
479         dev_priv->cp_running = 0;
480 }
481
482 /* Reset the engine.  This will stop the CP if it is running.
483  */
484 static int radeon_do_engine_reset(struct drm_device * dev)
485 {
486         drm_radeon_private_t *dev_priv = dev->dev_private;
487         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
488         DRM_DEBUG("\n");
489
490         radeon_do_pixcache_flush(dev_priv);
491
492         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
493                 /* may need something similar for newer chips */
494                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
495                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
496
497                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
498                                                     RADEON_FORCEON_MCLKA |
499                                                     RADEON_FORCEON_MCLKB |
500                                                     RADEON_FORCEON_YCLKA |
501                                                     RADEON_FORCEON_YCLKB |
502                                                     RADEON_FORCEON_MC |
503                                                     RADEON_FORCEON_AIC));
504         }
505
506         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
507
508         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
509                                               RADEON_SOFT_RESET_CP |
510                                               RADEON_SOFT_RESET_HI |
511                                               RADEON_SOFT_RESET_SE |
512                                               RADEON_SOFT_RESET_RE |
513                                               RADEON_SOFT_RESET_PP |
514                                               RADEON_SOFT_RESET_E2 |
515                                               RADEON_SOFT_RESET_RB));
516         RADEON_READ(RADEON_RBBM_SOFT_RESET);
517         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
518                                               ~(RADEON_SOFT_RESET_CP |
519                                                 RADEON_SOFT_RESET_HI |
520                                                 RADEON_SOFT_RESET_SE |
521                                                 RADEON_SOFT_RESET_RE |
522                                                 RADEON_SOFT_RESET_PP |
523                                                 RADEON_SOFT_RESET_E2 |
524                                                 RADEON_SOFT_RESET_RB)));
525         RADEON_READ(RADEON_RBBM_SOFT_RESET);
526
527         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
528                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
529                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
530                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
531         }
532
533         /* setup the raster pipes */
534         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
535             radeon_init_pipes(dev_priv);
536
537         /* Reset the CP ring */
538         radeon_do_cp_reset(dev_priv);
539
540         /* The CP is no longer running after an engine reset */
541         dev_priv->cp_running = 0;
542
543         /* Reset any pending vertex, indirect buffers */
544         radeon_freelist_reset(dev);
545
546         return 0;
547 }
548
549 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
550                                        drm_radeon_private_t * dev_priv)
551 {
552         u32 ring_start, cur_read_ptr;
553         u32 tmp;
554
555         /* Initialize the memory controller. With new memory map, the fb location
556          * is not changed, it should have been properly initialized already. Part
557          * of the problem is that the code below is bogus, assuming the GART is
558          * always appended to the fb which is not necessarily the case
559          */
560         if (!dev_priv->new_memmap)
561                 radeon_write_fb_location(dev_priv,
562                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
563                              | (dev_priv->fb_location >> 16));
564
565 #if __OS_HAS_AGP
566         if (dev_priv->flags & RADEON_IS_AGP) {
567                 radeon_write_agp_base(dev_priv, dev->agp->base);
568
569                 radeon_write_agp_location(dev_priv,
570                              (((dev_priv->gart_vm_start - 1 +
571                                 dev_priv->gart_size) & 0xffff0000) |
572                               (dev_priv->gart_vm_start >> 16)));
573
574                 ring_start = (dev_priv->cp_ring->offset
575                               - dev->agp->base
576                               + dev_priv->gart_vm_start);
577         } else
578 #endif
579                 ring_start = (dev_priv->cp_ring->offset
580                               - (unsigned long)dev->sg->virtual
581                               + dev_priv->gart_vm_start);
582
583         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
584
585         /* Set the write pointer delay */
586         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
587
588         /* Initialize the ring buffer's read and write pointers */
589         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
590         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
591         SET_RING_HEAD(dev_priv, cur_read_ptr);
592         dev_priv->ring.tail = cur_read_ptr;
593
594 #if __OS_HAS_AGP
595         if (dev_priv->flags & RADEON_IS_AGP) {
596                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
597                              dev_priv->ring_rptr->offset
598                              - dev->agp->base + dev_priv->gart_vm_start);
599         } else
600 #endif
601         {
602                 struct drm_sg_mem *entry = dev->sg;
603                 unsigned long tmp_ofs, page_ofs;
604
605                 tmp_ofs = dev_priv->ring_rptr->offset -
606                                 (unsigned long)dev->sg->virtual;
607                 page_ofs = tmp_ofs >> PAGE_SHIFT;
608
609                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
610                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
611                           (unsigned long)entry->busaddr[page_ofs],
612                           entry->handle + tmp_ofs);
613         }
614
615         /* Set ring buffer size */
616 #ifdef __BIG_ENDIAN
617         RADEON_WRITE(RADEON_CP_RB_CNTL,
618                      RADEON_BUF_SWAP_32BIT |
619                      (dev_priv->ring.fetch_size_l2ow << 18) |
620                      (dev_priv->ring.rptr_update_l2qw << 8) |
621                      dev_priv->ring.size_l2qw);
622 #else
623         RADEON_WRITE(RADEON_CP_RB_CNTL,
624                      (dev_priv->ring.fetch_size_l2ow << 18) |
625                      (dev_priv->ring.rptr_update_l2qw << 8) |
626                      dev_priv->ring.size_l2qw);
627 #endif
628
629         /* Start with assuming that writeback doesn't work */
630         dev_priv->writeback_works = 0;
631
632         /* Initialize the scratch register pointer.  This will cause
633          * the scratch register values to be written out to memory
634          * whenever they are updated.
635          *
636          * We simply put this behind the ring read pointer, this works
637          * with PCI GART as well as (whatever kind of) AGP GART
638          */
639         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
640                      + RADEON_SCRATCH_REG_OFFSET);
641
642         dev_priv->scratch = ((__volatile__ u32 *)
643                              dev_priv->ring_rptr->handle +
644                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
645
646         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
647
648         /* Turn on bus mastering */
649         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
650         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
651
652         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
653         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
654
655         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
656         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
657                      dev_priv->sarea_priv->last_dispatch);
658
659         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
660         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
661
662         radeon_do_wait_for_idle(dev_priv);
663
664         /* Sync everything up */
665         RADEON_WRITE(RADEON_ISYNC_CNTL,
666                      (RADEON_ISYNC_ANY2D_IDLE3D |
667                       RADEON_ISYNC_ANY3D_IDLE2D |
668                       RADEON_ISYNC_WAIT_IDLEGUI |
669                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
670
671 }
672
673 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
674 {
675         u32 tmp;
676
677         /* Writeback doesn't seem to work everywhere, test it here and possibly
678          * enable it if it appears to work
679          */
680         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
681         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
682
683         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
684                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
685                     0xdeadbeef)
686                         break;
687                 DRM_UDELAY(1);
688         }
689
690         if (tmp < dev_priv->usec_timeout) {
691                 dev_priv->writeback_works = 1;
692                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
693         } else {
694                 dev_priv->writeback_works = 0;
695                 DRM_INFO("writeback test failed\n");
696         }
697         if (radeon_no_wb == 1) {
698                 dev_priv->writeback_works = 0;
699                 DRM_INFO("writeback forced off\n");
700         }
701
702         if (!dev_priv->writeback_works) {
703                 /* Disable writeback to avoid unnecessary bus master transfer */
704                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
705                              RADEON_RB_NO_UPDATE);
706                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
707         }
708 }
709
710 /* Enable or disable IGP GART on the chip */
711 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
712 {
713         u32 temp;
714
715         if (on) {
716                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
717                           dev_priv->gart_vm_start,
718                           (long)dev_priv->gart_info.bus_addr,
719                           dev_priv->gart_size);
720
721                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
722                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
723                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
724                                                              RS690_BLOCK_GFX_D3_EN));
725                 else
726                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
727
728                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
729                                                                RS480_VA_SIZE_32MB));
730
731                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
732                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
733                                                         RS480_TLB_ENABLE |
734                                                         RS480_GTW_LAC_EN |
735                                                         RS480_1LEVEL_GART));
736
737                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
738                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
739                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
740
741                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
742                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
743                                                       RS480_REQ_TYPE_SNOOP_DIS));
744
745                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
746
747                 dev_priv->gart_size = 32*1024*1024;
748                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
749                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
750
751                 radeon_write_agp_location(dev_priv, temp);
752
753                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
754                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
755                                                                RS480_VA_SIZE_32MB));
756
757                 do {
758                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
759                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
760                                 break;
761                         DRM_UDELAY(1);
762                 } while (1);
763
764                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
765                                 RS480_GART_CACHE_INVALIDATE);
766
767                 do {
768                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
769                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
770                                 break;
771                         DRM_UDELAY(1);
772                 } while (1);
773
774                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
775         } else {
776                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
777         }
778 }
779
780 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
781 {
782         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
783         if (on) {
784
785                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
786                           dev_priv->gart_vm_start,
787                           (long)dev_priv->gart_info.bus_addr,
788                           dev_priv->gart_size);
789                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
790                                   dev_priv->gart_vm_start);
791                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
792                                   dev_priv->gart_info.bus_addr);
793                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
794                                   dev_priv->gart_vm_start);
795                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
796                                   dev_priv->gart_vm_start +
797                                   dev_priv->gart_size - 1);
798
799                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
800
801                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
802                                   RADEON_PCIE_TX_GART_EN);
803         } else {
804                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
805                                   tmp & ~RADEON_PCIE_TX_GART_EN);
806         }
807 }
808
809 /* Enable or disable PCI GART on the chip */
810 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
811 {
812         u32 tmp;
813
814         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
815             (dev_priv->flags & RADEON_IS_IGPGART)) {
816                 radeon_set_igpgart(dev_priv, on);
817                 return;
818         }
819
820         if (dev_priv->flags & RADEON_IS_PCIE) {
821                 radeon_set_pciegart(dev_priv, on);
822                 return;
823         }
824
825         tmp = RADEON_READ(RADEON_AIC_CNTL);
826
827         if (on) {
828                 RADEON_WRITE(RADEON_AIC_CNTL,
829                              tmp | RADEON_PCIGART_TRANSLATE_EN);
830
831                 /* set PCI GART page-table base address
832                  */
833                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
834
835                 /* set address range for PCI address translate
836                  */
837                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
838                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
839                              + dev_priv->gart_size - 1);
840
841                 /* Turn off AGP aperture -- is this required for PCI GART?
842                  */
843                 radeon_write_agp_location(dev_priv, 0xffffffc0);
844                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
845         } else {
846                 RADEON_WRITE(RADEON_AIC_CNTL,
847                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
848         }
849 }
850
851 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
852 {
853         drm_radeon_private_t *dev_priv = dev->dev_private;
854
855         DRM_DEBUG("\n");
856
857         /* if we require new memory map but we don't have it fail */
858         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
859                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
860                 radeon_do_cleanup_cp(dev);
861                 return -EINVAL;
862         }
863
864         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
865                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
866                 dev_priv->flags &= ~RADEON_IS_AGP;
867         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
868                    && !init->is_pci) {
869                 DRM_DEBUG("Restoring AGP flag\n");
870                 dev_priv->flags |= RADEON_IS_AGP;
871         }
872
873         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
874                 DRM_ERROR("PCI GART memory not allocated!\n");
875                 radeon_do_cleanup_cp(dev);
876                 return -EINVAL;
877         }
878
879         dev_priv->usec_timeout = init->usec_timeout;
880         if (dev_priv->usec_timeout < 1 ||
881             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
882                 DRM_DEBUG("TIMEOUT problem!\n");
883                 radeon_do_cleanup_cp(dev);
884                 return -EINVAL;
885         }
886
887         /* Enable vblank on CRTC1 for older X servers
888          */
889         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
890
891         switch(init->func) {
892         case RADEON_INIT_R200_CP:
893                 dev_priv->microcode_version = UCODE_R200;
894                 break;
895         case RADEON_INIT_R300_CP:
896                 dev_priv->microcode_version = UCODE_R300;
897                 break;
898         default:
899                 dev_priv->microcode_version = UCODE_R100;
900         }
901
902         dev_priv->do_boxes = 0;
903         dev_priv->cp_mode = init->cp_mode;
904
905         /* We don't support anything other than bus-mastering ring mode,
906          * but the ring can be in either AGP or PCI space for the ring
907          * read pointer.
908          */
909         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
910             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
911                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
912                 radeon_do_cleanup_cp(dev);
913                 return -EINVAL;
914         }
915
916         switch (init->fb_bpp) {
917         case 16:
918                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
919                 break;
920         case 32:
921         default:
922                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
923                 break;
924         }
925         dev_priv->front_offset = init->front_offset;
926         dev_priv->front_pitch = init->front_pitch;
927         dev_priv->back_offset = init->back_offset;
928         dev_priv->back_pitch = init->back_pitch;
929
930         switch (init->depth_bpp) {
931         case 16:
932                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
933                 break;
934         case 32:
935         default:
936                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
937                 break;
938         }
939         dev_priv->depth_offset = init->depth_offset;
940         dev_priv->depth_pitch = init->depth_pitch;
941
942         /* Hardware state for depth clears.  Remove this if/when we no
943          * longer clear the depth buffer with a 3D rectangle.  Hard-code
944          * all values to prevent unwanted 3D state from slipping through
945          * and screwing with the clear operation.
946          */
947         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
948                                            (dev_priv->color_fmt << 10) |
949                                            (dev_priv->microcode_version ==
950                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
951
952         dev_priv->depth_clear.rb3d_zstencilcntl =
953             (dev_priv->depth_fmt |
954              RADEON_Z_TEST_ALWAYS |
955              RADEON_STENCIL_TEST_ALWAYS |
956              RADEON_STENCIL_S_FAIL_REPLACE |
957              RADEON_STENCIL_ZPASS_REPLACE |
958              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
959
960         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
961                                          RADEON_BFACE_SOLID |
962                                          RADEON_FFACE_SOLID |
963                                          RADEON_FLAT_SHADE_VTX_LAST |
964                                          RADEON_DIFFUSE_SHADE_FLAT |
965                                          RADEON_ALPHA_SHADE_FLAT |
966                                          RADEON_SPECULAR_SHADE_FLAT |
967                                          RADEON_FOG_SHADE_FLAT |
968                                          RADEON_VTX_PIX_CENTER_OGL |
969                                          RADEON_ROUND_MODE_TRUNC |
970                                          RADEON_ROUND_PREC_8TH_PIX);
971
972
973         dev_priv->ring_offset = init->ring_offset;
974         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
975         dev_priv->buffers_offset = init->buffers_offset;
976         dev_priv->gart_textures_offset = init->gart_textures_offset;
977
978         dev_priv->sarea = drm_getsarea(dev);
979         if (!dev_priv->sarea) {
980                 DRM_ERROR("could not find sarea!\n");
981                 radeon_do_cleanup_cp(dev);
982                 return -EINVAL;
983         }
984
985         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
986         if (!dev_priv->cp_ring) {
987                 DRM_ERROR("could not find cp ring region!\n");
988                 radeon_do_cleanup_cp(dev);
989                 return -EINVAL;
990         }
991         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
992         if (!dev_priv->ring_rptr) {
993                 DRM_ERROR("could not find ring read pointer!\n");
994                 radeon_do_cleanup_cp(dev);
995                 return -EINVAL;
996         }
997         dev->agp_buffer_token = init->buffers_offset;
998         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
999         if (!dev->agp_buffer_map) {
1000                 DRM_ERROR("could not find dma buffer region!\n");
1001                 radeon_do_cleanup_cp(dev);
1002                 return -EINVAL;
1003         }
1004
1005         if (init->gart_textures_offset) {
1006                 dev_priv->gart_textures =
1007                     drm_core_findmap(dev, init->gart_textures_offset);
1008                 if (!dev_priv->gart_textures) {
1009                         DRM_ERROR("could not find GART texture region!\n");
1010                         radeon_do_cleanup_cp(dev);
1011                         return -EINVAL;
1012                 }
1013         }
1014
1015         dev_priv->sarea_priv =
1016             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1017                                     init->sarea_priv_offset);
1018
1019 #if __OS_HAS_AGP
1020         if (dev_priv->flags & RADEON_IS_AGP) {
1021                 drm_core_ioremap(dev_priv->cp_ring, dev);
1022                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1023                 drm_core_ioremap(dev->agp_buffer_map, dev);
1024                 if (!dev_priv->cp_ring->handle ||
1025                     !dev_priv->ring_rptr->handle ||
1026                     !dev->agp_buffer_map->handle) {
1027                         DRM_ERROR("could not find ioremap agp regions!\n");
1028                         radeon_do_cleanup_cp(dev);
1029                         return -EINVAL;
1030                 }
1031         } else
1032 #endif
1033         {
1034                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1035                 dev_priv->ring_rptr->handle =
1036                     (void *)dev_priv->ring_rptr->offset;
1037                 dev->agp_buffer_map->handle =
1038                     (void *)dev->agp_buffer_map->offset;
1039
1040                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1041                           dev_priv->cp_ring->handle);
1042                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1043                           dev_priv->ring_rptr->handle);
1044                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1045                           dev->agp_buffer_map->handle);
1046         }
1047
1048         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1049         dev_priv->fb_size =
1050                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1051                 - dev_priv->fb_location;
1052
1053         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1054                                         ((dev_priv->front_offset
1055                                           + dev_priv->fb_location) >> 10));
1056
1057         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1058                                        ((dev_priv->back_offset
1059                                          + dev_priv->fb_location) >> 10));
1060
1061         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1062                                         ((dev_priv->depth_offset
1063                                           + dev_priv->fb_location) >> 10));
1064
1065         dev_priv->gart_size = init->gart_size;
1066
1067         /* New let's set the memory map ... */
1068         if (dev_priv->new_memmap) {
1069                 u32 base = 0;
1070
1071                 DRM_INFO("Setting GART location based on new memory map\n");
1072
1073                 /* If using AGP, try to locate the AGP aperture at the same
1074                  * location in the card and on the bus, though we have to
1075                  * align it down.
1076                  */
1077 #if __OS_HAS_AGP
1078                 if (dev_priv->flags & RADEON_IS_AGP) {
1079                         base = dev->agp->base;
1080                         /* Check if valid */
1081                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1082                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1083                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1084                                          dev->agp->base);
1085                                 base = 0;
1086                         }
1087                 }
1088 #endif
1089                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1090                 if (base == 0) {
1091                         base = dev_priv->fb_location + dev_priv->fb_size;
1092                         if (base < dev_priv->fb_location ||
1093                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1094                                 base = dev_priv->fb_location
1095                                         - dev_priv->gart_size;
1096                 }
1097                 dev_priv->gart_vm_start = base & 0xffc00000u;
1098                 if (dev_priv->gart_vm_start != base)
1099                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1100                                  base, dev_priv->gart_vm_start);
1101         } else {
1102                 DRM_INFO("Setting GART location based on old memory map\n");
1103                 dev_priv->gart_vm_start = dev_priv->fb_location +
1104                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1105         }
1106
1107 #if __OS_HAS_AGP
1108         if (dev_priv->flags & RADEON_IS_AGP)
1109                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1110                                                  - dev->agp->base
1111                                                  + dev_priv->gart_vm_start);
1112         else
1113 #endif
1114                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1115                                         - (unsigned long)dev->sg->virtual
1116                                         + dev_priv->gart_vm_start);
1117
1118         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1119         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1120         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1121                   dev_priv->gart_buffers_offset);
1122
1123         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1124         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1125                               + init->ring_size / sizeof(u32));
1126         dev_priv->ring.size = init->ring_size;
1127         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1128
1129         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1130         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1131
1132         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1133         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1134         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1135
1136         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1137
1138 #if __OS_HAS_AGP
1139         if (dev_priv->flags & RADEON_IS_AGP) {
1140                 /* Turn off PCI GART */
1141                 radeon_set_pcigart(dev_priv, 0);
1142         } else
1143 #endif
1144         {
1145                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1146                 /* if we have an offset set from userspace */
1147                 if (dev_priv->pcigart_offset_set) {
1148                         dev_priv->gart_info.bus_addr =
1149                             dev_priv->pcigart_offset + dev_priv->fb_location;
1150                         dev_priv->gart_info.mapping.offset =
1151                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1152                         dev_priv->gart_info.mapping.size =
1153                             dev_priv->gart_info.table_size;
1154
1155                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1156                         dev_priv->gart_info.addr =
1157                             dev_priv->gart_info.mapping.handle;
1158
1159                         if (dev_priv->flags & RADEON_IS_PCIE)
1160                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1161                         else
1162                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1163                         dev_priv->gart_info.gart_table_location =
1164                             DRM_ATI_GART_FB;
1165
1166                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1167                                   dev_priv->gart_info.addr,
1168                                   dev_priv->pcigart_offset);
1169                 } else {
1170                         if (dev_priv->flags & RADEON_IS_IGPGART)
1171                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1172                         else
1173                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1174                         dev_priv->gart_info.gart_table_location =
1175                             DRM_ATI_GART_MAIN;
1176                         dev_priv->gart_info.addr = NULL;
1177                         dev_priv->gart_info.bus_addr = 0;
1178                         if (dev_priv->flags & RADEON_IS_PCIE) {
1179                                 DRM_ERROR
1180                                     ("Cannot use PCI Express without GART in FB memory\n");
1181                                 radeon_do_cleanup_cp(dev);
1182                                 return -EINVAL;
1183                         }
1184                 }
1185
1186                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1187                         DRM_ERROR("failed to init PCI GART!\n");
1188                         radeon_do_cleanup_cp(dev);
1189                         return -ENOMEM;
1190                 }
1191
1192                 /* Turn on PCI GART */
1193                 radeon_set_pcigart(dev_priv, 1);
1194         }
1195
1196         radeon_cp_load_microcode(dev_priv);
1197         radeon_cp_init_ring_buffer(dev, dev_priv);
1198
1199         dev_priv->last_buf = 0;
1200
1201         radeon_do_engine_reset(dev);
1202         radeon_test_writeback(dev_priv);
1203
1204         return 0;
1205 }
1206
1207 static int radeon_do_cleanup_cp(struct drm_device * dev)
1208 {
1209         drm_radeon_private_t *dev_priv = dev->dev_private;
1210         DRM_DEBUG("\n");
1211
1212         /* Make sure interrupts are disabled here because the uninstall ioctl
1213          * may not have been called from userspace and after dev_private
1214          * is freed, it's too late.
1215          */
1216         if (dev->irq_enabled)
1217                 drm_irq_uninstall(dev);
1218
1219 #if __OS_HAS_AGP
1220         if (dev_priv->flags & RADEON_IS_AGP) {
1221                 if (dev_priv->cp_ring != NULL) {
1222                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1223                         dev_priv->cp_ring = NULL;
1224                 }
1225                 if (dev_priv->ring_rptr != NULL) {
1226                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1227                         dev_priv->ring_rptr = NULL;
1228                 }
1229                 if (dev->agp_buffer_map != NULL) {
1230                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1231                         dev->agp_buffer_map = NULL;
1232                 }
1233         } else
1234 #endif
1235         {
1236
1237                 if (dev_priv->gart_info.bus_addr) {
1238                         /* Turn off PCI GART */
1239                         radeon_set_pcigart(dev_priv, 0);
1240                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1241                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1242                 }
1243
1244                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1245                 {
1246                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1247                         dev_priv->gart_info.addr = 0;
1248                 }
1249         }
1250         /* only clear to the start of flags */
1251         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1252
1253         return 0;
1254 }
1255
1256 /* This code will reinit the Radeon CP hardware after a resume from disc.
1257  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1258  * here we make sure that all Radeon hardware initialisation is re-done without
1259  * affecting running applications.
1260  *
1261  * Charl P. Botha <http://cpbotha.net>
1262  */
1263 static int radeon_do_resume_cp(struct drm_device * dev)
1264 {
1265         drm_radeon_private_t *dev_priv = dev->dev_private;
1266
1267         if (!dev_priv) {
1268                 DRM_ERROR("Called with no initialization\n");
1269                 return -EINVAL;
1270         }
1271
1272         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1273
1274 #if __OS_HAS_AGP
1275         if (dev_priv->flags & RADEON_IS_AGP) {
1276                 /* Turn off PCI GART */
1277                 radeon_set_pcigart(dev_priv, 0);
1278         } else
1279 #endif
1280         {
1281                 /* Turn on PCI GART */
1282                 radeon_set_pcigart(dev_priv, 1);
1283         }
1284
1285         radeon_cp_load_microcode(dev_priv);
1286         radeon_cp_init_ring_buffer(dev, dev_priv);
1287
1288         radeon_do_engine_reset(dev);
1289         radeon_enable_interrupt(dev);
1290
1291         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1292
1293         return 0;
1294 }
1295
1296 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1297 {
1298         drm_radeon_init_t *init = data;
1299
1300         LOCK_TEST_WITH_RETURN(dev, file_priv);
1301
1302         if (init->func == RADEON_INIT_R300_CP)
1303                 r300_init_reg_flags(dev);
1304
1305         switch (init->func) {
1306         case RADEON_INIT_CP:
1307         case RADEON_INIT_R200_CP:
1308         case RADEON_INIT_R300_CP:
1309                 return radeon_do_init_cp(dev, init);
1310         case RADEON_CLEANUP_CP:
1311                 return radeon_do_cleanup_cp(dev);
1312         }
1313
1314         return -EINVAL;
1315 }
1316
1317 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1318 {
1319         drm_radeon_private_t *dev_priv = dev->dev_private;
1320         DRM_DEBUG("\n");
1321
1322         LOCK_TEST_WITH_RETURN(dev, file_priv);
1323
1324         if (dev_priv->cp_running) {
1325                 DRM_DEBUG("while CP running\n");
1326                 return 0;
1327         }
1328         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1329                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1330                           dev_priv->cp_mode);
1331                 return 0;
1332         }
1333
1334         radeon_do_cp_start(dev_priv);
1335
1336         return 0;
1337 }
1338
1339 /* Stop the CP.  The engine must have been idled before calling this
1340  * routine.
1341  */
1342 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1343 {
1344         drm_radeon_private_t *dev_priv = dev->dev_private;
1345         drm_radeon_cp_stop_t *stop = data;
1346         int ret;
1347         DRM_DEBUG("\n");
1348
1349         LOCK_TEST_WITH_RETURN(dev, file_priv);
1350
1351         if (!dev_priv->cp_running)
1352                 return 0;
1353
1354         /* Flush any pending CP commands.  This ensures any outstanding
1355          * commands are exectuted by the engine before we turn it off.
1356          */
1357         if (stop->flush) {
1358                 radeon_do_cp_flush(dev_priv);
1359         }
1360
1361         /* If we fail to make the engine go idle, we return an error
1362          * code so that the DRM ioctl wrapper can try again.
1363          */
1364         if (stop->idle) {
1365                 ret = radeon_do_cp_idle(dev_priv);
1366                 if (ret)
1367                         return ret;
1368         }
1369
1370         /* Finally, we can turn off the CP.  If the engine isn't idle,
1371          * we will get some dropped triangles as they won't be fully
1372          * rendered before the CP is shut down.
1373          */
1374         radeon_do_cp_stop(dev_priv);
1375
1376         /* Reset the engine */
1377         radeon_do_engine_reset(dev);
1378
1379         return 0;
1380 }
1381
1382 void radeon_do_release(struct drm_device * dev)
1383 {
1384         drm_radeon_private_t *dev_priv = dev->dev_private;
1385         int i, ret;
1386
1387         if (dev_priv) {
1388                 if (dev_priv->cp_running) {
1389                         /* Stop the cp */
1390                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1391                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1392 #ifdef __linux__
1393                                 schedule();
1394 #else
1395                                 tsleep(&ret, PZERO, "rdnrel", 1);
1396 #endif
1397                         }
1398                         radeon_do_cp_stop(dev_priv);
1399                         radeon_do_engine_reset(dev);
1400                 }
1401
1402                 /* Disable *all* interrupts */
1403                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1404                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1405
1406                 if (dev_priv->mmio) {   /* remove all surfaces */
1407                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1408                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1409                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1410                                              16 * i, 0);
1411                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1412                                              16 * i, 0);
1413                         }
1414                 }
1415
1416                 /* Free memory heap structures */
1417                 radeon_mem_takedown(&(dev_priv->gart_heap));
1418                 radeon_mem_takedown(&(dev_priv->fb_heap));
1419
1420                 /* deallocate kernel resources */
1421                 radeon_do_cleanup_cp(dev);
1422         }
1423 }
1424
1425 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1426  */
1427 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1428 {
1429         drm_radeon_private_t *dev_priv = dev->dev_private;
1430         DRM_DEBUG("\n");
1431
1432         LOCK_TEST_WITH_RETURN(dev, file_priv);
1433
1434         if (!dev_priv) {
1435                 DRM_DEBUG("called before init done\n");
1436                 return -EINVAL;
1437         }
1438
1439         radeon_do_cp_reset(dev_priv);
1440
1441         /* The CP is no longer running after an engine reset */
1442         dev_priv->cp_running = 0;
1443
1444         return 0;
1445 }
1446
1447 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1448 {
1449         drm_radeon_private_t *dev_priv = dev->dev_private;
1450         DRM_DEBUG("\n");
1451
1452         LOCK_TEST_WITH_RETURN(dev, file_priv);
1453
1454         return radeon_do_cp_idle(dev_priv);
1455 }
1456
1457 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1458  */
1459 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1460 {
1461
1462         return radeon_do_resume_cp(dev);
1463 }
1464
1465 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1466 {
1467         DRM_DEBUG("\n");
1468
1469         LOCK_TEST_WITH_RETURN(dev, file_priv);
1470
1471         return radeon_do_engine_reset(dev);
1472 }
1473
1474 /* ================================================================
1475  * Fullscreen mode
1476  */
1477
1478 /* KW: Deprecated to say the least:
1479  */
1480 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1481 {
1482         return 0;
1483 }
1484
1485 /* ================================================================
1486  * Freelist management
1487  */
1488
1489 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1490  *   bufs until freelist code is used.  Note this hides a problem with
1491  *   the scratch register * (used to keep track of last buffer
1492  *   completed) being written to before * the last buffer has actually
1493  *   completed rendering.
1494  *
1495  * KW:  It's also a good way to find free buffers quickly.
1496  *
1497  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1498  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1499  * we essentially have to do this, else old clients will break.
1500  *
1501  * However, it does leave open a potential deadlock where all the
1502  * buffers are held by other clients, which can't release them because
1503  * they can't get the lock.
1504  */
1505
1506 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1507 {
1508         struct drm_device_dma *dma = dev->dma;
1509         drm_radeon_private_t *dev_priv = dev->dev_private;
1510         drm_radeon_buf_priv_t *buf_priv;
1511         struct drm_buf *buf;
1512         int i, t;
1513         int start;
1514
1515         if (++dev_priv->last_buf >= dma->buf_count)
1516                 dev_priv->last_buf = 0;
1517
1518         start = dev_priv->last_buf;
1519
1520         for (t = 0; t < dev_priv->usec_timeout; t++) {
1521                 u32 done_age = GET_SCRATCH(1);
1522                 DRM_DEBUG("done_age = %d\n", done_age);
1523                 for (i = start; i < dma->buf_count; i++) {
1524                         buf = dma->buflist[i];
1525                         buf_priv = buf->dev_private;
1526                         if (buf->file_priv == NULL || (buf->pending &&
1527                                                        buf_priv->age <=
1528                                                        done_age)) {
1529                                 dev_priv->stats.requested_bufs++;
1530                                 buf->pending = 0;
1531                                 return buf;
1532                         }
1533                         start = 0;
1534                 }
1535
1536                 if (t) {
1537                         DRM_UDELAY(1);
1538                         dev_priv->stats.freelist_loops++;
1539                 }
1540         }
1541
1542         DRM_DEBUG("returning NULL!\n");
1543         return NULL;
1544 }
1545
1546 #if 0
1547 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1548 {
1549         struct drm_device_dma *dma = dev->dma;
1550         drm_radeon_private_t *dev_priv = dev->dev_private;
1551         drm_radeon_buf_priv_t *buf_priv;
1552         struct drm_buf *buf;
1553         int i, t;
1554         int start;
1555         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1556
1557         if (++dev_priv->last_buf >= dma->buf_count)
1558                 dev_priv->last_buf = 0;
1559
1560         start = dev_priv->last_buf;
1561         dev_priv->stats.freelist_loops++;
1562
1563         for (t = 0; t < 2; t++) {
1564                 for (i = start; i < dma->buf_count; i++) {
1565                         buf = dma->buflist[i];
1566                         buf_priv = buf->dev_private;
1567                         if (buf->file_priv == 0 || (buf->pending &&
1568                                                     buf_priv->age <=
1569                                                     done_age)) {
1570                                 dev_priv->stats.requested_bufs++;
1571                                 buf->pending = 0;
1572                                 return buf;
1573                         }
1574                 }
1575                 start = 0;
1576         }
1577
1578         return NULL;
1579 }
1580 #endif
1581
1582 void radeon_freelist_reset(struct drm_device * dev)
1583 {
1584         struct drm_device_dma *dma = dev->dma;
1585         drm_radeon_private_t *dev_priv = dev->dev_private;
1586         int i;
1587
1588         dev_priv->last_buf = 0;
1589         for (i = 0; i < dma->buf_count; i++) {
1590                 struct drm_buf *buf = dma->buflist[i];
1591                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1592                 buf_priv->age = 0;
1593         }
1594 }
1595
1596 /* ================================================================
1597  * CP command submission
1598  */
1599
1600 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1601 {
1602         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1603         int i;
1604         u32 last_head = GET_RING_HEAD(dev_priv);
1605
1606         for (i = 0; i < dev_priv->usec_timeout; i++) {
1607                 u32 head = GET_RING_HEAD(dev_priv);
1608
1609                 ring->space = (head - ring->tail) * sizeof(u32);
1610                 if (ring->space <= 0)
1611                         ring->space += ring->size;
1612                 if (ring->space > n)
1613                         return 0;
1614
1615                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1616
1617                 if (head != last_head)
1618                         i = 0;
1619                 last_head = head;
1620
1621                 DRM_UDELAY(1);
1622         }
1623
1624         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1625 #if RADEON_FIFO_DEBUG
1626         radeon_status(dev_priv);
1627         DRM_ERROR("failed!\n");
1628 #endif
1629         return -EBUSY;
1630 }
1631
1632 static int radeon_cp_get_buffers(struct drm_device *dev,
1633                                  struct drm_file *file_priv,
1634                                  struct drm_dma * d)
1635 {
1636         int i;
1637         struct drm_buf *buf;
1638
1639         for (i = d->granted_count; i < d->request_count; i++) {
1640                 buf = radeon_freelist_get(dev);
1641                 if (!buf)
1642                         return -EBUSY;  /* NOTE: broken client */
1643
1644                 buf->file_priv = file_priv;
1645
1646                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1647                                      sizeof(buf->idx)))
1648                         return -EFAULT;
1649                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1650                                      sizeof(buf->total)))
1651                         return -EFAULT;
1652
1653                 d->granted_count++;
1654         }
1655         return 0;
1656 }
1657
1658 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1659 {
1660         struct drm_device_dma *dma = dev->dma;
1661         int ret = 0;
1662         struct drm_dma *d = data;
1663
1664         LOCK_TEST_WITH_RETURN(dev, file_priv);
1665
1666         /* Please don't send us buffers.
1667          */
1668         if (d->send_count != 0) {
1669                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1670                           DRM_CURRENTPID, d->send_count);
1671                 return -EINVAL;
1672         }
1673
1674         /* We'll send you buffers.
1675          */
1676         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1677                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1678                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1679                 return -EINVAL;
1680         }
1681
1682         d->granted_count = 0;
1683
1684         if (d->request_count) {
1685                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1686         }
1687
1688         return ret;
1689 }
1690
1691 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1692 {
1693         drm_radeon_private_t *dev_priv;
1694         int ret = 0;
1695
1696         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1697         if (dev_priv == NULL)
1698                 return -ENOMEM;
1699
1700         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1701         dev->dev_private = (void *)dev_priv;
1702         dev_priv->flags = flags;
1703
1704         switch (flags & RADEON_FAMILY_MASK) {
1705         case CHIP_R100:
1706         case CHIP_RV200:
1707         case CHIP_R200:
1708         case CHIP_R300:
1709         case CHIP_R350:
1710         case CHIP_R420:
1711         case CHIP_RV410:
1712         case CHIP_RV515:
1713         case CHIP_R520:
1714         case CHIP_RV570:
1715         case CHIP_R580:
1716                 dev_priv->flags |= RADEON_HAS_HIERZ;
1717                 break;
1718         default:
1719                 /* all other chips have no hierarchical z buffer */
1720                 break;
1721         }
1722
1723         if (drm_device_is_agp(dev))
1724                 dev_priv->flags |= RADEON_IS_AGP;
1725         else if (drm_device_is_pcie(dev))
1726                 dev_priv->flags |= RADEON_IS_PCIE;
1727         else
1728                 dev_priv->flags |= RADEON_IS_PCI;
1729
1730         DRM_DEBUG("%s card detected\n",
1731                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1732         return ret;
1733 }
1734
1735 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1736  * have to find them.
1737  */
1738 int radeon_driver_firstopen(struct drm_device *dev)
1739 {
1740         int ret;
1741         drm_local_map_t *map;
1742         drm_radeon_private_t *dev_priv = dev->dev_private;
1743
1744         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1745
1746         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1747                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1748                          _DRM_READ_ONLY, &dev_priv->mmio);
1749         if (ret != 0)
1750                 return ret;
1751
1752         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1753         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1754                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1755                          _DRM_WRITE_COMBINING, &map);
1756         if (ret != 0)
1757                 return ret;
1758
1759         return 0;
1760 }
1761
1762 int radeon_driver_unload(struct drm_device *dev)
1763 {
1764         drm_radeon_private_t *dev_priv = dev->dev_private;
1765
1766         DRM_DEBUG("\n");
1767         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1768
1769         dev->dev_private = NULL;
1770         return 0;
1771 }