git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/io_apic_32.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/mc146818rtc.h>
  29 #include <linux/compiler.h>
  30 #include <linux/acpi.h>
  31 #include <linux/module.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/pci.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/timer.h>
  44 #include <asm/i8259.h>
  45 #include <asm/nmi.h>
  46 #include <asm/msidef.h>
  47 #include <asm/hypertransport.h>
  48
  49 #include <mach_apic.h>
  50 #include <mach_apicdef.h>
  51
  52 int (*ioapic_renumber_irq)(int ioapic, int irq);
  53 atomic_t irq_mis_count;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59 static DEFINE_SPINLOCK(vector_lock);
  60
  61 int timer_over_8254 __initdata = 1;
  62
  63 /*
  64  *      Is the SiS APIC rmw bug present ?
  65  *      -1 = don't know, 0 = no, 1 = yes
  66  */
  67 int sis_apic_bug = -1;
  68
  69 /*
  70  * # of IRQ routing registers
  71  */
  72 int nr_ioapic_registers[MAX_IO_APICS];
  73
  74 static int disable_timer_pin_1 __initdata;
  75
  76 /*
  77  * Rough estimation of how many shared IRQs there are, can
  78  * be changed anytime.
  79  */
  80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  82
  83 /*
  84  * This is performance-critical, we want to do it O(1)
  85  *
  86  * the indexing order of this array favors 1:1 mappings
  87  * between pins and IRQs.
  88  */
  89
  90 static struct irq_pin_list {
  91         int apic, pin, next;
  92 } irq_2_pin[PIN_MAP_SIZE];
  93
  94 struct io_apic {
  95         unsigned int index;
  96         unsigned int unused[3];
  97         unsigned int data;
  98 };
  99
 100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 101 {
 102         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 103                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 104 }
 105
 106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 107 {
 108         struct io_apic __iomem *io_apic = io_apic_base(apic);
 109         writel(reg, &io_apic->index);
 110         return readl(&io_apic->data);
 111 }
 112
 113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 114 {
 115         struct io_apic __iomem *io_apic = io_apic_base(apic);
 116         writel(reg, &io_apic->index);
 117         writel(value, &io_apic->data);
 118 }
 119
 120 /*
 121  * Re-write a value: to be used for read-modify-write
 122  * cycles where the read already set up the index register.
 123  *
 124  * Older SiS APIC requires we rewrite the index register
 125  */
 126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 127 {
 128         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 129         if (sis_apic_bug)
 130                 writel(reg, &io_apic->index);
 131         writel(value, &io_apic->data);
 132 }
 133
 134 union entry_union {
 135         struct { u32 w1, w2; };
 136         struct IO_APIC_route_entry entry;
 137 };
 138
 139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 140 {
 141         union entry_union eu;
 142         unsigned long flags;
 143         spin_lock_irqsave(&ioapic_lock, flags);
 144         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 145         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 146         spin_unlock_irqrestore(&ioapic_lock, flags);
 147         return eu.entry;
 148 }
 149
 150 /*
 151  * When we write a new IO APIC routing entry, we need to write the high
 152  * word first! If the mask bit in the low word is clear, we will enable
 153  * the interrupt, and we need to make sure the entry is fully populated
 154  * before that happens.
 155  */
 156 static void
 157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 158 {
 159         union entry_union eu;
 160         eu.entry = e;
 161         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 162         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 163 }
 164
 165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 166 {
 167         unsigned long flags;
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         __ioapic_write_entry(apic, pin, e);
 170         spin_unlock_irqrestore(&ioapic_lock, flags);
 171 }
 172
 173 /*
 174  * When we mask an IO APIC routing entry, we need to write the low
 175  * word first, in order to set the mask bit before we change the
 176  * high bits!
 177  */
 178 static void ioapic_mask_entry(int apic, int pin)
 179 {
 180         unsigned long flags;
 181         union entry_union eu = { .entry.mask = 1 };
 182
 183         spin_lock_irqsave(&ioapic_lock, flags);
 184         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 185         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 186         spin_unlock_irqrestore(&ioapic_lock, flags);
 187 }
 188
 189 /*
 190  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 191  * shared ISA-space IRQs, so we have to support them. We are super
 192  * fast in the common case, and fast for shared ISA-space IRQs.
 193  */
 194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 195 {
 196         static int first_free_entry = NR_IRQS;
 197         struct irq_pin_list *entry = irq_2_pin + irq;
 198
 199         while (entry->next)
 200                 entry = irq_2_pin + entry->next;
 201
 202         if (entry->pin != -1) {
 203                 entry->next = first_free_entry;
 204                 entry = irq_2_pin + entry->next;
 205                 if (++first_free_entry >= PIN_MAP_SIZE)
 206                         panic("io_apic.c: whoops");
 207         }
 208         entry->apic = apic;
 209         entry->pin = pin;
 210 }
 211
 212 /*
 213  * Reroute an IRQ to a different pin.
 214  */
 215 static void __init replace_pin_at_irq(unsigned int irq,
 216                                       int oldapic, int oldpin,
 217                                       int newapic, int newpin)
 218 {
 219         struct irq_pin_list *entry = irq_2_pin + irq;
 220
 221         while (1) {
 222                 if (entry->apic == oldapic && entry->pin == oldpin) {
 223                         entry->apic = newapic;
 224                         entry->pin = newpin;
 225                 }
 226                 if (!entry->next)
 227                         break;
 228                 entry = irq_2_pin + entry->next;
 229         }
 230 }
 231
 232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 233 {
 234         struct irq_pin_list *entry = irq_2_pin + irq;
 235         unsigned int pin, reg;
 236
 237         for (;;) {
 238                 pin = entry->pin;
 239                 if (pin == -1)
 240                         break;
 241                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 242                 reg &= ~disable;
 243                 reg |= enable;
 244                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 245                 if (!entry->next)
 246                         break;
 247                 entry = irq_2_pin + entry->next;
 248         }
 249 }
 250
 251 /* mask = 1 */
 252 static void __mask_IO_APIC_irq (unsigned int irq)
 253 {
 254         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 255 }
 256
 257 /* mask = 0 */
 258 static void __unmask_IO_APIC_irq (unsigned int irq)
 259 {
 260         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 261 }
 262
 263 /* mask = 1, trigger = 0 */
 264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 265 {
 266         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 267 }
 268
 269 /* mask = 0, trigger = 1 */
 270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 271 {
 272         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 273 }
 274
 275 static void mask_IO_APIC_irq (unsigned int irq)
 276 {
 277         unsigned long flags;
 278
 279         spin_lock_irqsave(&ioapic_lock, flags);
 280         __mask_IO_APIC_irq(irq);
 281         spin_unlock_irqrestore(&ioapic_lock, flags);
 282 }
 283
 284 static void unmask_IO_APIC_irq (unsigned int irq)
 285 {
 286         unsigned long flags;
 287
 288         spin_lock_irqsave(&ioapic_lock, flags);
 289         __unmask_IO_APIC_irq(irq);
 290         spin_unlock_irqrestore(&ioapic_lock, flags);
 291 }
 292
 293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 294 {
 295         struct IO_APIC_route_entry entry;
 296
 297         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 298         entry = ioapic_read_entry(apic, pin);
 299         if (entry.delivery_mode == dest_SMI)
 300                 return;
 301
 302         /*
 303          * Disable it in the IO-APIC irq-routing table:
 304          */
 305         ioapic_mask_entry(apic, pin);
 306 }
 307
 308 static void clear_IO_APIC (void)
 309 {
 310         int apic, pin;
 311
 312         for (apic = 0; apic < nr_ioapics; apic++)
 313                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 314                         clear_IO_APIC_pin(apic, pin);
 315 }
 316
 317 #ifdef CONFIG_SMP
 318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 319 {
 320         unsigned long flags;
 321         int pin;
 322         struct irq_pin_list *entry = irq_2_pin + irq;
 323         unsigned int apicid_value;
 324         cpumask_t tmp;
 325
 326         cpus_and(tmp, cpumask, cpu_online_map);
 327         if (cpus_empty(tmp))
 328                 tmp = TARGET_CPUS;
 329
 330         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 331
 332         apicid_value = cpu_mask_to_apicid(cpumask);
 333         /* Prepare to do the io_apic_write */
 334         apicid_value = apicid_value << 24;
 335         spin_lock_irqsave(&ioapic_lock, flags);
 336         for (;;) {
 337                 pin = entry->pin;
 338                 if (pin == -1)
 339                         break;
 340                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 341                 if (!entry->next)
 342                         break;
 343                 entry = irq_2_pin + entry->next;
 344         }
 345         irq_desc[irq].affinity = cpumask;
 346         spin_unlock_irqrestore(&ioapic_lock, flags);
 347 }
 348
 349 #if defined(CONFIG_IRQBALANCE)
 350 # include <asm/processor.h>     /* kernel_thread() */
 351 # include <linux/kernel_stat.h> /* kstat */
 352 # include <linux/slab.h>                /* kmalloc() */
 353 # include <linux/timer.h>
 354
 355 #define IRQBALANCE_CHECK_ARCH -999
 356 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 357 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 358 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 359 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 360
 361 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 362 static int physical_balance __read_mostly;
 363 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 364
 365 static struct irq_cpu_info {
 366         unsigned long * last_irq;
 367         unsigned long * irq_delta;
 368         unsigned long irq;
 369 } irq_cpu_data[NR_CPUS];
 370
 371 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 372 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 373 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 374
 375 #define IDLE_ENOUGH(cpu,now) \
 376         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 377
 378 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 379
 380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
 381
 382 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 383         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 384 };
 385
 386 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 387 {
 388         balance_irq_affinity[irq] = mask;
 389 }
 390
 391 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 392                         unsigned long now, int direction)
 393 {
 394         int search_idle = 1;
 395         int cpu = curr_cpu;
 396
 397         goto inside;
 398
 399         do {
 400                 if (unlikely(cpu == curr_cpu))
 401                         search_idle = 0;
 402 inside:
 403                 if (direction == 1) {
 404                         cpu++;
 405                         if (cpu >= NR_CPUS)
 406                                 cpu = 0;
 407                 } else {
 408                         cpu--;
 409                         if (cpu == -1)
 410                                 cpu = NR_CPUS-1;
 411                 }
 412         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 413                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 414
 415         return cpu;
 416 }
 417
 418 static inline void balance_irq(int cpu, int irq)
 419 {
 420         unsigned long now = jiffies;
 421         cpumask_t allowed_mask;
 422         unsigned int new_cpu;
 423
 424         if (irqbalance_disabled)
 425                 return;
 426
 427         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 428         new_cpu = move(cpu, allowed_mask, now, 1);
 429         if (cpu != new_cpu) {
 430                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 431         }
 432 }
 433
 434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 435 {
 436         int i, j;
 437
 438         for_each_online_cpu(i) {
 439                 for (j = 0; j < NR_IRQS; j++) {
 440                         if (!irq_desc[j].action)
 441                                 continue;
 442                         /* Is it a significant load ?  */
 443                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 444                                                 useful_load_threshold)
 445                                 continue;
 446                         balance_irq(i, j);
 447                 }
 448         }
 449         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 450                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 451         return;
 452 }
 453
 454 static void do_irq_balance(void)
 455 {
 456         int i, j;
 457         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 458         unsigned long move_this_load = 0;
 459         int max_loaded = 0, min_loaded = 0;
 460         int load;
 461         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 462         int selected_irq;
 463         int tmp_loaded, first_attempt = 1;
 464         unsigned long tmp_cpu_irq;
 465         unsigned long imbalance = 0;
 466         cpumask_t allowed_mask, target_cpu_mask, tmp;
 467
 468         for_each_possible_cpu(i) {
 469                 int package_index;
 470                 CPU_IRQ(i) = 0;
 471                 if (!cpu_online(i))
 472                         continue;
 473                 package_index = CPU_TO_PACKAGEINDEX(i);
 474                 for (j = 0; j < NR_IRQS; j++) {
 475                         unsigned long value_now, delta;
 476                         /* Is this an active IRQ or balancing disabled ? */
 477                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 478                                 continue;
 479                         if ( package_index == i )
 480                                 IRQ_DELTA(package_index,j) = 0;
 481                         /* Determine the total count per processor per IRQ */
 482                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 483
 484                         /* Determine the activity per processor per IRQ */
 485                         delta = value_now - LAST_CPU_IRQ(i,j);
 486
 487                         /* Update last_cpu_irq[][] for the next time */
 488                         LAST_CPU_IRQ(i,j) = value_now;
 489
 490                         /* Ignore IRQs whose rate is less than the clock */
 491                         if (delta < useful_load_threshold)
 492                                 continue;
 493                         /* update the load for the processor or package total */
 494                         IRQ_DELTA(package_index,j) += delta;
 495
 496                         /* Keep track of the higher numbered sibling as well */
 497                         if (i != package_index)
 498                                 CPU_IRQ(i) += delta;
 499                         /*
 500                          * We have sibling A and sibling B in the package
 501                          *
 502                          * cpu_irq[A] = load for cpu A + load for cpu B
 503                          * cpu_irq[B] = load for cpu B
 504                          */
 505                         CPU_IRQ(package_index) += delta;
 506                 }
 507         }
 508         /* Find the least loaded processor package */
 509         for_each_online_cpu(i) {
 510                 if (i != CPU_TO_PACKAGEINDEX(i))
 511                         continue;
 512                 if (min_cpu_irq > CPU_IRQ(i)) {
 513                         min_cpu_irq = CPU_IRQ(i);
 514                         min_loaded = i;
 515                 }
 516         }
 517         max_cpu_irq = ULONG_MAX;
 518
 519 tryanothercpu:
 520         /* Look for heaviest loaded processor.
 521          * We may come back to get the next heaviest loaded processor.
 522          * Skip processors with trivial loads.
 523          */
 524         tmp_cpu_irq = 0;
 525         tmp_loaded = -1;
 526         for_each_online_cpu(i) {
 527                 if (i != CPU_TO_PACKAGEINDEX(i))
 528                         continue;
 529                 if (max_cpu_irq <= CPU_IRQ(i))
 530                         continue;
 531                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 532                         tmp_cpu_irq = CPU_IRQ(i);
 533                         tmp_loaded = i;
 534                 }
 535         }
 536
 537         if (tmp_loaded == -1) {
 538          /* In the case of small number of heavy interrupt sources,
 539           * loading some of the cpus too much. We use Ingo's original
 540           * approach to rotate them around.
 541           */
 542                 if (!first_attempt && imbalance >= useful_load_threshold) {
 543                         rotate_irqs_among_cpus(useful_load_threshold);
 544                         return;
 545                 }
 546                 goto not_worth_the_effort;
 547         }
 548
 549         first_attempt = 0;              /* heaviest search */
 550         max_cpu_irq = tmp_cpu_irq;      /* load */
 551         max_loaded = tmp_loaded;        /* processor */
 552         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 553
 554         /* if imbalance is less than approx 10% of max load, then
 555          * observe diminishing returns action. - quit
 556          */
 557         if (imbalance < (max_cpu_irq >> 3))
 558                 goto not_worth_the_effort;
 559
 560 tryanotherirq:
 561         /* if we select an IRQ to move that can't go where we want, then
 562          * see if there is another one to try.
 563          */
 564         move_this_load = 0;
 565         selected_irq = -1;
 566         for (j = 0; j < NR_IRQS; j++) {
 567                 /* Is this an active IRQ? */
 568                 if (!irq_desc[j].action)
 569                         continue;
 570                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 571                         continue;
 572                 /* Try to find the IRQ that is closest to the imbalance
 573                  * without going over.
 574                  */
 575                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 576                         move_this_load = IRQ_DELTA(max_loaded,j);
 577                         selected_irq = j;
 578                 }
 579         }
 580         if (selected_irq == -1) {
 581                 goto tryanothercpu;
 582         }
 583
 584         imbalance = move_this_load;
 585
 586         /* For physical_balance case, we accumulated both load
 587          * values in the one of the siblings cpu_irq[],
 588          * to use the same code for physical and logical processors
 589          * as much as possible.
 590          *
 591          * NOTE: the cpu_irq[] array holds the sum of the load for
 592          * sibling A and sibling B in the slot for the lowest numbered
 593          * sibling (A), _AND_ the load for sibling B in the slot for
 594          * the higher numbered sibling.
 595          *
 596          * We seek the least loaded sibling by making the comparison
 597          * (A+B)/2 vs B
 598          */
 599         load = CPU_IRQ(min_loaded) >> 1;
 600         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
 601                 if (load > CPU_IRQ(j)) {
 602                         /* This won't change cpu_sibling_map[min_loaded] */
 603                         load = CPU_IRQ(j);
 604                         min_loaded = j;
 605                 }
 606         }
 607
 608         cpus_and(allowed_mask,
 609                 cpu_online_map,
 610                 balance_irq_affinity[selected_irq]);
 611         target_cpu_mask = cpumask_of_cpu(min_loaded);
 612         cpus_and(tmp, target_cpu_mask, allowed_mask);
 613
 614         if (!cpus_empty(tmp)) {
 615                 /* mark for change destination */
 616                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 617
 618                 /* Since we made a change, come back sooner to
 619                  * check for more variation.
 620                  */
 621                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 622                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 623                 return;
 624         }
 625         goto tryanotherirq;
 626
 627 not_worth_the_effort:
 628         /*
 629          * if we did not find an IRQ to move, then adjust the time interval
 630          * upward
 631          */
 632         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 633                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 634         return;
 635 }
 636
 637 static int balanced_irq(void *unused)
 638 {
 639         int i;
 640         unsigned long prev_balance_time = jiffies;
 641         long time_remaining = balanced_irq_interval;
 642
 643         /* push everything to CPU 0 to give us a starting point.  */
 644         for (i = 0 ; i < NR_IRQS ; i++) {
 645                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 646                 set_pending_irq(i, cpumask_of_cpu(0));
 647         }
 648
 649         set_freezable();
 650         for ( ; ; ) {
 651                 time_remaining = schedule_timeout_interruptible(time_remaining);
 652                 try_to_freeze();
 653                 if (time_after(jiffies,
 654                                 prev_balance_time+balanced_irq_interval)) {
 655                         preempt_disable();
 656                         do_irq_balance();
 657                         prev_balance_time = jiffies;
 658                         time_remaining = balanced_irq_interval;
 659                         preempt_enable();
 660                 }
 661         }
 662         return 0;
 663 }
 664
 665 static int __init balanced_irq_init(void)
 666 {
 667         int i;
 668         struct cpuinfo_x86 *c;
 669         cpumask_t tmp;
 670
 671         cpus_shift_right(tmp, cpu_online_map, 2);
 672         c = &boot_cpu_data;
 673         /* When not overwritten by the command line ask subarchitecture. */
 674         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 675                 irqbalance_disabled = NO_BALANCE_IRQ;
 676         if (irqbalance_disabled)
 677                 return 0;
 678
 679          /* disable irqbalance completely if there is only one processor online */
 680         if (num_online_cpus() < 2) {
 681                 irqbalance_disabled = 1;
 682                 return 0;
 683         }
 684         /*
 685          * Enable physical balance only if more than 1 physical processor
 686          * is present
 687          */
 688         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 689                 physical_balance = 1;
 690
 691         for_each_online_cpu(i) {
 692                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 693                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 694                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 695                         printk(KERN_ERR "balanced_irq_init: out of memory");
 696                         goto failed;
 697                 }
 698                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 699                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 700         }
 701
 702         printk(KERN_INFO "Starting balanced_irq\n");
 703         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
 704                 return 0;
 705         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 706 failed:
 707         for_each_possible_cpu(i) {
 708                 kfree(irq_cpu_data[i].irq_delta);
 709                 irq_cpu_data[i].irq_delta = NULL;
 710                 kfree(irq_cpu_data[i].last_irq);
 711                 irq_cpu_data[i].last_irq = NULL;
 712         }
 713         return 0;
 714 }
 715
 716 int __devinit irqbalance_disable(char *str)
 717 {
 718         irqbalance_disabled = 1;
 719         return 1;
 720 }
 721
 722 __setup("noirqbalance", irqbalance_disable);
 723
 724 late_initcall(balanced_irq_init);
 725 #endif /* CONFIG_IRQBALANCE */
 726 #endif /* CONFIG_SMP */
 727
 728 #ifndef CONFIG_SMP
 729 void send_IPI_self(int vector)
 730 {
 731         unsigned int cfg;
 732
 733         /*
 734          * Wait for idle.
 735          */
 736         apic_wait_icr_idle();
 737         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 738         /*
 739          * Send the IPI. The write to APIC_ICR fires this off.
 740          */
 741         apic_write_around(APIC_ICR, cfg);
 742 }
 743 #endif /* !CONFIG_SMP */
 744
 745
 746 /*
 747  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 748  * specific CPU-side IRQs.
 749  */
 750
 751 #define MAX_PIRQS 8
 752 static int pirq_entries [MAX_PIRQS];
 753 static int pirqs_enabled;
 754 int skip_ioapic_setup;
 755
 756 static int __init ioapic_pirq_setup(char *str)
 757 {
 758         int i, max;
 759         int ints[MAX_PIRQS+1];
 760
 761         get_options(str, ARRAY_SIZE(ints), ints);
 762
 763         for (i = 0; i < MAX_PIRQS; i++)
 764                 pirq_entries[i] = -1;
 765
 766         pirqs_enabled = 1;
 767         apic_printk(APIC_VERBOSE, KERN_INFO
 768                         "PIRQ redirection, working around broken MP-BIOS.\n");
 769         max = MAX_PIRQS;
 770         if (ints[0] < MAX_PIRQS)
 771                 max = ints[0];
 772
 773         for (i = 0; i < max; i++) {
 774                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 775                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 776                 /*
 777                  * PIRQs are mapped upside down, usually.
 778                  */
 779                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 780         }
 781         return 1;
 782 }
 783
 784 __setup("pirq=", ioapic_pirq_setup);
 785
 786 /*
 787  * Find the IRQ entry number of a certain pin.
 788  */
 789 static int find_irq_entry(int apic, int pin, int type)
 790 {
 791         int i;
 792
 793         for (i = 0; i < mp_irq_entries; i++)
 794                 if (mp_irqs[i].mpc_irqtype == type &&
 795                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 796                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 797                     mp_irqs[i].mpc_dstirq == pin)
 798                         return i;
 799
 800         return -1;
 801 }
 802
 803 /*
 804  * Find the pin to which IRQ[irq] (ISA) is connected
 805  */
 806 static int __init find_isa_irq_pin(int irq, int type)
 807 {
 808         int i;
 809
 810         for (i = 0; i < mp_irq_entries; i++) {
 811                 int lbus = mp_irqs[i].mpc_srcbus;
 812
 813                 if (test_bit(lbus, mp_bus_not_pci) &&
 814                     (mp_irqs[i].mpc_irqtype == type) &&
 815                     (mp_irqs[i].mpc_srcbusirq == irq))
 816
 817                         return mp_irqs[i].mpc_dstirq;
 818         }
 819         return -1;
 820 }
 821
 822 static int __init find_isa_irq_apic(int irq, int type)
 823 {
 824         int i;
 825
 826         for (i = 0; i < mp_irq_entries; i++) {
 827                 int lbus = mp_irqs[i].mpc_srcbus;
 828
 829                 if (test_bit(lbus, mp_bus_not_pci) &&
 830                     (mp_irqs[i].mpc_irqtype == type) &&
 831                     (mp_irqs[i].mpc_srcbusirq == irq))
 832                         break;
 833         }
 834         if (i < mp_irq_entries) {
 835                 int apic;
 836                 for(apic = 0; apic < nr_ioapics; apic++) {
 837                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 838                                 return apic;
 839                 }
 840         }
 841
 842         return -1;
 843 }
 844
 845 /*
 846  * Find a specific PCI IRQ entry.
 847  * Not an __init, possibly needed by modules
 848  */
 849 static int pin_2_irq(int idx, int apic, int pin);
 850
 851 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 852 {
 853         int apic, i, best_guess = -1;
 854
 855         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 856                 "slot:%d, pin:%d.\n", bus, slot, pin);
 857         if (mp_bus_id_to_pci_bus[bus] == -1) {
 858                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 859                 return -1;
 860         }
 861         for (i = 0; i < mp_irq_entries; i++) {
 862                 int lbus = mp_irqs[i].mpc_srcbus;
 863
 864                 for (apic = 0; apic < nr_ioapics; apic++)
 865                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 866                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 867                                 break;
 868
 869                 if (!test_bit(lbus, mp_bus_not_pci) &&
 870                     !mp_irqs[i].mpc_irqtype &&
 871                     (bus == lbus) &&
 872                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 873                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 874
 875                         if (!(apic || IO_APIC_IRQ(irq)))
 876                                 continue;
 877
 878                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 879                                 return irq;
 880                         /*
 881                          * Use the first all-but-pin matching entry as a
 882                          * best-guess fuzzy result for broken mptables.
 883                          */
 884                         if (best_guess < 0)
 885                                 best_guess = irq;
 886                 }
 887         }
 888         return best_guess;
 889 }
 890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 891
 892 /*
 893  * This function currently is only a helper for the i386 smp boot process where
 894  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 895  * so mask in all cases should simply be TARGET_CPUS
 896  */
 897 #ifdef CONFIG_SMP
 898 void __init setup_ioapic_dest(void)
 899 {
 900         int pin, ioapic, irq, irq_entry;
 901
 902         if (skip_ioapic_setup == 1)
 903                 return;
 904
 905         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 906                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 907                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 908                         if (irq_entry == -1)
 909                                 continue;
 910                         irq = pin_2_irq(irq_entry, ioapic, pin);
 911                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 912                 }
 913
 914         }
 915 }
 916 #endif
 917
 918 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
 919 /*
 920  * EISA Edge/Level control register, ELCR
 921  */
 922 static int EISA_ELCR(unsigned int irq)
 923 {
 924         if (irq < 16) {
 925                 unsigned int port = 0x4d0 + (irq >> 3);
 926                 return (inb(port) >> (irq & 7)) & 1;
 927         }
 928         apic_printk(APIC_VERBOSE, KERN_INFO
 929                         "Broken MPtable reports ISA irq %d\n", irq);
 930         return 0;
 931 }
 932 #endif
 933
 934 /* ISA interrupts are always polarity zero edge triggered,
 935  * when listed as conforming in the MP table. */
 936
 937 #define default_ISA_trigger(idx)        (0)
 938 #define default_ISA_polarity(idx)       (0)
 939
 940 /* EISA interrupts are always polarity zero and can be edge or level
 941  * trigger depending on the ELCR value.  If an interrupt is listed as
 942  * EISA conforming in the MP table, that means its trigger type must
 943  * be read in from the ELCR */
 944
 945 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 946 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 947
 948 /* PCI interrupts are always polarity one level triggered,
 949  * when listed as conforming in the MP table. */
 950
 951 #define default_PCI_trigger(idx)        (1)
 952 #define default_PCI_polarity(idx)       (1)
 953
 954 /* MCA interrupts are always polarity zero level triggered,
 955  * when listed as conforming in the MP table. */
 956
 957 #define default_MCA_trigger(idx)        (1)
 958 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
 959
 960 static int MPBIOS_polarity(int idx)
 961 {
 962         int bus = mp_irqs[idx].mpc_srcbus;
 963         int polarity;
 964
 965         /*
 966          * Determine IRQ line polarity (high active or low active):
 967          */
 968         switch (mp_irqs[idx].mpc_irqflag & 3)
 969         {
 970                 case 0: /* conforms, ie. bus-type dependent polarity */
 971                 {
 972                         polarity = test_bit(bus, mp_bus_not_pci)?
 973                                 default_ISA_polarity(idx):
 974                                 default_PCI_polarity(idx);
 975                         break;
 976                 }
 977                 case 1: /* high active */
 978                 {
 979                         polarity = 0;
 980                         break;
 981                 }
 982                 case 2: /* reserved */
 983                 {
 984                         printk(KERN_WARNING "broken BIOS!!\n");
 985                         polarity = 1;
 986                         break;
 987                 }
 988                 case 3: /* low active */
 989                 {
 990                         polarity = 1;
 991                         break;
 992                 }
 993                 default: /* invalid */
 994                 {
 995                         printk(KERN_WARNING "broken BIOS!!\n");
 996                         polarity = 1;
 997                         break;
 998                 }
 999         }
1000         return polarity;
1001 }
1002
1003 static int MPBIOS_trigger(int idx)
1004 {
1005         int bus = mp_irqs[idx].mpc_srcbus;
1006         int trigger;
1007
1008         /*
1009          * Determine IRQ trigger mode (edge or level sensitive):
1010          */
1011         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1012         {
1013                 case 0: /* conforms, ie. bus-type dependent */
1014                 {
1015                         trigger = test_bit(bus, mp_bus_not_pci)?
1016                                         default_ISA_trigger(idx):
1017                                         default_PCI_trigger(idx);
1018 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1019                         switch (mp_bus_id_to_type[bus])
1020                         {
1021                                 case MP_BUS_ISA: /* ISA pin */
1022                                 {
1023                                         /* set before the switch */
1024                                         break;
1025                                 }
1026                                 case MP_BUS_EISA: /* EISA pin */
1027                                 {
1028                                         trigger = default_EISA_trigger(idx);
1029                                         break;
1030                                 }
1031                                 case MP_BUS_PCI: /* PCI pin */
1032                                 {
1033                                         /* set before the switch */
1034                                         break;
1035                                 }
1036                                 case MP_BUS_MCA: /* MCA pin */
1037                                 {
1038                                         trigger = default_MCA_trigger(idx);
1039                                         break;
1040                                 }
1041                                 default:
1042                                 {
1043                                         printk(KERN_WARNING "broken BIOS!!\n");
1044                                         trigger = 1;
1045                                         break;
1046                                 }
1047                         }
1048 #endif
1049                         break;
1050                 }
1051                 case 1: /* edge */
1052                 {
1053                         trigger = 0;
1054                         break;
1055                 }
1056                 case 2: /* reserved */
1057                 {
1058                         printk(KERN_WARNING "broken BIOS!!\n");
1059                         trigger = 1;
1060                         break;
1061                 }
1062                 case 3: /* level */
1063                 {
1064                         trigger = 1;
1065                         break;
1066                 }
1067                 default: /* invalid */
1068                 {
1069                         printk(KERN_WARNING "broken BIOS!!\n");
1070                         trigger = 0;
1071                         break;
1072                 }
1073         }
1074         return trigger;
1075 }
1076
1077 static inline int irq_polarity(int idx)
1078 {
1079         return MPBIOS_polarity(idx);
1080 }
1081
1082 static inline int irq_trigger(int idx)
1083 {
1084         return MPBIOS_trigger(idx);
1085 }
1086
1087 static int pin_2_irq(int idx, int apic, int pin)
1088 {
1089         int irq, i;
1090         int bus = mp_irqs[idx].mpc_srcbus;
1091
1092         /*
1093          * Debugging check, we are in big trouble if this message pops up!
1094          */
1095         if (mp_irqs[idx].mpc_dstirq != pin)
1096                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1097
1098         if (test_bit(bus, mp_bus_not_pci))
1099                 irq = mp_irqs[idx].mpc_srcbusirq;
1100         else {
1101                 /*
1102                  * PCI IRQs are mapped in order
1103                  */
1104                 i = irq = 0;
1105                 while (i < apic)
1106                         irq += nr_ioapic_registers[i++];
1107                 irq += pin;
1108
1109                 /*
1110                  * For MPS mode, so far only needed by ES7000 platform
1111                  */
1112                 if (ioapic_renumber_irq)
1113                         irq = ioapic_renumber_irq(apic, irq);
1114         }
1115
1116         /*
1117          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1118          */
1119         if ((pin >= 16) && (pin <= 23)) {
1120                 if (pirq_entries[pin-16] != -1) {
1121                         if (!pirq_entries[pin-16]) {
1122                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1123                                                 "disabling PIRQ%d\n", pin-16);
1124                         } else {
1125                                 irq = pirq_entries[pin-16];
1126                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1127                                                 "using PIRQ%d -> IRQ %d\n",
1128                                                 pin-16, irq);
1129                         }
1130                 }
1131         }
1132         return irq;
1133 }
1134
1135 static inline int IO_APIC_irq_trigger(int irq)
1136 {
1137         int apic, idx, pin;
1138
1139         for (apic = 0; apic < nr_ioapics; apic++) {
1140                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1141                         idx = find_irq_entry(apic,pin,mp_INT);
1142                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1143                                 return irq_trigger(idx);
1144                 }
1145         }
1146         /*
1147          * nonexistent IRQs are edge default
1148          */
1149         return 0;
1150 }
1151
1152 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1153 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1154
1155 static int __assign_irq_vector(int irq)
1156 {
1157         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1158         int vector, offset;
1159
1160         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1161
1162         if (irq_vector[irq] > 0)
1163                 return irq_vector[irq];
1164
1165         vector = current_vector;
1166         offset = current_offset;
1167 next:
1168         vector += 8;
1169         if (vector >= FIRST_SYSTEM_VECTOR) {
1170                 offset = (offset + 1) % 8;
1171                 vector = FIRST_DEVICE_VECTOR + offset;
1172         }
1173         if (vector == current_vector)
1174                 return -ENOSPC;
1175         if (test_and_set_bit(vector, used_vectors))
1176                 goto next;
1177
1178         current_vector = vector;
1179         current_offset = offset;
1180         irq_vector[irq] = vector;
1181
1182         return vector;
1183 }
1184
1185 static int assign_irq_vector(int irq)
1186 {
1187         unsigned long flags;
1188         int vector;
1189
1190         spin_lock_irqsave(&vector_lock, flags);
1191         vector = __assign_irq_vector(irq);
1192         spin_unlock_irqrestore(&vector_lock, flags);
1193
1194         return vector;
1195 }
1196 static struct irq_chip ioapic_chip;
1197
1198 #define IOAPIC_AUTO     -1
1199 #define IOAPIC_EDGE     0
1200 #define IOAPIC_LEVEL    1
1201
1202 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1203 {
1204         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1205             trigger == IOAPIC_LEVEL) {
1206                 irq_desc[irq].status |= IRQ_LEVEL;
1207                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1208                                          handle_fasteoi_irq, "fasteoi");
1209         } else {
1210                 irq_desc[irq].status &= ~IRQ_LEVEL;
1211                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1212                                          handle_edge_irq, "edge");
1213         }
1214         set_intr_gate(vector, interrupt[irq]);
1215 }
1216
1217 static void __init setup_IO_APIC_irqs(void)
1218 {
1219         struct IO_APIC_route_entry entry;
1220         int apic, pin, idx, irq, first_notcon = 1, vector;
1221         unsigned long flags;
1222
1223         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1224
1225         for (apic = 0; apic < nr_ioapics; apic++) {
1226         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1227
1228                 /*
1229                  * add it to the IO-APIC irq-routing table:
1230                  */
1231                 memset(&entry,0,sizeof(entry));
1232
1233                 entry.delivery_mode = INT_DELIVERY_MODE;
1234                 entry.dest_mode = INT_DEST_MODE;
1235                 entry.mask = 0;                         /* enable IRQ */
1236                 entry.dest.logical.logical_dest =
1237                                         cpu_mask_to_apicid(TARGET_CPUS);
1238
1239                 idx = find_irq_entry(apic,pin,mp_INT);
1240                 if (idx == -1) {
1241                         if (first_notcon) {
1242                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1243                                                 " IO-APIC (apicid-pin) %d-%d",
1244                                                 mp_ioapics[apic].mpc_apicid,
1245                                                 pin);
1246                                 first_notcon = 0;
1247                         } else
1248                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1249                                         mp_ioapics[apic].mpc_apicid, pin);
1250                         continue;
1251                 }
1252
1253                 if (!first_notcon) {
1254                         apic_printk(APIC_VERBOSE, " not connected.\n");
1255                         first_notcon = 1;
1256                 }
1257
1258                 entry.trigger = irq_trigger(idx);
1259                 entry.polarity = irq_polarity(idx);
1260
1261                 if (irq_trigger(idx)) {
1262                         entry.trigger = 1;
1263                         entry.mask = 1;
1264                 }
1265
1266                 irq = pin_2_irq(idx, apic, pin);
1267                 /*
1268                  * skip adding the timer int on secondary nodes, which causes
1269                  * a small but painful rift in the time-space continuum
1270                  */
1271                 if (multi_timer_check(apic, irq))
1272                         continue;
1273                 else
1274                         add_pin_to_irq(irq, apic, pin);
1275
1276                 if (!apic && !IO_APIC_IRQ(irq))
1277                         continue;
1278
1279                 if (IO_APIC_IRQ(irq)) {
1280                         vector = assign_irq_vector(irq);
1281                         entry.vector = vector;
1282                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1283
1284                         if (!apic && (irq < 16))
1285                                 disable_8259A_irq(irq);
1286                 }
1287                 spin_lock_irqsave(&ioapic_lock, flags);
1288                 __ioapic_write_entry(apic, pin, entry);
1289                 spin_unlock_irqrestore(&ioapic_lock, flags);
1290         }
1291         }
1292
1293         if (!first_notcon)
1294                 apic_printk(APIC_VERBOSE, " not connected.\n");
1295 }
1296
1297 /*
1298  * Set up the 8259A-master output pin:
1299  */
1300 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1301 {
1302         struct IO_APIC_route_entry entry;
1303
1304         memset(&entry,0,sizeof(entry));
1305
1306         disable_8259A_irq(0);
1307
1308         /* mask LVT0 */
1309         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1310
1311         /*
1312          * We use logical delivery to get the timer IRQ
1313          * to the first CPU.
1314          */
1315         entry.dest_mode = INT_DEST_MODE;
1316         entry.mask = 0;                                 /* unmask IRQ now */
1317         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1318         entry.delivery_mode = INT_DELIVERY_MODE;
1319         entry.polarity = 0;
1320         entry.trigger = 0;
1321         entry.vector = vector;
1322
1323         /*
1324          * The timer IRQ doesn't have to know that behind the
1325          * scene we have a 8259A-master in AEOI mode ...
1326          */
1327         irq_desc[0].chip = &ioapic_chip;
1328         set_irq_handler(0, handle_edge_irq);
1329
1330         /*
1331          * Add it to the IO-APIC irq-routing table:
1332          */
1333         ioapic_write_entry(apic, pin, entry);
1334
1335         enable_8259A_irq(0);
1336 }
1337
1338 void __init print_IO_APIC(void)
1339 {
1340         int apic, i;
1341         union IO_APIC_reg_00 reg_00;
1342         union IO_APIC_reg_01 reg_01;
1343         union IO_APIC_reg_02 reg_02;
1344         union IO_APIC_reg_03 reg_03;
1345         unsigned long flags;
1346
1347         if (apic_verbosity == APIC_QUIET)
1348                 return;
1349
1350         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1351         for (i = 0; i < nr_ioapics; i++)
1352                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1353                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1354
1355         /*
1356          * We are a bit conservative about what we expect.  We have to
1357          * know about every hardware change ASAP.
1358          */
1359         printk(KERN_INFO "testing the IO APIC.......................\n");
1360
1361         for (apic = 0; apic < nr_ioapics; apic++) {
1362
1363         spin_lock_irqsave(&ioapic_lock, flags);
1364         reg_00.raw = io_apic_read(apic, 0);
1365         reg_01.raw = io_apic_read(apic, 1);
1366         if (reg_01.bits.version >= 0x10)
1367                 reg_02.raw = io_apic_read(apic, 2);
1368         if (reg_01.bits.version >= 0x20)
1369                 reg_03.raw = io_apic_read(apic, 3);
1370         spin_unlock_irqrestore(&ioapic_lock, flags);
1371
1372         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1373         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1374         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1375         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1376         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1377
1378         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1379         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1380
1381         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1382         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1383
1384         /*
1385          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1386          * but the value of reg_02 is read as the previous read register
1387          * value, so ignore it if reg_02 == reg_01.
1388          */
1389         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1390                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1391                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1392         }
1393
1394         /*
1395          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1396          * or reg_03, but the value of reg_0[23] is read as the previous read
1397          * register value, so ignore it if reg_03 == reg_0[12].
1398          */
1399         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1400             reg_03.raw != reg_01.raw) {
1401                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1402                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1403         }
1404
1405         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1406
1407         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1408                           " Stat Dest Deli Vect:   \n");
1409
1410         for (i = 0; i <= reg_01.bits.entries; i++) {
1411                 struct IO_APIC_route_entry entry;
1412
1413                 entry = ioapic_read_entry(apic, i);
1414
1415                 printk(KERN_DEBUG " %02x %03X %02X  ",
1416                         i,
1417                         entry.dest.logical.logical_dest,
1418                         entry.dest.physical.physical_dest
1419                 );
1420
1421                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1422                         entry.mask,
1423                         entry.trigger,
1424                         entry.irr,
1425                         entry.polarity,
1426                         entry.delivery_status,
1427                         entry.dest_mode,
1428                         entry.delivery_mode,
1429                         entry.vector
1430                 );
1431         }
1432         }
1433         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1434         for (i = 0; i < NR_IRQS; i++) {
1435                 struct irq_pin_list *entry = irq_2_pin + i;
1436                 if (entry->pin < 0)
1437                         continue;
1438                 printk(KERN_DEBUG "IRQ%d ", i);
1439                 for (;;) {
1440                         printk("-> %d:%d", entry->apic, entry->pin);
1441                         if (!entry->next)
1442                                 break;
1443                         entry = irq_2_pin + entry->next;
1444                 }
1445                 printk("\n");
1446         }
1447
1448         printk(KERN_INFO ".................................... done.\n");
1449
1450         return;
1451 }
1452
1453 #if 0
1454
1455 static void print_APIC_bitfield (int base)
1456 {
1457         unsigned int v;
1458         int i, j;
1459
1460         if (apic_verbosity == APIC_QUIET)
1461                 return;
1462
1463         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1464         for (i = 0; i < 8; i++) {
1465                 v = apic_read(base + i*0x10);
1466                 for (j = 0; j < 32; j++) {
1467                         if (v & (1<<j))
1468                                 printk("1");
1469                         else
1470                                 printk("0");
1471                 }
1472                 printk("\n");
1473         }
1474 }
1475
1476 void /*__init*/ print_local_APIC(void * dummy)
1477 {
1478         unsigned int v, ver, maxlvt;
1479
1480         if (apic_verbosity == APIC_QUIET)
1481                 return;
1482
1483         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1484                 smp_processor_id(), hard_smp_processor_id());
1485         v = apic_read(APIC_ID);
1486         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1487         v = apic_read(APIC_LVR);
1488         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1489         ver = GET_APIC_VERSION(v);
1490         maxlvt = lapic_get_maxlvt();
1491
1492         v = apic_read(APIC_TASKPRI);
1493         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1494
1495         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1496                 v = apic_read(APIC_ARBPRI);
1497                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1498                         v & APIC_ARBPRI_MASK);
1499                 v = apic_read(APIC_PROCPRI);
1500                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1501         }
1502
1503         v = apic_read(APIC_EOI);
1504         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1505         v = apic_read(APIC_RRR);
1506         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1507         v = apic_read(APIC_LDR);
1508         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1509         v = apic_read(APIC_DFR);
1510         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1511         v = apic_read(APIC_SPIV);
1512         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1513
1514         printk(KERN_DEBUG "... APIC ISR field:\n");
1515         print_APIC_bitfield(APIC_ISR);
1516         printk(KERN_DEBUG "... APIC TMR field:\n");
1517         print_APIC_bitfield(APIC_TMR);
1518         printk(KERN_DEBUG "... APIC IRR field:\n");
1519         print_APIC_bitfield(APIC_IRR);
1520
1521         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1522                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1523                         apic_write(APIC_ESR, 0);
1524                 v = apic_read(APIC_ESR);
1525                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1526         }
1527
1528         v = apic_read(APIC_ICR);
1529         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1530         v = apic_read(APIC_ICR2);
1531         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1532
1533         v = apic_read(APIC_LVTT);
1534         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1535
1536         if (maxlvt > 3) {                       /* PC is LVT#4. */
1537                 v = apic_read(APIC_LVTPC);
1538                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1539         }
1540         v = apic_read(APIC_LVT0);
1541         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1542         v = apic_read(APIC_LVT1);
1543         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1544
1545         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1546                 v = apic_read(APIC_LVTERR);
1547                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1548         }
1549
1550         v = apic_read(APIC_TMICT);
1551         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1552         v = apic_read(APIC_TMCCT);
1553         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1554         v = apic_read(APIC_TDCR);
1555         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1556         printk("\n");
1557 }
1558
1559 void print_all_local_APICs (void)
1560 {
1561         on_each_cpu(print_local_APIC, NULL, 1, 1);
1562 }
1563
1564 void /*__init*/ print_PIC(void)
1565 {
1566         unsigned int v;
1567         unsigned long flags;
1568
1569         if (apic_verbosity == APIC_QUIET)
1570                 return;
1571
1572         printk(KERN_DEBUG "\nprinting PIC contents\n");
1573
1574         spin_lock_irqsave(&i8259A_lock, flags);
1575
1576         v = inb(0xa1) << 8 | inb(0x21);
1577         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1578
1579         v = inb(0xa0) << 8 | inb(0x20);
1580         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1581
1582         outb(0x0b,0xa0);
1583         outb(0x0b,0x20);
1584         v = inb(0xa0) << 8 | inb(0x20);
1585         outb(0x0a,0xa0);
1586         outb(0x0a,0x20);
1587
1588         spin_unlock_irqrestore(&i8259A_lock, flags);
1589
1590         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1591
1592         v = inb(0x4d1) << 8 | inb(0x4d0);
1593         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1594 }
1595
1596 #endif  /*  0  */
1597
1598 static void __init enable_IO_APIC(void)
1599 {
1600         union IO_APIC_reg_01 reg_01;
1601         int i8259_apic, i8259_pin;
1602         int i, apic;
1603         unsigned long flags;
1604
1605         for (i = 0; i < PIN_MAP_SIZE; i++) {
1606                 irq_2_pin[i].pin = -1;
1607                 irq_2_pin[i].next = 0;
1608         }
1609         if (!pirqs_enabled)
1610                 for (i = 0; i < MAX_PIRQS; i++)
1611                         pirq_entries[i] = -1;
1612
1613         /*
1614          * The number of IO-APIC IRQ registers (== #pins):
1615          */
1616         for (apic = 0; apic < nr_ioapics; apic++) {
1617                 spin_lock_irqsave(&ioapic_lock, flags);
1618                 reg_01.raw = io_apic_read(apic, 1);
1619                 spin_unlock_irqrestore(&ioapic_lock, flags);
1620                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1621         }
1622         for(apic = 0; apic < nr_ioapics; apic++) {
1623                 int pin;
1624                 /* See if any of the pins is in ExtINT mode */
1625                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1626                         struct IO_APIC_route_entry entry;
1627                         entry = ioapic_read_entry(apic, pin);
1628
1629
1630                         /* If the interrupt line is enabled and in ExtInt mode
1631                          * I have found the pin where the i8259 is connected.
1632                          */
1633                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1634                                 ioapic_i8259.apic = apic;
1635                                 ioapic_i8259.pin  = pin;
1636                                 goto found_i8259;
1637                         }
1638                 }
1639         }
1640  found_i8259:
1641         /* Look to see what if the MP table has reported the ExtINT */
1642         /* If we could not find the appropriate pin by looking at the ioapic
1643          * the i8259 probably is not connected the ioapic but give the
1644          * mptable a chance anyway.
1645          */
1646         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1647         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1648         /* Trust the MP table if nothing is setup in the hardware */
1649         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1650                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1651                 ioapic_i8259.pin  = i8259_pin;
1652                 ioapic_i8259.apic = i8259_apic;
1653         }
1654         /* Complain if the MP table and the hardware disagree */
1655         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1656                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1657         {
1658                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1659         }
1660
1661         /*
1662          * Do not trust the IO-APIC being empty at bootup
1663          */
1664         clear_IO_APIC();
1665 }
1666
1667 /*
1668  * Not an __init, needed by the reboot code
1669  */
1670 void disable_IO_APIC(void)
1671 {
1672         /*
1673          * Clear the IO-APIC before rebooting:
1674          */
1675         clear_IO_APIC();
1676
1677         /*
1678          * If the i8259 is routed through an IOAPIC
1679          * Put that IOAPIC in virtual wire mode
1680          * so legacy interrupts can be delivered.
1681          */
1682         if (ioapic_i8259.pin != -1) {
1683                 struct IO_APIC_route_entry entry;
1684
1685                 memset(&entry, 0, sizeof(entry));
1686                 entry.mask            = 0; /* Enabled */
1687                 entry.trigger         = 0; /* Edge */
1688                 entry.irr             = 0;
1689                 entry.polarity        = 0; /* High */
1690                 entry.delivery_status = 0;
1691                 entry.dest_mode       = 0; /* Physical */
1692                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1693                 entry.vector          = 0;
1694                 entry.dest.physical.physical_dest =
1695                                         GET_APIC_ID(apic_read(APIC_ID));
1696
1697                 /*
1698                  * Add it to the IO-APIC irq-routing table:
1699                  */
1700                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1701         }
1702         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1703 }
1704
1705 /*
1706  * function to set the IO-APIC physical IDs based on the
1707  * values stored in the MPC table.
1708  *
1709  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1710  */
1711
1712 #ifndef CONFIG_X86_NUMAQ
1713 static void __init setup_ioapic_ids_from_mpc(void)
1714 {
1715         union IO_APIC_reg_00 reg_00;
1716         physid_mask_t phys_id_present_map;
1717         int apic;
1718         int i;
1719         unsigned char old_id;
1720         unsigned long flags;
1721
1722         /*
1723          * Don't check I/O APIC IDs for xAPIC systems.  They have
1724          * no meaning without the serial APIC bus.
1725          */
1726         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1727                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1728                 return;
1729         /*
1730          * This is broken; anything with a real cpu count has to
1731          * circumvent this idiocy regardless.
1732          */
1733         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1734
1735         /*
1736          * Set the IOAPIC ID to the value stored in the MPC table.
1737          */
1738         for (apic = 0; apic < nr_ioapics; apic++) {
1739
1740                 /* Read the register 0 value */
1741                 spin_lock_irqsave(&ioapic_lock, flags);
1742                 reg_00.raw = io_apic_read(apic, 0);
1743                 spin_unlock_irqrestore(&ioapic_lock, flags);
1744
1745                 old_id = mp_ioapics[apic].mpc_apicid;
1746
1747                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1748                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1749                                 apic, mp_ioapics[apic].mpc_apicid);
1750                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1751                                 reg_00.bits.ID);
1752                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1753                 }
1754
1755                 /*
1756                  * Sanity check, is the ID really free? Every APIC in a
1757                  * system must have a unique ID or we get lots of nice
1758                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1759                  */
1760                 if (check_apicid_used(phys_id_present_map,
1761                                         mp_ioapics[apic].mpc_apicid)) {
1762                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1763                                 apic, mp_ioapics[apic].mpc_apicid);
1764                         for (i = 0; i < get_physical_broadcast(); i++)
1765                                 if (!physid_isset(i, phys_id_present_map))
1766                                         break;
1767                         if (i >= get_physical_broadcast())
1768                                 panic("Max APIC ID exceeded!\n");
1769                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1770                                 i);
1771                         physid_set(i, phys_id_present_map);
1772                         mp_ioapics[apic].mpc_apicid = i;
1773                 } else {
1774                         physid_mask_t tmp;
1775                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1776                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1777                                         "phys_id_present_map\n",
1778                                         mp_ioapics[apic].mpc_apicid);
1779                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1780                 }
1781
1782
1783                 /*
1784                  * We need to adjust the IRQ routing table
1785                  * if the ID changed.
1786                  */
1787                 if (old_id != mp_ioapics[apic].mpc_apicid)
1788                         for (i = 0; i < mp_irq_entries; i++)
1789                                 if (mp_irqs[i].mpc_dstapic == old_id)
1790                                         mp_irqs[i].mpc_dstapic
1791                                                 = mp_ioapics[apic].mpc_apicid;
1792
1793                 /*
1794                  * Read the right value from the MPC table and
1795                  * write it into the ID register.
1796                  */
1797                 apic_printk(APIC_VERBOSE, KERN_INFO
1798                         "...changing IO-APIC physical APIC ID to %d ...",
1799                         mp_ioapics[apic].mpc_apicid);
1800
1801                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1802                 spin_lock_irqsave(&ioapic_lock, flags);
1803                 io_apic_write(apic, 0, reg_00.raw);
1804                 spin_unlock_irqrestore(&ioapic_lock, flags);
1805
1806                 /*
1807                  * Sanity check
1808                  */
1809                 spin_lock_irqsave(&ioapic_lock, flags);
1810                 reg_00.raw = io_apic_read(apic, 0);
1811                 spin_unlock_irqrestore(&ioapic_lock, flags);
1812                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1813                         printk("could not set ID!\n");
1814                 else
1815                         apic_printk(APIC_VERBOSE, " ok.\n");
1816         }
1817 }
1818 #else
1819 static void __init setup_ioapic_ids_from_mpc(void) { }
1820 #endif
1821
1822 int no_timer_check __initdata;
1823
1824 static int __init notimercheck(char *s)
1825 {
1826         no_timer_check = 1;
1827         return 1;
1828 }
1829 __setup("no_timer_check", notimercheck);
1830
1831 /*
1832  * There is a nasty bug in some older SMP boards, their mptable lies
1833  * about the timer IRQ. We do the following to work around the situation:
1834  *
1835  *      - timer IRQ defaults to IO-APIC IRQ
1836  *      - if this function detects that timer IRQs are defunct, then we fall
1837  *        back to ISA timer IRQs
1838  */
1839 static int __init timer_irq_works(void)
1840 {
1841         unsigned long t1 = jiffies;
1842         unsigned long flags;
1843
1844         if (no_timer_check)
1845                 return 1;
1846
1847         local_save_flags(flags);
1848         local_irq_enable();
1849         /* Let ten ticks pass... */
1850         mdelay((10 * 1000) / HZ);
1851         local_irq_restore(flags);
1852
1853         /*
1854          * Expect a few ticks at least, to be sure some possible
1855          * glue logic does not lock up after one or two first
1856          * ticks in a non-ExtINT mode.  Also the local APIC
1857          * might have cached one ExtINT interrupt.  Finally, at
1858          * least one tick may be lost due to delays.
1859          */
1860         if (time_after(jiffies, t1 + 4))
1861                 return 1;
1862
1863         return 0;
1864 }
1865
1866 /*
1867  * In the SMP+IOAPIC case it might happen that there are an unspecified
1868  * number of pending IRQ events unhandled. These cases are very rare,
1869  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1870  * better to do it this way as thus we do not have to be aware of
1871  * 'pending' interrupts in the IRQ path, except at this point.
1872  */
1873 /*
1874  * Edge triggered needs to resend any interrupt
1875  * that was delayed but this is now handled in the device
1876  * independent code.
1877  */
1878
1879 /*
1880  * Startup quirk:
1881  *
1882  * Starting up a edge-triggered IO-APIC interrupt is
1883  * nasty - we need to make sure that we get the edge.
1884  * If it is already asserted for some reason, we need
1885  * return 1 to indicate that is was pending.
1886  *
1887  * This is not complete - we should be able to fake
1888  * an edge even if it isn't on the 8259A...
1889  *
1890  * (We do this for level-triggered IRQs too - it cannot hurt.)
1891  */
1892 static unsigned int startup_ioapic_irq(unsigned int irq)
1893 {
1894         int was_pending = 0;
1895         unsigned long flags;
1896
1897         spin_lock_irqsave(&ioapic_lock, flags);
1898         if (irq < 16) {
1899                 disable_8259A_irq(irq);
1900                 if (i8259A_irq_pending(irq))
1901                         was_pending = 1;
1902         }
1903         __unmask_IO_APIC_irq(irq);
1904         spin_unlock_irqrestore(&ioapic_lock, flags);
1905
1906         return was_pending;
1907 }
1908
1909 static void ack_ioapic_irq(unsigned int irq)
1910 {
1911         move_native_irq(irq);
1912         ack_APIC_irq();
1913 }
1914
1915 static void ack_ioapic_quirk_irq(unsigned int irq)
1916 {
1917         unsigned long v;
1918         int i;
1919
1920         move_native_irq(irq);
1921 /*
1922  * It appears there is an erratum which affects at least version 0x11
1923  * of I/O APIC (that's the 82093AA and cores integrated into various
1924  * chipsets).  Under certain conditions a level-triggered interrupt is
1925  * erroneously delivered as edge-triggered one but the respective IRR
1926  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1927  * message but it will never arrive and further interrupts are blocked
1928  * from the source.  The exact reason is so far unknown, but the
1929  * phenomenon was observed when two consecutive interrupt requests
1930  * from a given source get delivered to the same CPU and the source is
1931  * temporarily disabled in between.
1932  *
1933  * A workaround is to simulate an EOI message manually.  We achieve it
1934  * by setting the trigger mode to edge and then to level when the edge
1935  * trigger mode gets detected in the TMR of a local APIC for a
1936  * level-triggered interrupt.  We mask the source for the time of the
1937  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1938  * The idea is from Manfred Spraul.  --macro
1939  */
1940         i = irq_vector[irq];
1941
1942         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1943
1944         ack_APIC_irq();
1945
1946         if (!(v & (1 << (i & 0x1f)))) {
1947                 atomic_inc(&irq_mis_count);
1948                 spin_lock(&ioapic_lock);
1949                 __mask_and_edge_IO_APIC_irq(irq);
1950                 __unmask_and_level_IO_APIC_irq(irq);
1951                 spin_unlock(&ioapic_lock);
1952         }
1953 }
1954
1955 static int ioapic_retrigger_irq(unsigned int irq)
1956 {
1957         send_IPI_self(irq_vector[irq]);
1958
1959         return 1;
1960 }
1961
1962 static struct irq_chip ioapic_chip __read_mostly = {
1963         .name           = "IO-APIC",
1964         .startup        = startup_ioapic_irq,
1965         .mask           = mask_IO_APIC_irq,
1966         .unmask         = unmask_IO_APIC_irq,
1967         .ack            = ack_ioapic_irq,
1968         .eoi            = ack_ioapic_quirk_irq,
1969 #ifdef CONFIG_SMP
1970         .set_affinity   = set_ioapic_affinity_irq,
1971 #endif
1972         .retrigger      = ioapic_retrigger_irq,
1973 };
1974
1975
1976 static inline void init_IO_APIC_traps(void)
1977 {
1978         int irq;
1979
1980         /*
1981          * NOTE! The local APIC isn't very good at handling
1982          * multiple interrupts at the same interrupt level.
1983          * As the interrupt level is determined by taking the
1984          * vector number and shifting that right by 4, we
1985          * want to spread these out a bit so that they don't
1986          * all fall in the same interrupt level.
1987          *
1988          * Also, we've got to be careful not to trash gate
1989          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1990          */
1991         for (irq = 0; irq < NR_IRQS ; irq++) {
1992                 int tmp = irq;
1993                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1994                         /*
1995                          * Hmm.. We don't have an entry for this,
1996                          * so default to an old-fashioned 8259
1997                          * interrupt if we can..
1998                          */
1999                         if (irq < 16)
2000                                 make_8259A_irq(irq);
2001                         else
2002                                 /* Strange. Oh, well.. */
2003                                 irq_desc[irq].chip = &no_irq_chip;
2004                 }
2005         }
2006 }
2007
2008 /*
2009  * The local APIC irq-chip implementation:
2010  */
2011
2012 static void ack_apic(unsigned int irq)
2013 {
2014         ack_APIC_irq();
2015 }
2016
2017 static void mask_lapic_irq (unsigned int irq)
2018 {
2019         unsigned long v;
2020
2021         v = apic_read(APIC_LVT0);
2022         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2023 }
2024
2025 static void unmask_lapic_irq (unsigned int irq)
2026 {
2027         unsigned long v;
2028
2029         v = apic_read(APIC_LVT0);
2030         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2031 }
2032
2033 static struct irq_chip lapic_chip __read_mostly = {
2034         .name           = "local-APIC-edge",
2035         .mask           = mask_lapic_irq,
2036         .unmask         = unmask_lapic_irq,
2037         .eoi            = ack_apic,
2038 };
2039
2040 static void __init setup_nmi(void)
2041 {
2042         /*
2043          * Dirty trick to enable the NMI watchdog ...
2044          * We put the 8259A master into AEOI mode and
2045          * unmask on all local APICs LVT0 as NMI.
2046          *
2047          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2048          * is from Maciej W. Rozycki - so we do not have to EOI from
2049          * the NMI handler or the timer interrupt.
2050          */
2051         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2052
2053         enable_NMI_through_LVT0();
2054
2055         apic_printk(APIC_VERBOSE, " done.\n");
2056 }
2057
2058 /*
2059  * This looks a bit hackish but it's about the only one way of sending
2060  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2061  * not support the ExtINT mode, unfortunately.  We need to send these
2062  * cycles as some i82489DX-based boards have glue logic that keeps the
2063  * 8259A interrupt line asserted until INTA.  --macro
2064  */
2065 static inline void unlock_ExtINT_logic(void)
2066 {
2067         int apic, pin, i;
2068         struct IO_APIC_route_entry entry0, entry1;
2069         unsigned char save_control, save_freq_select;
2070
2071         pin  = find_isa_irq_pin(8, mp_INT);
2072         if (pin == -1) {
2073                 WARN_ON_ONCE(1);
2074                 return;
2075         }
2076         apic = find_isa_irq_apic(8, mp_INT);
2077         if (apic == -1) {
2078                 WARN_ON_ONCE(1);
2079                 return;
2080         }
2081
2082         entry0 = ioapic_read_entry(apic, pin);
2083         clear_IO_APIC_pin(apic, pin);
2084
2085         memset(&entry1, 0, sizeof(entry1));
2086
2087         entry1.dest_mode = 0;                   /* physical delivery */
2088         entry1.mask = 0;                        /* unmask IRQ now */
2089         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2090         entry1.delivery_mode = dest_ExtINT;
2091         entry1.polarity = entry0.polarity;
2092         entry1.trigger = 0;
2093         entry1.vector = 0;
2094
2095         ioapic_write_entry(apic, pin, entry1);
2096
2097         save_control = CMOS_READ(RTC_CONTROL);
2098         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2099         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2100                    RTC_FREQ_SELECT);
2101         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2102
2103         i = 100;
2104         while (i-- > 0) {
2105                 mdelay(10);
2106                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2107                         i -= 10;
2108         }
2109
2110         CMOS_WRITE(save_control, RTC_CONTROL);
2111         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2112         clear_IO_APIC_pin(apic, pin);
2113
2114         ioapic_write_entry(apic, pin, entry0);
2115 }
2116
2117 int timer_uses_ioapic_pin_0;
2118
2119 /*
2120  * This code may look a bit paranoid, but it's supposed to cooperate with
2121  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2122  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2123  * fanatically on his truly buggy board.
2124  */
2125 static inline void __init check_timer(void)
2126 {
2127         int apic1, pin1, apic2, pin2;
2128         int vector;
2129         unsigned long flags;
2130
2131         local_irq_save(flags);
2132
2133         /*
2134          * get/set the timer IRQ vector:
2135          */
2136         disable_8259A_irq(0);
2137         vector = assign_irq_vector(0);
2138         set_intr_gate(vector, interrupt[0]);
2139
2140         /*
2141          * Subtle, code in do_timer_interrupt() expects an AEOI
2142          * mode for the 8259A whenever interrupts are routed
2143          * through I/O APICs.  Also IRQ0 has to be enabled in
2144          * the 8259A which implies the virtual wire has to be
2145          * disabled in the local APIC.
2146          */
2147         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2148         init_8259A(1);
2149         timer_ack = 1;
2150         if (timer_over_8254 > 0)
2151                 enable_8259A_irq(0);
2152
2153         pin1  = find_isa_irq_pin(0, mp_INT);
2154         apic1 = find_isa_irq_apic(0, mp_INT);
2155         pin2  = ioapic_i8259.pin;
2156         apic2 = ioapic_i8259.apic;
2157
2158         if (pin1 == 0)
2159                 timer_uses_ioapic_pin_0 = 1;
2160
2161         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2162                 vector, apic1, pin1, apic2, pin2);
2163
2164         if (pin1 != -1) {
2165                 /*
2166                  * Ok, does IRQ0 through the IOAPIC work?
2167                  */
2168                 unmask_IO_APIC_irq(0);
2169                 if (timer_irq_works()) {
2170                         if (nmi_watchdog == NMI_IO_APIC) {
2171                                 disable_8259A_irq(0);
2172                                 setup_nmi();
2173                                 enable_8259A_irq(0);
2174                         }
2175                         if (disable_timer_pin_1 > 0)
2176                                 clear_IO_APIC_pin(0, pin1);
2177                         goto out;
2178                 }
2179                 clear_IO_APIC_pin(apic1, pin1);
2180                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2181                                 "IO-APIC\n");
2182         }
2183
2184         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2185         if (pin2 != -1) {
2186                 printk("\n..... (found pin %d) ...", pin2);
2187                 /*
2188                  * legacy devices should be connected to IO APIC #0
2189                  */
2190                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2191                 if (timer_irq_works()) {
2192                         printk("works.\n");
2193                         if (pin1 != -1)
2194                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2195                         else
2196                                 add_pin_to_irq(0, apic2, pin2);
2197                         if (nmi_watchdog == NMI_IO_APIC) {
2198                                 setup_nmi();
2199                         }
2200                         goto out;
2201                 }
2202                 /*
2203                  * Cleanup, just in case ...
2204                  */
2205                 clear_IO_APIC_pin(apic2, pin2);
2206         }
2207         printk(" failed.\n");
2208
2209         if (nmi_watchdog == NMI_IO_APIC) {
2210                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2211                 nmi_watchdog = 0;
2212         }
2213
2214         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2215
2216         disable_8259A_irq(0);
2217         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2218                                       "fasteoi");
2219         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2220         enable_8259A_irq(0);
2221
2222         if (timer_irq_works()) {
2223                 printk(" works.\n");
2224                 goto out;
2225         }
2226         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2227         printk(" failed.\n");
2228
2229         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2230
2231         timer_ack = 0;
2232         init_8259A(0);
2233         make_8259A_irq(0);
2234         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2235
2236         unlock_ExtINT_logic();
2237
2238         if (timer_irq_works()) {
2239                 printk(" works.\n");
2240                 goto out;
2241         }
2242         printk(" failed :(.\n");
2243         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2244                 "report.  Then try booting with the 'noapic' option");
2245 out:
2246         local_irq_restore(flags);
2247 }
2248
2249 /*
2250  *
2251  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2252  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2253  *   Linux doesn't really care, as it's not actually used
2254  *   for any interrupt handling anyway.
2255  */
2256 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2257
2258 void __init setup_IO_APIC(void)
2259 {
2260         int i;
2261
2262         /* Reserve all the system vectors. */
2263         for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2264                 set_bit(i, used_vectors);
2265
2266         enable_IO_APIC();
2267
2268         if (acpi_ioapic)
2269                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2270         else
2271                 io_apic_irqs = ~PIC_IRQS;
2272
2273         printk("ENABLING IO-APIC IRQs\n");
2274
2275         /*
2276          * Set up IO-APIC IRQ routing.
2277          */
2278         if (!acpi_ioapic)
2279                 setup_ioapic_ids_from_mpc();
2280         sync_Arb_IDs();
2281         setup_IO_APIC_irqs();
2282         init_IO_APIC_traps();
2283         check_timer();
2284         if (!acpi_ioapic)
2285                 print_IO_APIC();
2286 }
2287
2288 static int __init setup_disable_8254_timer(char *s)
2289 {
2290         timer_over_8254 = -1;
2291         return 1;
2292 }
2293 static int __init setup_enable_8254_timer(char *s)
2294 {
2295         timer_over_8254 = 2;
2296         return 1;
2297 }
2298
2299 __setup("disable_8254_timer", setup_disable_8254_timer);
2300 __setup("enable_8254_timer", setup_enable_8254_timer);
2301
2302 /*
2303  *      Called after all the initialization is done. If we didnt find any
2304  *      APIC bugs then we can allow the modify fast path
2305  */
2306
2307 static int __init io_apic_bug_finalize(void)
2308 {
2309         if(sis_apic_bug == -1)
2310                 sis_apic_bug = 0;
2311         return 0;
2312 }
2313
2314 late_initcall(io_apic_bug_finalize);
2315
2316 struct sysfs_ioapic_data {
2317         struct sys_device dev;
2318         struct IO_APIC_route_entry entry[0];
2319 };
2320 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2321
2322 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2323 {
2324         struct IO_APIC_route_entry *entry;
2325         struct sysfs_ioapic_data *data;
2326         int i;
2327
2328         data = container_of(dev, struct sysfs_ioapic_data, dev);
2329         entry = data->entry;
2330         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2331                 entry[i] = ioapic_read_entry(dev->id, i);
2332
2333         return 0;
2334 }
2335
2336 static int ioapic_resume(struct sys_device *dev)
2337 {
2338         struct IO_APIC_route_entry *entry;
2339         struct sysfs_ioapic_data *data;
2340         unsigned long flags;
2341         union IO_APIC_reg_00 reg_00;
2342         int i;
2343
2344         data = container_of(dev, struct sysfs_ioapic_data, dev);
2345         entry = data->entry;
2346
2347         spin_lock_irqsave(&ioapic_lock, flags);
2348         reg_00.raw = io_apic_read(dev->id, 0);
2349         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2350                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2351                 io_apic_write(dev->id, 0, reg_00.raw);
2352         }
2353         spin_unlock_irqrestore(&ioapic_lock, flags);
2354         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2355                 ioapic_write_entry(dev->id, i, entry[i]);
2356
2357         return 0;
2358 }
2359
2360 static struct sysdev_class ioapic_sysdev_class = {
2361         .name = "ioapic",
2362         .suspend = ioapic_suspend,
2363         .resume = ioapic_resume,
2364 };
2365
2366 static int __init ioapic_init_sysfs(void)
2367 {
2368         struct sys_device * dev;
2369         int i, size, error = 0;
2370
2371         error = sysdev_class_register(&ioapic_sysdev_class);
2372         if (error)
2373                 return error;
2374
2375         for (i = 0; i < nr_ioapics; i++ ) {
2376                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2377                         * sizeof(struct IO_APIC_route_entry);
2378                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2379                 if (!mp_ioapic_data[i]) {
2380                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2381                         continue;
2382                 }
2383                 memset(mp_ioapic_data[i], 0, size);
2384                 dev = &mp_ioapic_data[i]->dev;
2385                 dev->id = i;
2386                 dev->cls = &ioapic_sysdev_class;
2387                 error = sysdev_register(dev);
2388                 if (error) {
2389                         kfree(mp_ioapic_data[i]);
2390                         mp_ioapic_data[i] = NULL;
2391                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2392                         continue;
2393                 }
2394         }
2395
2396         return 0;
2397 }
2398
2399 device_initcall(ioapic_init_sysfs);
2400
2401 /*
2402  * Dynamic irq allocate and deallocation
2403  */
2404 int create_irq(void)
2405 {
2406         /* Allocate an unused irq */
2407         int irq, new, vector = 0;
2408         unsigned long flags;
2409
2410         irq = -ENOSPC;
2411         spin_lock_irqsave(&vector_lock, flags);
2412         for (new = (NR_IRQS - 1); new >= 0; new--) {
2413                 if (platform_legacy_irq(new))
2414                         continue;
2415                 if (irq_vector[new] != 0)
2416                         continue;
2417                 vector = __assign_irq_vector(new);
2418                 if (likely(vector > 0))
2419                         irq = new;
2420                 break;
2421         }
2422         spin_unlock_irqrestore(&vector_lock, flags);
2423
2424         if (irq >= 0) {
2425                 set_intr_gate(vector, interrupt[irq]);
2426                 dynamic_irq_init(irq);
2427         }
2428         return irq;
2429 }
2430
2431 void destroy_irq(unsigned int irq)
2432 {
2433         unsigned long flags;
2434
2435         dynamic_irq_cleanup(irq);
2436
2437         spin_lock_irqsave(&vector_lock, flags);
2438         irq_vector[irq] = 0;
2439         spin_unlock_irqrestore(&vector_lock, flags);
2440 }
2441
2442 /*
2443  * MSI message composition
2444  */
2445 #ifdef CONFIG_PCI_MSI
2446 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2447 {
2448         int vector;
2449         unsigned dest;
2450
2451         vector = assign_irq_vector(irq);
2452         if (vector >= 0) {
2453                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2454
2455                 msg->address_hi = MSI_ADDR_BASE_HI;
2456                 msg->address_lo =
2457                         MSI_ADDR_BASE_LO |
2458                         ((INT_DEST_MODE == 0) ?
2459                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2460                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2461                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2462                                 MSI_ADDR_REDIRECTION_CPU:
2463                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2464                         MSI_ADDR_DEST_ID(dest);
2465
2466                 msg->data =
2467                         MSI_DATA_TRIGGER_EDGE |
2468                         MSI_DATA_LEVEL_ASSERT |
2469                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2470                                 MSI_DATA_DELIVERY_FIXED:
2471                                 MSI_DATA_DELIVERY_LOWPRI) |
2472                         MSI_DATA_VECTOR(vector);
2473         }
2474         return vector;
2475 }
2476
2477 #ifdef CONFIG_SMP
2478 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2479 {
2480         struct msi_msg msg;
2481         unsigned int dest;
2482         cpumask_t tmp;
2483         int vector;
2484
2485         cpus_and(tmp, mask, cpu_online_map);
2486         if (cpus_empty(tmp))
2487                 tmp = TARGET_CPUS;
2488
2489         vector = assign_irq_vector(irq);
2490         if (vector < 0)
2491                 return;
2492
2493         dest = cpu_mask_to_apicid(mask);
2494
2495         read_msi_msg(irq, &msg);
2496
2497         msg.data &= ~MSI_DATA_VECTOR_MASK;
2498         msg.data |= MSI_DATA_VECTOR(vector);
2499         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2500         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2501
2502         write_msi_msg(irq, &msg);
2503         irq_desc[irq].affinity = mask;
2504 }
2505 #endif /* CONFIG_SMP */
2506
2507 /*
2508  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2509  * which implement the MSI or MSI-X Capability Structure.
2510  */
2511 static struct irq_chip msi_chip = {
2512         .name           = "PCI-MSI",
2513         .unmask         = unmask_msi_irq,
2514         .mask           = mask_msi_irq,
2515         .ack            = ack_ioapic_irq,
2516 #ifdef CONFIG_SMP
2517         .set_affinity   = set_msi_irq_affinity,
2518 #endif
2519         .retrigger      = ioapic_retrigger_irq,
2520 };
2521
2522 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2523 {
2524         struct msi_msg msg;
2525         int irq, ret;
2526         irq = create_irq();
2527         if (irq < 0)
2528                 return irq;
2529
2530         ret = msi_compose_msg(dev, irq, &msg);
2531         if (ret < 0) {
2532                 destroy_irq(irq);
2533                 return ret;
2534         }
2535
2536         set_irq_msi(irq, desc);
2537         write_msi_msg(irq, &msg);
2538
2539         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2540                                       "edge");
2541
2542         return 0;
2543 }
2544
2545 void arch_teardown_msi_irq(unsigned int irq)
2546 {
2547         destroy_irq(irq);
2548 }
2549
2550 #endif /* CONFIG_PCI_MSI */
2551
2552 /*
2553  * Hypertransport interrupt support
2554  */
2555 #ifdef CONFIG_HT_IRQ
2556
2557 #ifdef CONFIG_SMP
2558
2559 static void target_ht_irq(unsigned int irq, unsigned int dest)
2560 {
2561         struct ht_irq_msg msg;
2562         fetch_ht_irq_msg(irq, &msg);
2563
2564         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2565         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2566
2567         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2568         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2569
2570         write_ht_irq_msg(irq, &msg);
2571 }
2572
2573 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2574 {
2575         unsigned int dest;
2576         cpumask_t tmp;
2577
2578         cpus_and(tmp, mask, cpu_online_map);
2579         if (cpus_empty(tmp))
2580                 tmp = TARGET_CPUS;
2581
2582         cpus_and(mask, tmp, CPU_MASK_ALL);
2583
2584         dest = cpu_mask_to_apicid(mask);
2585
2586         target_ht_irq(irq, dest);
2587         irq_desc[irq].affinity = mask;
2588 }
2589 #endif
2590
2591 static struct irq_chip ht_irq_chip = {
2592         .name           = "PCI-HT",
2593         .mask           = mask_ht_irq,
2594         .unmask         = unmask_ht_irq,
2595         .ack            = ack_ioapic_irq,
2596 #ifdef CONFIG_SMP
2597         .set_affinity   = set_ht_irq_affinity,
2598 #endif
2599         .retrigger      = ioapic_retrigger_irq,
2600 };
2601
2602 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2603 {
2604         int vector;
2605
2606         vector = assign_irq_vector(irq);
2607         if (vector >= 0) {
2608                 struct ht_irq_msg msg;
2609                 unsigned dest;
2610                 cpumask_t tmp;
2611
2612                 cpus_clear(tmp);
2613                 cpu_set(vector >> 8, tmp);
2614                 dest = cpu_mask_to_apicid(tmp);
2615
2616                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2617
2618                 msg.address_lo =
2619                         HT_IRQ_LOW_BASE |
2620                         HT_IRQ_LOW_DEST_ID(dest) |
2621                         HT_IRQ_LOW_VECTOR(vector) |
2622                         ((INT_DEST_MODE == 0) ?
2623                                 HT_IRQ_LOW_DM_PHYSICAL :
2624                                 HT_IRQ_LOW_DM_LOGICAL) |
2625                         HT_IRQ_LOW_RQEOI_EDGE |
2626                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2627                                 HT_IRQ_LOW_MT_FIXED :
2628                                 HT_IRQ_LOW_MT_ARBITRATED) |
2629                         HT_IRQ_LOW_IRQ_MASKED;
2630
2631                 write_ht_irq_msg(irq, &msg);
2632
2633                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2634                                               handle_edge_irq, "edge");
2635         }
2636         return vector;
2637 }
2638 #endif /* CONFIG_HT_IRQ */
2639
2640 /* --------------------------------------------------------------------------
2641                           ACPI-based IOAPIC Configuration
2642    -------------------------------------------------------------------------- */
2643
2644 #ifdef CONFIG_ACPI
2645
2646 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2647 {
2648         union IO_APIC_reg_00 reg_00;
2649         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2650         physid_mask_t tmp;
2651         unsigned long flags;
2652         int i = 0;
2653
2654         /*
2655          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2656          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2657          * supports up to 16 on one shared APIC bus.
2658          *
2659          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2660          *      advantage of new APIC bus architecture.
2661          */
2662
2663         if (physids_empty(apic_id_map))
2664                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2665
2666         spin_lock_irqsave(&ioapic_lock, flags);
2667         reg_00.raw = io_apic_read(ioapic, 0);
2668         spin_unlock_irqrestore(&ioapic_lock, flags);
2669
2670         if (apic_id >= get_physical_broadcast()) {
2671                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2672                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2673                 apic_id = reg_00.bits.ID;
2674         }
2675
2676         /*
2677          * Every APIC in a system must have a unique ID or we get lots of nice
2678          * 'stuck on smp_invalidate_needed IPI wait' messages.
2679          */
2680         if (check_apicid_used(apic_id_map, apic_id)) {
2681
2682                 for (i = 0; i < get_physical_broadcast(); i++) {
2683                         if (!check_apicid_used(apic_id_map, i))
2684                                 break;
2685                 }
2686
2687                 if (i == get_physical_broadcast())
2688                         panic("Max apic_id exceeded!\n");
2689
2690                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2691                         "trying %d\n", ioapic, apic_id, i);
2692
2693                 apic_id = i;
2694         }
2695
2696         tmp = apicid_to_cpu_present(apic_id);
2697         physids_or(apic_id_map, apic_id_map, tmp);
2698
2699         if (reg_00.bits.ID != apic_id) {
2700                 reg_00.bits.ID = apic_id;
2701
2702                 spin_lock_irqsave(&ioapic_lock, flags);
2703                 io_apic_write(ioapic, 0, reg_00.raw);
2704                 reg_00.raw = io_apic_read(ioapic, 0);
2705                 spin_unlock_irqrestore(&ioapic_lock, flags);
2706
2707                 /* Sanity check */
2708                 if (reg_00.bits.ID != apic_id) {
2709                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2710                         return -1;
2711                 }
2712         }
2713
2714         apic_printk(APIC_VERBOSE, KERN_INFO
2715                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2716
2717         return apic_id;
2718 }
2719
2720
2721 int __init io_apic_get_version (int ioapic)
2722 {
2723         union IO_APIC_reg_01    reg_01;
2724         unsigned long flags;
2725
2726         spin_lock_irqsave(&ioapic_lock, flags);
2727         reg_01.raw = io_apic_read(ioapic, 1);
2728         spin_unlock_irqrestore(&ioapic_lock, flags);
2729
2730         return reg_01.bits.version;
2731 }
2732
2733
2734 int __init io_apic_get_redir_entries (int ioapic)
2735 {
2736         union IO_APIC_reg_01    reg_01;
2737         unsigned long flags;
2738
2739         spin_lock_irqsave(&ioapic_lock, flags);
2740         reg_01.raw = io_apic_read(ioapic, 1);
2741         spin_unlock_irqrestore(&ioapic_lock, flags);
2742
2743         return reg_01.bits.entries;
2744 }
2745
2746
2747 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2748 {
2749         struct IO_APIC_route_entry entry;
2750         unsigned long flags;
2751
2752         if (!IO_APIC_IRQ(irq)) {
2753                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2754                         ioapic);
2755                 return -EINVAL;
2756         }
2757
2758         /*
2759          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2760          * Note that we mask (disable) IRQs now -- these get enabled when the
2761          * corresponding device driver registers for this IRQ.
2762          */
2763
2764         memset(&entry,0,sizeof(entry));
2765
2766         entry.delivery_mode = INT_DELIVERY_MODE;
2767         entry.dest_mode = INT_DEST_MODE;
2768         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2769         entry.trigger = edge_level;
2770         entry.polarity = active_high_low;
2771         entry.mask  = 1;
2772
2773         /*
2774          * IRQs < 16 are already in the irq_2_pin[] map
2775          */
2776         if (irq >= 16)
2777                 add_pin_to_irq(irq, ioapic, pin);
2778
2779         entry.vector = assign_irq_vector(irq);
2780
2781         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2782                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2783                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2784                 edge_level, active_high_low);
2785
2786         ioapic_register_intr(irq, entry.vector, edge_level);
2787
2788         if (!ioapic && (irq < 16))
2789                 disable_8259A_irq(irq);
2790
2791         spin_lock_irqsave(&ioapic_lock, flags);
2792         __ioapic_write_entry(ioapic, pin, entry);
2793         spin_unlock_irqrestore(&ioapic_lock, flags);
2794
2795         return 0;
2796 }
2797
2798 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2799 {
2800         int i;
2801
2802         if (skip_ioapic_setup)
2803                 return -1;
2804
2805         for (i = 0; i < mp_irq_entries; i++)
2806                 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2807                     mp_irqs[i].mpc_srcbusirq == bus_irq)
2808                         break;
2809         if (i >= mp_irq_entries)
2810                 return -1;
2811
2812         *trigger = irq_trigger(i);
2813         *polarity = irq_polarity(i);
2814         return 0;
2815 }
2816
2817 #endif /* CONFIG_ACPI */
2818
2819 static int __init parse_disable_timer_pin_1(char *arg)
2820 {
2821         disable_timer_pin_1 = 1;
2822         return 0;
2823 }
2824 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2825
2826 static int __init parse_enable_timer_pin_1(char *arg)
2827 {
2828         disable_timer_pin_1 = -1;
2829         return 0;
2830 }
2831 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2832
2833 static int __init parse_noapic(char *arg)
2834 {
2835         /* disable IO-APIC */
2836         disable_ioapic_setup();
2837         return 0;
2838 }
2839 early_param("noapic", parse_noapic);