git.oblomov.eu Git - linux-2.6/blob - drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/mm.h>
  16 #include <linux/timer.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/completion.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/platform_device.h>
  21
  22 #include <asm/blackfin.h>
  23 #include <asm/portmux.h>
  24 #include <asm/irq.h>
  25
  26 #define POLL_TIMEOUT       (2 * HZ)
  27
  28 /* SMBus mode*/
  29 #define TWI_I2C_MODE_STANDARD           1
  30 #define TWI_I2C_MODE_STANDARDSUB        2
  31 #define TWI_I2C_MODE_COMBINED           3
  32 #define TWI_I2C_MODE_REPEAT             4
  33
  34 struct bfin_twi_iface {
  35         int                     irq;
  36         spinlock_t              lock;
  37         char                    read_write;
  38         u8                      command;
  39         u8                      *transPtr;
  40         int                     readNum;
  41         int                     writeNum;
  42         int                     cur_mode;
  43         int                     manual_stop;
  44         int                     result;
  45         int                     timeout_count;
  46         struct timer_list       timeout_timer;
  47         struct i2c_adapter      adap;
  48         struct completion       complete;
  49         struct i2c_msg          *pmsg;
  50         int                     msg_num;
  51         int                     cur_msg;
  52         u16                     saved_clkdiv;
  53         u16                     saved_control;
  54         void __iomem            *regs_base;
  55 };
  56
  57
  58 #define DEFINE_TWI_REG(reg, off) \
  59 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  60         { return bfin_read16(iface->regs_base + (off)); } \
  61 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  62         { bfin_write16(iface->regs_base + (off), v); }
  63
  64 DEFINE_TWI_REG(CLKDIV, 0x00)
  65 DEFINE_TWI_REG(CONTROL, 0x04)
  66 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  67 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  68 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  69 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  70 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  71 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  72 DEFINE_TWI_REG(INT_STAT, 0x20)
  73 DEFINE_TWI_REG(INT_MASK, 0x24)
  74 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  75 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  76 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  77 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  78 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  79 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  80
  81 static const u16 pin_req[2][3] = {
  82         {P_TWI0_SCL, P_TWI0_SDA, 0},
  83         {P_TWI1_SCL, P_TWI1_SDA, 0},
  84 };
  85
  86 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
  87 {
  88         unsigned short twi_int_status = read_INT_STAT(iface);
  89         unsigned short mast_stat = read_MASTER_STAT(iface);
  90
  91         if (twi_int_status & XMTSERV) {
  92                 /* Transmit next data */
  93                 if (iface->writeNum > 0) {
  94                         write_XMT_DATA8(iface, *(iface->transPtr++));
  95                         iface->writeNum--;
  96                 }
  97                 /* start receive immediately after complete sending in
  98                  * combine mode.
  99                  */
 100                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
 101                         write_MASTER_CTL(iface,
 102                                 read_MASTER_CTL(iface) | MDIR | RSTART);
 103                 else if (iface->manual_stop)
 104                         write_MASTER_CTL(iface,
 105                                 read_MASTER_CTL(iface) | STOP);
 106                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 107                          iface->cur_msg + 1 < iface->msg_num) {
 108                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 109                                 write_MASTER_CTL(iface,
 110                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 111                         else
 112                                 write_MASTER_CTL(iface,
 113                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 114                 }
 115                 SSYNC();
 116                 /* Clear status */
 117                 write_INT_STAT(iface, XMTSERV);
 118                 SSYNC();
 119         }
 120         if (twi_int_status & RCVSERV) {
 121                 if (iface->readNum > 0) {
 122                         /* Receive next data */
 123                         *(iface->transPtr) = read_RCV_DATA8(iface);
 124                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 125                                 /* Change combine mode into sub mode after
 126                                  * read first data.
 127                                  */
 128                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 129                                 /* Get read number from first byte in block
 130                                  * combine mode.
 131                                  */
 132                                 if (iface->readNum == 1 && iface->manual_stop)
 133                                         iface->readNum = *iface->transPtr + 1;
 134                         }
 135                         iface->transPtr++;
 136                         iface->readNum--;
 137                 } else if (iface->manual_stop) {
 138                         write_MASTER_CTL(iface,
 139                                 read_MASTER_CTL(iface) | STOP);
 140                         SSYNC();
 141                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 142                            iface->cur_msg + 1 < iface->msg_num) {
 143                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 144                                 write_MASTER_CTL(iface,
 145                                         read_MASTER_CTL(iface) | RSTART | MDIR);
 146                         else
 147                                 write_MASTER_CTL(iface,
 148                                         (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
 149                         SSYNC();
 150                 }
 151                 /* Clear interrupt source */
 152                 write_INT_STAT(iface, RCVSERV);
 153                 SSYNC();
 154         }
 155         if (twi_int_status & MERR) {
 156                 write_INT_STAT(iface, MERR);
 157                 write_INT_MASK(iface, 0);
 158                 write_MASTER_STAT(iface, 0x3e);
 159                 write_MASTER_CTL(iface, 0);
 160                 SSYNC();
 161                 iface->result = -EIO;
 162                 /* if both err and complete int stats are set, return proper
 163                  * results.
 164                  */
 165                 if (twi_int_status & MCOMP) {
 166                         write_INT_STAT(iface, MCOMP);
 167                         write_INT_MASK(iface, 0);
 168                         write_MASTER_CTL(iface, 0);
 169                         SSYNC();
 170                         /* If it is a quick transfer, only address bug no data,
 171                          * not an err, return 1.
 172                          */
 173                         if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
 174                                 iface->result = 1;
 175                         /* If address not acknowledged return -1,
 176                          * else return 0.
 177                          */
 178                         else if (!(mast_stat & ANAK))
 179                                 iface->result = 0;
 180                 }
 181                 complete(&iface->complete);
 182                 return;
 183         }
 184         if (twi_int_status & MCOMP) {
 185                 write_INT_STAT(iface, MCOMP);
 186                 SSYNC();
 187                 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 188                         if (iface->readNum == 0) {
 189                                 /* set the read number to 1 and ask for manual
 190                                  * stop in block combine mode
 191                                  */
 192                                 iface->readNum = 1;
 193                                 iface->manual_stop = 1;
 194                                 write_MASTER_CTL(iface,
 195                                         read_MASTER_CTL(iface) | (0xff << 6));
 196                         } else {
 197                                 /* set the readd number in other
 198                                  * combine mode.
 199                                  */
 200                                 write_MASTER_CTL(iface,
 201                                         (read_MASTER_CTL(iface) &
 202                                         (~(0xff << 6))) |
 203                                         (iface->readNum << 6));
 204                         }
 205                         /* remove restart bit and enable master receive */
 206                         write_MASTER_CTL(iface,
 207                                 read_MASTER_CTL(iface) & ~RSTART);
 208                         SSYNC();
 209                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 210                                 iface->cur_msg+1 < iface->msg_num) {
 211                         iface->cur_msg++;
 212                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 213                         iface->writeNum = iface->readNum =
 214                                 iface->pmsg[iface->cur_msg].len;
 215                         /* Set Transmit device address */
 216                         write_MASTER_ADDR(iface,
 217                                 iface->pmsg[iface->cur_msg].addr);
 218                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 219                                 iface->read_write = I2C_SMBUS_READ;
 220                         else {
 221                                 iface->read_write = I2C_SMBUS_WRITE;
 222                                 /* Transmit first data */
 223                                 if (iface->writeNum > 0) {
 224                                         write_XMT_DATA8(iface,
 225                                                 *(iface->transPtr++));
 226                                         iface->writeNum--;
 227                                         SSYNC();
 228                                 }
 229                         }
 230
 231                         if (iface->pmsg[iface->cur_msg].len <= 255)
 232                                         write_MASTER_CTL(iface,
 233                                         (read_MASTER_CTL(iface) &
 234                                         (~(0xff << 6))) |
 235                                 (iface->pmsg[iface->cur_msg].len << 6));
 236                         else {
 237                                 write_MASTER_CTL(iface,
 238                                         (read_MASTER_CTL(iface) |
 239                                         (0xff << 6)));
 240                                 iface->manual_stop = 1;
 241                         }
 242                         /* remove restart bit and enable master receive */
 243                         write_MASTER_CTL(iface,
 244                                 read_MASTER_CTL(iface) & ~RSTART);
 245                         SSYNC();
 246                 } else {
 247                         iface->result = 1;
 248                         write_INT_MASK(iface, 0);
 249                         write_MASTER_CTL(iface, 0);
 250                         SSYNC();
 251                         complete(&iface->complete);
 252                 }
 253         }
 254 }
 255
 256 /* Interrupt handler */
 257 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 258 {
 259         struct bfin_twi_iface *iface = dev_id;
 260         unsigned long flags;
 261
 262         spin_lock_irqsave(&iface->lock, flags);
 263         del_timer(&iface->timeout_timer);
 264         bfin_twi_handle_interrupt(iface);
 265         spin_unlock_irqrestore(&iface->lock, flags);
 266         return IRQ_HANDLED;
 267 }
 268
 269 static void bfin_twi_timeout(unsigned long data)
 270 {
 271         struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
 272         unsigned long flags;
 273
 274         spin_lock_irqsave(&iface->lock, flags);
 275         bfin_twi_handle_interrupt(iface);
 276         if (iface->result == 0) {
 277                 iface->timeout_count--;
 278                 if (iface->timeout_count > 0) {
 279                         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 280                         add_timer(&iface->timeout_timer);
 281                 } else {
 282                         iface->result = -1;
 283                         complete(&iface->complete);
 284                 }
 285         }
 286         spin_unlock_irqrestore(&iface->lock, flags);
 287 }
 288
 289 /*
 290  * Generic i2c master transfer entrypoint
 291  */
 292 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 293                                 struct i2c_msg *msgs, int num)
 294 {
 295         struct bfin_twi_iface *iface = adap->algo_data;
 296         struct i2c_msg *pmsg;
 297         int rc = 0;
 298
 299         if (!(read_CONTROL(iface) & TWI_ENA))
 300                 return -ENXIO;
 301
 302         while (read_MASTER_STAT(iface) & BUSBUSY)
 303                 yield();
 304
 305         iface->pmsg = msgs;
 306         iface->msg_num = num;
 307         iface->cur_msg = 0;
 308
 309         pmsg = &msgs[0];
 310         if (pmsg->flags & I2C_M_TEN) {
 311                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 312                 return -EINVAL;
 313         }
 314
 315         iface->cur_mode = TWI_I2C_MODE_REPEAT;
 316         iface->manual_stop = 0;
 317         iface->transPtr = pmsg->buf;
 318         iface->writeNum = iface->readNum = pmsg->len;
 319         iface->result = 0;
 320         iface->timeout_count = 10;
 321         init_completion(&(iface->complete));
 322         /* Set Transmit device address */
 323         write_MASTER_ADDR(iface, pmsg->addr);
 324
 325         /* FIFO Initiation. Data in FIFO should be
 326          *  discarded before start a new operation.
 327          */
 328         write_FIFO_CTL(iface, 0x3);
 329         SSYNC();
 330         write_FIFO_CTL(iface, 0);
 331         SSYNC();
 332
 333         if (pmsg->flags & I2C_M_RD)
 334                 iface->read_write = I2C_SMBUS_READ;
 335         else {
 336                 iface->read_write = I2C_SMBUS_WRITE;
 337                 /* Transmit first data */
 338                 if (iface->writeNum > 0) {
 339                         write_XMT_DATA8(iface, *(iface->transPtr++));
 340                         iface->writeNum--;
 341                         SSYNC();
 342                 }
 343         }
 344
 345         /* clear int stat */
 346         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 347
 348         /* Interrupt mask . Enable XMT, RCV interrupt */
 349         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 350         SSYNC();
 351
 352         if (pmsg->len <= 255)
 353                 write_MASTER_CTL(iface, pmsg->len << 6);
 354         else {
 355                 write_MASTER_CTL(iface, 0xff << 6);
 356                 iface->manual_stop = 1;
 357         }
 358
 359         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 360         add_timer(&iface->timeout_timer);
 361
 362         /* Master enable */
 363         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 364                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 365                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 366         SSYNC();
 367
 368         wait_for_completion(&iface->complete);
 369
 370         rc = iface->result;
 371
 372         if (rc == 1)
 373                 return num;
 374         else
 375                 return rc;
 376 }
 377
 378 /*
 379  * SMBus type transfer entrypoint
 380  */
 381
 382 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 383                         unsigned short flags, char read_write,
 384                         u8 command, int size, union i2c_smbus_data *data)
 385 {
 386         struct bfin_twi_iface *iface = adap->algo_data;
 387         int rc = 0;
 388
 389         if (!(read_CONTROL(iface) & TWI_ENA))
 390                 return -ENXIO;
 391
 392         while (read_MASTER_STAT(iface) & BUSBUSY)
 393                 yield();
 394
 395         iface->writeNum = 0;
 396         iface->readNum = 0;
 397
 398         /* Prepare datas & select mode */
 399         switch (size) {
 400         case I2C_SMBUS_QUICK:
 401                 iface->transPtr = NULL;
 402                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 403                 break;
 404         case I2C_SMBUS_BYTE:
 405                 if (data == NULL)
 406                         iface->transPtr = NULL;
 407                 else {
 408                         if (read_write == I2C_SMBUS_READ)
 409                                 iface->readNum = 1;
 410                         else
 411                                 iface->writeNum = 1;
 412                         iface->transPtr = &data->byte;
 413                 }
 414                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 415                 break;
 416         case I2C_SMBUS_BYTE_DATA:
 417                 if (read_write == I2C_SMBUS_READ) {
 418                         iface->readNum = 1;
 419                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 420                 } else {
 421                         iface->writeNum = 1;
 422                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 423                 }
 424                 iface->transPtr = &data->byte;
 425                 break;
 426         case I2C_SMBUS_WORD_DATA:
 427                 if (read_write == I2C_SMBUS_READ) {
 428                         iface->readNum = 2;
 429                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 430                 } else {
 431                         iface->writeNum = 2;
 432                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 433                 }
 434                 iface->transPtr = (u8 *)&data->word;
 435                 break;
 436         case I2C_SMBUS_PROC_CALL:
 437                 iface->writeNum = 2;
 438                 iface->readNum = 2;
 439                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 440                 iface->transPtr = (u8 *)&data->word;
 441                 break;
 442         case I2C_SMBUS_BLOCK_DATA:
 443                 if (read_write == I2C_SMBUS_READ) {
 444                         iface->readNum = 0;
 445                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 446                 } else {
 447                         iface->writeNum = data->block[0] + 1;
 448                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 449                 }
 450                 iface->transPtr = data->block;
 451                 break;
 452         case I2C_SMBUS_I2C_BLOCK_DATA:
 453                 if (read_write == I2C_SMBUS_READ) {
 454                         iface->readNum = data->block[0];
 455                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 456                 } else {
 457                         iface->writeNum = data->block[0];
 458                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 459                 }
 460                 iface->transPtr = (u8 *)&data->block[1];
 461                 break;
 462         default:
 463                 return -1;
 464         }
 465
 466         iface->result = 0;
 467         iface->manual_stop = 0;
 468         iface->read_write = read_write;
 469         iface->command = command;
 470         iface->timeout_count = 10;
 471         init_completion(&(iface->complete));
 472
 473         /* FIFO Initiation. Data in FIFO should be discarded before
 474          * start a new operation.
 475          */
 476         write_FIFO_CTL(iface, 0x3);
 477         SSYNC();
 478         write_FIFO_CTL(iface, 0);
 479
 480         /* clear int stat */
 481         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 482
 483         /* Set Transmit device address */
 484         write_MASTER_ADDR(iface, addr);
 485         SSYNC();
 486
 487         iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
 488         add_timer(&iface->timeout_timer);
 489
 490         switch (iface->cur_mode) {
 491         case TWI_I2C_MODE_STANDARDSUB:
 492                 write_XMT_DATA8(iface, iface->command);
 493                 write_INT_MASK(iface, MCOMP | MERR |
 494                         ((iface->read_write == I2C_SMBUS_READ) ?
 495                         RCVSERV : XMTSERV));
 496                 SSYNC();
 497
 498                 if (iface->writeNum + 1 <= 255)
 499                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 500                 else {
 501                         write_MASTER_CTL(iface, 0xff << 6);
 502                         iface->manual_stop = 1;
 503                 }
 504                 /* Master enable */
 505                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 506                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 507                 break;
 508         case TWI_I2C_MODE_COMBINED:
 509                 write_XMT_DATA8(iface, iface->command);
 510                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 511                 SSYNC();
 512
 513                 if (iface->writeNum > 0)
 514                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 515                 else
 516                         write_MASTER_CTL(iface, 0x1 << 6);
 517                 /* Master enable */
 518                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 519                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 520                 break;
 521         default:
 522                 write_MASTER_CTL(iface, 0);
 523                 if (size != I2C_SMBUS_QUICK) {
 524                         /* Don't access xmit data register when this is a
 525                          * read operation.
 526                          */
 527                         if (iface->read_write != I2C_SMBUS_READ) {
 528                                 if (iface->writeNum > 0) {
 529                                         write_XMT_DATA8(iface,
 530                                                 *(iface->transPtr++));
 531                                         if (iface->writeNum <= 255)
 532                                                 write_MASTER_CTL(iface,
 533                                                         iface->writeNum << 6);
 534                                         else {
 535                                                 write_MASTER_CTL(iface,
 536                                                         0xff << 6);
 537                                                 iface->manual_stop = 1;
 538                                         }
 539                                         iface->writeNum--;
 540                                 } else {
 541                                         write_XMT_DATA8(iface, iface->command);
 542                                         write_MASTER_CTL(iface, 1 << 6);
 543                                 }
 544                         } else {
 545                                 if (iface->readNum > 0 && iface->readNum <= 255)
 546                                         write_MASTER_CTL(iface,
 547                                                 iface->readNum << 6);
 548                                 else if (iface->readNum > 255) {
 549                                         write_MASTER_CTL(iface, 0xff << 6);
 550                                         iface->manual_stop = 1;
 551                                 } else {
 552                                         del_timer(&iface->timeout_timer);
 553                                         break;
 554                                 }
 555                         }
 556                 }
 557                 write_INT_MASK(iface, MCOMP | MERR |
 558                         ((iface->read_write == I2C_SMBUS_READ) ?
 559                         RCVSERV : XMTSERV));
 560                 SSYNC();
 561
 562                 /* Master enable */
 563                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 564                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 565                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 566                 break;
 567         }
 568         SSYNC();
 569
 570         wait_for_completion(&iface->complete);
 571
 572         rc = (iface->result >= 0) ? 0 : -1;
 573
 574         return rc;
 575 }
 576
 577 /*
 578  * Return what the adapter supports
 579  */
 580 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 581 {
 582         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 583                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 584                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 585                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 586 }
 587
 588 static struct i2c_algorithm bfin_twi_algorithm = {
 589         .master_xfer   = bfin_twi_master_xfer,
 590         .smbus_xfer    = bfin_twi_smbus_xfer,
 591         .functionality = bfin_twi_functionality,
 592 };
 593
 594 static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state)
 595 {
 596         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 597
 598         iface->saved_clkdiv = read_CLKDIV(iface);
 599         iface->saved_control = read_CONTROL(iface);
 600
 601         free_irq(iface->irq, iface);
 602
 603         /* Disable TWI */
 604         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 605
 606         return 0;
 607 }
 608
 609 static int i2c_bfin_twi_resume(struct platform_device *pdev)
 610 {
 611         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 612
 613         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 614                 IRQF_DISABLED, pdev->name, iface);
 615         if (rc) {
 616                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 617                 return -ENODEV;
 618         }
 619
 620         /* Resume TWI interface clock as specified */
 621         write_CLKDIV(iface, iface->saved_clkdiv);
 622
 623         /* Resume TWI */
 624         write_CONTROL(iface, iface->saved_control);
 625
 626         return 0;
 627 }
 628
 629 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 630 {
 631         struct bfin_twi_iface *iface;
 632         struct i2c_adapter *p_adap;
 633         struct resource *res;
 634         int rc;
 635         unsigned int clkhilow;
 636
 637         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 638         if (!iface) {
 639                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 640                 rc = -ENOMEM;
 641                 goto out_error_nomem;
 642         }
 643
 644         spin_lock_init(&(iface->lock));
 645
 646         /* Find and map our resources */
 647         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 648         if (res == NULL) {
 649                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 650                 rc = -ENOENT;
 651                 goto out_error_get_res;
 652         }
 653
 654         iface->regs_base = ioremap(res->start, res->end - res->start + 1);
 655         if (iface->regs_base == NULL) {
 656                 dev_err(&pdev->dev, "Cannot map IO\n");
 657                 rc = -ENXIO;
 658                 goto out_error_ioremap;
 659         }
 660
 661         iface->irq = platform_get_irq(pdev, 0);
 662         if (iface->irq < 0) {
 663                 dev_err(&pdev->dev, "No IRQ specified\n");
 664                 rc = -ENOENT;
 665                 goto out_error_no_irq;
 666         }
 667
 668         init_timer(&(iface->timeout_timer));
 669         iface->timeout_timer.function = bfin_twi_timeout;
 670         iface->timeout_timer.data = (unsigned long)iface;
 671
 672         p_adap = &iface->adap;
 673         p_adap->nr = pdev->id;
 674         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 675         p_adap->algo = &bfin_twi_algorithm;
 676         p_adap->algo_data = iface;
 677         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 678         p_adap->dev.parent = &pdev->dev;
 679
 680         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
 681         if (rc) {
 682                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 683                 goto out_error_pin_mux;
 684         }
 685
 686         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 687                 IRQF_DISABLED, pdev->name, iface);
 688         if (rc) {
 689                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 690                 rc = -ENODEV;
 691                 goto out_error_req_irq;
 692         }
 693
 694         /* Set TWI internal clock as 10MHz */
 695         write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
 696
 697         /*
 698          * We will not end up with a CLKDIV=0 because no one will specify
 699          * 20kHz SCL or less in Kconfig now. (5 * 1024 / 20 = 0x100)
 700          */
 701         clkhilow = 5 * 1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ;
 702
 703         /* Set Twi interface clock as specified */
 704         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 705
 706         /* Enable TWI */
 707         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 708         SSYNC();
 709
 710         rc = i2c_add_numbered_adapter(p_adap);
 711         if (rc < 0) {
 712                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 713                 goto out_error_add_adapter;
 714         }
 715
 716         platform_set_drvdata(pdev, iface);
 717
 718         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 719                 "regs_base@%p\n", iface->regs_base);
 720
 721         return 0;
 722
 723 out_error_add_adapter:
 724         free_irq(iface->irq, iface);
 725 out_error_req_irq:
 726 out_error_no_irq:
 727         peripheral_free_list(pin_req[pdev->id]);
 728 out_error_pin_mux:
 729         iounmap(iface->regs_base);
 730 out_error_ioremap:
 731 out_error_get_res:
 732         kfree(iface);
 733 out_error_nomem:
 734         return rc;
 735 }
 736
 737 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 738 {
 739         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 740
 741         platform_set_drvdata(pdev, NULL);
 742
 743         i2c_del_adapter(&(iface->adap));
 744         free_irq(iface->irq, iface);
 745         peripheral_free_list(pin_req[pdev->id]);
 746         iounmap(iface->regs_base);
 747         kfree(iface);
 748
 749         return 0;
 750 }
 751
 752 static struct platform_driver i2c_bfin_twi_driver = {
 753         .probe          = i2c_bfin_twi_probe,
 754         .remove         = i2c_bfin_twi_remove,
 755         .suspend        = i2c_bfin_twi_suspend,
 756         .resume         = i2c_bfin_twi_resume,
 757         .driver         = {
 758                 .name   = "i2c-bfin-twi",
 759                 .owner  = THIS_MODULE,
 760         },
 761 };
 762
 763 static int __init i2c_bfin_twi_init(void)
 764 {
 765         return platform_driver_register(&i2c_bfin_twi_driver);
 766 }
 767
 768 static void __exit i2c_bfin_twi_exit(void)
 769 {
 770         platform_driver_unregister(&i2c_bfin_twi_driver);
 771 }
 772
 773 module_init(i2c_bfin_twi_init);
 774 module_exit(i2c_bfin_twi_exit);
 775
 776 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 777 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 778 MODULE_LICENSE("GPL");
 779 MODULE_ALIAS("platform:i2c-bfin-twi");