1 /******************************************************************************
2 * QLOGIC LINUX SOFTWARE
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2005 QLogic Corporation
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 ******************************************************************************/
22 #include <linux/delay.h>
23 #include <asm/uaccess.h>
25 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
26 static void qla2x00_nv_deselect(scsi_qla_host_t *);
27 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
30 * NVRAM support routines
34 * qla2x00_lock_nvram_access() -
38 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
41 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
43 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
44 data = RD_REG_WORD(®->nvram);
45 while (data & NVR_BUSY) {
47 data = RD_REG_WORD(®->nvram);
51 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
52 RD_REG_WORD(®->u.isp2300.host_semaphore);
54 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
55 while ((data & BIT_0) == 0) {
58 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
59 RD_REG_WORD(®->u.isp2300.host_semaphore);
61 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
67 * qla2x00_unlock_nvram_access() -
71 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
76 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
77 RD_REG_WORD(®->u.isp2300.host_semaphore);
82 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
83 * request routine to get the word from NVRAM.
85 * @addr: Address in NVRAM to read
87 * Returns the word read from nvram @addr.
90 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
97 data = qla2x00_nvram_request(ha, nv_cmd);
103 * qla2x00_write_nvram_word() - Write NVRAM data.
105 * @addr: Address in NVRAM to write
106 * @data: word to program
109 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
114 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
116 qla2x00_nv_write(ha, NVR_DATA_OUT);
117 qla2x00_nv_write(ha, 0);
118 qla2x00_nv_write(ha, 0);
120 for (word = 0; word < 8; word++)
121 qla2x00_nv_write(ha, NVR_DATA_OUT);
123 qla2x00_nv_deselect(ha);
126 nv_cmd = (addr << 16) | NV_WRITE_OP;
129 for (count = 0; count < 27; count++) {
131 qla2x00_nv_write(ha, NVR_DATA_OUT);
133 qla2x00_nv_write(ha, 0);
138 qla2x00_nv_deselect(ha);
140 /* Wait for NVRAM to become ready */
141 WRT_REG_WORD(®->nvram, NVR_SELECT);
144 word = RD_REG_WORD(®->nvram);
145 } while ((word & NVR_DATA_IN) == 0);
147 qla2x00_nv_deselect(ha);
150 qla2x00_nv_write(ha, NVR_DATA_OUT);
151 for (count = 0; count < 10; count++)
152 qla2x00_nv_write(ha, 0);
154 qla2x00_nv_deselect(ha);
158 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
164 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
168 qla2x00_nv_write(ha, NVR_DATA_OUT);
169 qla2x00_nv_write(ha, 0);
170 qla2x00_nv_write(ha, 0);
172 for (word = 0; word < 8; word++)
173 qla2x00_nv_write(ha, NVR_DATA_OUT);
175 qla2x00_nv_deselect(ha);
178 nv_cmd = (addr << 16) | NV_WRITE_OP;
181 for (count = 0; count < 27; count++) {
183 qla2x00_nv_write(ha, NVR_DATA_OUT);
185 qla2x00_nv_write(ha, 0);
190 qla2x00_nv_deselect(ha);
192 /* Wait for NVRAM to become ready */
193 WRT_REG_WORD(®->nvram, NVR_SELECT);
196 word = RD_REG_WORD(®->nvram);
198 ret = QLA_FUNCTION_FAILED;
201 } while ((word & NVR_DATA_IN) == 0);
203 qla2x00_nv_deselect(ha);
206 qla2x00_nv_write(ha, NVR_DATA_OUT);
207 for (count = 0; count < 10; count++)
208 qla2x00_nv_write(ha, 0);
210 qla2x00_nv_deselect(ha);
216 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
219 * @nv_cmd: NVRAM command
221 * Bit definitions for NVRAM command:
224 * Bit 25, 24 = opcode
225 * Bit 23-16 = address
226 * Bit 15-0 = write data
228 * Returns the word read from nvram @addr.
231 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
234 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
238 /* Send command to NVRAM. */
240 for (cnt = 0; cnt < 11; cnt++) {
242 qla2x00_nv_write(ha, NVR_DATA_OUT);
244 qla2x00_nv_write(ha, 0);
248 /* Read data from NVRAM. */
249 for (cnt = 0; cnt < 16; cnt++) {
250 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
253 reg_data = RD_REG_WORD(®->nvram);
254 if (reg_data & NVR_DATA_IN)
256 WRT_REG_WORD(®->nvram, NVR_SELECT);
257 RD_REG_WORD(®->nvram); /* PCI Posting. */
262 WRT_REG_WORD(®->nvram, NVR_DESELECT);
263 RD_REG_WORD(®->nvram); /* PCI Posting. */
270 * qla2x00_nv_write() - Clean NVRAM operations.
274 qla2x00_nv_deselect(scsi_qla_host_t *ha)
276 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
278 WRT_REG_WORD(®->nvram, NVR_DESELECT);
279 RD_REG_WORD(®->nvram); /* PCI Posting. */
284 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
286 * @data: Serial interface selector
289 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
291 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
293 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
294 RD_REG_WORD(®->nvram); /* PCI Posting. */
296 WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK |
298 RD_REG_WORD(®->nvram); /* PCI Posting. */
300 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
301 RD_REG_WORD(®->nvram); /* PCI Posting. */
306 * qla2x00_clear_nvram_protection() -
310 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
313 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
315 uint16_t wprot, wprot_old;
317 /* Clear NVRAM write protection. */
318 ret = QLA_FUNCTION_FAILED;
319 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
320 stat = qla2x00_write_nvram_word_tmo(ha, 0,
321 __constant_cpu_to_le16(0x1234), 100000);
322 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
323 if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
325 qla2x00_nv_write(ha, NVR_DATA_OUT);
326 qla2x00_nv_write(ha, 0);
327 qla2x00_nv_write(ha, 0);
328 for (word = 0; word < 8; word++)
329 qla2x00_nv_write(ha, NVR_DATA_OUT);
331 qla2x00_nv_deselect(ha);
333 /* Enable protection register. */
334 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
335 qla2x00_nv_write(ha, NVR_PR_ENABLE);
336 qla2x00_nv_write(ha, NVR_PR_ENABLE);
337 for (word = 0; word < 8; word++)
338 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
340 qla2x00_nv_deselect(ha);
342 /* Clear protection register (ffff is cleared). */
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
345 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
346 for (word = 0; word < 8; word++)
347 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
349 qla2x00_nv_deselect(ha);
351 /* Wait for NVRAM to become ready. */
352 WRT_REG_WORD(®->nvram, NVR_SELECT);
355 word = RD_REG_WORD(®->nvram);
356 } while ((word & NVR_DATA_IN) == 0);
360 qla2x00_write_nvram_word(ha, 0, wprot_old);
366 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
368 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
371 if (stat != QLA_SUCCESS)
374 /* Set NVRAM write protection. */
376 qla2x00_nv_write(ha, NVR_DATA_OUT);
377 qla2x00_nv_write(ha, 0);
378 qla2x00_nv_write(ha, 0);
379 for (word = 0; word < 8; word++)
380 qla2x00_nv_write(ha, NVR_DATA_OUT);
382 qla2x00_nv_deselect(ha);
384 /* Enable protection register. */
385 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
386 qla2x00_nv_write(ha, NVR_PR_ENABLE);
387 qla2x00_nv_write(ha, NVR_PR_ENABLE);
388 for (word = 0; word < 8; word++)
389 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
391 qla2x00_nv_deselect(ha);
393 /* Enable protection register. */
394 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
395 qla2x00_nv_write(ha, NVR_PR_ENABLE);
396 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
397 for (word = 0; word < 8; word++)
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
400 qla2x00_nv_deselect(ha);
402 /* Wait for NVRAM to become ready. */
403 WRT_REG_WORD(®->nvram, NVR_SELECT);
406 word = RD_REG_WORD(®->nvram);
407 } while ((word & NVR_DATA_IN) == 0);
411 /*****************************************************************************/
412 /* Flash Manipulation Routines */
413 /*****************************************************************************/
415 static inline uint32_t
416 flash_conf_to_access_addr(uint32_t faddr)
418 return FARX_ACCESS_FLASH_CONF | faddr;
421 static inline uint32_t
422 flash_data_to_access_addr(uint32_t faddr)
424 return FARX_ACCESS_FLASH_DATA | faddr;
427 static inline uint32_t
428 nvram_conf_to_access_addr(uint32_t naddr)
430 return FARX_ACCESS_NVRAM_CONF | naddr;
433 static inline uint32_t
434 nvram_data_to_access_addr(uint32_t naddr)
436 return FARX_ACCESS_NVRAM_DATA | naddr;
440 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
444 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
446 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
447 /* Wait for READ cycle to complete. */
450 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
451 rval == QLA_SUCCESS; cnt--) {
455 rval = QLA_FUNCTION_TIMEOUT;
458 /* TODO: What happens if we time out? */
460 if (rval == QLA_SUCCESS)
461 data = RD_REG_DWORD(®->flash_data);
467 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
472 /* Dword reads to flash. */
473 for (i = 0; i < dwords; i++, faddr++)
474 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
475 flash_data_to_access_addr(faddr)));
481 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
485 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
487 WRT_REG_DWORD(®->flash_data, data);
488 RD_REG_DWORD(®->flash_data); /* PCI Posting. */
489 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
490 /* Wait for Write cycle to complete. */
492 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
493 rval == QLA_SUCCESS; cnt--) {
497 rval = QLA_FUNCTION_TIMEOUT;
503 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
508 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
510 *flash_id = MSB(ids);
514 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
519 uint32_t sec_mask, rest_addr, conf_addr;
521 uint8_t man_id, flash_id;
522 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
526 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
527 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
528 ha->host_no, man_id, flash_id));
530 conf_addr = flash_conf_to_access_addr(0x03d8);
532 case 0xbf: /* STT flash. */
535 if (flash_id == 0x80)
536 conf_addr = flash_conf_to_access_addr(0x0352);
538 case 0x13: /* ST M25P80. */
543 /* Default to 64 kb sector size. */
549 /* Enable flash write. */
550 WRT_REG_DWORD(®->ctrl_status,
551 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
552 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
554 /* Disable flash write-protection. */
555 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
557 do { /* Loop once to provide quick error exit. */
558 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
559 /* Are we at the beginning of a sector? */
560 if ((faddr & rest_addr) == 0) {
561 fdata = (faddr & sec_mask) << 2;
562 ret = qla24xx_write_flash_dword(ha, conf_addr,
563 (fdata & 0xff00) |((fdata << 16) &
564 0xff0000) | ((fdata >> 16) & 0xff));
565 if (ret != QLA_SUCCESS) {
566 DEBUG9(printk("%s(%ld) Unable to flash "
567 "sector: address=%x.\n", __func__,
568 ha->host_no, faddr));
572 ret = qla24xx_write_flash_dword(ha,
573 flash_data_to_access_addr(faddr),
574 cpu_to_le32(*dwptr));
575 if (ret != QLA_SUCCESS) {
576 DEBUG9(printk("%s(%ld) Unable to program flash "
577 "address=%x data=%x.\n", __func__,
578 ha->host_no, faddr, *dwptr));
584 /* Disable flash write. */
585 WRT_REG_DWORD(®->ctrl_status,
586 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
587 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
593 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
599 /* Word reads to NVRAM via registers. */
600 wptr = (uint16_t *)buf;
601 qla2x00_lock_nvram_access(ha);
602 for (i = 0; i < bytes >> 1; i++, naddr++)
603 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
605 qla2x00_unlock_nvram_access(ha);
611 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
617 /* Dword reads to flash. */
618 dwptr = (uint32_t *)buf;
619 for (i = 0; i < bytes >> 2; i++, naddr++)
620 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
621 nvram_data_to_access_addr(naddr)));
627 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
636 qla2x00_lock_nvram_access(ha);
638 /* Disable NVRAM write-protection. */
639 stat = qla2x00_clear_nvram_protection(ha);
641 wptr = (uint16_t *)buf;
642 for (i = 0; i < bytes >> 1; i++, naddr++) {
643 qla2x00_write_nvram_word(ha, naddr,
648 /* Enable NVRAM write-protection. */
649 qla2x00_set_nvram_protection(ha, stat);
651 qla2x00_unlock_nvram_access(ha);
657 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
663 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
667 /* Enable flash write. */
668 WRT_REG_DWORD(®->ctrl_status,
669 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
670 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
672 /* Disable NVRAM write-protection. */
673 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
675 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
678 /* Dword writes to flash. */
679 dwptr = (uint32_t *)buf;
680 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
681 ret = qla24xx_write_flash_dword(ha,
682 nvram_data_to_access_addr(naddr),
683 cpu_to_le32(*dwptr));
684 if (ret != QLA_SUCCESS) {
685 DEBUG9(printk("%s(%ld) Unable to program "
686 "nvram address=%x data=%x.\n", __func__,
687 ha->host_no, naddr, *dwptr));
692 /* Enable NVRAM write-protection. */
693 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
696 /* Disable flash write. */
697 WRT_REG_DWORD(®->ctrl_status,
698 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
699 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */