2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 unsigned int pci_pm_d3_delay = 10;
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus* bus)
34 struct list_head *tmp;
37 max = bus->subordinate;
38 list_for_each(tmp, &bus->children) {
39 n = pci_bus_max_busnr(pci_bus_b(tmp));
45 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
49 * pci_max_busnr - returns maximum PCI bus number
51 * Returns the highest PCI bus number present in the system global list of
54 unsigned char __devinit
57 struct pci_bus *bus = NULL;
61 while ((bus = pci_find_next_bus(bus)) != NULL) {
62 n = pci_bus_max_busnr(bus);
71 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
77 pci_bus_read_config_byte(bus, devfn, pos, &pos);
81 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
87 pos += PCI_CAP_LIST_NEXT;
92 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
94 return __pci_find_next_cap(dev->bus, dev->devfn,
95 pos + PCI_CAP_LIST_NEXT, cap);
97 EXPORT_SYMBOL_GPL(pci_find_next_capability);
99 static int __pci_bus_find_cap_start(struct pci_bus *bus,
100 unsigned int devfn, u8 hdr_type)
104 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
105 if (!(status & PCI_STATUS_CAP_LIST))
109 case PCI_HEADER_TYPE_NORMAL:
110 case PCI_HEADER_TYPE_BRIDGE:
111 return PCI_CAPABILITY_LIST;
112 case PCI_HEADER_TYPE_CARDBUS:
113 return PCI_CB_CAPABILITY_LIST;
122 * pci_find_capability - query for devices' capabilities
123 * @dev: PCI device to query
124 * @cap: capability code
126 * Tell if a device supports a given PCI capability.
127 * Returns the address of the requested capability structure within the
128 * device's PCI configuration space or 0 in case the device does not
129 * support it. Possible values for @cap:
131 * %PCI_CAP_ID_PM Power Management
132 * %PCI_CAP_ID_AGP Accelerated Graphics Port
133 * %PCI_CAP_ID_VPD Vital Product Data
134 * %PCI_CAP_ID_SLOTID Slot Identification
135 * %PCI_CAP_ID_MSI Message Signalled Interrupts
136 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
137 * %PCI_CAP_ID_PCIX PCI-X
138 * %PCI_CAP_ID_EXP PCI Express
140 int pci_find_capability(struct pci_dev *dev, int cap)
144 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
146 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
152 * pci_bus_find_capability - query for devices' capabilities
153 * @bus: the PCI bus to query
154 * @devfn: PCI device to query
155 * @cap: capability code
157 * Like pci_find_capability() but works for pci devices that do not have a
158 * pci_dev structure set up yet.
160 * Returns the address of the requested capability structure within the
161 * device's PCI configuration space or 0 in case the device does not
164 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
169 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
171 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
173 pos = __pci_find_next_cap(bus, devfn, pos, cap);
179 * pci_find_ext_capability - Find an extended capability
180 * @dev: PCI device to query
181 * @cap: capability code
183 * Returns the address of the requested extended capability structure
184 * within the device's PCI configuration space or 0 if the device does
185 * not support it. Possible values for @cap:
187 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
188 * %PCI_EXT_CAP_ID_VC Virtual Channel
189 * %PCI_EXT_CAP_ID_DSN Device Serial Number
190 * %PCI_EXT_CAP_ID_PWR Power Budgeting
192 int pci_find_ext_capability(struct pci_dev *dev, int cap)
195 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
198 if (dev->cfg_size <= 256)
201 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
205 * If we have no capabilities, this is indicated by cap ID,
206 * cap version and next pointer all being 0.
212 if (PCI_EXT_CAP_ID(header) == cap)
215 pos = PCI_EXT_CAP_NEXT(header);
219 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
225 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
228 * pci_find_parent_resource - return resource region of parent bus of given region
229 * @dev: PCI device structure contains resources to be searched
230 * @res: child resource record for which parent is sought
232 * For given resource region of given device, return the resource
233 * region of parent bus the given region is contained in or where
234 * it should be allocated from.
237 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
239 const struct pci_bus *bus = dev->bus;
241 struct resource *best = NULL;
243 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
244 struct resource *r = bus->resource[i];
247 if (res->start && !(res->start >= r->start && res->end <= r->end))
248 continue; /* Not contained */
249 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
250 continue; /* Wrong type */
251 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
252 return r; /* Exact match */
253 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
254 best = r; /* Approximating prefetchable by non-prefetchable */
260 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
261 * @dev: PCI device to have its BARs restored
263 * Restore the BAR values for a given device, so as to make it
264 * accessible by its driver.
267 pci_restore_bars(struct pci_dev *dev)
271 switch (dev->hdr_type) {
272 case PCI_HEADER_TYPE_NORMAL:
275 case PCI_HEADER_TYPE_BRIDGE:
278 case PCI_HEADER_TYPE_CARDBUS:
282 /* Should never get here, but just in case... */
286 for (i = 0; i < numres; i ++)
287 pci_update_resource(dev, &dev->resource[i], i);
290 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
293 * pci_set_power_state - Set the power state of a PCI device
294 * @dev: PCI device to be suspended
295 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
297 * Transition a device to a new power state, using the Power Management
298 * Capabilities in the device's config space.
301 * -EINVAL if trying to enter a lower state than we're already in.
302 * 0 if we're already in the requested state.
303 * -EIO if device does not support PCI PM.
304 * 0 if we can successfully change the power state.
307 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
309 int pm, need_restore = 0;
312 /* bound the state we're entering */
313 if (state > PCI_D3hot)
316 /* Validate current state:
317 * Can enter D0 from any state, but if we can only go deeper
318 * to sleep if we're already in a low power state
320 if (state != PCI_D0 && dev->current_state > state) {
321 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
322 __FUNCTION__, pci_name(dev), state, dev->current_state);
324 } else if (dev->current_state == state)
325 return 0; /* we're already there */
328 * If the device or the parent bridge can't support PCI PM, ignore
329 * the request if we're doing anything besides putting it into D0
330 * (which would only happen on boot).
332 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
335 /* find PCI PM capability in list */
336 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
338 /* abort if the device doesn't support PM capabilities */
342 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
343 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
345 "PCI: %s has unsupported PM cap regs version (%u)\n",
346 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
350 /* check if this device supports the desired state */
351 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
353 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
356 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
358 /* If we're (effectively) in D3, force entire word to 0.
359 * This doesn't affect PME_Status, disables PME_En, and
360 * sets PowerState to 0.
362 switch (dev->current_state) {
366 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
369 case PCI_UNKNOWN: /* Boot-up */
370 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
371 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
373 /* Fall-through: force to D0 */
379 /* enter specified state */
380 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
382 /* Mandatory power management transition delays */
383 /* see PCI PM 1.1 5.6.1 table 18 */
384 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
385 msleep(pci_pm_d3_delay);
386 else if (state == PCI_D2 || dev->current_state == PCI_D2)
390 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
391 * Firmware method after native method ?
393 if (platform_pci_set_power_state)
394 platform_pci_set_power_state(dev, state);
396 dev->current_state = state;
398 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
399 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
400 * from D3hot to D0 _may_ perform an internal reset, thereby
401 * going to "D0 Uninitialized" rather than "D0 Initialized".
402 * For example, at least some versions of the 3c905B and the
403 * 3c556B exhibit this behaviour.
405 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
406 * devices in a D3hot state at boot. Consequently, we need to
407 * restore at least the BARs so that the device will be
408 * accessible to its driver.
411 pci_restore_bars(dev);
416 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
419 * pci_choose_state - Choose the power state of a PCI device
420 * @dev: PCI device to be suspended
421 * @state: target sleep state for the whole system. This is the value
422 * that is passed to suspend() function.
424 * Returns PCI power state suitable for given device and given system
428 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
432 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
435 if (platform_pci_choose_state) {
436 ret = platform_pci_choose_state(dev, state);
441 switch (state.event) {
444 case PM_EVENT_FREEZE:
445 case PM_EVENT_PRETHAW:
446 /* REVISIT both freeze and pre-thaw "should" use D0 */
447 case PM_EVENT_SUSPEND:
450 printk("Unrecognized suspend event %d\n", state.event);
456 EXPORT_SYMBOL(pci_choose_state);
458 static int pci_save_pcie_state(struct pci_dev *dev)
461 struct pci_cap_saved_state *save_state;
464 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
468 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
470 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
473 cap = (u16 *)&save_state->data[0];
475 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
476 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
477 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
478 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
479 pci_add_saved_cap(dev, save_state);
483 static void pci_restore_pcie_state(struct pci_dev *dev)
486 struct pci_cap_saved_state *save_state;
489 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
490 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
491 if (!save_state || pos <= 0)
493 cap = (u16 *)&save_state->data[0];
495 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
496 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
497 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
498 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
499 pci_remove_saved_cap(save_state);
504 static int pci_save_pcix_state(struct pci_dev *dev)
507 struct pci_cap_saved_state *save_state;
510 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
514 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
516 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
519 cap = (u16 *)&save_state->data[0];
521 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
522 pci_add_saved_cap(dev, save_state);
526 static void pci_restore_pcix_state(struct pci_dev *dev)
529 struct pci_cap_saved_state *save_state;
532 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
533 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
534 if (!save_state || pos <= 0)
536 cap = (u16 *)&save_state->data[0];
538 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
539 pci_remove_saved_cap(save_state);
545 * pci_save_state - save the PCI configuration space of a device before suspending
546 * @dev: - PCI device that we're dealing with
549 pci_save_state(struct pci_dev *dev)
552 /* XXX: 100% dword access ok here? */
553 for (i = 0; i < 16; i++)
554 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
555 if ((i = pci_save_msi_state(dev)) != 0)
557 if ((i = pci_save_msix_state(dev)) != 0)
559 if ((i = pci_save_pcie_state(dev)) != 0)
561 if ((i = pci_save_pcix_state(dev)) != 0)
567 * pci_restore_state - Restore the saved state of a PCI device
568 * @dev: - PCI device that we're dealing with
571 pci_restore_state(struct pci_dev *dev)
576 /* PCI Express register must be restored first */
577 pci_restore_pcie_state(dev);
580 * The Base Address register should be programmed before the command
583 for (i = 15; i >= 0; i--) {
584 pci_read_config_dword(dev, i * 4, &val);
585 if (val != dev->saved_config_space[i]) {
586 printk(KERN_DEBUG "PM: Writing back config space on "
587 "device %s at offset %x (was %x, writing %x)\n",
589 val, (int)dev->saved_config_space[i]);
590 pci_write_config_dword(dev,i * 4,
591 dev->saved_config_space[i]);
594 pci_restore_pcix_state(dev);
595 pci_restore_msi_state(dev);
596 pci_restore_msix_state(dev);
601 * pci_enable_device_bars - Initialize some of a device for use
602 * @dev: PCI device to be initialized
603 * @bars: bitmask of BAR's that must be configured
605 * Initialize device before it's used by a driver. Ask low-level code
606 * to enable selected I/O and memory resources. Wake up the device if it
607 * was suspended. Beware, this function can fail.
611 pci_enable_device_bars(struct pci_dev *dev, int bars)
615 err = pci_set_power_state(dev, PCI_D0);
616 if (err < 0 && err != -EIO)
618 err = pcibios_enable_device(dev, bars);
625 * __pci_enable_device - Initialize device before it's used by a driver.
626 * @dev: PCI device to be initialized
628 * Initialize device before it's used by a driver. Ask low-level code
629 * to enable I/O and memory. Wake up the device if it was suspended.
630 * Beware, this function can fail.
632 * Note this function is a backend and is not supposed to be called by
633 * normal code, use pci_enable_device() instead.
636 __pci_enable_device(struct pci_dev *dev)
640 err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
643 pci_fixup_device(pci_fixup_enable, dev);
648 * pci_enable_device - Initialize device before it's used by a driver.
649 * @dev: PCI device to be initialized
651 * Initialize device before it's used by a driver. Ask low-level code
652 * to enable I/O and memory. Wake up the device if it was suspended.
653 * Beware, this function can fail.
655 * Note we don't actually enable the device many times if we call
656 * this function repeatedly (we just increment the count).
658 int pci_enable_device(struct pci_dev *dev)
661 if (atomic_add_return(1, &dev->enable_cnt) > 1)
662 return 0; /* already enabled */
663 result = __pci_enable_device(dev);
665 atomic_dec(&dev->enable_cnt);
670 * pcibios_disable_device - disable arch specific PCI resources for device dev
671 * @dev: the PCI device to disable
673 * Disables architecture specific PCI resources for the device. This
674 * is the default implementation. Architecture implementations can
677 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
680 * pci_disable_device - Disable PCI device after use
681 * @dev: PCI device to be disabled
683 * Signal to the system that the PCI device is not in use by the system
684 * anymore. This only involves disabling PCI bus-mastering, if active.
686 * Note we don't actually disable the device until all callers of
687 * pci_device_enable() have called pci_device_disable().
690 pci_disable_device(struct pci_dev *dev)
694 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
697 if (dev->msi_enabled)
698 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
700 if (dev->msix_enabled)
701 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
704 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
705 if (pci_command & PCI_COMMAND_MASTER) {
706 pci_command &= ~PCI_COMMAND_MASTER;
707 pci_write_config_word(dev, PCI_COMMAND, pci_command);
709 dev->is_busmaster = 0;
711 pcibios_disable_device(dev);
715 * pci_enable_wake - enable device to generate PME# when suspended
716 * @dev: - PCI device to operate on
717 * @state: - Current state of device.
718 * @enable: - Flag to enable or disable generation
720 * Set the bits in the device's PM Capabilities to generate PME# when
721 * the system is suspended.
723 * -EIO is returned if device doesn't have PM Capabilities.
724 * -EINVAL is returned if device supports it, but can't generate wake events.
725 * 0 if operation is successful.
728 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
733 /* find PCI PM capability in list */
734 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
736 /* If device doesn't support PM Capabilities, but request is to disable
737 * wake events, it's a nop; otherwise fail */
739 return enable ? -EIO : 0;
741 /* Check device's ability to generate PME# */
742 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
744 value &= PCI_PM_CAP_PME_MASK;
745 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
747 /* Check if it can generate PME# from requested state. */
748 if (!value || !(value & (1 << state)))
749 return enable ? -EINVAL : 0;
751 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
753 /* Clear PME_Status by writing 1 to it and enable PME# */
754 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
757 value &= ~PCI_PM_CTRL_PME_ENABLE;
759 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
765 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
773 while (dev->bus->self) {
774 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
775 dev = dev->bus->self;
782 * pci_release_region - Release a PCI bar
783 * @pdev: PCI device whose resources were previously reserved by pci_request_region
784 * @bar: BAR to release
786 * Releases the PCI I/O and memory resources previously reserved by a
787 * successful call to pci_request_region. Call this function only
788 * after all use of the PCI regions has ceased.
790 void pci_release_region(struct pci_dev *pdev, int bar)
792 if (pci_resource_len(pdev, bar) == 0)
794 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
795 release_region(pci_resource_start(pdev, bar),
796 pci_resource_len(pdev, bar));
797 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
798 release_mem_region(pci_resource_start(pdev, bar),
799 pci_resource_len(pdev, bar));
803 * pci_request_region - Reserved PCI I/O and memory resource
804 * @pdev: PCI device whose resources are to be reserved
805 * @bar: BAR to be reserved
806 * @res_name: Name to be associated with resource.
808 * Mark the PCI region associated with PCI device @pdev BR @bar as
809 * being reserved by owner @res_name. Do not access any
810 * address inside the PCI regions unless this call returns
813 * Returns 0 on success, or %EBUSY on error. A warning
814 * message is also printed on failure.
816 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
818 if (pci_resource_len(pdev, bar) == 0)
821 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
822 if (!request_region(pci_resource_start(pdev, bar),
823 pci_resource_len(pdev, bar), res_name))
826 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
827 if (!request_mem_region(pci_resource_start(pdev, bar),
828 pci_resource_len(pdev, bar), res_name))
835 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
837 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
838 bar + 1, /* PCI BAR # */
839 (unsigned long long)pci_resource_len(pdev, bar),
840 (unsigned long long)pci_resource_start(pdev, bar),
847 * pci_release_regions - Release reserved PCI I/O and memory resources
848 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
850 * Releases all PCI I/O and memory resources previously reserved by a
851 * successful call to pci_request_regions. Call this function only
852 * after all use of the PCI regions has ceased.
855 void pci_release_regions(struct pci_dev *pdev)
859 for (i = 0; i < 6; i++)
860 pci_release_region(pdev, i);
864 * pci_request_regions - Reserved PCI I/O and memory resources
865 * @pdev: PCI device whose resources are to be reserved
866 * @res_name: Name to be associated with resource.
868 * Mark all PCI regions associated with PCI device @pdev as
869 * being reserved by owner @res_name. Do not access any
870 * address inside the PCI regions unless this call returns
873 * Returns 0 on success, or %EBUSY on error. A warning
874 * message is also printed on failure.
876 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
880 for (i = 0; i < 6; i++)
881 if(pci_request_region(pdev, i, res_name))
887 pci_release_region(pdev, i);
893 * pci_set_master - enables bus-mastering for device dev
894 * @dev: the PCI device to enable
896 * Enables bus-mastering on the device and calls pcibios_set_master()
897 * to do the needed arch specific settings.
900 pci_set_master(struct pci_dev *dev)
904 pci_read_config_word(dev, PCI_COMMAND, &cmd);
905 if (! (cmd & PCI_COMMAND_MASTER)) {
906 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
907 cmd |= PCI_COMMAND_MASTER;
908 pci_write_config_word(dev, PCI_COMMAND, cmd);
910 dev->is_busmaster = 1;
911 pcibios_set_master(dev);
914 #ifdef PCI_DISABLE_MWI
915 int pci_set_mwi(struct pci_dev *dev)
920 void pci_clear_mwi(struct pci_dev *dev)
926 #ifndef PCI_CACHE_LINE_BYTES
927 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
930 /* This can be overridden by arch code. */
931 /* Don't forget this is measured in 32-bit words, not bytes */
932 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
935 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
936 * @dev: the PCI device for which MWI is to be enabled
938 * Helper function for pci_set_mwi.
939 * Originally copied from drivers/net/acenic.c.
940 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
942 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
945 pci_set_cacheline_size(struct pci_dev *dev)
949 if (!pci_cache_line_size)
950 return -EINVAL; /* The system doesn't support MWI. */
952 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
953 equal to or multiple of the right value. */
954 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
955 if (cacheline_size >= pci_cache_line_size &&
956 (cacheline_size % pci_cache_line_size) == 0)
959 /* Write the correct value. */
960 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
962 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
963 if (cacheline_size == pci_cache_line_size)
966 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
967 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
973 * pci_set_mwi - enables memory-write-invalidate PCI transaction
974 * @dev: the PCI device for which MWI is enabled
976 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
977 * and then calls @pcibios_set_mwi to do the needed arch specific
978 * operations or a generic mwi-prep function.
980 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
983 pci_set_mwi(struct pci_dev *dev)
988 rc = pci_set_cacheline_size(dev);
992 pci_read_config_word(dev, PCI_COMMAND, &cmd);
993 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
994 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
995 cmd |= PCI_COMMAND_INVALIDATE;
996 pci_write_config_word(dev, PCI_COMMAND, cmd);
1003 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1004 * @dev: the PCI device to disable
1006 * Disables PCI Memory-Write-Invalidate transaction on the device
1009 pci_clear_mwi(struct pci_dev *dev)
1013 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1014 if (cmd & PCI_COMMAND_INVALIDATE) {
1015 cmd &= ~PCI_COMMAND_INVALIDATE;
1016 pci_write_config_word(dev, PCI_COMMAND, cmd);
1019 #endif /* ! PCI_DISABLE_MWI */
1022 * pci_intx - enables/disables PCI INTx for device dev
1023 * @pdev: the PCI device to operate on
1024 * @enable: boolean: whether to enable or disable PCI INTx
1026 * Enables/disables PCI INTx for device dev
1029 pci_intx(struct pci_dev *pdev, int enable)
1031 u16 pci_command, new;
1033 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1036 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1038 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1041 if (new != pci_command) {
1042 pci_write_config_word(pdev, PCI_COMMAND, new);
1046 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1048 * These can be overridden by arch-specific implementations
1051 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1053 if (!pci_dma_supported(dev, mask))
1056 dev->dma_mask = mask;
1062 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1064 if (!pci_dma_supported(dev, mask))
1067 dev->dev.coherent_dma_mask = mask;
1073 static int __devinit pci_init(void)
1075 struct pci_dev *dev = NULL;
1077 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1078 pci_fixup_device(pci_fixup_final, dev);
1083 static int __devinit pci_setup(char *str)
1086 char *k = strchr(str, ',');
1089 if (*str && (str = pcibios_setup(str)) && *str) {
1090 if (!strcmp(str, "nomsi")) {
1093 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1101 early_param("pci", pci_setup);
1103 device_initcall(pci_init);
1105 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
1106 /* FIXME: Some boxes have multiple ISA bridges! */
1107 struct pci_dev *isa_bridge;
1108 EXPORT_SYMBOL(isa_bridge);
1111 EXPORT_SYMBOL_GPL(pci_restore_bars);
1112 EXPORT_SYMBOL(pci_enable_device_bars);
1113 EXPORT_SYMBOL(pci_enable_device);
1114 EXPORT_SYMBOL(pci_disable_device);
1115 EXPORT_SYMBOL(pci_find_capability);
1116 EXPORT_SYMBOL(pci_bus_find_capability);
1117 EXPORT_SYMBOL(pci_release_regions);
1118 EXPORT_SYMBOL(pci_request_regions);
1119 EXPORT_SYMBOL(pci_release_region);
1120 EXPORT_SYMBOL(pci_request_region);
1121 EXPORT_SYMBOL(pci_set_master);
1122 EXPORT_SYMBOL(pci_set_mwi);
1123 EXPORT_SYMBOL(pci_clear_mwi);
1124 EXPORT_SYMBOL_GPL(pci_intx);
1125 EXPORT_SYMBOL(pci_set_dma_mask);
1126 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1127 EXPORT_SYMBOL(pci_assign_resource);
1128 EXPORT_SYMBOL(pci_find_parent_resource);
1130 EXPORT_SYMBOL(pci_set_power_state);
1131 EXPORT_SYMBOL(pci_save_state);
1132 EXPORT_SYMBOL(pci_restore_state);
1133 EXPORT_SYMBOL(pci_enable_wake);
1137 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1138 EXPORT_SYMBOL(pci_pci_problems);