Automatic merge of /spare/repo/libata-dev branch ahci-msi
[linux-2.6] / drivers / ide / pci / serverworks.c
1 /*
2  * linux/drivers/ide/pci/serverworks.c          Version 0.8      25 Ebr 2003
3  *
4  * Copyright (C) 1998-2000 Michel Aubry
5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7  * Portions copyright (c) 2001 Sun Microsystems
8  *
9  *
10  * RCC/ServerWorks IDE driver for Linux
11  *
12  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
13  *         supports UDMA mode 2 (33 MB/s)
14  *
15  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
16  *         all revisions support UDMA mode 4 (66 MB/s)
17  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
18  *
19  *         *** The CSB5 does not provide ANY register ***
20  *         *** to detect 80-conductor cable presence. ***
21  *
22  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
23  *
24  * Documentation:
25  *      Available under NDA only. Errata info very hard to get.
26  *
27  */
28
29 #include <linux/config.h>
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/ioport.h>
34 #include <linux/pci.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39
40 #include <asm/io.h>
41
42 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
43 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
44
45 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
46  * can overrun their FIFOs when used with the CSB5 */
47 static const char *svwks_bad_ata100[] = {
48         "ST320011A",
49         "ST340016A",
50         "ST360021A",
51         "ST380021A",
52         NULL
53 };
54
55 static u8 svwks_revision = 0;
56 static struct pci_dev *isa_dev;
57
58 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
59 {
60         while (*list)
61                 if (!strcmp(*list++, drive->id->model))
62                         return 1;
63         return 0;
64 }
65
66 static u8 svwks_ratemask (ide_drive_t *drive)
67 {
68         struct pci_dev *dev     = HWIF(drive)->pci_dev;
69         u8 mode;
70
71         if (!svwks_revision)
72                 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
73
74         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
75                 u32 reg = 0;
76                 if (isa_dev)
77                         pci_read_config_dword(isa_dev, 0x64, &reg);
78                         
79                 /*
80                  *      Don't enable UDMA on disk devices for the moment
81                  */
82                 if(drive->media == ide_disk)
83                         return 0;
84                 /* Check the OSB4 DMA33 enable bit */
85                 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
86         } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
87                 return 1;
88         } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
89                 u8 btr = 0;
90                 pci_read_config_byte(dev, 0x5A, &btr);
91                 mode = btr & 0x3;
92                 if (!eighty_ninty_three(drive))
93                         mode = min(mode, (u8)1);
94                 /* If someone decides to do UDMA133 on CSB5 the same
95                    issue will bite so be inclusive */
96                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
97                         mode = 2;
98         }
99         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
100              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
101             (!(PCI_FUNC(dev->devfn) & 1)))
102                 mode = 2;
103         return mode;
104 }
105
106 static u8 svwks_csb_check (struct pci_dev *dev)
107 {
108         switch (dev->device) {
109                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
110                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
111                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
112                         return 1;
113                 default:
114                         break;
115         }
116         return 0;
117 }
118 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
119 {
120         u8 udma_modes[]         = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
121         u8 dma_modes[]          = { 0x77, 0x21, 0x20 };
122         u8 pio_modes[]          = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
123         u8 drive_pci[]          = { 0x41, 0x40, 0x43, 0x42 };
124         u8 drive_pci2[]         = { 0x45, 0x44, 0x47, 0x46 };
125
126         ide_hwif_t *hwif        = HWIF(drive);
127         struct pci_dev *dev     = hwif->pci_dev;
128         u8 speed;
129         u8 pio                  = ide_get_best_pio_mode(drive, 255, 5, NULL);
130         u8 unit                 = (drive->select.b.unit & 0x01);
131         u8 csb5                 = svwks_csb_check(dev);
132         u8 ultra_enable         = 0, ultra_timing = 0;
133         u8 dma_timing           = 0, pio_timing = 0;
134         u16 csb5_pio            = 0;
135
136         if (xferspeed == 255)   /* PIO auto-tuning */
137                 speed = XFER_PIO_0 + pio;
138         else
139                 speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
140
141         /* If we are about to put a disk into UDMA mode we screwed up.
142            Our code assumes we never _ever_ do this on an OSB4 */
143            
144         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
145                 drive->media == ide_disk && speed >= XFER_UDMA_0)
146                         BUG();
147                         
148         pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
149         pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
150         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
151         pci_read_config_word(dev, 0x4A, &csb5_pio);
152         pci_read_config_byte(dev, 0x54, &ultra_enable);
153
154         /* Per Specified Design by OEM, and ASIC Architect */
155         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
156             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
157                 if (!drive->init_speed) {
158                         u8 dma_stat = hwif->INB(hwif->dma_status);
159
160 dma_pio:
161                         if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
162                             ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
163                                 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
164                                 return 0;
165                         } else if ((dma_timing) &&
166                                    ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
167                                 u8 dmaspeed = dma_timing;
168
169                                 dma_timing &= ~0xFF;
170                                 if ((dmaspeed & 0x20) == 0x20)
171                                         dmaspeed = XFER_MW_DMA_2;
172                                 else if ((dmaspeed & 0x21) == 0x21)
173                                         dmaspeed = XFER_MW_DMA_1;
174                                 else if ((dmaspeed & 0x77) == 0x77)
175                                         dmaspeed = XFER_MW_DMA_0;
176                                 else
177                                         goto dma_pio;
178                                 drive->current_speed = drive->init_speed = dmaspeed;
179                                 return 0;
180                         } else if (pio_timing) {
181                                 u8 piospeed = pio_timing;
182
183                                 pio_timing &= ~0xFF;
184                                 if ((piospeed & 0x20) == 0x20)
185                                         piospeed = XFER_PIO_4;
186                                 else if ((piospeed & 0x22) == 0x22)
187                                         piospeed = XFER_PIO_3;
188                                 else if ((piospeed & 0x34) == 0x34)
189                                         piospeed = XFER_PIO_2;
190                                 else if ((piospeed & 0x47) == 0x47)
191                                         piospeed = XFER_PIO_1;
192                                 else if ((piospeed & 0x5d) == 0x5d)
193                                         piospeed = XFER_PIO_0;
194                                 else
195                                         goto oem_setup_failed;
196                                 drive->current_speed = drive->init_speed = piospeed;
197                                 return 0;
198                         }
199                 }
200         }
201
202 oem_setup_failed:
203
204         pio_timing      &= ~0xFF;
205         dma_timing      &= ~0xFF;
206         ultra_timing    &= ~(0x0F << (4*unit));
207         ultra_enable    &= ~(0x01 << drive->dn);
208         csb5_pio        &= ~(0x0F << (4*drive->dn));
209
210         switch(speed) {
211                 case XFER_PIO_4:
212                 case XFER_PIO_3:
213                 case XFER_PIO_2:
214                 case XFER_PIO_1:
215                 case XFER_PIO_0:
216                         pio_timing |= pio_modes[speed - XFER_PIO_0];
217                         csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
218                         break;
219
220                 case XFER_MW_DMA_2:
221                 case XFER_MW_DMA_1:
222                 case XFER_MW_DMA_0:
223                         pio_timing |= pio_modes[pio];
224                         csb5_pio   |= (pio << (4*drive->dn));
225                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
226                         break;
227
228                 case XFER_UDMA_5:
229                 case XFER_UDMA_4:
230                 case XFER_UDMA_3:
231                 case XFER_UDMA_2:
232                 case XFER_UDMA_1:
233                 case XFER_UDMA_0:
234                         pio_timing   |= pio_modes[pio];
235                         csb5_pio     |= (pio << (4*drive->dn));
236                         dma_timing   |= dma_modes[2];
237                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
238                         ultra_enable |= (0x01 << drive->dn);
239                 default:
240                         break;
241         }
242
243         pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
244         if (csb5)
245                 pci_write_config_word(dev, 0x4A, csb5_pio);
246
247         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
248         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
249         pci_write_config_byte(dev, 0x54, ultra_enable);
250
251         return (ide_config_drive_speed(drive, speed));
252 }
253
254 static void config_chipset_for_pio (ide_drive_t *drive)
255 {
256         u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
257         u16 xfer_pio = drive->id->eide_pio_modes;
258         u8 timing, speed, pio;
259
260         pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
261
262         if (xfer_pio > 4)
263                 xfer_pio = 0;
264
265         if (drive->id->eide_pio_iordy > 0)
266                 for (xfer_pio = 5;
267                         xfer_pio>0 &&
268                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
269                         xfer_pio--);
270         else
271                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
272                            (drive->id->eide_pio_modes & 2) ? 0x04 :
273                            (drive->id->eide_pio_modes & 1) ? 0x03 :
274                            (drive->id->tPIO & 2) ? 0x02 :
275                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
276
277         timing = (xfer_pio >= pio) ? xfer_pio : pio;
278
279         switch(timing) {
280                 case 4: speed = XFER_PIO_4;break;
281                 case 3: speed = XFER_PIO_3;break;
282                 case 2: speed = XFER_PIO_2;break;
283                 case 1: speed = XFER_PIO_1;break;
284                 default:
285                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
286                         break;
287         }
288         (void) svwks_tune_chipset(drive, speed);
289         drive->current_speed = speed;
290 }
291
292 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
293 {
294         if(pio == 255)
295                 (void) svwks_tune_chipset(drive, 255);
296         else
297                 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
298 }
299
300 static int config_chipset_for_dma (ide_drive_t *drive)
301 {
302         u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
303
304         if (!(speed))
305                 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
306
307         (void) svwks_tune_chipset(drive, speed);
308         return ide_dma_enable(drive);
309 }
310
311 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
312 {
313         ide_hwif_t *hwif        = HWIF(drive);
314         struct hd_driveid *id   = drive->id;
315
316         drive->init_speed = 0;
317
318         if ((id->capability & 1) && drive->autodma) {
319
320                 if (ide_use_dma(drive)) {
321                         if (config_chipset_for_dma(drive))
322                                 return hwif->ide_dma_on(drive);
323                 }
324
325                 goto fast_ata_pio;
326
327         } else if ((id->capability & 8) || (id->field_valid & 2)) {
328 fast_ata_pio:
329                 config_chipset_for_pio(drive);
330                 //      hwif->tuneproc(drive, 5);
331                 return hwif->ide_dma_off_quietly(drive);
332         }
333         /* IORDY not supported */
334         return 0;
335 }
336
337 /* This can go soon */
338
339 static int svwks_ide_dma_end (ide_drive_t *drive)
340 {
341         return __ide_dma_end(drive);
342 }
343
344 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
345 {
346         unsigned int reg;
347         u8 btr;
348
349         /* save revision id to determine DMA capability */
350         pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
351
352         /* force Master Latency Timer value to 64 PCICLKs */
353         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
354
355         /* OSB4 : South Bridge and IDE */
356         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
357                 isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
358                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
359                 if (isa_dev) {
360                         pci_read_config_dword(isa_dev, 0x64, &reg);
361                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
362                         if(!(reg & 0x00004000))
363                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
364                         reg |=  0x00004000; /* enable UDMA/33 support */
365                         pci_write_config_dword(isa_dev, 0x64, reg);
366                 }
367         }
368
369         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
370         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
371                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
372                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
373
374                 /* Third Channel Test */
375                 if (!(PCI_FUNC(dev->devfn) & 1)) {
376                         struct pci_dev * findev = NULL;
377                         u32 reg4c = 0;
378                         findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
379                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
380                         if (findev) {
381                                 pci_read_config_dword(findev, 0x4C, &reg4c);
382                                 reg4c &= ~0x000007FF;
383                                 reg4c |=  0x00000040;
384                                 reg4c |=  0x00000020;
385                                 pci_write_config_dword(findev, 0x4C, reg4c);
386                         }
387                         outb_p(0x06, 0x0c00);
388                         dev->irq = inb_p(0x0c01);
389 #if 0
390                         printk("%s: device class (0x%04x)\n",
391                                 name, dev->class);
392                         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
393                                 dev->class &= ~0x000F0F00;
394                 //              dev->class |= ~0x00000400;
395                                 dev->class |= ~0x00010100;
396                                 /**/
397                         }
398 #endif
399                 } else {
400                         struct pci_dev * findev = NULL;
401                         u8 reg41 = 0;
402
403                         findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
404                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
405                         if (findev) {
406                                 pci_read_config_byte(findev, 0x41, &reg41);
407                                 reg41 &= ~0x40;
408                                 pci_write_config_byte(findev, 0x41, reg41);
409                         }
410                         /*
411                          * This is a device pin issue on CSB6.
412                          * Since there will be a future raid mode,
413                          * early versions of the chipset require the
414                          * interrupt pin to be set, and it is a compatibility
415                          * mode issue.
416                          */
417                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
418                                 dev->irq = 0;
419                 }
420 //              pci_read_config_dword(dev, 0x40, &pioreg)
421 //              pci_write_config_dword(dev, 0x40, 0x99999999);
422 //              pci_read_config_dword(dev, 0x44, &dmareg);
423 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
424                 /* setup the UDMA Control register
425                  *
426                  * 1. clear bit 6 to enable DMA
427                  * 2. enable DMA modes with bits 0-1
428                  *      00 : legacy
429                  *      01 : udma2
430                  *      10 : udma2/udma4
431                  *      11 : udma2/udma4/udma5
432                  */
433                 pci_read_config_byte(dev, 0x5A, &btr);
434                 btr &= ~0x40;
435                 if (!(PCI_FUNC(dev->devfn) & 1))
436                         btr |= 0x2;
437                 else
438                         btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
439                 pci_write_config_byte(dev, 0x5A, btr);
440         }
441
442         return (dev->irq) ? dev->irq : 0;
443 }
444
445 static unsigned int __init ata66_svwks_svwks (ide_hwif_t *hwif)
446 {
447         return 1;
448 }
449
450 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
451  * of the subsystem device ID indicate presence of an 80-pin cable.
452  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
453  * Bit 15 set   = secondary IDE channel has 80-pin cable.
454  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
455  * Bit 14 set   = primary IDE channel has 80-pin cable.
456  */
457 static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif)
458 {
459         struct pci_dev *dev = hwif->pci_dev;
460         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
461             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
462             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
463              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
464                 return ((1 << (hwif->channel + 14)) &
465                         dev->subsystem_device) ? 1 : 0;
466         return 0;
467 }
468
469 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
470  * detect issue by attaching the drives directly to the board.
471  * This check follows the Dell precedent (how scary is that?!)
472  *
473  * WARNING: this only works on Alpine hardware!
474  */
475 static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif)
476 {
477         struct pci_dev *dev = hwif->pci_dev;
478         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
479             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
480             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
481                 return ((1 << (hwif->channel + 14)) &
482                         dev->subsystem_device) ? 1 : 0;
483         return 0;
484 }
485
486 static unsigned int __init ata66_svwks (ide_hwif_t *hwif)
487 {
488         struct pci_dev *dev = hwif->pci_dev;
489
490         /* Per Specified Design by OEM, and ASIC Architect */
491         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
492             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
493                 return 1;
494
495         /* Server Works */
496         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
497                 return ata66_svwks_svwks (hwif);
498         
499         /* Dell PowerEdge */
500         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
501                 return ata66_svwks_dell (hwif);
502
503         /* Cobalt Alpine */
504         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
505                 return ata66_svwks_cobalt (hwif);
506
507         return 0;
508 }
509
510 #undef CAN_SW_DMA
511 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
512 {
513         u8 dma_stat = 0;
514
515         if (!hwif->irq)
516                 hwif->irq = hwif->channel ? 15 : 14;
517
518         hwif->tuneproc = &svwks_tune_drive;
519         hwif->speedproc = &svwks_tune_chipset;
520
521         hwif->atapi_dma = 1;
522
523         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
524                 hwif->ultra_mask = 0x3f;
525
526         hwif->mwdma_mask = 0x07;
527 #ifdef CAN_SW_DMA
528         hwif->swdma_mask = 0x07;
529 #endif /* CAN_SW_DMA */
530
531         hwif->autodma = 0;
532
533         if (!hwif->dma_base) {
534                 hwif->drives[0].autotune = 1;
535                 hwif->drives[1].autotune = 1;
536                 return;
537         }
538
539         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
540         if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
541                 hwif->ide_dma_end = &svwks_ide_dma_end;
542         else if (!(hwif->udma_four))
543                 hwif->udma_four = ata66_svwks(hwif);
544         if (!noautodma)
545                 hwif->autodma = 1;
546
547         dma_stat = hwif->INB(hwif->dma_status);
548         hwif->drives[0].autodma = (dma_stat & 0x20);
549         hwif->drives[1].autodma = (dma_stat & 0x40);
550         hwif->drives[0].autotune = (!(dma_stat & 0x20));
551         hwif->drives[1].autotune = (!(dma_stat & 0x40));
552 //      hwif->drives[0].autodma = hwif->autodma;
553 //      hwif->drives[1].autodma = hwif->autodma;
554 }
555
556 /*
557  * We allow the BM-DMA driver to only work on enabled interfaces.
558  */
559 static void __devinit init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
560 {
561         struct pci_dev *dev = hwif->pci_dev;
562
563         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
564              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
565             (!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
566                 return;
567
568         ide_setup_dma(hwif, dmabase, 8);
569 }
570
571 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
572 {
573         return ide_setup_pci_device(dev, d);
574 }
575
576 static int __init init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
577 {
578         if (!(PCI_FUNC(dev->devfn) & 1)) {
579                 d->bootable = NEVER_BOARD;
580                 if (dev->resource[0].start == 0x01f1)
581                         d->bootable = ON_BOARD;
582         }
583 #if 0
584         if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_CSB6) &&
585              (!(PCI_FUNC(dev->devfn) & 1)))
586                 d->autodma = AUTODMA;
587 #endif
588
589         d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
590                         dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
591                        (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
592
593         return ide_setup_pci_device(dev, d);
594 }
595
596 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
597         {       /* 0 */
598                 .name           = "SvrWks OSB4",
599                 .init_setup     = init_setup_svwks,
600                 .init_chipset   = init_chipset_svwks,
601                 .init_hwif      = init_hwif_svwks,
602                 .channels       = 2,
603                 .autodma        = AUTODMA,
604                 .bootable       = ON_BOARD,
605         },{     /* 1 */
606                 .name           = "SvrWks CSB5",
607                 .init_setup     = init_setup_svwks,
608                 .init_chipset   = init_chipset_svwks,
609                 .init_hwif      = init_hwif_svwks,
610                 .init_dma       = init_dma_svwks,
611                 .channels       = 2,
612                 .autodma        = AUTODMA,
613                 .bootable       = ON_BOARD,
614         },{     /* 2 */
615                 .name           = "SvrWks CSB6",
616                 .init_setup     = init_setup_csb6,
617                 .init_chipset   = init_chipset_svwks,
618                 .init_hwif      = init_hwif_svwks,
619                 .init_dma       = init_dma_svwks,
620                 .channels       = 2,
621                 .autodma        = AUTODMA,
622                 .bootable       = ON_BOARD,
623         },{     /* 3 */
624                 .name           = "SvrWks CSB6",
625                 .init_setup     = init_setup_csb6,
626                 .init_chipset   = init_chipset_svwks,
627                 .init_hwif      = init_hwif_svwks,
628                 .init_dma       = init_dma_svwks,
629                 .channels       = 1,    /* 2 */
630                 .autodma        = AUTODMA,
631                 .bootable       = ON_BOARD,
632         }
633 };
634
635 /**
636  *      svwks_init_one  -       called when a OSB/CSB is found
637  *      @dev: the svwks device
638  *      @id: the matching pci id
639  *
640  *      Called when the PCI registration layer (or the IDE initialization)
641  *      finds a device matching our IDE device tables.
642  */
643  
644 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
645 {
646         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
647
648         return d->init_setup(dev, d);
649 }
650
651 static struct pci_device_id svwks_pci_tbl[] = {
652         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
653         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
654         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
655         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
656         { 0, },
657 };
658 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
659
660 static struct pci_driver driver = {
661         .name           = "Serverworks_IDE",
662         .id_table       = svwks_pci_tbl,
663         .probe          = svwks_init_one,
664 };
665
666 static int svwks_ide_init(void)
667 {
668         return ide_pci_register_driver(&driver);
669 }
670
671 module_init(svwks_ide_init);
672
673 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
674 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
675 MODULE_LICENSE("GPL");