2 * linux/arch/sh/boards/se/770x/irq.c
4 * Copyright (C) 2000 Kazumoto Kojima
5 * Copyright (C) 2006 Nobuhiro Iwamatsu
7 * Hitachi SolutionEngine Support.
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
16 #include <mach-se/mach/se.h>
18 static struct ipr_data ipr_irq_table[] = {
20 * Super I/O (Just mimic PC):
30 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
31 /* This is default value */
32 { 13, 0, 8, 0x0f-13, },
33 { 5 , 0, 4, 0x0f- 5, },
34 { 10, 1, 0, 0x0f-10, },
35 { 7 , 2, 4, 0x0f- 7, },
36 { 3 , 2, 0, 0x0f- 3, },
37 { 1 , 3, 12, 0x0f- 1, },
38 { 12, 3, 4, 0x0f-12, }, /* LAN */
39 { 2 , 4, 8, 0x0f- 2, }, /* PCIRQ2 */
40 { 6 , 4, 4, 0x0f- 6, }, /* PCIRQ1 */
41 { 14, 4, 0, 0x0f-14, }, /* PCIRQ0 */
42 { 0 , 5, 12, 0x0f , },
43 { 4 , 5, 4, 0x0f- 4, },
44 { 8 , 6, 12, 0x0f- 8, },
45 { 9 , 6, 8, 0x0f- 9, },
46 { 11, 6, 4, 0x0f-11, },
48 { 14, 0, 8, 0x0f-14, },
49 { 12, 0, 4, 0x0f-12, },
50 { 8, 1, 4, 0x0f- 8, },
51 { 6, 2, 12, 0x0f- 6, },
52 { 5, 2, 8, 0x0f- 5, },
53 { 4, 2, 4, 0x0f- 4, },
54 { 3, 2, 0, 0x0f- 3, },
55 { 1, 3, 12, 0x0f- 1, },
56 #if defined(CONFIG_STNIC)
58 { 10, 3, 4, 0x0f-10, }, /* LAN */
60 /* MRSHPC IRQs setting */
61 { 0, 4, 12, 0x0f- 0, }, /* PCIRQ3 */
62 { 11, 4, 8, 0x0f-11, }, /* PCIRQ2 */
63 { 9, 4, 4, 0x0f- 9, }, /* PCIRQ1 */
64 { 7, 4, 0, 0x0f- 7, }, /* PCIRQ0 */
65 /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
66 /* NOTE: #2 and #13 are not used on PC */
67 { 13, 6, 4, 0x0f-13, }, /* SLOTIRQ2 */
68 { 2, 6, 0, 0x0f- 2, }, /* SLOTIRQ1 */
72 static unsigned long ipr_offsets[] = {
82 static struct ipr_desc ipr_irq_desc = {
83 .ipr_offsets = ipr_offsets,
84 .nr_offsets = ARRAY_SIZE(ipr_offsets),
86 .ipr_data = ipr_irq_table,
87 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
94 * Initialize IRQ setting
96 void __init init_se_IRQ(void)
98 /* Disable all interrupts */
99 ctrl_outw(0, BCR_ILCRA);
100 ctrl_outw(0, BCR_ILCRB);
101 ctrl_outw(0, BCR_ILCRC);
102 ctrl_outw(0, BCR_ILCRD);
103 ctrl_outw(0, BCR_ILCRE);
104 ctrl_outw(0, BCR_ILCRF);
105 ctrl_outw(0, BCR_ILCRG);
107 register_ipr_controller(&ipr_irq_desc);