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   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #include <linux/if_vlan.h>
  39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50 #include <linux/log2.h>
  51
  52 #include "bnx2.h"
  53 #include "bnx2_fw.h"
  54 #include "bnx2_fw2.h"
  55
  56 #define FW_BUF_SIZE             0x10000
  57
  58 #define DRV_MODULE_NAME         "bnx2"
  59 #define PFX DRV_MODULE_NAME     ": "
  60 #define DRV_MODULE_VERSION      "1.9.0"
  61 #define DRV_MODULE_RELDATE      "Dec 16, 2008"
  62
  63 #define RUN_AT(x) (jiffies + (x))
  64
  65 /* Time in jiffies before concluding the transmitter is hung. */
  66 #define TX_TIMEOUT  (5*HZ)
  67
  68 static char version[] __devinitdata =
  69         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  70
  71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
  73 MODULE_LICENSE("GPL");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 static int disable_msi = 0;
  77
  78 module_param(disable_msi, int, 0);
  79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  80
  81 typedef enum {
  82         BCM5706 = 0,
  83         NC370T,
  84         NC370I,
  85         BCM5706S,
  86         NC370F,
  87         BCM5708,
  88         BCM5708S,
  89         BCM5709,
  90         BCM5709S,
  91         BCM5716,
  92         BCM5716S,
  93 } board_t;
  94
  95 /* indexed by board_t, above */
  96 static struct {
  97         char *name;
  98 } board_info[] __devinitdata = {
  99         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
 100         { "HP NC370T Multifunction Gigabit Server Adapter" },
 101         { "HP NC370i Multifunction Gigabit Server Adapter" },
 102         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 103         { "HP NC370F Multifunction Gigabit Server Adapter" },
 104         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 105         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 106         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 107         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 108         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
 109         { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
 110         };
 111
 112 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
 113         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 114           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 116           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 118           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 120           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 121         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 122           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 123         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 124           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 125         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 126           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 127         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 128           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 129         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 130           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 131         { PCI_VENDOR_ID_BROADCOM, 0x163b,
 132           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 133         { PCI_VENDOR_ID_BROADCOM, 0x163c,
 134           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
 135         { 0, }
 136 };
 137
 138 static struct flash_spec flash_table[] =
 139 {
 140 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 141 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 142         /* Slow EEPROM */
 143         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 144          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 145          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 146          "EEPROM - slow"},
 147         /* Expansion entry 0001 */
 148         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 149          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 150          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 151          "Entry 0001"},
 152         /* Saifun SA25F010 (non-buffered flash) */
 153         /* strap, cfg1, & write1 need updates */
 154         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 155          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 156          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 157          "Non-buffered flash (128kB)"},
 158         /* Saifun SA25F020 (non-buffered flash) */
 159         /* strap, cfg1, & write1 need updates */
 160         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 161          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 162          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 163          "Non-buffered flash (256kB)"},
 164         /* Expansion entry 0100 */
 165         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 166          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 167          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 168          "Entry 0100"},
 169         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 170         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 171          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 172          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 173          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 174         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 175         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 176          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 177          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 178          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 179         /* Saifun SA25F005 (non-buffered flash) */
 180         /* strap, cfg1, & write1 need updates */
 181         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 184          "Non-buffered flash (64kB)"},
 185         /* Fast EEPROM */
 186         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 187          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 188          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 189          "EEPROM - fast"},
 190         /* Expansion entry 1001 */
 191         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 192          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 193          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 194          "Entry 1001"},
 195         /* Expansion entry 1010 */
 196         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 197          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 198          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 199          "Entry 1010"},
 200         /* ATMEL AT45DB011B (buffered flash) */
 201         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 202          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 203          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 204          "Buffered flash (128kB)"},
 205         /* Expansion entry 1100 */
 206         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 207          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 208          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 209          "Entry 1100"},
 210         /* Expansion entry 1101 */
 211         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 212          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 213          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 214          "Entry 1101"},
 215         /* Ateml Expansion entry 1110 */
 216         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 217          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 218          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 219          "Entry 1110 (Atmel)"},
 220         /* ATMEL AT45DB021B (buffered flash) */
 221         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 222          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 223          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 224          "Buffered flash (256kB)"},
 225 };
 226
 227 static struct flash_spec flash_5709 = {
 228         .flags          = BNX2_NV_BUFFERED,
 229         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 230         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 231         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 232         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 233         .name           = "5709 Buffered flash (256kB)",
 234 };
 235
 236 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 237
 238 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
 239 {
 240         u32 diff;
 241
 242         smp_mb();
 243
 244         /* The ring uses 256 indices for 255 entries, one of them
 245          * needs to be skipped.
 246          */
 247         diff = txr->tx_prod - txr->tx_cons;
 248         if (unlikely(diff >= TX_DESC_CNT)) {
 249                 diff &= 0xffff;
 250                 if (diff == TX_DESC_CNT)
 251                         diff = MAX_TX_DESC_CNT;
 252         }
 253         return (bp->tx_ring_size - diff);
 254 }
 255
 256 static u32
 257 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 258 {
 259         u32 val;
 260
 261         spin_lock_bh(&bp->indirect_lock);
 262         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 263         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 264         spin_unlock_bh(&bp->indirect_lock);
 265         return val;
 266 }
 267
 268 static void
 269 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 270 {
 271         spin_lock_bh(&bp->indirect_lock);
 272         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 273         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 274         spin_unlock_bh(&bp->indirect_lock);
 275 }
 276
 277 static void
 278 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 279 {
 280         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 281 }
 282
 283 static u32
 284 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 285 {
 286         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 287 }
 288
 289 static void
 290 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 291 {
 292         offset += cid_addr;
 293         spin_lock_bh(&bp->indirect_lock);
 294         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 295                 int i;
 296
 297                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 298                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 299                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 300                 for (i = 0; i < 5; i++) {
 301                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 302                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 303                                 break;
 304                         udelay(5);
 305                 }
 306         } else {
 307                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 308                 REG_WR(bp, BNX2_CTX_DATA, val);
 309         }
 310         spin_unlock_bh(&bp->indirect_lock);
 311 }
 312
 313 static int
 314 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 315 {
 316         u32 val1;
 317         int i, ret;
 318
 319         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 320                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 321                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 322
 323                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 324                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 325
 326                 udelay(40);
 327         }
 328
 329         val1 = (bp->phy_addr << 21) | (reg << 16) |
 330                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 331                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 332         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 333
 334         for (i = 0; i < 50; i++) {
 335                 udelay(10);
 336
 337                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 338                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 339                         udelay(5);
 340
 341                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 342                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 343
 344                         break;
 345                 }
 346         }
 347
 348         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 349                 *val = 0x0;
 350                 ret = -EBUSY;
 351         }
 352         else {
 353                 *val = val1;
 354                 ret = 0;
 355         }
 356
 357         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 358                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 359                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 360
 361                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 362                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 363
 364                 udelay(40);
 365         }
 366
 367         return ret;
 368 }
 369
 370 static int
 371 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 372 {
 373         u32 val1;
 374         int i, ret;
 375
 376         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 377                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 378                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 379
 380                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 381                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 382
 383                 udelay(40);
 384         }
 385
 386         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 387                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 388                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 389         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 390
 391         for (i = 0; i < 50; i++) {
 392                 udelay(10);
 393
 394                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 395                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 396                         udelay(5);
 397                         break;
 398                 }
 399         }
 400
 401         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 402                 ret = -EBUSY;
 403         else
 404                 ret = 0;
 405
 406         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 407                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 408                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 409
 410                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 411                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 412
 413                 udelay(40);
 414         }
 415
 416         return ret;
 417 }
 418
 419 static void
 420 bnx2_disable_int(struct bnx2 *bp)
 421 {
 422         int i;
 423         struct bnx2_napi *bnapi;
 424
 425         for (i = 0; i < bp->irq_nvecs; i++) {
 426                 bnapi = &bp->bnx2_napi[i];
 427                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 428                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 429         }
 430         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 431 }
 432
 433 static void
 434 bnx2_enable_int(struct bnx2 *bp)
 435 {
 436         int i;
 437         struct bnx2_napi *bnapi;
 438
 439         for (i = 0; i < bp->irq_nvecs; i++) {
 440                 bnapi = &bp->bnx2_napi[i];
 441
 442                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 443                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 444                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 445                        bnapi->last_status_idx);
 446
 447                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 448                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 449                        bnapi->last_status_idx);
 450         }
 451         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 452 }
 453
 454 static void
 455 bnx2_disable_int_sync(struct bnx2 *bp)
 456 {
 457         int i;
 458
 459         atomic_inc(&bp->intr_sem);
 460         bnx2_disable_int(bp);
 461         for (i = 0; i < bp->irq_nvecs; i++)
 462                 synchronize_irq(bp->irq_tbl[i].vector);
 463 }
 464
 465 static void
 466 bnx2_napi_disable(struct bnx2 *bp)
 467 {
 468         int i;
 469
 470         for (i = 0; i < bp->irq_nvecs; i++)
 471                 napi_disable(&bp->bnx2_napi[i].napi);
 472 }
 473
 474 static void
 475 bnx2_napi_enable(struct bnx2 *bp)
 476 {
 477         int i;
 478
 479         for (i = 0; i < bp->irq_nvecs; i++)
 480                 napi_enable(&bp->bnx2_napi[i].napi);
 481 }
 482
 483 static void
 484 bnx2_netif_stop(struct bnx2 *bp)
 485 {
 486         bnx2_disable_int_sync(bp);
 487         if (netif_running(bp->dev)) {
 488                 bnx2_napi_disable(bp);
 489                 netif_tx_disable(bp->dev);
 490                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 491         }
 492 }
 493
 494 static void
 495 bnx2_netif_start(struct bnx2 *bp)
 496 {
 497         if (atomic_dec_and_test(&bp->intr_sem)) {
 498                 if (netif_running(bp->dev)) {
 499                         netif_tx_wake_all_queues(bp->dev);
 500                         bnx2_napi_enable(bp);
 501                         bnx2_enable_int(bp);
 502                 }
 503         }
 504 }
 505
 506 static void
 507 bnx2_free_tx_mem(struct bnx2 *bp)
 508 {
 509         int i;
 510
 511         for (i = 0; i < bp->num_tx_rings; i++) {
 512                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 513                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 514
 515                 if (txr->tx_desc_ring) {
 516                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 517                                             txr->tx_desc_ring,
 518                                             txr->tx_desc_mapping);
 519                         txr->tx_desc_ring = NULL;
 520                 }
 521                 kfree(txr->tx_buf_ring);
 522                 txr->tx_buf_ring = NULL;
 523         }
 524 }
 525
 526 static void
 527 bnx2_free_rx_mem(struct bnx2 *bp)
 528 {
 529         int i;
 530
 531         for (i = 0; i < bp->num_rx_rings; i++) {
 532                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 533                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 534                 int j;
 535
 536                 for (j = 0; j < bp->rx_max_ring; j++) {
 537                         if (rxr->rx_desc_ring[j])
 538                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 539                                                     rxr->rx_desc_ring[j],
 540                                                     rxr->rx_desc_mapping[j]);
 541                         rxr->rx_desc_ring[j] = NULL;
 542                 }
 543                 if (rxr->rx_buf_ring)
 544                         vfree(rxr->rx_buf_ring);
 545                 rxr->rx_buf_ring = NULL;
 546
 547                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 548                         if (rxr->rx_pg_desc_ring[j])
 549                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 550                                                     rxr->rx_pg_desc_ring[j],
 551                                                     rxr->rx_pg_desc_mapping[j]);
 552                         rxr->rx_pg_desc_ring[j] = NULL;
 553                 }
 554                 if (rxr->rx_pg_ring)
 555                         vfree(rxr->rx_pg_ring);
 556                 rxr->rx_pg_ring = NULL;
 557         }
 558 }
 559
 560 static int
 561 bnx2_alloc_tx_mem(struct bnx2 *bp)
 562 {
 563         int i;
 564
 565         for (i = 0; i < bp->num_tx_rings; i++) {
 566                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 567                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 568
 569                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 570                 if (txr->tx_buf_ring == NULL)
 571                         return -ENOMEM;
 572
 573                 txr->tx_desc_ring =
 574                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 575                                              &txr->tx_desc_mapping);
 576                 if (txr->tx_desc_ring == NULL)
 577                         return -ENOMEM;
 578         }
 579         return 0;
 580 }
 581
 582 static int
 583 bnx2_alloc_rx_mem(struct bnx2 *bp)
 584 {
 585         int i;
 586
 587         for (i = 0; i < bp->num_rx_rings; i++) {
 588                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 589                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 590                 int j;
 591
 592                 rxr->rx_buf_ring =
 593                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 594                 if (rxr->rx_buf_ring == NULL)
 595                         return -ENOMEM;
 596
 597                 memset(rxr->rx_buf_ring, 0,
 598                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
 599
 600                 for (j = 0; j < bp->rx_max_ring; j++) {
 601                         rxr->rx_desc_ring[j] =
 602                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 603                                                      &rxr->rx_desc_mapping[j]);
 604                         if (rxr->rx_desc_ring[j] == NULL)
 605                                 return -ENOMEM;
 606
 607                 }
 608
 609                 if (bp->rx_pg_ring_size) {
 610                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 611                                                   bp->rx_max_pg_ring);
 612                         if (rxr->rx_pg_ring == NULL)
 613                                 return -ENOMEM;
 614
 615                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 616                                bp->rx_max_pg_ring);
 617                 }
 618
 619                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 620                         rxr->rx_pg_desc_ring[j] =
 621                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 622                                                 &rxr->rx_pg_desc_mapping[j]);
 623                         if (rxr->rx_pg_desc_ring[j] == NULL)
 624                                 return -ENOMEM;
 625
 626                 }
 627         }
 628         return 0;
 629 }
 630
 631 static void
 632 bnx2_free_mem(struct bnx2 *bp)
 633 {
 634         int i;
 635         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 636
 637         bnx2_free_tx_mem(bp);
 638         bnx2_free_rx_mem(bp);
 639
 640         for (i = 0; i < bp->ctx_pages; i++) {
 641                 if (bp->ctx_blk[i]) {
 642                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 643                                             bp->ctx_blk[i],
 644                                             bp->ctx_blk_mapping[i]);
 645                         bp->ctx_blk[i] = NULL;
 646                 }
 647         }
 648         if (bnapi->status_blk.msi) {
 649                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 650                                     bnapi->status_blk.msi,
 651                                     bp->status_blk_mapping);
 652                 bnapi->status_blk.msi = NULL;
 653                 bp->stats_blk = NULL;
 654         }
 655 }
 656
 657 static int
 658 bnx2_alloc_mem(struct bnx2 *bp)
 659 {
 660         int i, status_blk_size, err;
 661         struct bnx2_napi *bnapi;
 662         void *status_blk;
 663
 664         /* Combine status and statistics blocks into one allocation. */
 665         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 666         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 667                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 668                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 669         bp->status_stats_size = status_blk_size +
 670                                 sizeof(struct statistics_block);
 671
 672         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 673                                           &bp->status_blk_mapping);
 674         if (status_blk == NULL)
 675                 goto alloc_mem_err;
 676
 677         memset(status_blk, 0, bp->status_stats_size);
 678
 679         bnapi = &bp->bnx2_napi[0];
 680         bnapi->status_blk.msi = status_blk;
 681         bnapi->hw_tx_cons_ptr =
 682                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
 683         bnapi->hw_rx_cons_ptr =
 684                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
 685         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 686                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 687                         struct status_block_msix *sblk;
 688
 689                         bnapi = &bp->bnx2_napi[i];
 690
 691                         sblk = (void *) (status_blk +
 692                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 693                         bnapi->status_blk.msix = sblk;
 694                         bnapi->hw_tx_cons_ptr =
 695                                 &sblk->status_tx_quick_consumer_index;
 696                         bnapi->hw_rx_cons_ptr =
 697                                 &sblk->status_rx_quick_consumer_index;
 698                         bnapi->int_num = i << 24;
 699                 }
 700         }
 701
 702         bp->stats_blk = status_blk + status_blk_size;
 703
 704         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 705
 706         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 707                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 708                 if (bp->ctx_pages == 0)
 709                         bp->ctx_pages = 1;
 710                 for (i = 0; i < bp->ctx_pages; i++) {
 711                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 712                                                 BCM_PAGE_SIZE,
 713                                                 &bp->ctx_blk_mapping[i]);
 714                         if (bp->ctx_blk[i] == NULL)
 715                                 goto alloc_mem_err;
 716                 }
 717         }
 718
 719         err = bnx2_alloc_rx_mem(bp);
 720         if (err)
 721                 goto alloc_mem_err;
 722
 723         err = bnx2_alloc_tx_mem(bp);
 724         if (err)
 725                 goto alloc_mem_err;
 726
 727         return 0;
 728
 729 alloc_mem_err:
 730         bnx2_free_mem(bp);
 731         return -ENOMEM;
 732 }
 733
 734 static void
 735 bnx2_report_fw_link(struct bnx2 *bp)
 736 {
 737         u32 fw_link_status = 0;
 738
 739         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 740                 return;
 741
 742         if (bp->link_up) {
 743                 u32 bmsr;
 744
 745                 switch (bp->line_speed) {
 746                 case SPEED_10:
 747                         if (bp->duplex == DUPLEX_HALF)
 748                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 749                         else
 750                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 751                         break;
 752                 case SPEED_100:
 753                         if (bp->duplex == DUPLEX_HALF)
 754                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 755                         else
 756                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 757                         break;
 758                 case SPEED_1000:
 759                         if (bp->duplex == DUPLEX_HALF)
 760                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 761                         else
 762                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 763                         break;
 764                 case SPEED_2500:
 765                         if (bp->duplex == DUPLEX_HALF)
 766                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 767                         else
 768                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 769                         break;
 770                 }
 771
 772                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 773
 774                 if (bp->autoneg) {
 775                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 776
 777                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 778                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 779
 780                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 781                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 782                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 783                         else
 784                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 785                 }
 786         }
 787         else
 788                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 789
 790         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 791 }
 792
 793 static char *
 794 bnx2_xceiver_str(struct bnx2 *bp)
 795 {
 796         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 797                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 798                  "Copper"));
 799 }
 800
 801 static void
 802 bnx2_report_link(struct bnx2 *bp)
 803 {
 804         if (bp->link_up) {
 805                 netif_carrier_on(bp->dev);
 806                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 807                        bnx2_xceiver_str(bp));
 808
 809                 printk("%d Mbps ", bp->line_speed);
 810
 811                 if (bp->duplex == DUPLEX_FULL)
 812                         printk("full duplex");
 813                 else
 814                         printk("half duplex");
 815
 816                 if (bp->flow_ctrl) {
 817                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 818                                 printk(", receive ");
 819                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 820                                         printk("& transmit ");
 821                         }
 822                         else {
 823                                 printk(", transmit ");
 824                         }
 825                         printk("flow control ON");
 826                 }
 827                 printk("\n");
 828         }
 829         else {
 830                 netif_carrier_off(bp->dev);
 831                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 832                        bnx2_xceiver_str(bp));
 833         }
 834
 835         bnx2_report_fw_link(bp);
 836 }
 837
 838 static void
 839 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 840 {
 841         u32 local_adv, remote_adv;
 842
 843         bp->flow_ctrl = 0;
 844         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 845                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 846
 847                 if (bp->duplex == DUPLEX_FULL) {
 848                         bp->flow_ctrl = bp->req_flow_ctrl;
 849                 }
 850                 return;
 851         }
 852
 853         if (bp->duplex != DUPLEX_FULL) {
 854                 return;
 855         }
 856
 857         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
 858             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 859                 u32 val;
 860
 861                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 862                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 863                         bp->flow_ctrl |= FLOW_CTRL_TX;
 864                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 865                         bp->flow_ctrl |= FLOW_CTRL_RX;
 866                 return;
 867         }
 868
 869         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 870         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 871
 872         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
 873                 u32 new_local_adv = 0;
 874                 u32 new_remote_adv = 0;
 875
 876                 if (local_adv & ADVERTISE_1000XPAUSE)
 877                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 878                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 879                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 880                 if (remote_adv & ADVERTISE_1000XPAUSE)
 881                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 882                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 883                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 884
 885                 local_adv = new_local_adv;
 886                 remote_adv = new_remote_adv;
 887         }
 888
 889         /* See Table 28B-3 of 802.3ab-1999 spec. */
 890         if (local_adv & ADVERTISE_PAUSE_CAP) {
 891                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 892                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 893                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 894                         }
 895                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 896                                 bp->flow_ctrl = FLOW_CTRL_RX;
 897                         }
 898                 }
 899                 else {
 900                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 901                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 902                         }
 903                 }
 904         }
 905         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 906                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 907                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 908
 909                         bp->flow_ctrl = FLOW_CTRL_TX;
 910                 }
 911         }
 912 }
 913
 914 static int
 915 bnx2_5709s_linkup(struct bnx2 *bp)
 916 {
 917         u32 val, speed;
 918
 919         bp->link_up = 1;
 920
 921         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 922         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 923         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 924
 925         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 926                 bp->line_speed = bp->req_line_speed;
 927                 bp->duplex = bp->req_duplex;
 928                 return 0;
 929         }
 930         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 931         switch (speed) {
 932                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 933                         bp->line_speed = SPEED_10;
 934                         break;
 935                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 936                         bp->line_speed = SPEED_100;
 937                         break;
 938                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 939                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 940                         bp->line_speed = SPEED_1000;
 941                         break;
 942                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 943                         bp->line_speed = SPEED_2500;
 944                         break;
 945         }
 946         if (val & MII_BNX2_GP_TOP_AN_FD)
 947                 bp->duplex = DUPLEX_FULL;
 948         else
 949                 bp->duplex = DUPLEX_HALF;
 950         return 0;
 951 }
 952
 953 static int
 954 bnx2_5708s_linkup(struct bnx2 *bp)
 955 {
 956         u32 val;
 957
 958         bp->link_up = 1;
 959         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 960         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 961                 case BCM5708S_1000X_STAT1_SPEED_10:
 962                         bp->line_speed = SPEED_10;
 963                         break;
 964                 case BCM5708S_1000X_STAT1_SPEED_100:
 965                         bp->line_speed = SPEED_100;
 966                         break;
 967                 case BCM5708S_1000X_STAT1_SPEED_1G:
 968                         bp->line_speed = SPEED_1000;
 969                         break;
 970                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 971                         bp->line_speed = SPEED_2500;
 972                         break;
 973         }
 974         if (val & BCM5708S_1000X_STAT1_FD)
 975                 bp->duplex = DUPLEX_FULL;
 976         else
 977                 bp->duplex = DUPLEX_HALF;
 978
 979         return 0;
 980 }
 981
 982 static int
 983 bnx2_5706s_linkup(struct bnx2 *bp)
 984 {
 985         u32 bmcr, local_adv, remote_adv, common;
 986
 987         bp->link_up = 1;
 988         bp->line_speed = SPEED_1000;
 989
 990         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 991         if (bmcr & BMCR_FULLDPLX) {
 992                 bp->duplex = DUPLEX_FULL;
 993         }
 994         else {
 995                 bp->duplex = DUPLEX_HALF;
 996         }
 997
 998         if (!(bmcr & BMCR_ANENABLE)) {
 999                 return 0;
1000         }
1001
1002         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1003         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1004
1005         common = local_adv & remote_adv;
1006         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1007
1008                 if (common & ADVERTISE_1000XFULL) {
1009                         bp->duplex = DUPLEX_FULL;
1010                 }
1011                 else {
1012                         bp->duplex = DUPLEX_HALF;
1013                 }
1014         }
1015
1016         return 0;
1017 }
1018
1019 static int
1020 bnx2_copper_linkup(struct bnx2 *bp)
1021 {
1022         u32 bmcr;
1023
1024         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1025         if (bmcr & BMCR_ANENABLE) {
1026                 u32 local_adv, remote_adv, common;
1027
1028                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1029                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1030
1031                 common = local_adv & (remote_adv >> 2);
1032                 if (common & ADVERTISE_1000FULL) {
1033                         bp->line_speed = SPEED_1000;
1034                         bp->duplex = DUPLEX_FULL;
1035                 }
1036                 else if (common & ADVERTISE_1000HALF) {
1037                         bp->line_speed = SPEED_1000;
1038                         bp->duplex = DUPLEX_HALF;
1039                 }
1040                 else {
1041                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1042                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1043
1044                         common = local_adv & remote_adv;
1045                         if (common & ADVERTISE_100FULL) {
1046                                 bp->line_speed = SPEED_100;
1047                                 bp->duplex = DUPLEX_FULL;
1048                         }
1049                         else if (common & ADVERTISE_100HALF) {
1050                                 bp->line_speed = SPEED_100;
1051                                 bp->duplex = DUPLEX_HALF;
1052                         }
1053                         else if (common & ADVERTISE_10FULL) {
1054                                 bp->line_speed = SPEED_10;
1055                                 bp->duplex = DUPLEX_FULL;
1056                         }
1057                         else if (common & ADVERTISE_10HALF) {
1058                                 bp->line_speed = SPEED_10;
1059                                 bp->duplex = DUPLEX_HALF;
1060                         }
1061                         else {
1062                                 bp->line_speed = 0;
1063                                 bp->link_up = 0;
1064                         }
1065                 }
1066         }
1067         else {
1068                 if (bmcr & BMCR_SPEED100) {
1069                         bp->line_speed = SPEED_100;
1070                 }
1071                 else {
1072                         bp->line_speed = SPEED_10;
1073                 }
1074                 if (bmcr & BMCR_FULLDPLX) {
1075                         bp->duplex = DUPLEX_FULL;
1076                 }
1077                 else {
1078                         bp->duplex = DUPLEX_HALF;
1079                 }
1080         }
1081
1082         return 0;
1083 }
1084
1085 static void
1086 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1087 {
1088         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1089
1090         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1091         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1092         val |= 0x02 << 8;
1093
1094         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1095                 u32 lo_water, hi_water;
1096
1097                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1098                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1099                 else
1100                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1101                 if (lo_water >= bp->rx_ring_size)
1102                         lo_water = 0;
1103
1104                 hi_water = bp->rx_ring_size / 4;
1105
1106                 if (hi_water <= lo_water)
1107                         lo_water = 0;
1108
1109                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1110                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1111
1112                 if (hi_water > 0xf)
1113                         hi_water = 0xf;
1114                 else if (hi_water == 0)
1115                         lo_water = 0;
1116                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1117         }
1118         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1119 }
1120
1121 static void
1122 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1123 {
1124         int i;
1125         u32 cid;
1126
1127         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1128                 if (i == 1)
1129                         cid = RX_RSS_CID;
1130                 bnx2_init_rx_context(bp, cid);
1131         }
1132 }
1133
1134 static void
1135 bnx2_set_mac_link(struct bnx2 *bp)
1136 {
1137         u32 val;
1138
1139         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1140         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1141                 (bp->duplex == DUPLEX_HALF)) {
1142                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1143         }
1144
1145         /* Configure the EMAC mode register. */
1146         val = REG_RD(bp, BNX2_EMAC_MODE);
1147
1148         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1149                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1150                 BNX2_EMAC_MODE_25G_MODE);
1151
1152         if (bp->link_up) {
1153                 switch (bp->line_speed) {
1154                         case SPEED_10:
1155                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1156                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1157                                         break;
1158                                 }
1159                                 /* fall through */
1160                         case SPEED_100:
1161                                 val |= BNX2_EMAC_MODE_PORT_MII;
1162                                 break;
1163                         case SPEED_2500:
1164                                 val |= BNX2_EMAC_MODE_25G_MODE;
1165                                 /* fall through */
1166                         case SPEED_1000:
1167                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1168                                 break;
1169                 }
1170         }
1171         else {
1172                 val |= BNX2_EMAC_MODE_PORT_GMII;
1173         }
1174
1175         /* Set the MAC to operate in the appropriate duplex mode. */
1176         if (bp->duplex == DUPLEX_HALF)
1177                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1178         REG_WR(bp, BNX2_EMAC_MODE, val);
1179
1180         /* Enable/disable rx PAUSE. */
1181         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1182
1183         if (bp->flow_ctrl & FLOW_CTRL_RX)
1184                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1185         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1186
1187         /* Enable/disable tx PAUSE. */
1188         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1189         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1190
1191         if (bp->flow_ctrl & FLOW_CTRL_TX)
1192                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1193         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1194
1195         /* Acknowledge the interrupt. */
1196         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1197
1198         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1199                 bnx2_init_all_rx_contexts(bp);
1200 }
1201
1202 static void
1203 bnx2_enable_bmsr1(struct bnx2 *bp)
1204 {
1205         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1206             (CHIP_NUM(bp) == CHIP_NUM_5709))
1207                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1208                                MII_BNX2_BLK_ADDR_GP_STATUS);
1209 }
1210
1211 static void
1212 bnx2_disable_bmsr1(struct bnx2 *bp)
1213 {
1214         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1215             (CHIP_NUM(bp) == CHIP_NUM_5709))
1216                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1217                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1218 }
1219
1220 static int
1221 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1222 {
1223         u32 up1;
1224         int ret = 1;
1225
1226         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1227                 return 0;
1228
1229         if (bp->autoneg & AUTONEG_SPEED)
1230                 bp->advertising |= ADVERTISED_2500baseX_Full;
1231
1232         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1233                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1234
1235         bnx2_read_phy(bp, bp->mii_up1, &up1);
1236         if (!(up1 & BCM5708S_UP1_2G5)) {
1237                 up1 |= BCM5708S_UP1_2G5;
1238                 bnx2_write_phy(bp, bp->mii_up1, up1);
1239                 ret = 0;
1240         }
1241
1242         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1243                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1244                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1245
1246         return ret;
1247 }
1248
1249 static int
1250 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1251 {
1252         u32 up1;
1253         int ret = 0;
1254
1255         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1256                 return 0;
1257
1258         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1259                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1260
1261         bnx2_read_phy(bp, bp->mii_up1, &up1);
1262         if (up1 & BCM5708S_UP1_2G5) {
1263                 up1 &= ~BCM5708S_UP1_2G5;
1264                 bnx2_write_phy(bp, bp->mii_up1, up1);
1265                 ret = 1;
1266         }
1267
1268         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1269                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1270                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1271
1272         return ret;
1273 }
1274
1275 static void
1276 bnx2_enable_forced_2g5(struct bnx2 *bp)
1277 {
1278         u32 bmcr;
1279
1280         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1281                 return;
1282
1283         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1284                 u32 val;
1285
1286                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1287                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1288                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1289                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1290                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1291                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1292
1293                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1294                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1295                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1296
1297         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1298                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1299                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1300         }
1301
1302         if (bp->autoneg & AUTONEG_SPEED) {
1303                 bmcr &= ~BMCR_ANENABLE;
1304                 if (bp->req_duplex == DUPLEX_FULL)
1305                         bmcr |= BMCR_FULLDPLX;
1306         }
1307         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1308 }
1309
1310 static void
1311 bnx2_disable_forced_2g5(struct bnx2 *bp)
1312 {
1313         u32 bmcr;
1314
1315         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1316                 return;
1317
1318         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1319                 u32 val;
1320
1321                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1322                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1323                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1324                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1325                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1326
1327                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1328                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1329                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1330
1331         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1332                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1333                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1334         }
1335
1336         if (bp->autoneg & AUTONEG_SPEED)
1337                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1338         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1339 }
1340
1341 static void
1342 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1343 {
1344         u32 val;
1345
1346         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1347         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1348         if (start)
1349                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1350         else
1351                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1352 }
1353
1354 static int
1355 bnx2_set_link(struct bnx2 *bp)
1356 {
1357         u32 bmsr;
1358         u8 link_up;
1359
1360         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1361                 bp->link_up = 1;
1362                 return 0;
1363         }
1364
1365         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1366                 return 0;
1367
1368         link_up = bp->link_up;
1369
1370         bnx2_enable_bmsr1(bp);
1371         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1372         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1373         bnx2_disable_bmsr1(bp);
1374
1375         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1376             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1377                 u32 val, an_dbg;
1378
1379                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1380                         bnx2_5706s_force_link_dn(bp, 0);
1381                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1382                 }
1383                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1384
1385                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1386                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1387                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1388
1389                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1390                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1391                         bmsr |= BMSR_LSTATUS;
1392                 else
1393                         bmsr &= ~BMSR_LSTATUS;
1394         }
1395
1396         if (bmsr & BMSR_LSTATUS) {
1397                 bp->link_up = 1;
1398
1399                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1400                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1401                                 bnx2_5706s_linkup(bp);
1402                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1403                                 bnx2_5708s_linkup(bp);
1404                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1405                                 bnx2_5709s_linkup(bp);
1406                 }
1407                 else {
1408                         bnx2_copper_linkup(bp);
1409                 }
1410                 bnx2_resolve_flow_ctrl(bp);
1411         }
1412         else {
1413                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1414                     (bp->autoneg & AUTONEG_SPEED))
1415                         bnx2_disable_forced_2g5(bp);
1416
1417                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1418                         u32 bmcr;
1419
1420                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1421                         bmcr |= BMCR_ANENABLE;
1422                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1423
1424                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1425                 }
1426                 bp->link_up = 0;
1427         }
1428
1429         if (bp->link_up != link_up) {
1430                 bnx2_report_link(bp);
1431         }
1432
1433         bnx2_set_mac_link(bp);
1434
1435         return 0;
1436 }
1437
1438 static int
1439 bnx2_reset_phy(struct bnx2 *bp)
1440 {
1441         int i;
1442         u32 reg;
1443
1444         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1445
1446 #define PHY_RESET_MAX_WAIT 100
1447         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1448                 udelay(10);
1449
1450                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1451                 if (!(reg & BMCR_RESET)) {
1452                         udelay(20);
1453                         break;
1454                 }
1455         }
1456         if (i == PHY_RESET_MAX_WAIT) {
1457                 return -EBUSY;
1458         }
1459         return 0;
1460 }
1461
1462 static u32
1463 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1464 {
1465         u32 adv = 0;
1466
1467         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1468                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1469
1470                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1471                         adv = ADVERTISE_1000XPAUSE;
1472                 }
1473                 else {
1474                         adv = ADVERTISE_PAUSE_CAP;
1475                 }
1476         }
1477         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1478                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1479                         adv = ADVERTISE_1000XPSE_ASYM;
1480                 }
1481                 else {
1482                         adv = ADVERTISE_PAUSE_ASYM;
1483                 }
1484         }
1485         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1486                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1487                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1488                 }
1489                 else {
1490                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1491                 }
1492         }
1493         return adv;
1494 }
1495
1496 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1497
1498 static int
1499 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1500 {
1501         u32 speed_arg = 0, pause_adv;
1502
1503         pause_adv = bnx2_phy_get_pause_adv(bp);
1504
1505         if (bp->autoneg & AUTONEG_SPEED) {
1506                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1507                 if (bp->advertising & ADVERTISED_10baseT_Half)
1508                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1509                 if (bp->advertising & ADVERTISED_10baseT_Full)
1510                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1511                 if (bp->advertising & ADVERTISED_100baseT_Half)
1512                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1513                 if (bp->advertising & ADVERTISED_100baseT_Full)
1514                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1515                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1516                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1517                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1518                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1519         } else {
1520                 if (bp->req_line_speed == SPEED_2500)
1521                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1522                 else if (bp->req_line_speed == SPEED_1000)
1523                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1524                 else if (bp->req_line_speed == SPEED_100) {
1525                         if (bp->req_duplex == DUPLEX_FULL)
1526                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1527                         else
1528                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1529                 } else if (bp->req_line_speed == SPEED_10) {
1530                         if (bp->req_duplex == DUPLEX_FULL)
1531                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1532                         else
1533                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1534                 }
1535         }
1536
1537         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1538                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1539         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1540                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1541
1542         if (port == PORT_TP)
1543                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1544                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1545
1546         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1547
1548         spin_unlock_bh(&bp->phy_lock);
1549         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1550         spin_lock_bh(&bp->phy_lock);
1551
1552         return 0;
1553 }
1554
1555 static int
1556 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1557 {
1558         u32 adv, bmcr;
1559         u32 new_adv = 0;
1560
1561         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1562                 return (bnx2_setup_remote_phy(bp, port));
1563
1564         if (!(bp->autoneg & AUTONEG_SPEED)) {
1565                 u32 new_bmcr;
1566                 int force_link_down = 0;
1567
1568                 if (bp->req_line_speed == SPEED_2500) {
1569                         if (!bnx2_test_and_enable_2g5(bp))
1570                                 force_link_down = 1;
1571                 } else if (bp->req_line_speed == SPEED_1000) {
1572                         if (bnx2_test_and_disable_2g5(bp))
1573                                 force_link_down = 1;
1574                 }
1575                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1576                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1577
1578                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1579                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1580                 new_bmcr |= BMCR_SPEED1000;
1581
1582                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1583                         if (bp->req_line_speed == SPEED_2500)
1584                                 bnx2_enable_forced_2g5(bp);
1585                         else if (bp->req_line_speed == SPEED_1000) {
1586                                 bnx2_disable_forced_2g5(bp);
1587                                 new_bmcr &= ~0x2000;
1588                         }
1589
1590                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1591                         if (bp->req_line_speed == SPEED_2500)
1592                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1593                         else
1594                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1595                 }
1596
1597                 if (bp->req_duplex == DUPLEX_FULL) {
1598                         adv |= ADVERTISE_1000XFULL;
1599                         new_bmcr |= BMCR_FULLDPLX;
1600                 }
1601                 else {
1602                         adv |= ADVERTISE_1000XHALF;
1603                         new_bmcr &= ~BMCR_FULLDPLX;
1604                 }
1605                 if ((new_bmcr != bmcr) || (force_link_down)) {
1606                         /* Force a link down visible on the other side */
1607                         if (bp->link_up) {
1608                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1609                                                ~(ADVERTISE_1000XFULL |
1610                                                  ADVERTISE_1000XHALF));
1611                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1612                                         BMCR_ANRESTART | BMCR_ANENABLE);
1613
1614                                 bp->link_up = 0;
1615                                 netif_carrier_off(bp->dev);
1616                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1617                                 bnx2_report_link(bp);
1618                         }
1619                         bnx2_write_phy(bp, bp->mii_adv, adv);
1620                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1621                 } else {
1622                         bnx2_resolve_flow_ctrl(bp);
1623                         bnx2_set_mac_link(bp);
1624                 }
1625                 return 0;
1626         }
1627
1628         bnx2_test_and_enable_2g5(bp);
1629
1630         if (bp->advertising & ADVERTISED_1000baseT_Full)
1631                 new_adv |= ADVERTISE_1000XFULL;
1632
1633         new_adv |= bnx2_phy_get_pause_adv(bp);
1634
1635         bnx2_read_phy(bp, bp->mii_adv, &adv);
1636         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1637
1638         bp->serdes_an_pending = 0;
1639         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1640                 /* Force a link down visible on the other side */
1641                 if (bp->link_up) {
1642                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1643                         spin_unlock_bh(&bp->phy_lock);
1644                         msleep(20);
1645                         spin_lock_bh(&bp->phy_lock);
1646                 }
1647
1648                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1649                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1650                         BMCR_ANENABLE);
1651                 /* Speed up link-up time when the link partner
1652                  * does not autonegotiate which is very common
1653                  * in blade servers. Some blade servers use
1654                  * IPMI for kerboard input and it's important
1655                  * to minimize link disruptions. Autoneg. involves
1656                  * exchanging base pages plus 3 next pages and
1657                  * normally completes in about 120 msec.
1658                  */
1659                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1660                 bp->serdes_an_pending = 1;
1661                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1662         } else {
1663                 bnx2_resolve_flow_ctrl(bp);
1664                 bnx2_set_mac_link(bp);
1665         }
1666
1667         return 0;
1668 }
1669
1670 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1671         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1672                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1673                 (ADVERTISED_1000baseT_Full)
1674
1675 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1676         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1677         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1678         ADVERTISED_1000baseT_Full)
1679
1680 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1681         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1682
1683 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1684
1685 static void
1686 bnx2_set_default_remote_link(struct bnx2 *bp)
1687 {
1688         u32 link;
1689
1690         if (bp->phy_port == PORT_TP)
1691                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1692         else
1693                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1694
1695         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1696                 bp->req_line_speed = 0;
1697                 bp->autoneg |= AUTONEG_SPEED;
1698                 bp->advertising = ADVERTISED_Autoneg;
1699                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1700                         bp->advertising |= ADVERTISED_10baseT_Half;
1701                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1702                         bp->advertising |= ADVERTISED_10baseT_Full;
1703                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1704                         bp->advertising |= ADVERTISED_100baseT_Half;
1705                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1706                         bp->advertising |= ADVERTISED_100baseT_Full;
1707                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1708                         bp->advertising |= ADVERTISED_1000baseT_Full;
1709                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1710                         bp->advertising |= ADVERTISED_2500baseX_Full;
1711         } else {
1712                 bp->autoneg = 0;
1713                 bp->advertising = 0;
1714                 bp->req_duplex = DUPLEX_FULL;
1715                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1716                         bp->req_line_speed = SPEED_10;
1717                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1718                                 bp->req_duplex = DUPLEX_HALF;
1719                 }
1720                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1721                         bp->req_line_speed = SPEED_100;
1722                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1723                                 bp->req_duplex = DUPLEX_HALF;
1724                 }
1725                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1726                         bp->req_line_speed = SPEED_1000;
1727                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1728                         bp->req_line_speed = SPEED_2500;
1729         }
1730 }
1731
1732 static void
1733 bnx2_set_default_link(struct bnx2 *bp)
1734 {
1735         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1736                 bnx2_set_default_remote_link(bp);
1737                 return;
1738         }
1739
1740         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1741         bp->req_line_speed = 0;
1742         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1743                 u32 reg;
1744
1745                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1746
1747                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1748                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1749                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1750                         bp->autoneg = 0;
1751                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1752                         bp->req_duplex = DUPLEX_FULL;
1753                 }
1754         } else
1755                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1756 }
1757
1758 static void
1759 bnx2_send_heart_beat(struct bnx2 *bp)
1760 {
1761         u32 msg;
1762         u32 addr;
1763
1764         spin_lock(&bp->indirect_lock);
1765         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1766         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1767         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1768         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1769         spin_unlock(&bp->indirect_lock);
1770 }
1771
1772 static void
1773 bnx2_remote_phy_event(struct bnx2 *bp)
1774 {
1775         u32 msg;
1776         u8 link_up = bp->link_up;
1777         u8 old_port;
1778
1779         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1780
1781         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1782                 bnx2_send_heart_beat(bp);
1783
1784         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1785
1786         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1787                 bp->link_up = 0;
1788         else {
1789                 u32 speed;
1790
1791                 bp->link_up = 1;
1792                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1793                 bp->duplex = DUPLEX_FULL;
1794                 switch (speed) {
1795                         case BNX2_LINK_STATUS_10HALF:
1796                                 bp->duplex = DUPLEX_HALF;
1797                         case BNX2_LINK_STATUS_10FULL:
1798                                 bp->line_speed = SPEED_10;
1799                                 break;
1800                         case BNX2_LINK_STATUS_100HALF:
1801                                 bp->duplex = DUPLEX_HALF;
1802                         case BNX2_LINK_STATUS_100BASE_T4:
1803                         case BNX2_LINK_STATUS_100FULL:
1804                                 bp->line_speed = SPEED_100;
1805                                 break;
1806                         case BNX2_LINK_STATUS_1000HALF:
1807                                 bp->duplex = DUPLEX_HALF;
1808                         case BNX2_LINK_STATUS_1000FULL:
1809                                 bp->line_speed = SPEED_1000;
1810                                 break;
1811                         case BNX2_LINK_STATUS_2500HALF:
1812                                 bp->duplex = DUPLEX_HALF;
1813                         case BNX2_LINK_STATUS_2500FULL:
1814                                 bp->line_speed = SPEED_2500;
1815                                 break;
1816                         default:
1817                                 bp->line_speed = 0;
1818                                 break;
1819                 }
1820
1821                 bp->flow_ctrl = 0;
1822                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1823                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1824                         if (bp->duplex == DUPLEX_FULL)
1825                                 bp->flow_ctrl = bp->req_flow_ctrl;
1826                 } else {
1827                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1828                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1829                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1830                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1831                 }
1832
1833                 old_port = bp->phy_port;
1834                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1835                         bp->phy_port = PORT_FIBRE;
1836                 else
1837                         bp->phy_port = PORT_TP;
1838
1839                 if (old_port != bp->phy_port)
1840                         bnx2_set_default_link(bp);
1841
1842         }
1843         if (bp->link_up != link_up)
1844                 bnx2_report_link(bp);
1845
1846         bnx2_set_mac_link(bp);
1847 }
1848
1849 static int
1850 bnx2_set_remote_link(struct bnx2 *bp)
1851 {
1852         u32 evt_code;
1853
1854         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1855         switch (evt_code) {
1856                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1857                         bnx2_remote_phy_event(bp);
1858                         break;
1859                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1860                 default:
1861                         bnx2_send_heart_beat(bp);
1862                         break;
1863         }
1864         return 0;
1865 }
1866
1867 static int
1868 bnx2_setup_copper_phy(struct bnx2 *bp)
1869 {
1870         u32 bmcr;
1871         u32 new_bmcr;
1872
1873         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1874
1875         if (bp->autoneg & AUTONEG_SPEED) {
1876                 u32 adv_reg, adv1000_reg;
1877                 u32 new_adv_reg = 0;
1878                 u32 new_adv1000_reg = 0;
1879
1880                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1881                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1882                         ADVERTISE_PAUSE_ASYM);
1883
1884                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1885                 adv1000_reg &= PHY_ALL_1000_SPEED;
1886
1887                 if (bp->advertising & ADVERTISED_10baseT_Half)
1888                         new_adv_reg |= ADVERTISE_10HALF;
1889                 if (bp->advertising & ADVERTISED_10baseT_Full)
1890                         new_adv_reg |= ADVERTISE_10FULL;
1891                 if (bp->advertising & ADVERTISED_100baseT_Half)
1892                         new_adv_reg |= ADVERTISE_100HALF;
1893                 if (bp->advertising & ADVERTISED_100baseT_Full)
1894                         new_adv_reg |= ADVERTISE_100FULL;
1895                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1896                         new_adv1000_reg |= ADVERTISE_1000FULL;
1897
1898                 new_adv_reg |= ADVERTISE_CSMA;
1899
1900                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1901
1902                 if ((adv1000_reg != new_adv1000_reg) ||
1903                         (adv_reg != new_adv_reg) ||
1904                         ((bmcr & BMCR_ANENABLE) == 0)) {
1905
1906                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1907                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1908                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1909                                 BMCR_ANENABLE);
1910                 }
1911                 else if (bp->link_up) {
1912                         /* Flow ctrl may have changed from auto to forced */
1913                         /* or vice-versa. */
1914
1915                         bnx2_resolve_flow_ctrl(bp);
1916                         bnx2_set_mac_link(bp);
1917                 }
1918                 return 0;
1919         }
1920
1921         new_bmcr = 0;
1922         if (bp->req_line_speed == SPEED_100) {
1923                 new_bmcr |= BMCR_SPEED100;
1924         }
1925         if (bp->req_duplex == DUPLEX_FULL) {
1926                 new_bmcr |= BMCR_FULLDPLX;
1927         }
1928         if (new_bmcr != bmcr) {
1929                 u32 bmsr;
1930
1931                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1932                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1933
1934                 if (bmsr & BMSR_LSTATUS) {
1935                         /* Force link down */
1936                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1937                         spin_unlock_bh(&bp->phy_lock);
1938                         msleep(50);
1939                         spin_lock_bh(&bp->phy_lock);
1940
1941                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1942                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1943                 }
1944
1945                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1946
1947                 /* Normally, the new speed is setup after the link has
1948                  * gone down and up again. In some cases, link will not go
1949                  * down so we need to set up the new speed here.
1950                  */
1951                 if (bmsr & BMSR_LSTATUS) {
1952                         bp->line_speed = bp->req_line_speed;
1953                         bp->duplex = bp->req_duplex;
1954                         bnx2_resolve_flow_ctrl(bp);
1955                         bnx2_set_mac_link(bp);
1956                 }
1957         } else {
1958                 bnx2_resolve_flow_ctrl(bp);
1959                 bnx2_set_mac_link(bp);
1960         }
1961         return 0;
1962 }
1963
1964 static int
1965 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1966 {
1967         if (bp->loopback == MAC_LOOPBACK)
1968                 return 0;
1969
1970         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1971                 return (bnx2_setup_serdes_phy(bp, port));
1972         }
1973         else {
1974                 return (bnx2_setup_copper_phy(bp));
1975         }
1976 }
1977
1978 static int
1979 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1980 {
1981         u32 val;
1982
1983         bp->mii_bmcr = MII_BMCR + 0x10;
1984         bp->mii_bmsr = MII_BMSR + 0x10;
1985         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1986         bp->mii_adv = MII_ADVERTISE + 0x10;
1987         bp->mii_lpa = MII_LPA + 0x10;
1988         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1989
1990         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1991         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1992
1993         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1994         if (reset_phy)
1995                 bnx2_reset_phy(bp);
1996
1997         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1998
1999         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2000         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2001         val |= MII_BNX2_SD_1000XCTL1_FIBER;
2002         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2003
2004         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2005         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2006         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2007                 val |= BCM5708S_UP1_2G5;
2008         else
2009                 val &= ~BCM5708S_UP1_2G5;
2010         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2011
2012         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2013         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2014         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2015         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2016
2017         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2018
2019         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2020               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2021         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2022
2023         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2024
2025         return 0;
2026 }
2027
2028 static int
2029 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2030 {
2031         u32 val;
2032
2033         if (reset_phy)
2034                 bnx2_reset_phy(bp);
2035
2036         bp->mii_up1 = BCM5708S_UP1;
2037
2038         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2039         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2040         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2041
2042         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2043         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2044         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2045
2046         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2047         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2048         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2049
2050         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2051                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2052                 val |= BCM5708S_UP1_2G5;
2053                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2054         }
2055
2056         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2057             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2058             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2059                 /* increase tx signal amplitude */
2060                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2061                                BCM5708S_BLK_ADDR_TX_MISC);
2062                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2063                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2064                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2065                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2066         }
2067
2068         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2069               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2070
2071         if (val) {
2072                 u32 is_backplane;
2073
2074                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2075                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2076                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2077                                        BCM5708S_BLK_ADDR_TX_MISC);
2078                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2079                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2080                                        BCM5708S_BLK_ADDR_DIG);
2081                 }
2082         }
2083         return 0;
2084 }
2085
2086 static int
2087 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2088 {
2089         if (reset_phy)
2090                 bnx2_reset_phy(bp);
2091
2092         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2093
2094         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2095                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2096
2097         if (bp->dev->mtu > 1500) {
2098                 u32 val;
2099
2100                 /* Set extended packet length bit */
2101                 bnx2_write_phy(bp, 0x18, 0x7);
2102                 bnx2_read_phy(bp, 0x18, &val);
2103                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2104
2105                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2106                 bnx2_read_phy(bp, 0x1c, &val);
2107                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2108         }
2109         else {
2110                 u32 val;
2111
2112                 bnx2_write_phy(bp, 0x18, 0x7);
2113                 bnx2_read_phy(bp, 0x18, &val);
2114                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2115
2116                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2117                 bnx2_read_phy(bp, 0x1c, &val);
2118                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2119         }
2120
2121         return 0;
2122 }
2123
2124 static int
2125 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2126 {
2127         u32 val;
2128
2129         if (reset_phy)
2130                 bnx2_reset_phy(bp);
2131
2132         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2133                 bnx2_write_phy(bp, 0x18, 0x0c00);
2134                 bnx2_write_phy(bp, 0x17, 0x000a);
2135                 bnx2_write_phy(bp, 0x15, 0x310b);
2136                 bnx2_write_phy(bp, 0x17, 0x201f);
2137                 bnx2_write_phy(bp, 0x15, 0x9506);
2138                 bnx2_write_phy(bp, 0x17, 0x401f);
2139                 bnx2_write_phy(bp, 0x15, 0x14e2);
2140                 bnx2_write_phy(bp, 0x18, 0x0400);
2141         }
2142
2143         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2144                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2145                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2146                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2147                 val &= ~(1 << 8);
2148                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2149         }
2150
2151         if (bp->dev->mtu > 1500) {
2152                 /* Set extended packet length bit */
2153                 bnx2_write_phy(bp, 0x18, 0x7);
2154                 bnx2_read_phy(bp, 0x18, &val);
2155                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2156
2157                 bnx2_read_phy(bp, 0x10, &val);
2158                 bnx2_write_phy(bp, 0x10, val | 0x1);
2159         }
2160         else {
2161                 bnx2_write_phy(bp, 0x18, 0x7);
2162                 bnx2_read_phy(bp, 0x18, &val);
2163                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2164
2165                 bnx2_read_phy(bp, 0x10, &val);
2166                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2167         }
2168
2169         /* ethernet@wirespeed */
2170         bnx2_write_phy(bp, 0x18, 0x7007);
2171         bnx2_read_phy(bp, 0x18, &val);
2172         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2173         return 0;
2174 }
2175
2176
2177 static int
2178 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2179 {
2180         u32 val;
2181         int rc = 0;
2182
2183         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2184         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2185
2186         bp->mii_bmcr = MII_BMCR;
2187         bp->mii_bmsr = MII_BMSR;
2188         bp->mii_bmsr1 = MII_BMSR;
2189         bp->mii_adv = MII_ADVERTISE;
2190         bp->mii_lpa = MII_LPA;
2191
2192         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2193
2194         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2195                 goto setup_phy;
2196
2197         bnx2_read_phy(bp, MII_PHYSID1, &val);
2198         bp->phy_id = val << 16;
2199         bnx2_read_phy(bp, MII_PHYSID2, &val);
2200         bp->phy_id |= val & 0xffff;
2201
2202         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2203                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2204                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2205                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2206                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2207                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2208                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2209         }
2210         else {
2211                 rc = bnx2_init_copper_phy(bp, reset_phy);
2212         }
2213
2214 setup_phy:
2215         if (!rc)
2216                 rc = bnx2_setup_phy(bp, bp->phy_port);
2217
2218         return rc;
2219 }
2220
2221 static int
2222 bnx2_set_mac_loopback(struct bnx2 *bp)
2223 {
2224         u32 mac_mode;
2225
2226         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2227         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2228         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2229         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2230         bp->link_up = 1;
2231         return 0;
2232 }
2233
2234 static int bnx2_test_link(struct bnx2 *);
2235
2236 static int
2237 bnx2_set_phy_loopback(struct bnx2 *bp)
2238 {
2239         u32 mac_mode;
2240         int rc, i;
2241
2242         spin_lock_bh(&bp->phy_lock);
2243         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2244                             BMCR_SPEED1000);
2245         spin_unlock_bh(&bp->phy_lock);
2246         if (rc)
2247                 return rc;
2248
2249         for (i = 0; i < 10; i++) {
2250                 if (bnx2_test_link(bp) == 0)
2251                         break;
2252                 msleep(100);
2253         }
2254
2255         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2256         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2257                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2258                       BNX2_EMAC_MODE_25G_MODE);
2259
2260         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2261         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2262         bp->link_up = 1;
2263         return 0;
2264 }
2265
2266 static int
2267 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2268 {
2269         int i;
2270         u32 val;
2271
2272         bp->fw_wr_seq++;
2273         msg_data |= bp->fw_wr_seq;
2274
2275         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2276
2277         if (!ack)
2278                 return 0;
2279
2280         /* wait for an acknowledgement. */
2281         for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2282                 msleep(10);
2283
2284                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2285
2286                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2287                         break;
2288         }
2289         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2290                 return 0;
2291
2292         /* If we timed out, inform the firmware that this is the case. */
2293         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2294                 if (!silent)
2295                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2296                                             "%x\n", msg_data);
2297
2298                 msg_data &= ~BNX2_DRV_MSG_CODE;
2299                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2300
2301                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2302
2303                 return -EBUSY;
2304         }
2305
2306         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2307                 return -EIO;
2308
2309         return 0;
2310 }
2311
2312 static int
2313 bnx2_init_5709_context(struct bnx2 *bp)
2314 {
2315         int i, ret = 0;
2316         u32 val;
2317
2318         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2319         val |= (BCM_PAGE_BITS - 8) << 16;
2320         REG_WR(bp, BNX2_CTX_COMMAND, val);
2321         for (i = 0; i < 10; i++) {
2322                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2323                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2324                         break;
2325                 udelay(2);
2326         }
2327         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2328                 return -EBUSY;
2329
2330         for (i = 0; i < bp->ctx_pages; i++) {
2331                 int j;
2332
2333                 if (bp->ctx_blk[i])
2334                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2335                 else
2336                         return -ENOMEM;
2337
2338                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2339                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2340                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2341                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2342                        (u64) bp->ctx_blk_mapping[i] >> 32);
2343                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2344                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2345                 for (j = 0; j < 10; j++) {
2346
2347                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2348                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2349                                 break;
2350                         udelay(5);
2351                 }
2352                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2353                         ret = -EBUSY;
2354                         break;
2355                 }
2356         }
2357         return ret;
2358 }
2359
2360 static void
2361 bnx2_init_context(struct bnx2 *bp)
2362 {
2363         u32 vcid;
2364
2365         vcid = 96;
2366         while (vcid) {
2367                 u32 vcid_addr, pcid_addr, offset;
2368                 int i;
2369
2370                 vcid--;
2371
2372                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2373                         u32 new_vcid;
2374
2375                         vcid_addr = GET_PCID_ADDR(vcid);
2376                         if (vcid & 0x8) {
2377                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2378                         }
2379                         else {
2380                                 new_vcid = vcid;
2381                         }
2382                         pcid_addr = GET_PCID_ADDR(new_vcid);
2383                 }
2384                 else {
2385                         vcid_addr = GET_CID_ADDR(vcid);
2386                         pcid_addr = vcid_addr;
2387                 }
2388
2389                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2390                         vcid_addr += (i << PHY_CTX_SHIFT);
2391                         pcid_addr += (i << PHY_CTX_SHIFT);
2392
2393                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2394                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2395
2396                         /* Zero out the context. */
2397                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2398                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2399                 }
2400         }
2401 }
2402
2403 static int
2404 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2405 {
2406         u16 *good_mbuf;
2407         u32 good_mbuf_cnt;
2408         u32 val;
2409
2410         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2411         if (good_mbuf == NULL) {
2412                 printk(KERN_ERR PFX "Failed to allocate memory in "
2413                                     "bnx2_alloc_bad_rbuf\n");
2414                 return -ENOMEM;
2415         }
2416
2417         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2418                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2419
2420         good_mbuf_cnt = 0;
2421
2422         /* Allocate a bunch of mbufs and save the good ones in an array. */
2423         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2424         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2425                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2426                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2427
2428                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2429
2430                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2431
2432                 /* The addresses with Bit 9 set are bad memory blocks. */
2433                 if (!(val & (1 << 9))) {
2434                         good_mbuf[good_mbuf_cnt] = (u16) val;
2435                         good_mbuf_cnt++;
2436                 }
2437
2438                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2439         }
2440
2441         /* Free the good ones back to the mbuf pool thus discarding
2442          * all the bad ones. */
2443         while (good_mbuf_cnt) {
2444                 good_mbuf_cnt--;
2445
2446                 val = good_mbuf[good_mbuf_cnt];
2447                 val = (val << 9) | val | 1;
2448
2449                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2450         }
2451         kfree(good_mbuf);
2452         return 0;
2453 }
2454
2455 static void
2456 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2457 {
2458         u32 val;
2459
2460         val = (mac_addr[0] << 8) | mac_addr[1];
2461
2462         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2463
2464         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2465                 (mac_addr[4] << 8) | mac_addr[5];
2466
2467         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2468 }
2469
2470 static inline int
2471 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2472 {
2473         dma_addr_t mapping;
2474         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2475         struct rx_bd *rxbd =
2476                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2477         struct page *page = alloc_page(GFP_ATOMIC);
2478
2479         if (!page)
2480                 return -ENOMEM;
2481         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2482                                PCI_DMA_FROMDEVICE);
2483         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2484                 __free_page(page);
2485                 return -EIO;
2486         }
2487
2488         rx_pg->page = page;
2489         pci_unmap_addr_set(rx_pg, mapping, mapping);
2490         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2491         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2492         return 0;
2493 }
2494
2495 static void
2496 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2497 {
2498         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2499         struct page *page = rx_pg->page;
2500
2501         if (!page)
2502                 return;
2503
2504         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2505                        PCI_DMA_FROMDEVICE);
2506
2507         __free_page(page);
2508         rx_pg->page = NULL;
2509 }
2510
2511 static inline int
2512 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2513 {
2514         struct sk_buff *skb;
2515         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2516         dma_addr_t mapping;
2517         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2518         unsigned long align;
2519
2520         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2521         if (skb == NULL) {
2522                 return -ENOMEM;
2523         }
2524
2525         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2526                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2527
2528         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2529                 PCI_DMA_FROMDEVICE);
2530         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2531                 dev_kfree_skb(skb);
2532                 return -EIO;
2533         }
2534
2535         rx_buf->skb = skb;
2536         pci_unmap_addr_set(rx_buf, mapping, mapping);
2537
2538         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2539         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2540
2541         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2542
2543         return 0;
2544 }
2545
2546 static int
2547 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2548 {
2549         struct status_block *sblk = bnapi->status_blk.msi;
2550         u32 new_link_state, old_link_state;
2551         int is_set = 1;
2552
2553         new_link_state = sblk->status_attn_bits & event;
2554         old_link_state = sblk->status_attn_bits_ack & event;
2555         if (new_link_state != old_link_state) {
2556                 if (new_link_state)
2557                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2558                 else
2559                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2560         } else
2561                 is_set = 0;
2562
2563         return is_set;
2564 }
2565
2566 static void
2567 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2568 {
2569         spin_lock(&bp->phy_lock);
2570
2571         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2572                 bnx2_set_link(bp);
2573         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2574                 bnx2_set_remote_link(bp);
2575
2576         spin_unlock(&bp->phy_lock);
2577
2578 }
2579
2580 static inline u16
2581 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2582 {
2583         u16 cons;
2584
2585         /* Tell compiler that status block fields can change. */
2586         barrier();
2587         cons = *bnapi->hw_tx_cons_ptr;
2588         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2589                 cons++;
2590         return cons;
2591 }
2592
2593 static int
2594 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2595 {
2596         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2597         u16 hw_cons, sw_cons, sw_ring_cons;
2598         int tx_pkt = 0, index;
2599         struct netdev_queue *txq;
2600
2601         index = (bnapi - bp->bnx2_napi);
2602         txq = netdev_get_tx_queue(bp->dev, index);
2603
2604         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2605         sw_cons = txr->tx_cons;
2606
2607         while (sw_cons != hw_cons) {
2608                 struct sw_tx_bd *tx_buf;
2609                 struct sk_buff *skb;
2610                 int i, last;
2611
2612                 sw_ring_cons = TX_RING_IDX(sw_cons);
2613
2614                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2615                 skb = tx_buf->skb;
2616
2617                 /* partial BD completions possible with TSO packets */
2618                 if (skb_is_gso(skb)) {
2619                         u16 last_idx, last_ring_idx;
2620
2621                         last_idx = sw_cons +
2622                                 skb_shinfo(skb)->nr_frags + 1;
2623                         last_ring_idx = sw_ring_cons +
2624                                 skb_shinfo(skb)->nr_frags + 1;
2625                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2626                                 last_idx++;
2627                         }
2628                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2629                                 break;
2630                         }
2631                 }
2632
2633                 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2634
2635                 tx_buf->skb = NULL;
2636                 last = skb_shinfo(skb)->nr_frags;
2637
2638                 for (i = 0; i < last; i++) {
2639                         sw_cons = NEXT_TX_BD(sw_cons);
2640                 }
2641
2642                 sw_cons = NEXT_TX_BD(sw_cons);
2643
2644                 dev_kfree_skb(skb);
2645                 tx_pkt++;
2646                 if (tx_pkt == budget)
2647                         break;
2648
2649                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2650         }
2651
2652         txr->hw_tx_cons = hw_cons;
2653         txr->tx_cons = sw_cons;
2654
2655         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2656          * before checking for netif_tx_queue_stopped().  Without the
2657          * memory barrier, there is a small possibility that bnx2_start_xmit()
2658          * will miss it and cause the queue to be stopped forever.
2659          */
2660         smp_mb();
2661
2662         if (unlikely(netif_tx_queue_stopped(txq)) &&
2663                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2664                 __netif_tx_lock(txq, smp_processor_id());
2665                 if ((netif_tx_queue_stopped(txq)) &&
2666                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2667                         netif_tx_wake_queue(txq);
2668                 __netif_tx_unlock(txq);
2669         }
2670
2671         return tx_pkt;
2672 }
2673
2674 static void
2675 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2676                         struct sk_buff *skb, int count)
2677 {
2678         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2679         struct rx_bd *cons_bd, *prod_bd;
2680         int i;
2681         u16 hw_prod, prod;
2682         u16 cons = rxr->rx_pg_cons;
2683
2684         cons_rx_pg = &rxr->rx_pg_ring[cons];
2685
2686         /* The caller was unable to allocate a new page to replace the
2687          * last one in the frags array, so we need to recycle that page
2688          * and then free the skb.
2689          */
2690         if (skb) {
2691                 struct page *page;
2692                 struct skb_shared_info *shinfo;
2693
2694                 shinfo = skb_shinfo(skb);
2695                 shinfo->nr_frags--;
2696                 page = shinfo->frags[shinfo->nr_frags].page;
2697                 shinfo->frags[shinfo->nr_frags].page = NULL;
2698
2699                 cons_rx_pg->page = page;
2700                 dev_kfree_skb(skb);
2701         }
2702
2703         hw_prod = rxr->rx_pg_prod;
2704
2705         for (i = 0; i < count; i++) {
2706                 prod = RX_PG_RING_IDX(hw_prod);
2707
2708                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2709                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2710                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2711                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2712
2713                 if (prod != cons) {
2714                         prod_rx_pg->page = cons_rx_pg->page;
2715                         cons_rx_pg->page = NULL;
2716                         pci_unmap_addr_set(prod_rx_pg, mapping,
2717                                 pci_unmap_addr(cons_rx_pg, mapping));
2718
2719                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2720                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2721
2722                 }
2723                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2724                 hw_prod = NEXT_RX_BD(hw_prod);
2725         }
2726         rxr->rx_pg_prod = hw_prod;
2727         rxr->rx_pg_cons = cons;
2728 }
2729
2730 static inline void
2731 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2732                   struct sk_buff *skb, u16 cons, u16 prod)
2733 {
2734         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2735         struct rx_bd *cons_bd, *prod_bd;
2736
2737         cons_rx_buf = &rxr->rx_buf_ring[cons];
2738         prod_rx_buf = &rxr->rx_buf_ring[prod];
2739
2740         pci_dma_sync_single_for_device(bp->pdev,
2741                 pci_unmap_addr(cons_rx_buf, mapping),
2742                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2743
2744         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2745
2746         prod_rx_buf->skb = skb;
2747
2748         if (cons == prod)
2749                 return;
2750
2751         pci_unmap_addr_set(prod_rx_buf, mapping,
2752                         pci_unmap_addr(cons_rx_buf, mapping));
2753
2754         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2755         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2756         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2757         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2758 }
2759
2760 static int
2761 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2762             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2763             u32 ring_idx)
2764 {
2765         int err;
2766         u16 prod = ring_idx & 0xffff;
2767
2768         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2769         if (unlikely(err)) {
2770                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2771                 if (hdr_len) {
2772                         unsigned int raw_len = len + 4;
2773                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2774
2775                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2776                 }
2777                 return err;
2778         }
2779
2780         skb_reserve(skb, BNX2_RX_OFFSET);
2781         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2782                          PCI_DMA_FROMDEVICE);
2783
2784         if (hdr_len == 0) {
2785                 skb_put(skb, len);
2786                 return 0;
2787         } else {
2788                 unsigned int i, frag_len, frag_size, pages;
2789                 struct sw_pg *rx_pg;
2790                 u16 pg_cons = rxr->rx_pg_cons;
2791                 u16 pg_prod = rxr->rx_pg_prod;
2792
2793                 frag_size = len + 4 - hdr_len;
2794                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2795                 skb_put(skb, hdr_len);
2796
2797                 for (i = 0; i < pages; i++) {
2798                         dma_addr_t mapping_old;
2799
2800                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2801                         if (unlikely(frag_len <= 4)) {
2802                                 unsigned int tail = 4 - frag_len;
2803
2804                                 rxr->rx_pg_cons = pg_cons;
2805                                 rxr->rx_pg_prod = pg_prod;
2806                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2807                                                         pages - i);
2808                                 skb->len -= tail;
2809                                 if (i == 0) {
2810                                         skb->tail -= tail;
2811                                 } else {
2812                                         skb_frag_t *frag =
2813                                                 &skb_shinfo(skb)->frags[i - 1];
2814                                         frag->size -= tail;
2815                                         skb->data_len -= tail;
2816                                         skb->truesize -= tail;
2817                                 }
2818                                 return 0;
2819                         }
2820                         rx_pg = &rxr->rx_pg_ring[pg_cons];
2821
2822                         /* Don't unmap yet.  If we're unable to allocate a new
2823                          * page, we need to recycle the page and the DMA addr.
2824                          */
2825                         mapping_old = pci_unmap_addr(rx_pg, mapping);
2826                         if (i == pages - 1)
2827                                 frag_len -= 4;
2828
2829                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2830                         rx_pg->page = NULL;
2831
2832                         err = bnx2_alloc_rx_page(bp, rxr,
2833                                                  RX_PG_RING_IDX(pg_prod));
2834                         if (unlikely(err)) {
2835                                 rxr->rx_pg_cons = pg_cons;
2836                                 rxr->rx_pg_prod = pg_prod;
2837                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2838                                                         pages - i);
2839                                 return err;
2840                         }
2841
2842                         pci_unmap_page(bp->pdev, mapping_old,
2843                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2844
2845                         frag_size -= frag_len;
2846                         skb->data_len += frag_len;
2847                         skb->truesize += frag_len;
2848                         skb->len += frag_len;
2849
2850                         pg_prod = NEXT_RX_BD(pg_prod);
2851                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2852                 }
2853                 rxr->rx_pg_prod = pg_prod;
2854                 rxr->rx_pg_cons = pg_cons;
2855         }
2856         return 0;
2857 }
2858
2859 static inline u16
2860 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2861 {
2862         u16 cons;
2863
2864         /* Tell compiler that status block fields can change. */
2865         barrier();
2866         cons = *bnapi->hw_rx_cons_ptr;
2867         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2868                 cons++;
2869         return cons;
2870 }
2871
2872 static int
2873 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2874 {
2875         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2876         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2877         struct l2_fhdr *rx_hdr;
2878         int rx_pkt = 0, pg_ring_used = 0;
2879
2880         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2881         sw_cons = rxr->rx_cons;
2882         sw_prod = rxr->rx_prod;
2883
2884         /* Memory barrier necessary as speculative reads of the rx
2885          * buffer can be ahead of the index in the status block
2886          */
2887         rmb();
2888         while (sw_cons != hw_cons) {
2889                 unsigned int len, hdr_len;
2890                 u32 status;
2891                 struct sw_bd *rx_buf;
2892                 struct sk_buff *skb;
2893                 dma_addr_t dma_addr;
2894                 u16 vtag = 0;
2895                 int hw_vlan __maybe_unused = 0;
2896
2897                 sw_ring_cons = RX_RING_IDX(sw_cons);
2898                 sw_ring_prod = RX_RING_IDX(sw_prod);
2899
2900                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2901                 skb = rx_buf->skb;
2902
2903                 rx_buf->skb = NULL;
2904
2905                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2906
2907                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2908                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2909                         PCI_DMA_FROMDEVICE);
2910
2911                 rx_hdr = (struct l2_fhdr *) skb->data;
2912                 len = rx_hdr->l2_fhdr_pkt_len;
2913
2914                 if ((status = rx_hdr->l2_fhdr_status) &
2915                         (L2_FHDR_ERRORS_BAD_CRC |
2916                         L2_FHDR_ERRORS_PHY_DECODE |
2917                         L2_FHDR_ERRORS_ALIGNMENT |
2918                         L2_FHDR_ERRORS_TOO_SHORT |
2919                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2920
2921                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2922                                           sw_ring_prod);
2923                         goto next_rx;
2924                 }
2925                 hdr_len = 0;
2926                 if (status & L2_FHDR_STATUS_SPLIT) {
2927                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2928                         pg_ring_used = 1;
2929                 } else if (len > bp->rx_jumbo_thresh) {
2930                         hdr_len = bp->rx_jumbo_thresh;
2931                         pg_ring_used = 1;
2932                 }
2933
2934                 len -= 4;
2935
2936                 if (len <= bp->rx_copy_thresh) {
2937                         struct sk_buff *new_skb;
2938
2939                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
2940                         if (new_skb == NULL) {
2941                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2942                                                   sw_ring_prod);
2943                                 goto next_rx;
2944                         }
2945
2946                         /* aligned copy */
2947                         skb_copy_from_linear_data_offset(skb,
2948                                                          BNX2_RX_OFFSET - 6,
2949                                       new_skb->data, len + 6);
2950                         skb_reserve(new_skb, 6);
2951                         skb_put(new_skb, len);
2952
2953                         bnx2_reuse_rx_skb(bp, rxr, skb,
2954                                 sw_ring_cons, sw_ring_prod);
2955
2956                         skb = new_skb;
2957                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2958                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2959                         goto next_rx;
2960
2961                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2962                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2963                         vtag = rx_hdr->l2_fhdr_vlan_tag;
2964 #ifdef BCM_VLAN
2965                         if (bp->vlgrp)
2966                                 hw_vlan = 1;
2967                         else
2968 #endif
2969                         {
2970                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2971                                         __skb_push(skb, 4);
2972
2973                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2974                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
2975                                 ve->h_vlan_TCI = htons(vtag);
2976                                 len += 4;
2977                         }
2978                 }
2979
2980                 skb->protocol = eth_type_trans(skb, bp->dev);
2981
2982                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2983                         (ntohs(skb->protocol) != 0x8100)) {
2984
2985                         dev_kfree_skb(skb);
2986                         goto next_rx;
2987
2988                 }
2989
2990                 skb->ip_summed = CHECKSUM_NONE;
2991                 if (bp->rx_csum &&
2992                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2993                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2994
2995                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2996                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2997                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2998                 }
2999
3000 #ifdef BCM_VLAN
3001                 if (hw_vlan)
3002                         vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3003                 else
3004 #endif
3005                         netif_receive_skb(skb);
3006
3007                 rx_pkt++;
3008
3009 next_rx:
3010                 sw_cons = NEXT_RX_BD(sw_cons);
3011                 sw_prod = NEXT_RX_BD(sw_prod);
3012
3013                 if ((rx_pkt == budget))
3014                         break;
3015
3016                 /* Refresh hw_cons to see if there is new work */
3017                 if (sw_cons == hw_cons) {
3018                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3019                         rmb();
3020                 }
3021         }
3022         rxr->rx_cons = sw_cons;
3023         rxr->rx_prod = sw_prod;
3024
3025         if (pg_ring_used)
3026                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3027
3028         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3029
3030         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3031
3032         mmiowb();
3033
3034         return rx_pkt;
3035
3036 }
3037
3038 /* MSI ISR - The only difference between this and the INTx ISR
3039  * is that the MSI interrupt is always serviced.
3040  */
3041 static irqreturn_t
3042 bnx2_msi(int irq, void *dev_instance)
3043 {
3044         struct bnx2_napi *bnapi = dev_instance;
3045         struct bnx2 *bp = bnapi->bp;
3046
3047         prefetch(bnapi->status_blk.msi);
3048         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3049                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3050                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3051
3052         /* Return here if interrupt is disabled. */
3053         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3054                 return IRQ_HANDLED;
3055
3056         netif_rx_schedule(&bnapi->napi);
3057
3058         return IRQ_HANDLED;
3059 }
3060
3061 static irqreturn_t
3062 bnx2_msi_1shot(int irq, void *dev_instance)
3063 {
3064         struct bnx2_napi *bnapi = dev_instance;
3065         struct bnx2 *bp = bnapi->bp;
3066
3067         prefetch(bnapi->status_blk.msi);
3068
3069         /* Return here if interrupt is disabled. */
3070         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3071                 return IRQ_HANDLED;
3072
3073         netif_rx_schedule(&bnapi->napi);
3074
3075         return IRQ_HANDLED;
3076 }
3077
3078 static irqreturn_t
3079 bnx2_interrupt(int irq, void *dev_instance)
3080 {
3081         struct bnx2_napi *bnapi = dev_instance;
3082         struct bnx2 *bp = bnapi->bp;
3083         struct status_block *sblk = bnapi->status_blk.msi;
3084
3085         /* When using INTx, it is possible for the interrupt to arrive
3086          * at the CPU before the status block posted prior to the
3087          * interrupt. Reading a register will flush the status block.
3088          * When using MSI, the MSI message will always complete after
3089          * the status block write.
3090          */
3091         if ((sblk->status_idx == bnapi->last_status_idx) &&
3092             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3093              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3094                 return IRQ_NONE;
3095
3096         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3097                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3098                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3099
3100         /* Read back to deassert IRQ immediately to avoid too many
3101          * spurious interrupts.
3102          */
3103         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3104
3105         /* Return here if interrupt is shared and is disabled. */
3106         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3107                 return IRQ_HANDLED;
3108
3109         if (netif_rx_schedule_prep(&bnapi->napi)) {
3110                 bnapi->last_status_idx = sblk->status_idx;
3111                 __netif_rx_schedule(&bnapi->napi);
3112         }
3113
3114         return IRQ_HANDLED;
3115 }
3116
3117 static inline int
3118 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3119 {
3120         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3121         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3122
3123         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3124             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3125                 return 1;
3126         return 0;
3127 }
3128
3129 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3130                                  STATUS_ATTN_BITS_TIMER_ABORT)
3131
3132 static inline int
3133 bnx2_has_work(struct bnx2_napi *bnapi)
3134 {
3135         struct status_block *sblk = bnapi->status_blk.msi;
3136
3137         if (bnx2_has_fast_work(bnapi))
3138                 return 1;
3139
3140         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3141             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3142                 return 1;
3143
3144         return 0;
3145 }
3146
3147 static void
3148 bnx2_chk_missed_msi(struct bnx2 *bp)
3149 {
3150         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3151         u32 msi_ctrl;
3152
3153         if (bnx2_has_work(bnapi)) {
3154                 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3155                 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3156                         return;
3157
3158                 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3159                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3160                                ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3161                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3162                         bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3163                 }
3164         }
3165
3166         bp->idle_chk_status_idx = bnapi->last_status_idx;
3167 }
3168
3169 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3170 {
3171         struct status_block *sblk = bnapi->status_blk.msi;
3172         u32 status_attn_bits = sblk->status_attn_bits;
3173         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3174
3175         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3176             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3177
3178                 bnx2_phy_int(bp, bnapi);
3179
3180                 /* This is needed to take care of transient status
3181                  * during link changes.
3182                  */
3183                 REG_WR(bp, BNX2_HC_COMMAND,
3184                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3185                 REG_RD(bp, BNX2_HC_COMMAND);
3186         }
3187 }
3188
3189 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3190                           int work_done, int budget)
3191 {
3192         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3193         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3194
3195         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3196                 bnx2_tx_int(bp, bnapi, 0);
3197
3198         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3199                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3200
3201         return work_done;
3202 }
3203
3204 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3205 {
3206         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3207         struct bnx2 *bp = bnapi->bp;
3208         int work_done = 0;
3209         struct status_block_msix *sblk = bnapi->status_blk.msix;
3210
3211         while (1) {
3212                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3213                 if (unlikely(work_done >= budget))
3214                         break;
3215
3216                 bnapi->last_status_idx = sblk->status_idx;
3217                 /* status idx must be read before checking for more work. */
3218                 rmb();
3219                 if (likely(!bnx2_has_fast_work(bnapi))) {
3220
3221                         netif_rx_complete(napi);
3222                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3223                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3224                                bnapi->last_status_idx);
3225                         break;
3226                 }
3227         }
3228         return work_done;
3229 }
3230
3231 static int bnx2_poll(struct napi_struct *napi, int budget)
3232 {
3233         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3234         struct bnx2 *bp = bnapi->bp;
3235         int work_done = 0;
3236         struct status_block *sblk = bnapi->status_blk.msi;
3237
3238         while (1) {
3239                 bnx2_poll_link(bp, bnapi);
3240
3241                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3242
3243                 /* bnapi->last_status_idx is used below to tell the hw how
3244                  * much work has been processed, so we must read it before
3245                  * checking for more work.
3246                  */
3247                 bnapi->last_status_idx = sblk->status_idx;
3248
3249                 if (unlikely(work_done >= budget))
3250                         break;
3251
3252                 rmb();
3253                 if (likely(!bnx2_has_work(bnapi))) {
3254                         netif_rx_complete(napi);
3255                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3256                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3257                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3258                                        bnapi->last_status_idx);
3259                                 break;
3260                         }
3261                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3262                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3263                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3264                                bnapi->last_status_idx);
3265
3266                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3267                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3268                                bnapi->last_status_idx);
3269                         break;
3270                 }
3271         }
3272
3273         return work_done;
3274 }
3275
3276 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3277  * from set_multicast.
3278  */
3279 static void
3280 bnx2_set_rx_mode(struct net_device *dev)
3281 {
3282         struct bnx2 *bp = netdev_priv(dev);
3283         u32 rx_mode, sort_mode;
3284         struct dev_addr_list *uc_ptr;
3285         int i;
3286
3287         if (!netif_running(dev))
3288                 return;
3289
3290         spin_lock_bh(&bp->phy_lock);
3291
3292         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3293                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3294         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3295 #ifdef BCM_VLAN
3296         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3297                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3298 #else
3299         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3300                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3301 #endif
3302         if (dev->flags & IFF_PROMISC) {
3303                 /* Promiscuous mode. */
3304                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3305                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3306                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3307         }
3308         else if (dev->flags & IFF_ALLMULTI) {
3309                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3310                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3311                                0xffffffff);
3312                 }
3313                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3314         }
3315         else {
3316                 /* Accept one or more multicast(s). */
3317                 struct dev_mc_list *mclist;
3318                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3319                 u32 regidx;
3320                 u32 bit;
3321                 u32 crc;
3322
3323                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3324
3325                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3326                      i++, mclist = mclist->next) {
3327
3328                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3329                         bit = crc & 0xff;
3330                         regidx = (bit & 0xe0) >> 5;
3331                         bit &= 0x1f;
3332                         mc_filter[regidx] |= (1 << bit);
3333                 }
3334
3335                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3336                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3337                                mc_filter[i]);
3338                 }
3339
3340                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3341         }
3342
3343         uc_ptr = NULL;
3344         if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3345                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3346                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3347                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3348         } else if (!(dev->flags & IFF_PROMISC)) {
3349                 uc_ptr = dev->uc_list;
3350
3351                 /* Add all entries into to the match filter list */
3352                 for (i = 0; i < dev->uc_count; i++) {
3353                         bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3354                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3355                         sort_mode |= (1 <<
3356                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3357                         uc_ptr = uc_ptr->next;
3358                 }
3359
3360         }
3361
3362         if (rx_mode != bp->rx_mode) {
3363                 bp->rx_mode = rx_mode;
3364                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3365         }
3366
3367         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3368         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3369         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3370
3371         spin_unlock_bh(&bp->phy_lock);
3372 }
3373
3374 static void
3375 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3376         u32 rv2p_proc)
3377 {
3378         int i;
3379         u32 val;
3380
3381         if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3382                 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3383                 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3384                 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3385                 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3386         }
3387
3388         for (i = 0; i < rv2p_code_len; i += 8) {
3389                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3390                 rv2p_code++;
3391                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3392                 rv2p_code++;
3393
3394                 if (rv2p_proc == RV2P_PROC1) {
3395                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3396                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3397                 }
3398                 else {
3399                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3400                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3401                 }
3402         }
3403
3404         /* Reset the processor, un-stall is done later. */
3405         if (rv2p_proc == RV2P_PROC1) {
3406                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3407         }
3408         else {
3409                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3410         }
3411 }
3412
3413 static int
3414 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3415 {
3416         u32 offset;
3417         u32 val;
3418         int rc;
3419
3420         /* Halt the CPU. */
3421         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3422         val |= cpu_reg->mode_value_halt;
3423         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3424         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3425
3426         /* Load the Text area. */
3427         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3428         if (fw->gz_text) {
3429                 int j;
3430
3431                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3432                                        fw->gz_text_len);
3433                 if (rc < 0)
3434                         return rc;
3435
3436                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3437                         bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3438                 }
3439         }
3440
3441         /* Load the Data area. */
3442         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3443         if (fw->data) {
3444                 int j;
3445
3446                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3447                         bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3448                 }
3449         }
3450
3451         /* Load the SBSS area. */
3452         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3453         if (fw->sbss_len) {
3454                 int j;
3455
3456                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3457                         bnx2_reg_wr_ind(bp, offset, 0);
3458                 }
3459         }
3460
3461         /* Load the BSS area. */
3462         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3463         if (fw->bss_len) {
3464                 int j;
3465
3466                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3467                         bnx2_reg_wr_ind(bp, offset, 0);
3468                 }
3469         }
3470
3471         /* Load the Read-Only area. */
3472         offset = cpu_reg->spad_base +
3473                 (fw->rodata_addr - cpu_reg->mips_view_base);
3474         if (fw->rodata) {
3475                 int j;
3476
3477                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3478                         bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3479                 }
3480         }
3481
3482         /* Clear the pre-fetch instruction. */
3483         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3484         bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3485
3486         /* Start the CPU. */
3487         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3488         val &= ~cpu_reg->mode_value_halt;
3489         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3490         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3491
3492         return 0;
3493 }
3494
3495 static int
3496 bnx2_init_cpus(struct bnx2 *bp)
3497 {
3498         struct fw_info *fw;
3499         int rc, rv2p_len;
3500         void *text, *rv2p;
3501
3502         /* Initialize the RV2P processor. */
3503         text = vmalloc(FW_BUF_SIZE);
3504         if (!text)
3505                 return -ENOMEM;
3506         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3507                 rv2p = bnx2_xi_rv2p_proc1;
3508                 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3509         } else {
3510                 rv2p = bnx2_rv2p_proc1;
3511                 rv2p_len = sizeof(bnx2_rv2p_proc1);
3512         }
3513         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3514         if (rc < 0)
3515                 goto init_cpu_err;
3516
3517         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3518
3519         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3520                 rv2p = bnx2_xi_rv2p_proc2;
3521                 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3522         } else {
3523                 rv2p = bnx2_rv2p_proc2;
3524                 rv2p_len = sizeof(bnx2_rv2p_proc2);
3525         }
3526         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3527         if (rc < 0)
3528                 goto init_cpu_err;
3529
3530         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3531
3532         /* Initialize the RX Processor. */
3533         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3534                 fw = &bnx2_rxp_fw_09;
3535         else
3536                 fw = &bnx2_rxp_fw_06;
3537
3538         fw->text = text;
3539         rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3540         if (rc)
3541                 goto init_cpu_err;
3542
3543         /* Initialize the TX Processor. */
3544         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3545                 fw = &bnx2_txp_fw_09;
3546         else
3547                 fw = &bnx2_txp_fw_06;
3548
3549         fw->text = text;
3550         rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3551         if (rc)
3552                 goto init_cpu_err;
3553
3554         /* Initialize the TX Patch-up Processor. */
3555         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3556                 fw = &bnx2_tpat_fw_09;
3557         else
3558                 fw = &bnx2_tpat_fw_06;
3559
3560         fw->text = text;
3561         rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3562         if (rc)
3563                 goto init_cpu_err;
3564
3565         /* Initialize the Completion Processor. */
3566         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3567                 fw = &bnx2_com_fw_09;
3568         else
3569                 fw = &bnx2_com_fw_06;
3570
3571         fw->text = text;
3572         rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3573         if (rc)
3574                 goto init_cpu_err;
3575
3576         /* Initialize the Command Processor. */
3577         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3578                 fw = &bnx2_cp_fw_09;
3579         else
3580                 fw = &bnx2_cp_fw_06;
3581
3582         fw->text = text;
3583         rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3584
3585 init_cpu_err:
3586         vfree(text);
3587         return rc;
3588 }
3589
3590 static int
3591 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3592 {
3593         u16 pmcsr;
3594
3595         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3596
3597         switch (state) {
3598         case PCI_D0: {
3599                 u32 val;
3600
3601                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3602                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3603                         PCI_PM_CTRL_PME_STATUS);
3604
3605                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3606                         /* delay required during transition out of D3hot */
3607                         msleep(20);
3608
3609                 val = REG_RD(bp, BNX2_EMAC_MODE);
3610                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3611                 val &= ~BNX2_EMAC_MODE_MPKT;
3612                 REG_WR(bp, BNX2_EMAC_MODE, val);
3613
3614                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3615                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3616                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3617                 break;
3618         }
3619         case PCI_D3hot: {
3620                 int i;
3621                 u32 val, wol_msg;
3622
3623                 if (bp->wol) {
3624                         u32 advertising;
3625                         u8 autoneg;
3626
3627                         autoneg = bp->autoneg;
3628                         advertising = bp->advertising;
3629
3630                         if (bp->phy_port == PORT_TP) {
3631                                 bp->autoneg = AUTONEG_SPEED;
3632                                 bp->advertising = ADVERTISED_10baseT_Half |
3633                                         ADVERTISED_10baseT_Full |
3634                                         ADVERTISED_100baseT_Half |
3635                                         ADVERTISED_100baseT_Full |
3636                                         ADVERTISED_Autoneg;
3637                         }
3638
3639                         spin_lock_bh(&bp->phy_lock);
3640                         bnx2_setup_phy(bp, bp->phy_port);
3641                         spin_unlock_bh(&bp->phy_lock);
3642
3643                         bp->autoneg = autoneg;
3644                         bp->advertising = advertising;
3645
3646                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3647
3648                         val = REG_RD(bp, BNX2_EMAC_MODE);
3649
3650                         /* Enable port mode. */
3651                         val &= ~BNX2_EMAC_MODE_PORT;
3652                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3653                                BNX2_EMAC_MODE_ACPI_RCVD |
3654                                BNX2_EMAC_MODE_MPKT;
3655                         if (bp->phy_port == PORT_TP)
3656                                 val |= BNX2_EMAC_MODE_PORT_MII;
3657                         else {
3658                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3659                                 if (bp->line_speed == SPEED_2500)
3660                                         val |= BNX2_EMAC_MODE_25G_MODE;
3661                         }
3662
3663                         REG_WR(bp, BNX2_EMAC_MODE, val);
3664
3665                         /* receive all multicast */
3666                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3667                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3668                                        0xffffffff);
3669                         }
3670                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3671                                BNX2_EMAC_RX_MODE_SORT_MODE);
3672
3673                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3674                               BNX2_RPM_SORT_USER0_MC_EN;
3675                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3676                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3677                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3678                                BNX2_RPM_SORT_USER0_ENA);
3679
3680                         /* Need to enable EMAC and RPM for WOL. */
3681                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3682                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3683                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3684                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3685
3686                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3687                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3688                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3689
3690                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3691                 }
3692                 else {
3693                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3694                 }
3695
3696                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3697                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3698                                      1, 0);
3699
3700                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3701                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3702                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3703
3704                         if (bp->wol)
3705                                 pmcsr |= 3;
3706                 }
3707                 else {
3708                         pmcsr |= 3;
3709                 }
3710                 if (bp->wol) {
3711                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3712                 }
3713                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3714                                       pmcsr);
3715
3716                 /* No more memory access after this point until
3717                  * device is brought back to D0.
3718                  */
3719                 udelay(50);
3720                 break;
3721         }
3722         default:
3723                 return -EINVAL;
3724         }
3725         return 0;
3726 }
3727
3728 static int
3729 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3730 {
3731         u32 val;
3732         int j;
3733
3734         /* Request access to the flash interface. */
3735         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3736         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3737                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3738                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3739                         break;
3740
3741                 udelay(5);
3742         }
3743
3744         if (j >= NVRAM_TIMEOUT_COUNT)
3745                 return -EBUSY;
3746
3747         return 0;
3748 }
3749
3750 static int
3751 bnx2_release_nvram_lock(struct bnx2 *bp)
3752 {
3753         int j;
3754         u32 val;
3755
3756         /* Relinquish nvram interface. */
3757         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3758
3759         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3760                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3761                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3762                         break;
3763
3764                 udelay(5);
3765         }
3766
3767         if (j >= NVRAM_TIMEOUT_COUNT)
3768                 return -EBUSY;
3769
3770         return 0;
3771 }
3772
3773
3774 static int
3775 bnx2_enable_nvram_write(struct bnx2 *bp)
3776 {
3777         u32 val;
3778
3779         val = REG_RD(bp, BNX2_MISC_CFG);
3780         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3781
3782         if (bp->flash_info->flags & BNX2_NV_WREN) {
3783                 int j;
3784
3785                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3786                 REG_WR(bp, BNX2_NVM_COMMAND,
3787                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3788
3789                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3790                         udelay(5);
3791
3792                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3793                         if (val & BNX2_NVM_COMMAND_DONE)
3794                                 break;
3795                 }
3796
3797                 if (j >= NVRAM_TIMEOUT_COUNT)
3798                         return -EBUSY;
3799         }
3800         return 0;
3801 }
3802
3803 static void
3804 bnx2_disable_nvram_write(struct bnx2 *bp)
3805 {
3806         u32 val;
3807
3808         val = REG_RD(bp, BNX2_MISC_CFG);
3809         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3810 }
3811
3812
3813 static void
3814 bnx2_enable_nvram_access(struct bnx2 *bp)
3815 {
3816         u32 val;
3817
3818         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3819         /* Enable both bits, even on read. */
3820         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3821                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3822 }
3823
3824 static void
3825 bnx2_disable_nvram_access(struct bnx2 *bp)
3826 {
3827         u32 val;
3828
3829         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3830         /* Disable both bits, even after read. */
3831         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3832                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3833                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3834 }
3835
3836 static int
3837 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3838 {
3839         u32 cmd;
3840         int j;
3841
3842         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3843                 /* Buffered flash, no erase needed */
3844                 return 0;
3845
3846         /* Build an erase command */
3847         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3848               BNX2_NVM_COMMAND_DOIT;
3849
3850         /* Need to clear DONE bit separately. */
3851         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3852
3853         /* Address of the NVRAM to read from. */
3854         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3855
3856         /* Issue an erase command. */
3857         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3858
3859         /* Wait for completion. */
3860         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3861                 u32 val;
3862
3863                 udelay(5);
3864
3865                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3866                 if (val & BNX2_NVM_COMMAND_DONE)
3867                         break;
3868         }
3869
3870         if (j >= NVRAM_TIMEOUT_COUNT)
3871                 return -EBUSY;
3872
3873         return 0;
3874 }
3875
3876 static int
3877 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3878 {
3879         u32 cmd;
3880         int j;
3881
3882         /* Build the command word. */
3883         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3884
3885         /* Calculate an offset of a buffered flash, not needed for 5709. */
3886         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3887                 offset = ((offset / bp->flash_info->page_size) <<
3888                            bp->flash_info->page_bits) +
3889                           (offset % bp->flash_info->page_size);
3890         }
3891
3892         /* Need to clear DONE bit separately. */
3893         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3894
3895         /* Address of the NVRAM to read from. */
3896         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3897
3898         /* Issue a read command. */
3899         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3900
3901         /* Wait for completion. */
3902         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3903                 u32 val;
3904
3905                 udelay(5);
3906
3907                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3908                 if (val & BNX2_NVM_COMMAND_DONE) {
3909                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3910                         memcpy(ret_val, &v, 4);
3911                         break;
3912                 }
3913         }
3914         if (j >= NVRAM_TIMEOUT_COUNT)
3915                 return -EBUSY;
3916
3917         return 0;
3918 }
3919
3920
3921 static int
3922 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3923 {
3924         u32 cmd;
3925         __be32 val32;
3926         int j;
3927
3928         /* Build the command word. */
3929         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3930
3931         /* Calculate an offset of a buffered flash, not needed for 5709. */
3932         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3933                 offset = ((offset / bp->flash_info->page_size) <<
3934                           bp->flash_info->page_bits) +
3935                          (offset % bp->flash_info->page_size);
3936         }
3937
3938         /* Need to clear DONE bit separately. */
3939         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3940
3941         memcpy(&val32, val, 4);
3942
3943         /* Write the data. */
3944         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3945
3946         /* Address of the NVRAM to write to. */
3947         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3948
3949         /* Issue the write command. */
3950         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3951
3952         /* Wait for completion. */
3953         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3954                 udelay(5);
3955
3956                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3957                         break;
3958         }
3959         if (j >= NVRAM_TIMEOUT_COUNT)
3960                 return -EBUSY;
3961
3962         return 0;
3963 }
3964
3965 static int
3966 bnx2_init_nvram(struct bnx2 *bp)
3967 {
3968         u32 val;
3969         int j, entry_count, rc = 0;
3970         struct flash_spec *flash;
3971
3972         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3973                 bp->flash_info = &flash_5709;
3974                 goto get_flash_size;
3975         }
3976
3977         /* Determine the selected interface. */
3978         val = REG_RD(bp, BNX2_NVM_CFG1);
3979
3980         entry_count = ARRAY_SIZE(flash_table);
3981
3982         if (val & 0x40000000) {
3983
3984                 /* Flash interface has been reconfigured */
3985                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3986                      j++, flash++) {
3987                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3988                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3989                                 bp->flash_info = flash;
3990                                 break;
3991                         }
3992                 }
3993         }
3994         else {
3995                 u32 mask;
3996                 /* Not yet been reconfigured */
3997
3998                 if (val & (1 << 23))
3999                         mask = FLASH_BACKUP_STRAP_MASK;
4000                 else
4001                         mask = FLASH_STRAP_MASK;
4002
4003                 for (j = 0, flash = &flash_table[0]; j < entry_count;
4004                         j++, flash++) {
4005
4006                         if ((val & mask) == (flash->strapping & mask)) {
4007                                 bp->flash_info = flash;
4008
4009                                 /* Request access to the flash interface. */
4010                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4011                                         return rc;
4012
4013                                 /* Enable access to flash interface */
4014                                 bnx2_enable_nvram_access(bp);
4015
4016                                 /* Reconfigure the flash interface */
4017                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4018                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4019                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4020                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4021
4022                                 /* Disable access to flash interface */
4023                                 bnx2_disable_nvram_access(bp);
4024                                 bnx2_release_nvram_lock(bp);
4025
4026                                 break;
4027                         }
4028                 }
4029         } /* if (val & 0x40000000) */
4030
4031         if (j == entry_count) {
4032                 bp->flash_info = NULL;
4033                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4034                 return -ENODEV;
4035         }
4036
4037 get_flash_size:
4038         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4039         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4040         if (val)
4041                 bp->flash_size = val;
4042         else
4043                 bp->flash_size = bp->flash_info->total_size;
4044
4045         return rc;
4046 }
4047
4048 static int
4049 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4050                 int buf_size)
4051 {
4052         int rc = 0;
4053         u32 cmd_flags, offset32, len32, extra;
4054
4055         if (buf_size == 0)
4056                 return 0;
4057
4058         /* Request access to the flash interface. */
4059         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4060                 return rc;
4061
4062         /* Enable access to flash interface */
4063         bnx2_enable_nvram_access(bp);
4064
4065         len32 = buf_size;
4066         offset32 = offset;
4067         extra = 0;
4068
4069         cmd_flags = 0;
4070
4071         if (offset32 & 3) {
4072                 u8 buf[4];
4073                 u32 pre_len;
4074
4075                 offset32 &= ~3;
4076                 pre_len = 4 - (offset & 3);
4077
4078                 if (pre_len >= len32) {
4079                         pre_len = len32;
4080                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4081                                     BNX2_NVM_COMMAND_LAST;
4082                 }
4083                 else {
4084                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4085                 }
4086
4087                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4088
4089                 if (rc)
4090                         return rc;
4091
4092                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4093
4094                 offset32 += 4;
4095                 ret_buf += pre_len;
4096                 len32 -= pre_len;
4097         }
4098         if (len32 & 3) {
4099                 extra = 4 - (len32 & 3);
4100                 len32 = (len32 + 4) & ~3;
4101         }
4102
4103         if (len32 == 4) {
4104                 u8 buf[4];
4105
4106                 if (cmd_flags)
4107                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4108                 else
4109                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4110                                     BNX2_NVM_COMMAND_LAST;
4111
4112                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4113
4114                 memcpy(ret_buf, buf, 4 - extra);
4115         }
4116         else if (len32 > 0) {
4117                 u8 buf[4];
4118
4119                 /* Read the first word. */
4120                 if (cmd_flags)
4121                         cmd_flags = 0;
4122                 else
4123                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4124
4125                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4126
4127                 /* Advance to the next dword. */
4128                 offset32 += 4;
4129                 ret_buf += 4;
4130                 len32 -= 4;
4131
4132                 while (len32 > 4 && rc == 0) {
4133                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4134
4135                         /* Advance to the next dword. */
4136                         offset32 += 4;
4137                         ret_buf += 4;
4138                         len32 -= 4;
4139                 }
4140
4141                 if (rc)
4142                         return rc;
4143
4144                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4145                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4146
4147                 memcpy(ret_buf, buf, 4 - extra);
4148         }
4149
4150         /* Disable access to flash interface */
4151         bnx2_disable_nvram_access(bp);
4152
4153         bnx2_release_nvram_lock(bp);
4154
4155         return rc;
4156 }
4157
4158 static int
4159 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4160                 int buf_size)
4161 {
4162         u32 written, offset32, len32;
4163         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4164         int rc = 0;
4165         int align_start, align_end;
4166
4167         buf = data_buf;
4168         offset32 = offset;
4169         len32 = buf_size;
4170         align_start = align_end = 0;
4171
4172         if ((align_start = (offset32 & 3))) {
4173                 offset32 &= ~3;
4174                 len32 += align_start;
4175                 if (len32 < 4)
4176                         len32 = 4;
4177                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4178                         return rc;
4179         }
4180
4181         if (len32 & 3) {
4182                 align_end = 4 - (len32 & 3);
4183                 len32 += align_end;
4184                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4185                         return rc;
4186         }
4187
4188         if (align_start || align_end) {
4189                 align_buf = kmalloc(len32, GFP_KERNEL);
4190                 if (align_buf == NULL)
4191                         return -ENOMEM;
4192                 if (align_start) {
4193                         memcpy(align_buf, start, 4);
4194                 }
4195                 if (align_end) {
4196                         memcpy(align_buf + len32 - 4, end, 4);
4197                 }
4198                 memcpy(align_buf + align_start, data_buf, buf_size);
4199                 buf = align_buf;
4200         }
4201
4202         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4203                 flash_buffer = kmalloc(264, GFP_KERNEL);
4204                 if (flash_buffer == NULL) {
4205                         rc = -ENOMEM;
4206                         goto nvram_write_end;
4207                 }
4208         }
4209
4210         written = 0;
4211         while ((written < len32) && (rc == 0)) {
4212                 u32 page_start, page_end, data_start, data_end;
4213                 u32 addr, cmd_flags;
4214                 int i;
4215
4216                 /* Find the page_start addr */
4217                 page_start = offset32 + written;
4218                 page_start -= (page_start % bp->flash_info->page_size);
4219                 /* Find the page_end addr */
4220                 page_end = page_start + bp->flash_info->page_size;
4221                 /* Find the data_start addr */
4222                 data_start = (written == 0) ? offset32 : page_start;
4223                 /* Find the data_end addr */
4224                 data_end = (page_end > offset32 + len32) ?
4225                         (offset32 + len32) : page_end;
4226
4227                 /* Request access to the flash interface. */
4228                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4229                         goto nvram_write_end;
4230
4231                 /* Enable access to flash interface */
4232                 bnx2_enable_nvram_access(bp);
4233
4234                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4235                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4236                         int j;
4237
4238                         /* Read the whole page into the buffer
4239                          * (non-buffer flash only) */
4240                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4241                                 if (j == (bp->flash_info->page_size - 4)) {
4242                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4243                                 }
4244                                 rc = bnx2_nvram_read_dword(bp,
4245                                         page_start + j,
4246                                         &flash_buffer[j],
4247                                         cmd_flags);
4248
4249                                 if (rc)
4250                                         goto nvram_write_end;
4251
4252                                 cmd_flags = 0;
4253                         }
4254                 }
4255
4256                 /* Enable writes to flash interface (unlock write-protect) */
4257                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4258                         goto nvram_write_end;
4259
4260                 /* Loop to write back the buffer data from page_start to
4261                  * data_start */
4262                 i = 0;
4263                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4264                         /* Erase the page */
4265                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4266                                 goto nvram_write_end;
4267
4268                         /* Re-enable the write again for the actual write */
4269                         bnx2_enable_nvram_write(bp);
4270
4271                         for (addr = page_start; addr < data_start;
4272                                 addr += 4, i += 4) {
4273
4274                                 rc = bnx2_nvram_write_dword(bp, addr,
4275                                         &flash_buffer[i], cmd_flags);
4276
4277                                 if (rc != 0)
4278                                         goto nvram_write_end;
4279
4280                                 cmd_flags = 0;
4281                         }
4282                 }
4283
4284                 /* Loop to write the new data from data_start to data_end */
4285                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4286                         if ((addr == page_end - 4) ||
4287                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4288                                  (addr == data_end - 4))) {
4289
4290                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4291                         }
4292                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4293                                 cmd_flags);
4294
4295                         if (rc != 0)
4296                                 goto nvram_write_end;
4297
4298                         cmd_flags = 0;
4299                         buf += 4;
4300                 }
4301
4302                 /* Loop to write back the buffer data from data_end
4303                  * to page_end */
4304                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4305                         for (addr = data_end; addr < page_end;
4306                                 addr += 4, i += 4) {
4307
4308                                 if (addr == page_end-4) {
4309                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4310                                 }
4311                                 rc = bnx2_nvram_write_dword(bp, addr,
4312                                         &flash_buffer[i], cmd_flags);
4313
4314                                 if (rc != 0)
4315                                         goto nvram_write_end;
4316
4317                                 cmd_flags = 0;
4318                         }
4319                 }
4320
4321                 /* Disable writes to flash interface (lock write-protect) */
4322                 bnx2_disable_nvram_write(bp);
4323
4324                 /* Disable access to flash interface */
4325                 bnx2_disable_nvram_access(bp);
4326                 bnx2_release_nvram_lock(bp);
4327
4328                 /* Increment written */
4329                 written += data_end - data_start;
4330         }
4331
4332 nvram_write_end:
4333         kfree(flash_buffer);
4334         kfree(align_buf);
4335         return rc;
4336 }
4337
4338 static void
4339 bnx2_init_fw_cap(struct bnx2 *bp)
4340 {
4341         u32 val, sig = 0;
4342
4343         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4344         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4345
4346         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4347                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4348
4349         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4350         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4351                 return;
4352
4353         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4354                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4355                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4356         }
4357
4358         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4359             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4360                 u32 link;
4361
4362                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4363
4364                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4365                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4366                         bp->phy_port = PORT_FIBRE;
4367                 else
4368                         bp->phy_port = PORT_TP;
4369
4370                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4371                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4372         }
4373
4374         if (netif_running(bp->dev) && sig)
4375                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4376 }
4377
4378 static void
4379 bnx2_setup_msix_tbl(struct bnx2 *bp)
4380 {
4381         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4382
4383         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4384         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4385 }
4386
4387 static int
4388 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4389 {
4390         u32 val;
4391         int i, rc = 0;
4392         u8 old_port;
4393
4394         /* Wait for the current PCI transaction to complete before
4395          * issuing a reset. */
4396         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4397                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4398                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4399                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4400                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4401         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4402         udelay(5);
4403
4404         /* Wait for the firmware to tell us it is ok to issue a reset. */
4405         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4406
4407         /* Deposit a driver reset signature so the firmware knows that
4408          * this is a soft reset. */
4409         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4410                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4411
4412         /* Do a dummy read to force the chip to complete all current transaction
4413          * before we issue a reset. */
4414         val = REG_RD(bp, BNX2_MISC_ID);
4415
4416         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4417                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4418                 REG_RD(bp, BNX2_MISC_COMMAND);
4419                 udelay(5);
4420
4421                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4422                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4423
4424                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4425
4426         } else {
4427                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4428                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4429                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4430
4431                 /* Chip reset. */
4432                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4433
4434                 /* Reading back any register after chip reset will hang the
4435                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4436                  * of margin for write posting.
4437                  */
4438                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4439                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4440                         msleep(20);
4441
4442                 /* Reset takes approximate 30 usec */
4443                 for (i = 0; i < 10; i++) {
4444                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4445                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4446                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4447                                 break;
4448                         udelay(10);
4449                 }
4450
4451                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4452                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4453                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4454                         return -EBUSY;
4455                 }
4456         }
4457
4458         /* Make sure byte swapping is properly configured. */
4459         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4460         if (val != 0x01020304) {
4461                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4462                 return -ENODEV;
4463         }
4464
4465         /* Wait for the firmware to finish its initialization. */
4466         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4467         if (rc)
4468                 return rc;
4469
4470         spin_lock_bh(&bp->phy_lock);
4471         old_port = bp->phy_port;
4472         bnx2_init_fw_cap(bp);
4473         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4474             old_port != bp->phy_port)
4475                 bnx2_set_default_remote_link(bp);
4476         spin_unlock_bh(&bp->phy_lock);
4477
4478         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4479                 /* Adjust the voltage regular to two steps lower.  The default
4480                  * of this register is 0x0000000e. */
4481                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4482
4483                 /* Remove bad rbuf memory from the free pool. */
4484                 rc = bnx2_alloc_bad_rbuf(bp);
4485         }
4486
4487         if (bp->flags & BNX2_FLAG_USING_MSIX)
4488                 bnx2_setup_msix_tbl(bp);
4489
4490         return rc;
4491 }
4492
4493 static int
4494 bnx2_init_chip(struct bnx2 *bp)
4495 {
4496         u32 val, mtu;
4497         int rc, i;
4498
4499         /* Make sure the interrupt is not active. */
4500         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4501
4502         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4503               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4504 #ifdef __BIG_ENDIAN
4505               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4506 #endif
4507               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4508               DMA_READ_CHANS << 12 |
4509               DMA_WRITE_CHANS << 16;
4510
4511         val |= (0x2 << 20) | (1 << 11);
4512
4513         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4514                 val |= (1 << 23);
4515
4516         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4517             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4518                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4519
4520         REG_WR(bp, BNX2_DMA_CONFIG, val);
4521
4522         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4523                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4524                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4525                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4526         }
4527
4528         if (bp->flags & BNX2_FLAG_PCIX) {
4529                 u16 val16;
4530
4531                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4532                                      &val16);
4533                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4534                                       val16 & ~PCI_X_CMD_ERO);
4535         }
4536
4537         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4538                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4539                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4540                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4541
4542         /* Initialize context mapping and zero out the quick contexts.  The
4543          * context block must have already been enabled. */
4544         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4545                 rc = bnx2_init_5709_context(bp);
4546                 if (rc)
4547                         return rc;
4548         } else
4549                 bnx2_init_context(bp);
4550
4551         if ((rc = bnx2_init_cpus(bp)) != 0)
4552                 return rc;
4553
4554         bnx2_init_nvram(bp);
4555
4556         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4557
4558         val = REG_RD(bp, BNX2_MQ_CONFIG);
4559         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4560         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4561         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4562                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4563
4564         REG_WR(bp, BNX2_MQ_CONFIG, val);
4565
4566         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4567         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4568         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4569
4570         val = (BCM_PAGE_BITS - 8) << 24;
4571         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4572
4573         /* Configure page size. */
4574         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4575         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4576         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4577         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4578
4579         val = bp->mac_addr[0] +
4580               (bp->mac_addr[1] << 8) +
4581               (bp->mac_addr[2] << 16) +
4582               bp->mac_addr[3] +
4583               (bp->mac_addr[4] << 8) +
4584               (bp->mac_addr[5] << 16);
4585         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4586
4587         /* Program the MTU.  Also include 4 bytes for CRC32. */
4588         mtu = bp->dev->mtu;
4589         val = mtu + ETH_HLEN + ETH_FCS_LEN;
4590         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4591                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4592         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4593
4594         if (mtu < 1500)
4595                 mtu = 1500;
4596
4597         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4598         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4599         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4600
4601         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4602                 bp->bnx2_napi[i].last_status_idx = 0;
4603
4604         bp->idle_chk_status_idx = 0xffff;
4605
4606         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4607
4608         /* Set up how to generate a link change interrupt. */
4609         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4610
4611         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4612                (u64) bp->status_blk_mapping & 0xffffffff);
4613         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4614
4615         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4616                (u64) bp->stats_blk_mapping & 0xffffffff);
4617         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4618                (u64) bp->stats_blk_mapping >> 32);
4619
4620         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4621                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4622
4623         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4624                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4625
4626         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4627                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4628
4629         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4630
4631         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4632
4633         REG_WR(bp, BNX2_HC_COM_TICKS,
4634                (bp->com_ticks_int << 16) | bp->com_ticks);
4635
4636         REG_WR(bp, BNX2_HC_CMD_TICKS,
4637                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4638
4639         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4640                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4641         else
4642                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4643         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4644
4645         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4646                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4647         else {
4648                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4649                       BNX2_HC_CONFIG_COLLECT_STATS;
4650         }
4651
4652         if (bp->irq_nvecs > 1) {
4653                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4654                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4655
4656                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4657         }
4658
4659         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4660                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4661
4662         REG_WR(bp, BNX2_HC_CONFIG, val);
4663
4664         for (i = 1; i < bp->irq_nvecs; i++) {
4665                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4666                            BNX2_HC_SB_CONFIG_1;
4667
4668                 REG_WR(bp, base,
4669                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4670                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4671                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4672
4673                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4674                         (bp->tx_quick_cons_trip_int << 16) |
4675                          bp->tx_quick_cons_trip);
4676
4677                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4678                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4679
4680                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4681                        (bp->rx_quick_cons_trip_int << 16) |
4682                         bp->rx_quick_cons_trip);
4683
4684                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4685                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4686         }
4687
4688         /* Clear internal stats counters. */
4689         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4690
4691         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4692
4693         /* Initialize the receive filter. */
4694         bnx2_set_rx_mode(bp->dev);
4695
4696         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4697                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4698                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4699                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4700         }
4701         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4702                           1, 0);
4703
4704         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4705         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4706
4707         udelay(20);
4708
4709         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4710
4711         return rc;
4712 }
4713
4714 static void
4715 bnx2_clear_ring_states(struct bnx2 *bp)
4716 {
4717         struct bnx2_napi *bnapi;
4718         struct bnx2_tx_ring_info *txr;
4719         struct bnx2_rx_ring_info *rxr;
4720         int i;
4721
4722         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4723                 bnapi = &bp->bnx2_napi[i];
4724                 txr = &bnapi->tx_ring;
4725                 rxr = &bnapi->rx_ring;
4726
4727                 txr->tx_cons = 0;
4728                 txr->hw_tx_cons = 0;
4729                 rxr->rx_prod_bseq = 0;
4730                 rxr->rx_prod = 0;
4731                 rxr->rx_cons = 0;
4732                 rxr->rx_pg_prod = 0;
4733                 rxr->rx_pg_cons = 0;
4734         }
4735 }
4736
4737 static void
4738 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4739 {
4740         u32 val, offset0, offset1, offset2, offset3;
4741         u32 cid_addr = GET_CID_ADDR(cid);
4742
4743         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4744                 offset0 = BNX2_L2CTX_TYPE_XI;
4745                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4746                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4747                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4748         } else {
4749                 offset0 = BNX2_L2CTX_TYPE;
4750                 offset1 = BNX2_L2CTX_CMD_TYPE;
4751                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4752                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4753         }
4754         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4755         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4756
4757         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4758         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4759
4760         val = (u64) txr->tx_desc_mapping >> 32;
4761         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4762
4763         val = (u64) txr->tx_desc_mapping & 0xffffffff;
4764         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4765 }
4766
4767 static void
4768 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4769 {
4770         struct tx_bd *txbd;
4771         u32 cid = TX_CID;
4772         struct bnx2_napi *bnapi;
4773         struct bnx2_tx_ring_info *txr;
4774
4775         bnapi = &bp->bnx2_napi[ring_num];
4776         txr = &bnapi->tx_ring;
4777
4778         if (ring_num == 0)
4779                 cid = TX_CID;
4780         else
4781                 cid = TX_TSS_CID + ring_num - 1;
4782
4783         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4784
4785         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4786
4787         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4788         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4789
4790         txr->tx_prod = 0;
4791         txr->tx_prod_bseq = 0;
4792
4793         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4794         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4795
4796         bnx2_init_tx_context(bp, cid, txr);
4797 }
4798
4799 static void
4800 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4801                      int num_rings)
4802 {
4803         int i;
4804         struct rx_bd *rxbd;
4805
4806         for (i = 0; i < num_rings; i++) {
4807                 int j;
4808
4809                 rxbd = &rx_ring[i][0];
4810                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4811                         rxbd->rx_bd_len = buf_size;
4812                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4813                 }
4814                 if (i == (num_rings - 1))
4815                         j = 0;
4816                 else
4817                         j = i + 1;
4818                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4819                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4820         }
4821 }
4822
4823 static void
4824 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4825 {
4826         int i;
4827         u16 prod, ring_prod;
4828         u32 cid, rx_cid_addr, val;
4829         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4830         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4831
4832         if (ring_num == 0)
4833                 cid = RX_CID;
4834         else
4835                 cid = RX_RSS_CID + ring_num - 1;
4836
4837         rx_cid_addr = GET_CID_ADDR(cid);
4838
4839         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4840                              bp->rx_buf_use_size, bp->rx_max_ring);
4841
4842         bnx2_init_rx_context(bp, cid);
4843
4844         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4845                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4846                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4847         }
4848
4849         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4850         if (bp->rx_pg_ring_size) {
4851                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4852                                      rxr->rx_pg_desc_mapping,
4853                                      PAGE_SIZE, bp->rx_max_pg_ring);
4854                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4855                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4856                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4857                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4858
4859                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4860                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4861
4862                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4863                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4864
4865                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4866                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4867         }
4868
4869         val = (u64) rxr->rx_desc_mapping[0] >> 32;
4870         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4871
4872         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4873         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4874
4875         ring_prod = prod = rxr->rx_pg_prod;
4876         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4877                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4878                         break;
4879                 prod = NEXT_RX_BD(prod);
4880                 ring_prod = RX_PG_RING_IDX(prod);
4881         }
4882         rxr->rx_pg_prod = prod;
4883
4884         ring_prod = prod = rxr->rx_prod;
4885         for (i = 0; i < bp->rx_ring_size; i++) {
4886                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4887                         break;
4888                 prod = NEXT_RX_BD(prod);
4889                 ring_prod = RX_RING_IDX(prod);
4890         }
4891         rxr->rx_prod = prod;
4892
4893         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4894         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4895         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4896
4897         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4898         REG_WR16(bp, rxr->rx_bidx_addr, prod);
4899
4900         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4901 }
4902
4903 static void
4904 bnx2_init_all_rings(struct bnx2 *bp)
4905 {
4906         int i;
4907         u32 val;
4908
4909         bnx2_clear_ring_states(bp);
4910
4911         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4912         for (i = 0; i < bp->num_tx_rings; i++)
4913                 bnx2_init_tx_ring(bp, i);
4914
4915         if (bp->num_tx_rings > 1)
4916                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4917                        (TX_TSS_CID << 7));
4918
4919         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4920         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4921
4922         for (i = 0; i < bp->num_rx_rings; i++)
4923                 bnx2_init_rx_ring(bp, i);
4924
4925         if (bp->num_rx_rings > 1) {
4926                 u32 tbl_32;
4927                 u8 *tbl = (u8 *) &tbl_32;
4928
4929                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4930                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4931
4932                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4933                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
4934                         if ((i % 4) == 3)
4935                                 bnx2_reg_wr_ind(bp,
4936                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
4937                                                 cpu_to_be32(tbl_32));
4938                 }
4939
4940                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4941                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4942
4943                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4944
4945         }
4946 }
4947
4948 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4949 {
4950         u32 max, num_rings = 1;
4951
4952         while (ring_size > MAX_RX_DESC_CNT) {
4953                 ring_size -= MAX_RX_DESC_CNT;
4954                 num_rings++;
4955         }
4956         /* round to next power of 2 */
4957         max = max_size;
4958         while ((max & num_rings) == 0)
4959                 max >>= 1;
4960
4961         if (num_rings != max)
4962                 max <<= 1;
4963
4964         return max;
4965 }
4966
4967 static void
4968 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4969 {
4970         u32 rx_size, rx_space, jumbo_size;
4971
4972         /* 8 for CRC and VLAN */
4973         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4974
4975         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4976                 sizeof(struct skb_shared_info);
4977
4978         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4979         bp->rx_pg_ring_size = 0;
4980         bp->rx_max_pg_ring = 0;
4981         bp->rx_max_pg_ring_idx = 0;
4982         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4983                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4984
4985                 jumbo_size = size * pages;
4986                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4987                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4988
4989                 bp->rx_pg_ring_size = jumbo_size;
4990                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4991                                                         MAX_RX_PG_RINGS);
4992                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4993                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4994                 bp->rx_copy_thresh = 0;
4995         }
4996
4997         bp->rx_buf_use_size = rx_size;
4998         /* hw alignment */
4999         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5000         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5001         bp->rx_ring_size = size;
5002         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5003         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5004 }
5005
5006 static void
5007 bnx2_free_tx_skbs(struct bnx2 *bp)
5008 {
5009         int i;
5010
5011         for (i = 0; i < bp->num_tx_rings; i++) {
5012                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5013                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5014                 int j;
5015
5016                 if (txr->tx_buf_ring == NULL)
5017                         continue;
5018
5019                 for (j = 0; j < TX_DESC_CNT; ) {
5020                         struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5021                         struct sk_buff *skb = tx_buf->skb;
5022
5023                         if (skb == NULL) {
5024                                 j++;
5025                                 continue;
5026                         }
5027
5028                         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5029
5030                         tx_buf->skb = NULL;
5031
5032                         j += skb_shinfo(skb)->nr_frags + 1;
5033                         dev_kfree_skb(skb);
5034                 }
5035         }
5036 }
5037
5038 static void
5039 bnx2_free_rx_skbs(struct bnx2 *bp)
5040 {
5041         int i;
5042
5043         for (i = 0; i < bp->num_rx_rings; i++) {
5044                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5045                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5046                 int j;
5047
5048                 if (rxr->rx_buf_ring == NULL)
5049                         return;
5050
5051                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5052                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5053                         struct sk_buff *skb = rx_buf->skb;
5054
5055                         if (skb == NULL)
5056                                 continue;
5057
5058                         pci_unmap_single(bp->pdev,
5059                                          pci_unmap_addr(rx_buf, mapping),
5060                                          bp->rx_buf_use_size,
5061                                          PCI_DMA_FROMDEVICE);
5062
5063                         rx_buf->skb = NULL;
5064
5065                         dev_kfree_skb(skb);
5066                 }
5067                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5068                         bnx2_free_rx_page(bp, rxr, j);
5069         }
5070 }
5071
5072 static void
5073 bnx2_free_skbs(struct bnx2 *bp)
5074 {
5075         bnx2_free_tx_skbs(bp);
5076         bnx2_free_rx_skbs(bp);
5077 }
5078
5079 static int
5080 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5081 {
5082         int rc;
5083
5084         rc = bnx2_reset_chip(bp, reset_code);
5085         bnx2_free_skbs(bp);
5086         if (rc)
5087                 return rc;
5088
5089         if ((rc = bnx2_init_chip(bp)) != 0)
5090                 return rc;
5091
5092         bnx2_init_all_rings(bp);
5093         return 0;
5094 }
5095
5096 static int
5097 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5098 {
5099         int rc;
5100
5101         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5102                 return rc;
5103
5104         spin_lock_bh(&bp->phy_lock);
5105         bnx2_init_phy(bp, reset_phy);
5106         bnx2_set_link(bp);
5107         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5108                 bnx2_remote_phy_event(bp);
5109         spin_unlock_bh(&bp->phy_lock);
5110         return 0;
5111 }
5112
5113 static int
5114 bnx2_shutdown_chip(struct bnx2 *bp)
5115 {
5116         u32 reset_code;
5117
5118         if (bp->flags & BNX2_FLAG_NO_WOL)
5119                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5120         else if (bp->wol)
5121                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5122         else
5123                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5124
5125         return bnx2_reset_chip(bp, reset_code);
5126 }
5127
5128 static int
5129 bnx2_test_registers(struct bnx2 *bp)
5130 {
5131         int ret;
5132         int i, is_5709;
5133         static const struct {
5134                 u16   offset;
5135                 u16   flags;
5136 #define BNX2_FL_NOT_5709        1
5137                 u32   rw_mask;
5138                 u32   ro_mask;
5139         } reg_tbl[] = {
5140                 { 0x006c, 0, 0x00000000, 0x0000003f },
5141                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5142                 { 0x0094, 0, 0x00000000, 0x00000000 },
5143
5144                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5145                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5146                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5147                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5148                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5149                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5150                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5151                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5152                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5153
5154                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5155                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5156                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5157                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5158                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5159                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5160
5161                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5162                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5163                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5164
5165                 { 0x1000, 0, 0x00000000, 0x00000001 },
5166                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5167
5168                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5169                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5170                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5171                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5172                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5173                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5174                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5175                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5176                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5177                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5178
5179                 { 0x1800, 0, 0x00000000, 0x00000001 },
5180                 { 0x1804, 0, 0x00000000, 0x00000003 },
5181
5182                 { 0x2800, 0, 0x00000000, 0x00000001 },
5183                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5184                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5185                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5186                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5187                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5188                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5189                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5190                 { 0x2840, 0, 0x00000000, 0xffffffff },
5191                 { 0x2844, 0, 0x00000000, 0xffffffff },
5192                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5193                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5194
5195                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5196                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5197
5198                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5199                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5200                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5201                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5202                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5203                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5204                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5205                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5206                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5207
5208                 { 0x5004, 0, 0x00000000, 0x0000007f },
5209                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5210
5211                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5212                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5213                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5214                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5215                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5216                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5217                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5218                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5219                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5220
5221                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5222                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5223                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5224                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5225                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5226                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5227                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5228                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5229                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5230                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5231                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5232                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5233                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5234                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5235                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5236                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5237                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5238                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5239                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5240                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5241                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5242                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5243                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5244
5245                 { 0xffff, 0, 0x00000000, 0x00000000 },
5246         };
5247
5248         ret = 0;
5249         is_5709 = 0;
5250         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5251                 is_5709 = 1;
5252
5253         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5254                 u32 offset, rw_mask, ro_mask, save_val, val;
5255                 u16 flags = reg_tbl[i].flags;
5256
5257                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5258                         continue;
5259
5260                 offset = (u32) reg_tbl[i].offset;
5261                 rw_mask = reg_tbl[i].rw_mask;
5262                 ro_mask = reg_tbl[i].ro_mask;
5263
5264                 save_val = readl(bp->regview + offset);
5265
5266                 writel(0, bp->regview + offset);
5267
5268                 val = readl(bp->regview + offset);
5269                 if ((val & rw_mask) != 0) {
5270                         goto reg_test_err;
5271                 }
5272
5273                 if ((val & ro_mask) != (save_val & ro_mask)) {
5274                         goto reg_test_err;
5275                 }
5276
5277                 writel(0xffffffff, bp->regview + offset);
5278
5279                 val = readl(bp->regview + offset);
5280                 if ((val & rw_mask) != rw_mask) {
5281                         goto reg_test_err;
5282                 }
5283
5284                 if ((val & ro_mask) != (save_val & ro_mask)) {
5285                         goto reg_test_err;
5286                 }
5287
5288                 writel(save_val, bp->regview + offset);
5289                 continue;
5290
5291 reg_test_err:
5292                 writel(save_val, bp->regview + offset);
5293                 ret = -ENODEV;
5294                 break;
5295         }
5296         return ret;
5297 }
5298
5299 static int
5300 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5301 {
5302         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5303                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5304         int i;
5305
5306         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5307                 u32 offset;
5308
5309                 for (offset = 0; offset < size; offset += 4) {
5310
5311                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5312
5313                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5314                                 test_pattern[i]) {
5315                                 return -ENODEV;
5316                         }
5317                 }
5318         }
5319         return 0;
5320 }
5321
5322 static int
5323 bnx2_test_memory(struct bnx2 *bp)
5324 {
5325         int ret = 0;
5326         int i;
5327         static struct mem_entry {
5328                 u32   offset;
5329                 u32   len;
5330         } mem_tbl_5706[] = {
5331                 { 0x60000,  0x4000 },
5332                 { 0xa0000,  0x3000 },
5333                 { 0xe0000,  0x4000 },
5334                 { 0x120000, 0x4000 },
5335                 { 0x1a0000, 0x4000 },
5336                 { 0x160000, 0x4000 },
5337                 { 0xffffffff, 0    },
5338         },
5339         mem_tbl_5709[] = {
5340                 { 0x60000,  0x4000 },
5341                 { 0xa0000,  0x3000 },
5342                 { 0xe0000,  0x4000 },
5343                 { 0x120000, 0x4000 },
5344                 { 0x1a0000, 0x4000 },
5345                 { 0xffffffff, 0    },
5346         };
5347         struct mem_entry *mem_tbl;
5348
5349         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5350                 mem_tbl = mem_tbl_5709;
5351         else
5352                 mem_tbl = mem_tbl_5706;
5353
5354         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5355                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5356                         mem_tbl[i].len)) != 0) {
5357                         return ret;
5358                 }
5359         }
5360
5361         return ret;
5362 }
5363
5364 #define BNX2_MAC_LOOPBACK       0
5365 #define BNX2_PHY_LOOPBACK       1
5366
5367 static int
5368 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5369 {
5370         unsigned int pkt_size, num_pkts, i;
5371         struct sk_buff *skb, *rx_skb;
5372         unsigned char *packet;
5373         u16 rx_start_idx, rx_idx;
5374         dma_addr_t map;
5375         struct tx_bd *txbd;
5376         struct sw_bd *rx_buf;
5377         struct l2_fhdr *rx_hdr;
5378         int ret = -ENODEV;
5379         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5380         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5381         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5382
5383         tx_napi = bnapi;
5384
5385         txr = &tx_napi->tx_ring;
5386         rxr = &bnapi->rx_ring;
5387         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5388                 bp->loopback = MAC_LOOPBACK;
5389                 bnx2_set_mac_loopback(bp);
5390         }
5391         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5392                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5393                         return 0;
5394
5395                 bp->loopback = PHY_LOOPBACK;
5396                 bnx2_set_phy_loopback(bp);
5397         }
5398         else
5399                 return -EINVAL;
5400
5401         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5402         skb = netdev_alloc_skb(bp->dev, pkt_size);
5403         if (!skb)
5404                 return -ENOMEM;
5405         packet = skb_put(skb, pkt_size);
5406         memcpy(packet, bp->dev->dev_addr, 6);
5407         memset(packet + 6, 0x0, 8);
5408         for (i = 14; i < pkt_size; i++)
5409                 packet[i] = (unsigned char) (i & 0xff);
5410
5411         if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5412                 dev_kfree_skb(skb);
5413                 return -EIO;
5414         }
5415         map = skb_shinfo(skb)->dma_maps[0];
5416
5417         REG_WR(bp, BNX2_HC_COMMAND,
5418                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5419
5420         REG_RD(bp, BNX2_HC_COMMAND);
5421
5422         udelay(5);
5423         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5424
5425         num_pkts = 0;
5426
5427         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5428
5429         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5430         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5431         txbd->tx_bd_mss_nbytes = pkt_size;
5432         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5433
5434         num_pkts++;
5435         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5436         txr->tx_prod_bseq += pkt_size;
5437
5438         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5439         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5440
5441         udelay(100);
5442
5443         REG_WR(bp, BNX2_HC_COMMAND,
5444                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5445
5446         REG_RD(bp, BNX2_HC_COMMAND);
5447
5448         udelay(5);
5449
5450         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5451         dev_kfree_skb(skb);
5452
5453         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5454                 goto loopback_test_done;
5455
5456         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5457         if (rx_idx != rx_start_idx + num_pkts) {
5458                 goto loopback_test_done;
5459         }
5460
5461         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5462         rx_skb = rx_buf->skb;
5463
5464         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5465         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5466
5467         pci_dma_sync_single_for_cpu(bp->pdev,
5468                 pci_unmap_addr(rx_buf, mapping),
5469                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5470
5471         if (rx_hdr->l2_fhdr_status &
5472                 (L2_FHDR_ERRORS_BAD_CRC |
5473                 L2_FHDR_ERRORS_PHY_DECODE |
5474                 L2_FHDR_ERRORS_ALIGNMENT |
5475                 L2_FHDR_ERRORS_TOO_SHORT |
5476                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5477
5478                 goto loopback_test_done;
5479         }
5480
5481         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5482                 goto loopback_test_done;
5483         }
5484
5485         for (i = 14; i < pkt_size; i++) {
5486                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5487                         goto loopback_test_done;
5488                 }
5489         }
5490
5491         ret = 0;
5492
5493 loopback_test_done:
5494         bp->loopback = 0;
5495         return ret;
5496 }
5497
5498 #define BNX2_MAC_LOOPBACK_FAILED        1
5499 #define BNX2_PHY_LOOPBACK_FAILED        2
5500 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5501                                          BNX2_PHY_LOOPBACK_FAILED)
5502
5503 static int
5504 bnx2_test_loopback(struct bnx2 *bp)
5505 {
5506         int rc = 0;
5507
5508         if (!netif_running(bp->dev))
5509                 return BNX2_LOOPBACK_FAILED;
5510
5511         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5512         spin_lock_bh(&bp->phy_lock);
5513         bnx2_init_phy(bp, 1);
5514         spin_unlock_bh(&bp->phy_lock);
5515         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5516                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5517         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5518                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5519         return rc;
5520 }
5521
5522 #define NVRAM_SIZE 0x200
5523 #define CRC32_RESIDUAL 0xdebb20e3
5524
5525 static int
5526 bnx2_test_nvram(struct bnx2 *bp)
5527 {
5528         __be32 buf[NVRAM_SIZE / 4];
5529         u8 *data = (u8 *) buf;
5530         int rc = 0;
5531         u32 magic, csum;
5532
5533         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5534                 goto test_nvram_done;
5535
5536         magic = be32_to_cpu(buf[0]);
5537         if (magic != 0x669955aa) {
5538                 rc = -ENODEV;
5539                 goto test_nvram_done;
5540         }
5541
5542         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5543                 goto test_nvram_done;
5544
5545         csum = ether_crc_le(0x100, data);
5546         if (csum != CRC32_RESIDUAL) {
5547                 rc = -ENODEV;
5548                 goto test_nvram_done;
5549         }
5550
5551         csum = ether_crc_le(0x100, data + 0x100);
5552         if (csum != CRC32_RESIDUAL) {
5553                 rc = -ENODEV;
5554         }
5555
5556 test_nvram_done:
5557         return rc;
5558 }
5559
5560 static int
5561 bnx2_test_link(struct bnx2 *bp)
5562 {
5563         u32 bmsr;
5564
5565         if (!netif_running(bp->dev))
5566                 return -ENODEV;
5567
5568         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5569                 if (bp->link_up)
5570                         return 0;
5571                 return -ENODEV;
5572         }
5573         spin_lock_bh(&bp->phy_lock);
5574         bnx2_enable_bmsr1(bp);
5575         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5576         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5577         bnx2_disable_bmsr1(bp);
5578         spin_unlock_bh(&bp->phy_lock);
5579
5580         if (bmsr & BMSR_LSTATUS) {
5581                 return 0;
5582         }
5583         return -ENODEV;
5584 }
5585
5586 static int
5587 bnx2_test_intr(struct bnx2 *bp)
5588 {
5589         int i;
5590         u16 status_idx;
5591
5592         if (!netif_running(bp->dev))
5593                 return -ENODEV;
5594
5595         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5596
5597         /* This register is not touched during run-time. */
5598         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5599         REG_RD(bp, BNX2_HC_COMMAND);
5600
5601         for (i = 0; i < 10; i++) {
5602                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5603                         status_idx) {
5604
5605                         break;
5606                 }
5607
5608                 msleep_interruptible(10);
5609         }
5610         if (i < 10)
5611                 return 0;
5612
5613         return -ENODEV;
5614 }
5615
5616 /* Determining link for parallel detection. */
5617 static int
5618 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5619 {
5620         u32 mode_ctl, an_dbg, exp;
5621
5622         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5623                 return 0;
5624
5625         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5626         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5627
5628         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5629                 return 0;
5630
5631         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5632         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5633         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5634
5635         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5636                 return 0;
5637
5638         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5639         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5640         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5641
5642         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5643                 return 0;
5644
5645         return 1;
5646 }
5647
5648 static void
5649 bnx2_5706_serdes_timer(struct bnx2 *bp)
5650 {
5651         int check_link = 1;
5652
5653         spin_lock(&bp->phy_lock);
5654         if (bp->serdes_an_pending) {
5655                 bp->serdes_an_pending--;
5656                 check_link = 0;
5657         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5658                 u32 bmcr;
5659
5660                 bp->current_interval = BNX2_TIMER_INTERVAL;
5661
5662                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5663
5664                 if (bmcr & BMCR_ANENABLE) {
5665                         if (bnx2_5706_serdes_has_link(bp)) {
5666                                 bmcr &= ~BMCR_ANENABLE;
5667                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5668                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5669                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5670                         }
5671                 }
5672         }
5673         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5674                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5675                 u32 phy2;
5676
5677                 bnx2_write_phy(bp, 0x17, 0x0f01);
5678                 bnx2_read_phy(bp, 0x15, &phy2);
5679                 if (phy2 & 0x20) {
5680                         u32 bmcr;
5681
5682                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5683                         bmcr |= BMCR_ANENABLE;
5684                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5685
5686                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5687                 }
5688         } else
5689                 bp->current_interval = BNX2_TIMER_INTERVAL;
5690
5691         if (check_link) {
5692                 u32 val;
5693
5694                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5695                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5696                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5697
5698                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5699                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5700                                 bnx2_5706s_force_link_dn(bp, 1);
5701                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5702                         } else
5703                                 bnx2_set_link(bp);
5704                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5705                         bnx2_set_link(bp);
5706         }
5707         spin_unlock(&bp->phy_lock);
5708 }
5709
5710 static void
5711 bnx2_5708_serdes_timer(struct bnx2 *bp)
5712 {
5713         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5714                 return;
5715
5716         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5717                 bp->serdes_an_pending = 0;
5718                 return;
5719         }
5720
5721         spin_lock(&bp->phy_lock);
5722         if (bp->serdes_an_pending)
5723                 bp->serdes_an_pending--;
5724         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5725                 u32 bmcr;
5726
5727                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5728                 if (bmcr & BMCR_ANENABLE) {
5729                         bnx2_enable_forced_2g5(bp);
5730                         bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5731                 } else {
5732                         bnx2_disable_forced_2g5(bp);
5733                         bp->serdes_an_pending = 2;
5734                         bp->current_interval = BNX2_TIMER_INTERVAL;
5735                 }
5736
5737         } else
5738                 bp->current_interval = BNX2_TIMER_INTERVAL;
5739
5740         spin_unlock(&bp->phy_lock);
5741 }
5742
5743 static void
5744 bnx2_timer(unsigned long data)
5745 {
5746         struct bnx2 *bp = (struct bnx2 *) data;
5747
5748         if (!netif_running(bp->dev))
5749                 return;
5750
5751         if (atomic_read(&bp->intr_sem) != 0)
5752                 goto bnx2_restart_timer;
5753
5754         if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
5755              BNX2_FLAG_USING_MSI)
5756                 bnx2_chk_missed_msi(bp);
5757
5758         bnx2_send_heart_beat(bp);
5759
5760         bp->stats_blk->stat_FwRxDrop =
5761                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5762
5763         /* workaround occasional corrupted counters */
5764         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5765                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5766                                             BNX2_HC_COMMAND_STATS_NOW);
5767
5768         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5769                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5770                         bnx2_5706_serdes_timer(bp);
5771                 else
5772                         bnx2_5708_serdes_timer(bp);
5773         }
5774
5775 bnx2_restart_timer:
5776         mod_timer(&bp->timer, jiffies + bp->current_interval);
5777 }
5778
5779 static int
5780 bnx2_request_irq(struct bnx2 *bp)
5781 {
5782         unsigned long flags;
5783         struct bnx2_irq *irq;
5784         int rc = 0, i;
5785
5786         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5787                 flags = 0;
5788         else
5789                 flags = IRQF_SHARED;
5790
5791         for (i = 0; i < bp->irq_nvecs; i++) {
5792                 irq = &bp->irq_tbl[i];
5793                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5794                                  &bp->bnx2_napi[i]);
5795                 if (rc)
5796                         break;
5797                 irq->requested = 1;
5798         }
5799         return rc;
5800 }
5801
5802 static void
5803 bnx2_free_irq(struct bnx2 *bp)
5804 {
5805         struct bnx2_irq *irq;
5806         int i;
5807
5808         for (i = 0; i < bp->irq_nvecs; i++) {
5809                 irq = &bp->irq_tbl[i];
5810                 if (irq->requested)
5811                         free_irq(irq->vector, &bp->bnx2_napi[i]);
5812                 irq->requested = 0;
5813         }
5814         if (bp->flags & BNX2_FLAG_USING_MSI)
5815                 pci_disable_msi(bp->pdev);
5816         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5817                 pci_disable_msix(bp->pdev);
5818
5819         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5820 }
5821
5822 static void
5823 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5824 {
5825         int i, rc;
5826         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5827         struct net_device *dev = bp->dev;
5828         const int len = sizeof(bp->irq_tbl[0].name);
5829
5830         bnx2_setup_msix_tbl(bp);
5831         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5832         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5833         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5834
5835         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5836                 msix_ent[i].entry = i;
5837                 msix_ent[i].vector = 0;
5838
5839                 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
5840                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5841         }
5842
5843         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5844         if (rc != 0)
5845                 return;
5846
5847         bp->irq_nvecs = msix_vecs;
5848         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5849         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5850                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5851 }
5852
5853 static void
5854 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5855 {
5856         int cpus = num_online_cpus();
5857         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5858
5859         bp->irq_tbl[0].handler = bnx2_interrupt;
5860         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5861         bp->irq_nvecs = 1;
5862         bp->irq_tbl[0].vector = bp->pdev->irq;
5863
5864         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5865                 bnx2_enable_msix(bp, msix_vecs);
5866
5867         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5868             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5869                 if (pci_enable_msi(bp->pdev) == 0) {
5870                         bp->flags |= BNX2_FLAG_USING_MSI;
5871                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5872                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5873                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5874                         } else
5875                                 bp->irq_tbl[0].handler = bnx2_msi;
5876
5877                         bp->irq_tbl[0].vector = bp->pdev->irq;
5878                 }
5879         }
5880
5881         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5882         bp->dev->real_num_tx_queues = bp->num_tx_rings;
5883
5884         bp->num_rx_rings = bp->irq_nvecs;
5885 }
5886
5887 /* Called with rtnl_lock */
5888 static int
5889 bnx2_open(struct net_device *dev)
5890 {
5891         struct bnx2 *bp = netdev_priv(dev);
5892         int rc;
5893
5894         netif_carrier_off(dev);
5895
5896         bnx2_set_power_state(bp, PCI_D0);
5897         bnx2_disable_int(bp);
5898
5899         bnx2_setup_int_mode(bp, disable_msi);
5900         bnx2_napi_enable(bp);
5901         rc = bnx2_alloc_mem(bp);
5902         if (rc)
5903                 goto open_err;
5904
5905         rc = bnx2_request_irq(bp);
5906         if (rc)
5907                 goto open_err;
5908
5909         rc = bnx2_init_nic(bp, 1);
5910         if (rc)
5911                 goto open_err;
5912
5913         mod_timer(&bp->timer, jiffies + bp->current_interval);
5914
5915         atomic_set(&bp->intr_sem, 0);
5916
5917         bnx2_enable_int(bp);
5918
5919         if (bp->flags & BNX2_FLAG_USING_MSI) {
5920                 /* Test MSI to make sure it is working
5921                  * If MSI test fails, go back to INTx mode
5922                  */
5923                 if (bnx2_test_intr(bp) != 0) {
5924                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5925                                " using MSI, switching to INTx mode. Please"
5926                                " report this failure to the PCI maintainer"
5927                                " and include system chipset information.\n",
5928                                bp->dev->name);
5929
5930                         bnx2_disable_int(bp);
5931                         bnx2_free_irq(bp);
5932
5933                         bnx2_setup_int_mode(bp, 1);
5934
5935                         rc = bnx2_init_nic(bp, 0);
5936
5937                         if (!rc)
5938                                 rc = bnx2_request_irq(bp);
5939
5940                         if (rc) {
5941                                 del_timer_sync(&bp->timer);
5942                                 goto open_err;
5943                         }
5944                         bnx2_enable_int(bp);
5945                 }
5946         }
5947         if (bp->flags & BNX2_FLAG_USING_MSI)
5948                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5949         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5950                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5951
5952         netif_tx_start_all_queues(dev);
5953
5954         return 0;
5955
5956 open_err:
5957         bnx2_napi_disable(bp);
5958         bnx2_free_skbs(bp);
5959         bnx2_free_irq(bp);
5960         bnx2_free_mem(bp);
5961         return rc;
5962 }
5963
5964 static void
5965 bnx2_reset_task(struct work_struct *work)
5966 {
5967         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5968
5969         if (!netif_running(bp->dev))
5970                 return;
5971
5972         bnx2_netif_stop(bp);
5973
5974         bnx2_init_nic(bp, 1);
5975
5976         atomic_set(&bp->intr_sem, 1);
5977         bnx2_netif_start(bp);
5978 }
5979
5980 static void
5981 bnx2_tx_timeout(struct net_device *dev)
5982 {
5983         struct bnx2 *bp = netdev_priv(dev);
5984
5985         /* This allows the netif to be shutdown gracefully before resetting */
5986         schedule_work(&bp->reset_task);
5987 }
5988
5989 #ifdef BCM_VLAN
5990 /* Called with rtnl_lock */
5991 static void
5992 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5993 {
5994         struct bnx2 *bp = netdev_priv(dev);
5995
5996         bnx2_netif_stop(bp);
5997
5998         bp->vlgrp = vlgrp;
5999         bnx2_set_rx_mode(dev);
6000         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6001                 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6002
6003         bnx2_netif_start(bp);
6004 }
6005 #endif
6006
6007 /* Called with netif_tx_lock.
6008  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6009  * netif_wake_queue().
6010  */
6011 static int
6012 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6013 {
6014         struct bnx2 *bp = netdev_priv(dev);
6015         dma_addr_t mapping;
6016         struct tx_bd *txbd;
6017         struct sw_tx_bd *tx_buf;
6018         u32 len, vlan_tag_flags, last_frag, mss;
6019         u16 prod, ring_prod;
6020         int i;
6021         struct bnx2_napi *bnapi;
6022         struct bnx2_tx_ring_info *txr;
6023         struct netdev_queue *txq;
6024         struct skb_shared_info *sp;
6025
6026         /*  Determine which tx ring we will be placed on */
6027         i = skb_get_queue_mapping(skb);
6028         bnapi = &bp->bnx2_napi[i];
6029         txr = &bnapi->tx_ring;
6030         txq = netdev_get_tx_queue(dev, i);
6031
6032         if (unlikely(bnx2_tx_avail(bp, txr) <
6033             (skb_shinfo(skb)->nr_frags + 1))) {
6034                 netif_tx_stop_queue(txq);
6035                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6036                         dev->name);
6037
6038                 return NETDEV_TX_BUSY;
6039         }
6040         len = skb_headlen(skb);
6041         prod = txr->tx_prod;
6042         ring_prod = TX_RING_IDX(prod);
6043
6044         vlan_tag_flags = 0;
6045         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6046                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6047         }
6048
6049 #ifdef BCM_VLAN
6050         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6051                 vlan_tag_flags |=
6052                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6053         }
6054 #endif
6055         if ((mss = skb_shinfo(skb)->gso_size)) {
6056                 u32 tcp_opt_len;
6057                 struct iphdr *iph;
6058
6059                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6060
6061                 tcp_opt_len = tcp_optlen(skb);
6062
6063                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6064                         u32 tcp_off = skb_transport_offset(skb) -
6065                                       sizeof(struct ipv6hdr) - ETH_HLEN;
6066
6067                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6068                                           TX_BD_FLAGS_SW_FLAGS;
6069                         if (likely(tcp_off == 0))
6070                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6071                         else {
6072                                 tcp_off >>= 3;
6073                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
6074                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
6075                                                   ((tcp_off & 0x10) <<
6076                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
6077                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6078                         }
6079                 } else {
6080                         iph = ip_hdr(skb);
6081                         if (tcp_opt_len || (iph->ihl > 5)) {
6082                                 vlan_tag_flags |= ((iph->ihl - 5) +
6083                                                    (tcp_opt_len >> 2)) << 8;
6084                         }
6085                 }
6086         } else
6087                 mss = 0;
6088
6089         if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6090                 dev_kfree_skb(skb);
6091                 return NETDEV_TX_OK;
6092         }
6093
6094         sp = skb_shinfo(skb);
6095         mapping = sp->dma_maps[0];
6096
6097         tx_buf = &txr->tx_buf_ring[ring_prod];
6098         tx_buf->skb = skb;
6099
6100         txbd = &txr->tx_desc_ring[ring_prod];
6101
6102         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6103         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6104         txbd->tx_bd_mss_nbytes = len | (mss << 16);
6105         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6106
6107         last_frag = skb_shinfo(skb)->nr_frags;
6108
6109         for (i = 0; i < last_frag; i++) {
6110                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6111
6112                 prod = NEXT_TX_BD(prod);
6113                 ring_prod = TX_RING_IDX(prod);
6114                 txbd = &txr->tx_desc_ring[ring_prod];
6115
6116                 len = frag->size;
6117                 mapping = sp->dma_maps[i + 1];
6118
6119                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6120                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6121                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6122                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6123
6124         }
6125         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6126
6127         prod = NEXT_TX_BD(prod);
6128         txr->tx_prod_bseq += skb->len;
6129
6130         REG_WR16(bp, txr->tx_bidx_addr, prod);
6131         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6132
6133         mmiowb();
6134
6135         txr->tx_prod = prod;
6136         dev->trans_start = jiffies;
6137
6138         if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6139                 netif_tx_stop_queue(txq);
6140                 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6141                         netif_tx_wake_queue(txq);
6142         }
6143
6144         return NETDEV_TX_OK;
6145 }
6146
6147 /* Called with rtnl_lock */
6148 static int
6149 bnx2_close(struct net_device *dev)
6150 {
6151         struct bnx2 *bp = netdev_priv(dev);
6152
6153         cancel_work_sync(&bp->reset_task);
6154
6155         bnx2_disable_int_sync(bp);
6156         bnx2_napi_disable(bp);
6157         del_timer_sync(&bp->timer);
6158         bnx2_shutdown_chip(bp);
6159         bnx2_free_irq(bp);
6160         bnx2_free_skbs(bp);
6161         bnx2_free_mem(bp);
6162         bp->link_up = 0;
6163         netif_carrier_off(bp->dev);
6164         bnx2_set_power_state(bp, PCI_D3hot);
6165         return 0;
6166 }
6167
6168 #define GET_NET_STATS64(ctr)                                    \
6169         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
6170         (unsigned long) (ctr##_lo)
6171
6172 #define GET_NET_STATS32(ctr)            \
6173         (ctr##_lo)
6174
6175 #if (BITS_PER_LONG == 64)
6176 #define GET_NET_STATS   GET_NET_STATS64
6177 #else
6178 #define GET_NET_STATS   GET_NET_STATS32
6179 #endif
6180
6181 static struct net_device_stats *
6182 bnx2_get_stats(struct net_device *dev)
6183 {
6184         struct bnx2 *bp = netdev_priv(dev);
6185         struct statistics_block *stats_blk = bp->stats_blk;
6186         struct net_device_stats *net_stats = &dev->stats;
6187
6188         if (bp->stats_blk == NULL) {
6189                 return net_stats;
6190         }
6191         net_stats->rx_packets =
6192                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6193                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6194                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6195
6196         net_stats->tx_packets =
6197                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6198                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6199                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6200
6201         net_stats->rx_bytes =
6202                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6203
6204         net_stats->tx_bytes =
6205                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6206
6207         net_stats->multicast =
6208                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6209
6210         net_stats->collisions =
6211                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6212
6213         net_stats->rx_length_errors =
6214                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6215                 stats_blk->stat_EtherStatsOverrsizePkts);
6216
6217         net_stats->rx_over_errors =
6218                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6219
6220         net_stats->rx_frame_errors =
6221                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6222
6223         net_stats->rx_crc_errors =
6224                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6225
6226         net_stats->rx_errors = net_stats->rx_length_errors +
6227                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6228                 net_stats->rx_crc_errors;
6229
6230         net_stats->tx_aborted_errors =
6231                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6232                 stats_blk->stat_Dot3StatsLateCollisions);
6233
6234         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6235             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6236                 net_stats->tx_carrier_errors = 0;
6237         else {
6238                 net_stats->tx_carrier_errors =
6239                         (unsigned long)
6240                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6241         }
6242
6243         net_stats->tx_errors =
6244                 (unsigned long)
6245                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6246                 +
6247                 net_stats->tx_aborted_errors +
6248                 net_stats->tx_carrier_errors;
6249
6250         net_stats->rx_missed_errors =
6251                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6252                 stats_blk->stat_FwRxDrop);
6253
6254         return net_stats;
6255 }
6256
6257 /* All ethtool functions called with rtnl_lock */
6258
6259 static int
6260 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6261 {
6262         struct bnx2 *bp = netdev_priv(dev);
6263         int support_serdes = 0, support_copper = 0;
6264
6265         cmd->supported = SUPPORTED_Autoneg;
6266         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6267                 support_serdes = 1;
6268                 support_copper = 1;
6269         } else if (bp->phy_port == PORT_FIBRE)
6270                 support_serdes = 1;
6271         else
6272                 support_copper = 1;
6273
6274         if (support_serdes) {
6275                 cmd->supported |= SUPPORTED_1000baseT_Full |
6276                         SUPPORTED_FIBRE;
6277                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6278                         cmd->supported |= SUPPORTED_2500baseX_Full;
6279
6280         }
6281         if (support_copper) {
6282                 cmd->supported |= SUPPORTED_10baseT_Half |
6283                         SUPPORTED_10baseT_Full |
6284                         SUPPORTED_100baseT_Half |
6285                         SUPPORTED_100baseT_Full |
6286                         SUPPORTED_1000baseT_Full |
6287                         SUPPORTED_TP;
6288
6289         }
6290
6291         spin_lock_bh(&bp->phy_lock);
6292         cmd->port = bp->phy_port;
6293         cmd->advertising = bp->advertising;
6294
6295         if (bp->autoneg & AUTONEG_SPEED) {
6296                 cmd->autoneg = AUTONEG_ENABLE;
6297         }
6298         else {
6299                 cmd->autoneg = AUTONEG_DISABLE;
6300         }
6301
6302         if (netif_carrier_ok(dev)) {
6303                 cmd->speed = bp->line_speed;
6304                 cmd->duplex = bp->duplex;
6305         }
6306         else {
6307                 cmd->speed = -1;
6308                 cmd->duplex = -1;
6309         }
6310         spin_unlock_bh(&bp->phy_lock);
6311
6312         cmd->transceiver = XCVR_INTERNAL;
6313         cmd->phy_address = bp->phy_addr;
6314
6315         return 0;
6316 }
6317
6318 static int
6319 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6320 {
6321         struct bnx2 *bp = netdev_priv(dev);
6322         u8 autoneg = bp->autoneg;
6323         u8 req_duplex = bp->req_duplex;
6324         u16 req_line_speed = bp->req_line_speed;
6325         u32 advertising = bp->advertising;
6326         int err = -EINVAL;
6327
6328         spin_lock_bh(&bp->phy_lock);
6329
6330         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6331                 goto err_out_unlock;
6332
6333         if (cmd->port != bp->phy_port &&
6334             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6335                 goto err_out_unlock;
6336
6337         /* If device is down, we can store the settings only if the user
6338          * is setting the currently active port.
6339          */
6340         if (!netif_running(dev) && cmd->port != bp->phy_port)
6341                 goto err_out_unlock;
6342
6343         if (cmd->autoneg == AUTONEG_ENABLE) {
6344                 autoneg |= AUTONEG_SPEED;
6345
6346                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6347
6348                 /* allow advertising 1 speed */
6349                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6350                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6351                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6352                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6353
6354                         if (cmd->port == PORT_FIBRE)
6355                                 goto err_out_unlock;
6356
6357                         advertising = cmd->advertising;
6358
6359                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6360                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6361                             (cmd->port == PORT_TP))
6362                                 goto err_out_unlock;
6363                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6364                         advertising = cmd->advertising;
6365                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6366                         goto err_out_unlock;
6367                 else {
6368                         if (cmd->port == PORT_FIBRE)
6369                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6370                         else
6371                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6372                 }
6373                 advertising |= ADVERTISED_Autoneg;
6374         }
6375         else {
6376                 if (cmd->port == PORT_FIBRE) {
6377                         if ((cmd->speed != SPEED_1000 &&
6378                              cmd->speed != SPEED_2500) ||
6379                             (cmd->duplex != DUPLEX_FULL))
6380                                 goto err_out_unlock;
6381
6382                         if (cmd->speed == SPEED_2500 &&
6383                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6384                                 goto err_out_unlock;
6385                 }
6386                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6387                         goto err_out_unlock;
6388
6389                 autoneg &= ~AUTONEG_SPEED;
6390                 req_line_speed = cmd->speed;
6391                 req_duplex = cmd->duplex;
6392                 advertising = 0;
6393         }
6394
6395         bp->autoneg = autoneg;
6396         bp->advertising = advertising;
6397         bp->req_line_speed = req_line_speed;
6398         bp->req_duplex = req_duplex;
6399
6400         err = 0;
6401         /* If device is down, the new settings will be picked up when it is
6402          * brought up.
6403          */
6404         if (netif_running(dev))
6405                 err = bnx2_setup_phy(bp, cmd->port);
6406
6407 err_out_unlock:
6408         spin_unlock_bh(&bp->phy_lock);
6409
6410         return err;
6411 }
6412
6413 static void
6414 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6415 {
6416         struct bnx2 *bp = netdev_priv(dev);
6417
6418         strcpy(info->driver, DRV_MODULE_NAME);
6419         strcpy(info->version, DRV_MODULE_VERSION);
6420         strcpy(info->bus_info, pci_name(bp->pdev));
6421         strcpy(info->fw_version, bp->fw_version);
6422 }
6423
6424 #define BNX2_REGDUMP_LEN                (32 * 1024)
6425
6426 static int
6427 bnx2_get_regs_len(struct net_device *dev)
6428 {
6429         return BNX2_REGDUMP_LEN;
6430 }
6431
6432 static void
6433 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6434 {
6435         u32 *p = _p, i, offset;
6436         u8 *orig_p = _p;
6437         struct bnx2 *bp = netdev_priv(dev);
6438         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6439                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6440                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6441                                  0x1040, 0x1048, 0x1080, 0x10a4,
6442                                  0x1400, 0x1490, 0x1498, 0x14f0,
6443                                  0x1500, 0x155c, 0x1580, 0x15dc,
6444                                  0x1600, 0x1658, 0x1680, 0x16d8,
6445                                  0x1800, 0x1820, 0x1840, 0x1854,
6446                                  0x1880, 0x1894, 0x1900, 0x1984,
6447                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6448                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6449                                  0x2000, 0x2030, 0x23c0, 0x2400,
6450                                  0x2800, 0x2820, 0x2830, 0x2850,
6451                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6452                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6453                                  0x4080, 0x4090, 0x43c0, 0x4458,
6454                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6455                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6456                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6457                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6458                                  0x6800, 0x6848, 0x684c, 0x6860,
6459                                  0x6888, 0x6910, 0x8000 };
6460
6461         regs->version = 0;
6462
6463         memset(p, 0, BNX2_REGDUMP_LEN);
6464
6465         if (!netif_running(bp->dev))
6466                 return;
6467
6468         i = 0;
6469         offset = reg_boundaries[0];
6470         p += offset;
6471         while (offset < BNX2_REGDUMP_LEN) {
6472                 *p++ = REG_RD(bp, offset);
6473                 offset += 4;
6474                 if (offset == reg_boundaries[i + 1]) {
6475                         offset = reg_boundaries[i + 2];
6476                         p = (u32 *) (orig_p + offset);
6477                         i += 2;
6478                 }
6479         }
6480 }
6481
6482 static void
6483 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6484 {
6485         struct bnx2 *bp = netdev_priv(dev);
6486
6487         if (bp->flags & BNX2_FLAG_NO_WOL) {
6488                 wol->supported = 0;
6489                 wol->wolopts = 0;
6490         }
6491         else {
6492                 wol->supported = WAKE_MAGIC;
6493                 if (bp->wol)
6494                         wol->wolopts = WAKE_MAGIC;
6495                 else
6496                         wol->wolopts = 0;
6497         }
6498         memset(&wol->sopass, 0, sizeof(wol->sopass));
6499 }
6500
6501 static int
6502 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6503 {
6504         struct bnx2 *bp = netdev_priv(dev);
6505
6506         if (wol->wolopts & ~WAKE_MAGIC)
6507                 return -EINVAL;
6508
6509         if (wol->wolopts & WAKE_MAGIC) {
6510                 if (bp->flags & BNX2_FLAG_NO_WOL)
6511                         return -EINVAL;
6512
6513                 bp->wol = 1;
6514         }
6515         else {
6516                 bp->wol = 0;
6517         }
6518         return 0;
6519 }
6520
6521 static int
6522 bnx2_nway_reset(struct net_device *dev)
6523 {
6524         struct bnx2 *bp = netdev_priv(dev);
6525         u32 bmcr;
6526
6527         if (!netif_running(dev))
6528                 return -EAGAIN;
6529
6530         if (!(bp->autoneg & AUTONEG_SPEED)) {
6531                 return -EINVAL;
6532         }
6533
6534         spin_lock_bh(&bp->phy_lock);
6535
6536         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6537                 int rc;
6538
6539                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6540                 spin_unlock_bh(&bp->phy_lock);
6541                 return rc;
6542         }
6543
6544         /* Force a link down visible on the other side */
6545         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6546                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6547                 spin_unlock_bh(&bp->phy_lock);
6548
6549                 msleep(20);
6550
6551                 spin_lock_bh(&bp->phy_lock);
6552
6553                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6554                 bp->serdes_an_pending = 1;
6555                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6556         }
6557
6558         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6559         bmcr &= ~BMCR_LOOPBACK;
6560         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6561
6562         spin_unlock_bh(&bp->phy_lock);
6563
6564         return 0;
6565 }
6566
6567 static int
6568 bnx2_get_eeprom_len(struct net_device *dev)
6569 {
6570         struct bnx2 *bp = netdev_priv(dev);
6571
6572         if (bp->flash_info == NULL)
6573                 return 0;
6574
6575         return (int) bp->flash_size;
6576 }
6577
6578 static int
6579 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6580                 u8 *eebuf)
6581 {
6582         struct bnx2 *bp = netdev_priv(dev);
6583         int rc;
6584
6585         if (!netif_running(dev))
6586                 return -EAGAIN;
6587
6588         /* parameters already validated in ethtool_get_eeprom */
6589
6590         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6591
6592         return rc;
6593 }
6594
6595 static int
6596 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6597                 u8 *eebuf)
6598 {
6599         struct bnx2 *bp = netdev_priv(dev);
6600         int rc;
6601
6602         if (!netif_running(dev))
6603                 return -EAGAIN;
6604
6605         /* parameters already validated in ethtool_set_eeprom */
6606
6607         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6608
6609         return rc;
6610 }
6611
6612 static int
6613 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6614 {
6615         struct bnx2 *bp = netdev_priv(dev);
6616
6617         memset(coal, 0, sizeof(struct ethtool_coalesce));
6618
6619         coal->rx_coalesce_usecs = bp->rx_ticks;
6620         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6621         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6622         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6623
6624         coal->tx_coalesce_usecs = bp->tx_ticks;
6625         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6626         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6627         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6628
6629         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6630
6631         return 0;
6632 }
6633
6634 static int
6635 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6636 {
6637         struct bnx2 *bp = netdev_priv(dev);
6638
6639         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6640         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6641
6642         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6643         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6644
6645         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6646         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6647
6648         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6649         if (bp->rx_quick_cons_trip_int > 0xff)
6650                 bp->rx_quick_cons_trip_int = 0xff;
6651
6652         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6653         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6654
6655         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6656         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6657
6658         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6659         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6660
6661         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6662         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6663                 0xff;
6664
6665         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6666         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6667                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6668                         bp->stats_ticks = USEC_PER_SEC;
6669         }
6670         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6671                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6672         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6673
6674         if (netif_running(bp->dev)) {
6675                 bnx2_netif_stop(bp);
6676                 bnx2_init_nic(bp, 0);
6677                 bnx2_netif_start(bp);
6678         }
6679
6680         return 0;
6681 }
6682
6683 static void
6684 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6685 {
6686         struct bnx2 *bp = netdev_priv(dev);
6687
6688         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6689         ering->rx_mini_max_pending = 0;
6690         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6691
6692         ering->rx_pending = bp->rx_ring_size;
6693         ering->rx_mini_pending = 0;
6694         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6695
6696         ering->tx_max_pending = MAX_TX_DESC_CNT;
6697         ering->tx_pending = bp->tx_ring_size;
6698 }
6699
6700 static int
6701 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6702 {
6703         if (netif_running(bp->dev)) {
6704                 bnx2_netif_stop(bp);
6705                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6706                 bnx2_free_skbs(bp);
6707                 bnx2_free_mem(bp);
6708         }
6709
6710         bnx2_set_rx_ring_size(bp, rx);
6711         bp->tx_ring_size = tx;
6712
6713         if (netif_running(bp->dev)) {
6714                 int rc;
6715
6716                 rc = bnx2_alloc_mem(bp);
6717                 if (rc)
6718                         return rc;
6719                 bnx2_init_nic(bp, 0);
6720                 bnx2_netif_start(bp);
6721         }
6722         return 0;
6723 }
6724
6725 static int
6726 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6727 {
6728         struct bnx2 *bp = netdev_priv(dev);
6729         int rc;
6730
6731         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6732                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6733                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6734
6735                 return -EINVAL;
6736         }
6737         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6738         return rc;
6739 }
6740
6741 static void
6742 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6743 {
6744         struct bnx2 *bp = netdev_priv(dev);
6745
6746         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6747         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6748         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6749 }
6750
6751 static int
6752 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6753 {
6754         struct bnx2 *bp = netdev_priv(dev);
6755
6756         bp->req_flow_ctrl = 0;
6757         if (epause->rx_pause)
6758                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6759         if (epause->tx_pause)
6760                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6761
6762         if (epause->autoneg) {
6763                 bp->autoneg |= AUTONEG_FLOW_CTRL;
6764         }
6765         else {
6766                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6767         }
6768
6769         if (netif_running(dev)) {
6770                 spin_lock_bh(&bp->phy_lock);
6771                 bnx2_setup_phy(bp, bp->phy_port);
6772                 spin_unlock_bh(&bp->phy_lock);
6773         }
6774
6775         return 0;
6776 }
6777
6778 static u32
6779 bnx2_get_rx_csum(struct net_device *dev)
6780 {
6781         struct bnx2 *bp = netdev_priv(dev);
6782
6783         return bp->rx_csum;
6784 }
6785
6786 static int
6787 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6788 {
6789         struct bnx2 *bp = netdev_priv(dev);
6790
6791         bp->rx_csum = data;
6792         return 0;
6793 }
6794
6795 static int
6796 bnx2_set_tso(struct net_device *dev, u32 data)
6797 {
6798         struct bnx2 *bp = netdev_priv(dev);
6799
6800         if (data) {
6801                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6802                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6803                         dev->features |= NETIF_F_TSO6;
6804         } else
6805                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6806                                    NETIF_F_TSO_ECN);
6807         return 0;
6808 }
6809
6810 #define BNX2_NUM_STATS 46
6811
6812 static struct {
6813         char string[ETH_GSTRING_LEN];
6814 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6815         { "rx_bytes" },
6816         { "rx_error_bytes" },
6817         { "tx_bytes" },
6818         { "tx_error_bytes" },
6819         { "rx_ucast_packets" },
6820         { "rx_mcast_packets" },
6821         { "rx_bcast_packets" },
6822         { "tx_ucast_packets" },
6823         { "tx_mcast_packets" },
6824         { "tx_bcast_packets" },
6825         { "tx_mac_errors" },
6826         { "tx_carrier_errors" },
6827         { "rx_crc_errors" },
6828         { "rx_align_errors" },
6829         { "tx_single_collisions" },
6830         { "tx_multi_collisions" },
6831         { "tx_deferred" },
6832         { "tx_excess_collisions" },
6833         { "tx_late_collisions" },
6834         { "tx_total_collisions" },
6835         { "rx_fragments" },
6836         { "rx_jabbers" },
6837         { "rx_undersize_packets" },
6838         { "rx_oversize_packets" },
6839         { "rx_64_byte_packets" },
6840         { "rx_65_to_127_byte_packets" },
6841         { "rx_128_to_255_byte_packets" },
6842         { "rx_256_to_511_byte_packets" },
6843         { "rx_512_to_1023_byte_packets" },
6844         { "rx_1024_to_1522_byte_packets" },
6845         { "rx_1523_to_9022_byte_packets" },
6846         { "tx_64_byte_packets" },
6847         { "tx_65_to_127_byte_packets" },
6848         { "tx_128_to_255_byte_packets" },
6849         { "tx_256_to_511_byte_packets" },
6850         { "tx_512_to_1023_byte_packets" },
6851         { "tx_1024_to_1522_byte_packets" },
6852         { "tx_1523_to_9022_byte_packets" },
6853         { "rx_xon_frames" },
6854         { "rx_xoff_frames" },
6855         { "tx_xon_frames" },
6856         { "tx_xoff_frames" },
6857         { "rx_mac_ctrl_frames" },
6858         { "rx_filtered_packets" },
6859         { "rx_discards" },
6860         { "rx_fw_discards" },
6861 };
6862
6863 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6864
6865 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6866     STATS_OFFSET32(stat_IfHCInOctets_hi),
6867     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6868     STATS_OFFSET32(stat_IfHCOutOctets_hi),
6869     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6870     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6871     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6872     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6873     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6874     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6875     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6876     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6877     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6878     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6879     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6880     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6881     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6882     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6883     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6884     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6885     STATS_OFFSET32(stat_EtherStatsCollisions),
6886     STATS_OFFSET32(stat_EtherStatsFragments),
6887     STATS_OFFSET32(stat_EtherStatsJabbers),
6888     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6889     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6890     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6891     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6892     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6893     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6894     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6895     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6896     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6897     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6898     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6899     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6900     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6901     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6902     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6903     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6904     STATS_OFFSET32(stat_XonPauseFramesReceived),
6905     STATS_OFFSET32(stat_XoffPauseFramesReceived),
6906     STATS_OFFSET32(stat_OutXonSent),
6907     STATS_OFFSET32(stat_OutXoffSent),
6908     STATS_OFFSET32(stat_MacControlFramesReceived),
6909     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6910     STATS_OFFSET32(stat_IfInMBUFDiscards),
6911     STATS_OFFSET32(stat_FwRxDrop),
6912 };
6913
6914 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6915  * skipped because of errata.
6916  */
6917 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6918         8,0,8,8,8,8,8,8,8,8,
6919         4,0,4,4,4,4,4,4,4,4,
6920         4,4,4,4,4,4,4,4,4,4,
6921         4,4,4,4,4,4,4,4,4,4,
6922         4,4,4,4,4,4,
6923 };
6924
6925 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6926         8,0,8,8,8,8,8,8,8,8,
6927         4,4,4,4,4,4,4,4,4,4,
6928         4,4,4,4,4,4,4,4,4,4,
6929         4,4,4,4,4,4,4,4,4,4,
6930         4,4,4,4,4,4,
6931 };
6932
6933 #define BNX2_NUM_TESTS 6
6934
6935 static struct {
6936         char string[ETH_GSTRING_LEN];
6937 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6938         { "register_test (offline)" },
6939         { "memory_test (offline)" },
6940         { "loopback_test (offline)" },
6941         { "nvram_test (online)" },
6942         { "interrupt_test (online)" },
6943         { "link_test (online)" },
6944 };
6945
6946 static int
6947 bnx2_get_sset_count(struct net_device *dev, int sset)
6948 {
6949         switch (sset) {
6950         case ETH_SS_TEST:
6951                 return BNX2_NUM_TESTS;
6952         case ETH_SS_STATS:
6953                 return BNX2_NUM_STATS;
6954         default:
6955                 return -EOPNOTSUPP;
6956         }
6957 }
6958
6959 static void
6960 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6961 {
6962         struct bnx2 *bp = netdev_priv(dev);
6963
6964         bnx2_set_power_state(bp, PCI_D0);
6965
6966         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6967         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6968                 int i;
6969
6970                 bnx2_netif_stop(bp);
6971                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6972                 bnx2_free_skbs(bp);
6973
6974                 if (bnx2_test_registers(bp) != 0) {
6975                         buf[0] = 1;
6976                         etest->flags |= ETH_TEST_FL_FAILED;
6977                 }
6978                 if (bnx2_test_memory(bp) != 0) {
6979                         buf[1] = 1;
6980                         etest->flags |= ETH_TEST_FL_FAILED;
6981                 }
6982                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6983                         etest->flags |= ETH_TEST_FL_FAILED;
6984
6985                 if (!netif_running(bp->dev))
6986                         bnx2_shutdown_chip(bp);
6987                 else {
6988                         bnx2_init_nic(bp, 1);
6989                         bnx2_netif_start(bp);
6990                 }
6991
6992                 /* wait for link up */
6993                 for (i = 0; i < 7; i++) {
6994                         if (bp->link_up)
6995                                 break;
6996                         msleep_interruptible(1000);
6997                 }
6998         }
6999
7000         if (bnx2_test_nvram(bp) != 0) {
7001                 buf[3] = 1;
7002                 etest->flags |= ETH_TEST_FL_FAILED;
7003         }
7004         if (bnx2_test_intr(bp) != 0) {
7005                 buf[4] = 1;
7006                 etest->flags |= ETH_TEST_FL_FAILED;
7007         }
7008
7009         if (bnx2_test_link(bp) != 0) {
7010                 buf[5] = 1;
7011                 etest->flags |= ETH_TEST_FL_FAILED;
7012
7013         }
7014         if (!netif_running(bp->dev))
7015                 bnx2_set_power_state(bp, PCI_D3hot);
7016 }
7017
7018 static void
7019 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7020 {
7021         switch (stringset) {
7022         case ETH_SS_STATS:
7023                 memcpy(buf, bnx2_stats_str_arr,
7024                         sizeof(bnx2_stats_str_arr));
7025                 break;
7026         case ETH_SS_TEST:
7027                 memcpy(buf, bnx2_tests_str_arr,
7028                         sizeof(bnx2_tests_str_arr));
7029                 break;
7030         }
7031 }
7032
7033 static void
7034 bnx2_get_ethtool_stats(struct net_device *dev,
7035                 struct ethtool_stats *stats, u64 *buf)
7036 {
7037         struct bnx2 *bp = netdev_priv(dev);
7038         int i;
7039         u32 *hw_stats = (u32 *) bp->stats_blk;
7040         u8 *stats_len_arr = NULL;
7041
7042         if (hw_stats == NULL) {
7043                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7044                 return;
7045         }
7046
7047         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7048             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7049             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7050             (CHIP_ID(bp) == CHIP_ID_5708_A0))
7051                 stats_len_arr = bnx2_5706_stats_len_arr;
7052         else
7053                 stats_len_arr = bnx2_5708_stats_len_arr;
7054
7055         for (i = 0; i < BNX2_NUM_STATS; i++) {
7056                 if (stats_len_arr[i] == 0) {
7057                         /* skip this counter */
7058                         buf[i] = 0;
7059                         continue;
7060                 }
7061                 if (stats_len_arr[i] == 4) {
7062                         /* 4-byte counter */
7063                         buf[i] = (u64)
7064                                 *(hw_stats + bnx2_stats_offset_arr[i]);
7065                         continue;
7066                 }
7067                 /* 8-byte counter */
7068                 buf[i] = (((u64) *(hw_stats +
7069                                         bnx2_stats_offset_arr[i])) << 32) +
7070                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7071         }
7072 }
7073
7074 static int
7075 bnx2_phys_id(struct net_device *dev, u32 data)
7076 {
7077         struct bnx2 *bp = netdev_priv(dev);
7078         int i;
7079         u32 save;
7080
7081         bnx2_set_power_state(bp, PCI_D0);
7082
7083         if (data == 0)
7084                 data = 2;
7085
7086         save = REG_RD(bp, BNX2_MISC_CFG);
7087         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7088
7089         for (i = 0; i < (data * 2); i++) {
7090                 if ((i % 2) == 0) {
7091                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7092                 }
7093                 else {
7094                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7095                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
7096                                 BNX2_EMAC_LED_100MB_OVERRIDE |
7097                                 BNX2_EMAC_LED_10MB_OVERRIDE |
7098                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7099                                 BNX2_EMAC_LED_TRAFFIC);
7100                 }
7101                 msleep_interruptible(500);
7102                 if (signal_pending(current))
7103                         break;
7104         }
7105         REG_WR(bp, BNX2_EMAC_LED, 0);
7106         REG_WR(bp, BNX2_MISC_CFG, save);
7107
7108         if (!netif_running(dev))
7109                 bnx2_set_power_state(bp, PCI_D3hot);
7110
7111         return 0;
7112 }
7113
7114 static int
7115 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7116 {
7117         struct bnx2 *bp = netdev_priv(dev);
7118
7119         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7120                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7121         else
7122                 return (ethtool_op_set_tx_csum(dev, data));
7123 }
7124
7125 static const struct ethtool_ops bnx2_ethtool_ops = {
7126         .get_settings           = bnx2_get_settings,
7127         .set_settings           = bnx2_set_settings,
7128         .get_drvinfo            = bnx2_get_drvinfo,
7129         .get_regs_len           = bnx2_get_regs_len,
7130         .get_regs               = bnx2_get_regs,
7131         .get_wol                = bnx2_get_wol,
7132         .set_wol                = bnx2_set_wol,
7133         .nway_reset             = bnx2_nway_reset,
7134         .get_link               = ethtool_op_get_link,
7135         .get_eeprom_len         = bnx2_get_eeprom_len,
7136         .get_eeprom             = bnx2_get_eeprom,
7137         .set_eeprom             = bnx2_set_eeprom,
7138         .get_coalesce           = bnx2_get_coalesce,
7139         .set_coalesce           = bnx2_set_coalesce,
7140         .get_ringparam          = bnx2_get_ringparam,
7141         .set_ringparam          = bnx2_set_ringparam,
7142         .get_pauseparam         = bnx2_get_pauseparam,
7143         .set_pauseparam         = bnx2_set_pauseparam,
7144         .get_rx_csum            = bnx2_get_rx_csum,
7145         .set_rx_csum            = bnx2_set_rx_csum,
7146         .set_tx_csum            = bnx2_set_tx_csum,
7147         .set_sg                 = ethtool_op_set_sg,
7148         .set_tso                = bnx2_set_tso,
7149         .self_test              = bnx2_self_test,
7150         .get_strings            = bnx2_get_strings,
7151         .phys_id                = bnx2_phys_id,
7152         .get_ethtool_stats      = bnx2_get_ethtool_stats,
7153         .get_sset_count         = bnx2_get_sset_count,
7154 };
7155
7156 /* Called with rtnl_lock */
7157 static int
7158 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7159 {
7160         struct mii_ioctl_data *data = if_mii(ifr);
7161         struct bnx2 *bp = netdev_priv(dev);
7162         int err;
7163
7164         switch(cmd) {
7165         case SIOCGMIIPHY:
7166                 data->phy_id = bp->phy_addr;
7167
7168                 /* fallthru */
7169         case SIOCGMIIREG: {
7170                 u32 mii_regval;
7171
7172                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7173                         return -EOPNOTSUPP;
7174
7175                 if (!netif_running(dev))
7176                         return -EAGAIN;
7177
7178                 spin_lock_bh(&bp->phy_lock);
7179                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7180                 spin_unlock_bh(&bp->phy_lock);
7181
7182                 data->val_out = mii_regval;
7183
7184                 return err;
7185         }
7186
7187         case SIOCSMIIREG:
7188                 if (!capable(CAP_NET_ADMIN))
7189                         return -EPERM;
7190
7191                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7192                         return -EOPNOTSUPP;
7193
7194                 if (!netif_running(dev))
7195                         return -EAGAIN;
7196
7197                 spin_lock_bh(&bp->phy_lock);
7198                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7199                 spin_unlock_bh(&bp->phy_lock);
7200
7201                 return err;
7202
7203         default:
7204                 /* do nothing */
7205                 break;
7206         }
7207         return -EOPNOTSUPP;
7208 }
7209
7210 /* Called with rtnl_lock */
7211 static int
7212 bnx2_change_mac_addr(struct net_device *dev, void *p)
7213 {
7214         struct sockaddr *addr = p;
7215         struct bnx2 *bp = netdev_priv(dev);
7216
7217         if (!is_valid_ether_addr(addr->sa_data))
7218                 return -EINVAL;
7219
7220         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7221         if (netif_running(dev))
7222                 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7223
7224         return 0;
7225 }
7226
7227 /* Called with rtnl_lock */
7228 static int
7229 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7230 {
7231         struct bnx2 *bp = netdev_priv(dev);
7232
7233         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7234                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7235                 return -EINVAL;
7236
7237         dev->mtu = new_mtu;
7238         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7239 }
7240
7241 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7242 static void
7243 poll_bnx2(struct net_device *dev)
7244 {
7245         struct bnx2 *bp = netdev_priv(dev);
7246         int i;
7247
7248         for (i = 0; i < bp->irq_nvecs; i++) {
7249                 disable_irq(bp->irq_tbl[i].vector);
7250                 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7251                 enable_irq(bp->irq_tbl[i].vector);
7252         }
7253 }
7254 #endif
7255
7256 static void __devinit
7257 bnx2_get_5709_media(struct bnx2 *bp)
7258 {
7259         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7260         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7261         u32 strap;
7262
7263         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7264                 return;
7265         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7266                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7267                 return;
7268         }
7269
7270         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7271                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7272         else
7273                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7274
7275         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7276                 switch (strap) {
7277                 case 0x4:
7278                 case 0x5:
7279                 case 0x6:
7280                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7281                         return;
7282                 }
7283         } else {
7284                 switch (strap) {
7285                 case 0x1:
7286                 case 0x2:
7287                 case 0x4:
7288                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7289                         return;
7290                 }
7291         }
7292 }
7293
7294 static void __devinit
7295 bnx2_get_pci_speed(struct bnx2 *bp)
7296 {
7297         u32 reg;
7298
7299         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7300         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7301                 u32 clkreg;
7302
7303                 bp->flags |= BNX2_FLAG_PCIX;
7304
7305                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7306
7307                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7308                 switch (clkreg) {
7309                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7310                         bp->bus_speed_mhz = 133;
7311                         break;
7312
7313                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7314                         bp->bus_speed_mhz = 100;
7315                         break;
7316
7317                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7318                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7319                         bp->bus_speed_mhz = 66;
7320                         break;
7321
7322                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7323                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7324                         bp->bus_speed_mhz = 50;
7325                         break;
7326
7327                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7328                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7329                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7330                         bp->bus_speed_mhz = 33;
7331                         break;
7332                 }
7333         }
7334         else {
7335                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7336                         bp->bus_speed_mhz = 66;
7337                 else
7338                         bp->bus_speed_mhz = 33;
7339         }
7340
7341         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7342                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7343
7344 }
7345
7346 static int __devinit
7347 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7348 {
7349         struct bnx2 *bp;
7350         unsigned long mem_len;
7351         int rc, i, j;
7352         u32 reg;
7353         u64 dma_mask, persist_dma_mask;
7354
7355         SET_NETDEV_DEV(dev, &pdev->dev);
7356         bp = netdev_priv(dev);
7357
7358         bp->flags = 0;
7359         bp->phy_flags = 0;
7360
7361         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7362         rc = pci_enable_device(pdev);
7363         if (rc) {
7364                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7365                 goto err_out;
7366         }
7367
7368         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7369                 dev_err(&pdev->dev,
7370                         "Cannot find PCI device base address, aborting.\n");
7371                 rc = -ENODEV;
7372                 goto err_out_disable;
7373         }
7374
7375         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7376         if (rc) {
7377                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7378                 goto err_out_disable;
7379         }
7380
7381         pci_set_master(pdev);
7382         pci_save_state(pdev);
7383
7384         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7385         if (bp->pm_cap == 0) {
7386                 dev_err(&pdev->dev,
7387                         "Cannot find power management capability, aborting.\n");
7388                 rc = -EIO;
7389                 goto err_out_release;
7390         }
7391
7392         bp->dev = dev;
7393         bp->pdev = pdev;
7394
7395         spin_lock_init(&bp->phy_lock);
7396         spin_lock_init(&bp->indirect_lock);
7397         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7398
7399         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7400         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7401         dev->mem_end = dev->mem_start + mem_len;
7402         dev->irq = pdev->irq;
7403
7404         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7405
7406         if (!bp->regview) {
7407                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7408                 rc = -ENOMEM;
7409                 goto err_out_release;
7410         }
7411
7412         /* Configure byte swap and enable write to the reg_window registers.
7413          * Rely on CPU to do target byte swapping on big endian systems
7414          * The chip's target access swapping will not swap all accesses
7415          */
7416         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7417                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7418                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7419
7420         bnx2_set_power_state(bp, PCI_D0);
7421
7422         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7423
7424         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7425                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7426                         dev_err(&pdev->dev,
7427                                 "Cannot find PCIE capability, aborting.\n");
7428                         rc = -EIO;
7429                         goto err_out_unmap;
7430                 }
7431                 bp->flags |= BNX2_FLAG_PCIE;
7432                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7433                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7434         } else {
7435                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7436                 if (bp->pcix_cap == 0) {
7437                         dev_err(&pdev->dev,
7438                                 "Cannot find PCIX capability, aborting.\n");
7439                         rc = -EIO;
7440                         goto err_out_unmap;
7441                 }
7442         }
7443
7444         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7445                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7446                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7447         }
7448
7449         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7450                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7451                         bp->flags |= BNX2_FLAG_MSI_CAP;
7452         }
7453
7454         /* 5708 cannot support DMA addresses > 40-bit.  */
7455         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7456                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7457         else
7458                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7459
7460         /* Configure DMA attributes. */
7461         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7462                 dev->features |= NETIF_F_HIGHDMA;
7463                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7464                 if (rc) {
7465                         dev_err(&pdev->dev,
7466                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7467                         goto err_out_unmap;
7468                 }
7469         } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7470                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7471                 goto err_out_unmap;
7472         }
7473
7474         if (!(bp->flags & BNX2_FLAG_PCIE))
7475                 bnx2_get_pci_speed(bp);
7476
7477         /* 5706A0 may falsely detect SERR and PERR. */
7478         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7479                 reg = REG_RD(bp, PCI_COMMAND);
7480                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7481                 REG_WR(bp, PCI_COMMAND, reg);
7482         }
7483         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7484                 !(bp->flags & BNX2_FLAG_PCIX)) {
7485
7486                 dev_err(&pdev->dev,
7487                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7488                 goto err_out_unmap;
7489         }
7490
7491         bnx2_init_nvram(bp);
7492
7493         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7494
7495         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7496             BNX2_SHM_HDR_SIGNATURE_SIG) {
7497                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7498
7499                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7500         } else
7501                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7502
7503         /* Get the permanent MAC address.  First we need to make sure the
7504          * firmware is actually running.
7505          */
7506         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7507
7508         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7509             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7510                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7511                 rc = -ENODEV;
7512                 goto err_out_unmap;
7513         }
7514
7515         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7516         for (i = 0, j = 0; i < 3; i++) {
7517                 u8 num, k, skip0;
7518
7519                 num = (u8) (reg >> (24 - (i * 8)));
7520                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7521                         if (num >= k || !skip0 || k == 1) {
7522                                 bp->fw_version[j++] = (num / k) + '0';
7523                                 skip0 = 0;
7524                         }
7525                 }
7526                 if (i != 2)
7527                         bp->fw_version[j++] = '.';
7528         }
7529         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7530         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7531                 bp->wol = 1;
7532
7533         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7534                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7535
7536                 for (i = 0; i < 30; i++) {
7537                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7538                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7539                                 break;
7540                         msleep(10);
7541                 }
7542         }
7543         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7544         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7545         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7546             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7547                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7548
7549                 bp->fw_version[j++] = ' ';
7550                 for (i = 0; i < 3; i++) {
7551                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7552                         reg = swab32(reg);
7553                         memcpy(&bp->fw_version[j], &reg, 4);
7554                         j += 4;
7555                 }
7556         }
7557
7558         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7559         bp->mac_addr[0] = (u8) (reg >> 8);
7560         bp->mac_addr[1] = (u8) reg;
7561
7562         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7563         bp->mac_addr[2] = (u8) (reg >> 24);
7564         bp->mac_addr[3] = (u8) (reg >> 16);
7565         bp->mac_addr[4] = (u8) (reg >> 8);
7566         bp->mac_addr[5] = (u8) reg;
7567
7568         bp->tx_ring_size = MAX_TX_DESC_CNT;
7569         bnx2_set_rx_ring_size(bp, 255);
7570
7571         bp->rx_csum = 1;
7572
7573         bp->tx_quick_cons_trip_int = 20;
7574         bp->tx_quick_cons_trip = 20;
7575         bp->tx_ticks_int = 80;
7576         bp->tx_ticks = 80;
7577
7578         bp->rx_quick_cons_trip_int = 6;
7579         bp->rx_quick_cons_trip = 6;
7580         bp->rx_ticks_int = 18;
7581         bp->rx_ticks = 18;
7582
7583         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7584
7585         bp->current_interval = BNX2_TIMER_INTERVAL;
7586
7587         bp->phy_addr = 1;
7588
7589         /* Disable WOL support if we are running on a SERDES chip. */
7590         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7591                 bnx2_get_5709_media(bp);
7592         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7593                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7594
7595         bp->phy_port = PORT_TP;
7596         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7597                 bp->phy_port = PORT_FIBRE;
7598                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7599                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7600                         bp->flags |= BNX2_FLAG_NO_WOL;
7601                         bp->wol = 0;
7602                 }
7603                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7604                         /* Don't do parallel detect on this board because of
7605                          * some board problems.  The link will not go down
7606                          * if we do parallel detect.
7607                          */
7608                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7609                             pdev->subsystem_device == 0x310c)
7610                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7611                 } else {
7612                         bp->phy_addr = 2;
7613                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7614                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7615                 }
7616         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7617                    CHIP_NUM(bp) == CHIP_NUM_5708)
7618                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7619         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7620                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7621                   CHIP_REV(bp) == CHIP_REV_Bx))
7622                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7623
7624         bnx2_init_fw_cap(bp);
7625
7626         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7627             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7628             (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7629             !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7630                 bp->flags |= BNX2_FLAG_NO_WOL;
7631                 bp->wol = 0;
7632         }
7633
7634         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7635                 bp->tx_quick_cons_trip_int =
7636                         bp->tx_quick_cons_trip;
7637                 bp->tx_ticks_int = bp->tx_ticks;
7638                 bp->rx_quick_cons_trip_int =
7639                         bp->rx_quick_cons_trip;
7640                 bp->rx_ticks_int = bp->rx_ticks;
7641                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7642                 bp->com_ticks_int = bp->com_ticks;
7643                 bp->cmd_ticks_int = bp->cmd_ticks;
7644         }
7645
7646         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7647          *
7648          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7649          * with byte enables disabled on the unused 32-bit word.  This is legal
7650          * but causes problems on the AMD 8132 which will eventually stop
7651          * responding after a while.
7652          *
7653          * AMD believes this incompatibility is unique to the 5706, and
7654          * prefers to locally disable MSI rather than globally disabling it.
7655          */
7656         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7657                 struct pci_dev *amd_8132 = NULL;
7658
7659                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7660                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7661                                                   amd_8132))) {
7662
7663                         if (amd_8132->revision >= 0x10 &&
7664                             amd_8132->revision <= 0x13) {
7665                                 disable_msi = 1;
7666                                 pci_dev_put(amd_8132);
7667                                 break;
7668                         }
7669                 }
7670         }
7671
7672         bnx2_set_default_link(bp);
7673         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7674
7675         init_timer(&bp->timer);
7676         bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7677         bp->timer.data = (unsigned long) bp;
7678         bp->timer.function = bnx2_timer;
7679
7680         return 0;
7681
7682 err_out_unmap:
7683         if (bp->regview) {
7684                 iounmap(bp->regview);
7685                 bp->regview = NULL;
7686         }
7687
7688 err_out_release:
7689         pci_release_regions(pdev);
7690
7691 err_out_disable:
7692         pci_disable_device(pdev);
7693         pci_set_drvdata(pdev, NULL);
7694
7695 err_out:
7696         return rc;
7697 }
7698
7699 static char * __devinit
7700 bnx2_bus_string(struct bnx2 *bp, char *str)
7701 {
7702         char *s = str;
7703
7704         if (bp->flags & BNX2_FLAG_PCIE) {
7705                 s += sprintf(s, "PCI Express");
7706         } else {
7707                 s += sprintf(s, "PCI");
7708                 if (bp->flags & BNX2_FLAG_PCIX)
7709                         s += sprintf(s, "-X");
7710                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7711                         s += sprintf(s, " 32-bit");
7712                 else
7713                         s += sprintf(s, " 64-bit");
7714                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7715         }
7716         return str;
7717 }
7718
7719 static void __devinit
7720 bnx2_init_napi(struct bnx2 *bp)
7721 {
7722         int i;
7723
7724         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7725                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7726                 int (*poll)(struct napi_struct *, int);
7727
7728                 if (i == 0)
7729                         poll = bnx2_poll;
7730                 else
7731                         poll = bnx2_poll_msix;
7732
7733                 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7734                 bnapi->bp = bp;
7735         }
7736 }
7737
7738 static const struct net_device_ops bnx2_netdev_ops = {
7739         .ndo_open               = bnx2_open,
7740         .ndo_start_xmit         = bnx2_start_xmit,
7741         .ndo_stop               = bnx2_close,
7742         .ndo_get_stats          = bnx2_get_stats,
7743         .ndo_set_rx_mode        = bnx2_set_rx_mode,
7744         .ndo_do_ioctl           = bnx2_ioctl,
7745         .ndo_validate_addr      = eth_validate_addr,
7746         .ndo_set_mac_address    = bnx2_change_mac_addr,
7747         .ndo_change_mtu         = bnx2_change_mtu,
7748         .ndo_tx_timeout         = bnx2_tx_timeout,
7749 #ifdef BCM_VLAN
7750         .ndo_vlan_rx_register   = bnx2_vlan_rx_register,
7751 #endif
7752 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7753         .ndo_poll_controller    = poll_bnx2,
7754 #endif
7755 };
7756
7757 static int __devinit
7758 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7759 {
7760         static int version_printed = 0;
7761         struct net_device *dev = NULL;
7762         struct bnx2 *bp;
7763         int rc;
7764         char str[40];
7765
7766         if (version_printed++ == 0)
7767                 printk(KERN_INFO "%s", version);
7768
7769         /* dev zeroed in init_etherdev */
7770         dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7771
7772         if (!dev)
7773                 return -ENOMEM;
7774
7775         rc = bnx2_init_board(pdev, dev);
7776         if (rc < 0) {
7777                 free_netdev(dev);
7778                 return rc;
7779         }
7780
7781         dev->netdev_ops = &bnx2_netdev_ops;
7782         dev->watchdog_timeo = TX_TIMEOUT;
7783         dev->ethtool_ops = &bnx2_ethtool_ops;
7784
7785         bp = netdev_priv(dev);
7786         bnx2_init_napi(bp);
7787
7788         pci_set_drvdata(pdev, dev);
7789
7790         memcpy(dev->dev_addr, bp->mac_addr, 6);
7791         memcpy(dev->perm_addr, bp->mac_addr, 6);
7792
7793         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7794         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7795                 dev->features |= NETIF_F_IPV6_CSUM;
7796
7797 #ifdef BCM_VLAN
7798         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7799 #endif
7800         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7801         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7802                 dev->features |= NETIF_F_TSO6;
7803
7804         if ((rc = register_netdev(dev))) {
7805                 dev_err(&pdev->dev, "Cannot register net device\n");
7806                 if (bp->regview)
7807                         iounmap(bp->regview);
7808                 pci_release_regions(pdev);
7809                 pci_disable_device(pdev);
7810                 pci_set_drvdata(pdev, NULL);
7811                 free_netdev(dev);
7812                 return rc;
7813         }
7814
7815         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7816                 "IRQ %d, node addr %pM\n",
7817                 dev->name,
7818                 board_info[ent->driver_data].name,
7819                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7820                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7821                 bnx2_bus_string(bp, str),
7822                 dev->base_addr,
7823                 bp->pdev->irq, dev->dev_addr);
7824
7825         return 0;
7826 }
7827
7828 static void __devexit
7829 bnx2_remove_one(struct pci_dev *pdev)
7830 {
7831         struct net_device *dev = pci_get_drvdata(pdev);
7832         struct bnx2 *bp = netdev_priv(dev);
7833
7834         flush_scheduled_work();
7835
7836         unregister_netdev(dev);
7837
7838         if (bp->regview)
7839                 iounmap(bp->regview);
7840
7841         free_netdev(dev);
7842         pci_release_regions(pdev);
7843         pci_disable_device(pdev);
7844         pci_set_drvdata(pdev, NULL);
7845 }
7846
7847 static int
7848 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7849 {
7850         struct net_device *dev = pci_get_drvdata(pdev);
7851         struct bnx2 *bp = netdev_priv(dev);
7852
7853         /* PCI register 4 needs to be saved whether netif_running() or not.
7854          * MSI address and data need to be saved if using MSI and
7855          * netif_running().
7856          */
7857         pci_save_state(pdev);
7858         if (!netif_running(dev))
7859                 return 0;
7860
7861         flush_scheduled_work();
7862         bnx2_netif_stop(bp);
7863         netif_device_detach(dev);
7864         del_timer_sync(&bp->timer);
7865         bnx2_shutdown_chip(bp);
7866         bnx2_free_skbs(bp);
7867         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7868         return 0;
7869 }
7870
7871 static int
7872 bnx2_resume(struct pci_dev *pdev)
7873 {
7874         struct net_device *dev = pci_get_drvdata(pdev);
7875         struct bnx2 *bp = netdev_priv(dev);
7876
7877         pci_restore_state(pdev);
7878         if (!netif_running(dev))
7879                 return 0;
7880
7881         bnx2_set_power_state(bp, PCI_D0);
7882         netif_device_attach(dev);
7883         bnx2_init_nic(bp, 1);
7884         bnx2_netif_start(bp);
7885         return 0;
7886 }
7887
7888 /**
7889  * bnx2_io_error_detected - called when PCI error is detected
7890  * @pdev: Pointer to PCI device
7891  * @state: The current pci connection state
7892  *
7893  * This function is called after a PCI bus error affecting
7894  * this device has been detected.
7895  */
7896 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7897                                                pci_channel_state_t state)
7898 {
7899         struct net_device *dev = pci_get_drvdata(pdev);
7900         struct bnx2 *bp = netdev_priv(dev);
7901
7902         rtnl_lock();
7903         netif_device_detach(dev);
7904
7905         if (netif_running(dev)) {
7906                 bnx2_netif_stop(bp);
7907                 del_timer_sync(&bp->timer);
7908                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7909         }
7910
7911         pci_disable_device(pdev);
7912         rtnl_unlock();
7913
7914         /* Request a slot slot reset. */
7915         return PCI_ERS_RESULT_NEED_RESET;
7916 }
7917
7918 /**
7919  * bnx2_io_slot_reset - called after the pci bus has been reset.
7920  * @pdev: Pointer to PCI device
7921  *
7922  * Restart the card from scratch, as if from a cold-boot.
7923  */
7924 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7925 {
7926         struct net_device *dev = pci_get_drvdata(pdev);
7927         struct bnx2 *bp = netdev_priv(dev);
7928
7929         rtnl_lock();
7930         if (pci_enable_device(pdev)) {
7931                 dev_err(&pdev->dev,
7932                         "Cannot re-enable PCI device after reset.\n");
7933                 rtnl_unlock();
7934                 return PCI_ERS_RESULT_DISCONNECT;
7935         }
7936         pci_set_master(pdev);
7937         pci_restore_state(pdev);
7938
7939         if (netif_running(dev)) {
7940                 bnx2_set_power_state(bp, PCI_D0);
7941                 bnx2_init_nic(bp, 1);
7942         }
7943
7944         rtnl_unlock();
7945         return PCI_ERS_RESULT_RECOVERED;
7946 }
7947
7948 /**
7949  * bnx2_io_resume - called when traffic can start flowing again.
7950  * @pdev: Pointer to PCI device
7951  *
7952  * This callback is called when the error recovery driver tells us that
7953  * its OK to resume normal operation.
7954  */
7955 static void bnx2_io_resume(struct pci_dev *pdev)
7956 {
7957         struct net_device *dev = pci_get_drvdata(pdev);
7958         struct bnx2 *bp = netdev_priv(dev);
7959
7960         rtnl_lock();
7961         if (netif_running(dev))
7962                 bnx2_netif_start(bp);
7963
7964         netif_device_attach(dev);
7965         rtnl_unlock();
7966 }
7967
7968 static struct pci_error_handlers bnx2_err_handler = {
7969         .error_detected = bnx2_io_error_detected,
7970         .slot_reset     = bnx2_io_slot_reset,
7971         .resume         = bnx2_io_resume,
7972 };
7973
7974 static struct pci_driver bnx2_pci_driver = {
7975         .name           = DRV_MODULE_NAME,
7976         .id_table       = bnx2_pci_tbl,
7977         .probe          = bnx2_init_one,
7978         .remove         = __devexit_p(bnx2_remove_one),
7979         .suspend        = bnx2_suspend,
7980         .resume         = bnx2_resume,
7981         .err_handler    = &bnx2_err_handler,
7982 };
7983
7984 static int __init bnx2_init(void)
7985 {
7986         return pci_register_driver(&bnx2_pci_driver);
7987 }
7988
7989 static void __exit bnx2_cleanup(void)
7990 {
7991         pci_unregister_driver(&bnx2_pci_driver);
7992 }
7993
7994 module_init(bnx2_init);
7995 module_exit(bnx2_cleanup);
7996
7997
7998