1 /************************************************************************
5 * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
7 ************************************************************************/
9 /* Defines necessary for cplb initialisation routines. */
14 # include <asm/blackfin.h>
16 #define CPLB_ENABLE_ICACHE_P 0
17 #define CPLB_ENABLE_DCACHE_P 1
18 #define CPLB_ENABLE_DCACHE2_P 2
19 #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
20 #define CPLB_ENABLE_ICPLBS_P 4
21 #define CPLB_ENABLE_DCPLBS_P 5
23 #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
24 #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
25 #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
26 #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
27 #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
28 #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
29 #define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
30 CPLB_ENABLE_ICPLBS | \
33 #define CPLB_RELOADED 0x0000
34 #define CPLB_NO_UNLOCKED 0x0001
35 #define CPLB_NO_ADDR_MATCH 0x0002
36 #define CPLB_PROT_VIOL 0x0003
37 #define CPLB_UNKNOWN_ERR 0x0004
39 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
40 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
42 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
44 #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
45 #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
46 #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
47 #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
48 #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
49 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL