2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/compiler.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
42 #include <linux/pci.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
47 #include <linux/tcp.h>
48 #include <linux/skbuff.h>
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
56 #include <linux/mman.h>
57 #include <linux/vmalloc.h>
59 #include <asm/system.h>
61 #include <asm/byteorder.h>
62 #include <asm/uaccess.h>
63 #include <asm/pgtable.h>
65 #include "netxen_nic_hw.h"
67 #define _NETXEN_NIC_LINUX_MAJOR 4
68 #define _NETXEN_NIC_LINUX_MINOR 0
69 #define _NETXEN_NIC_LINUX_SUBVERSION 11
70 #define NETXEN_NIC_LINUX_VERSIONID "4.0.11"
72 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
74 #define NETXEN_NUM_FLASH_SECTORS (64)
75 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
76 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
77 * NETXEN_FLASH_SECTOR_SIZE)
79 #define PHAN_VENDOR_ID 0x4040
81 #define RCV_DESC_RINGSIZE \
82 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
83 #define STATUS_DESC_RINGSIZE \
84 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
85 #define LRO_DESC_RINGSIZE \
86 (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
88 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
89 #define RCV_BUFFSIZE \
90 (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
91 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
93 #define NETXEN_NETDEV_STATUS 0x1
94 #define NETXEN_RCV_PRODUCER_OFFSET 0
95 #define NETXEN_RCV_PEG_DB_ID 2
96 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
97 #define FLASH_SUCCESS 0
99 #define ADDR_IN_WINDOW1(off) \
100 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
103 * normalize a 64MB crb address to 32MB PCI window
104 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
106 #define NETXEN_CRB_NORMAL(reg) \
107 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
109 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
110 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
112 #define DB_NORMALIZE(adapter, off) \
113 (adapter->ahw.db_base + (off))
115 #define NX_P2_C0 0x24
116 #define NX_P2_C1 0x25
117 #define NX_P3_A0 0x30
118 #define NX_P3_A2 0x30
119 #define NX_P3_B0 0x40
120 #define NX_P3_B1 0x41
122 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
123 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
125 #define FIRST_PAGE_GROUP_START 0
126 #define FIRST_PAGE_GROUP_END 0x100000
128 #define SECOND_PAGE_GROUP_START 0x6000000
129 #define SECOND_PAGE_GROUP_END 0x68BC000
131 #define THIRD_PAGE_GROUP_START 0x70E4000
132 #define THIRD_PAGE_GROUP_END 0x8000000
134 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
135 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
136 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
138 #define P2_MAX_MTU (8000)
139 #define P3_MAX_MTU (9600)
140 #define NX_ETHERMTU 1500
141 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
143 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
144 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
145 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
146 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
148 #define MAX_RX_BUFFER_LENGTH 1760
149 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
150 #define MAX_RX_LRO_BUFFER_LENGTH (8062)
151 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
152 #define RX_JUMBO_DMA_MAP_LEN \
153 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
154 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
157 * Maximum number of ring contexts
159 #define MAX_RING_CTX 1
161 /* Opcodes to be used with the commands */
162 #define TX_ETHER_PKT 0x01
163 #define TX_TCP_PKT 0x02
164 #define TX_UDP_PKT 0x03
165 #define TX_IP_PKT 0x04
166 #define TX_TCP_LSO 0x05
167 #define TX_TCP_LSO6 0x06
168 #define TX_IPSEC 0x07
169 #define TX_IPSEC_CMD 0x0a
170 #define TX_TCPV6_PKT 0x0b
171 #define TX_UDPV6_PKT 0x0c
173 /* The following opcodes are for internal consumption. */
174 #define NETXEN_CONTROL_OP 0x10
175 #define PEGNET_REQUEST 0x11
177 #define MAX_NUM_CARDS 4
179 #define MAX_BUFFERS_PER_CMD 32
182 * Following are the states of the Phantom. Phantom will set them and
183 * Host will read to check if the fields are correct.
185 #define PHAN_INITIALIZE_START 0xff00
186 #define PHAN_INITIALIZE_FAILED 0xffff
187 #define PHAN_INITIALIZE_COMPLETE 0xff01
189 /* Host writes the following to notify that it has done the init-handshake */
190 #define PHAN_INITIALIZE_ACK 0xf00f
192 #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
194 /* descriptor types */
195 #define RCV_DESC_NORMAL 0x01
196 #define RCV_DESC_JUMBO 0x02
197 #define RCV_DESC_LRO 0x04
198 #define RCV_DESC_NORMAL_CTXID 0
199 #define RCV_DESC_JUMBO_CTXID 1
200 #define RCV_DESC_LRO_CTXID 2
202 #define RCV_DESC_TYPE(ID) \
203 ((ID == RCV_DESC_JUMBO_CTXID) \
205 : ((ID == RCV_DESC_LRO_CTXID) \
209 #define MAX_CMD_DESCRIPTORS 4096
210 #define MAX_RCV_DESCRIPTORS 16384
211 #define MAX_CMD_DESCRIPTORS_HOST 1024
212 #define MAX_RCV_DESCRIPTORS_1G 2048
213 #define MAX_RCV_DESCRIPTORS_10G 4096
214 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
215 #define MAX_LRO_RCV_DESCRIPTORS 8
216 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
217 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
218 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
219 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
220 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
221 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
222 MAX_LRO_RCV_DESCRIPTORS)
223 #define MIN_TX_COUNT 4096
224 #define MIN_RX_COUNT 4096
225 #define NETXEN_CTX_SIGNATURE 0xdee0
226 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
227 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
229 #define PHAN_PEG_RCV_INITIALIZED 0xff01
230 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
232 #define get_next_index(index, length) \
233 (((index) + 1) & ((length) - 1))
235 #define get_index_range(index,length,count) \
236 (((index) + (count)) & ((length) - 1))
238 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
239 #define MPORT_MULTI_FUNCTION_MODE 0x2222
241 #include "netxen_nic_phan_reg.h"
244 * NetXen host-peg signal message structure
246 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
247 * Bit 2 : priv_id => must be 1
248 * Bit 3-17 : count => for doorbell
249 * Bit 18-27 : ctx_id => Context id
253 typedef u32 netxen_ctx_msg;
255 #define netxen_set_msg_peg_id(config_word, val) \
256 ((config_word) &= ~3, (config_word) |= val & 3)
257 #define netxen_set_msg_privid(config_word) \
258 ((config_word) |= 1 << 2)
259 #define netxen_set_msg_count(config_word, val) \
260 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
261 #define netxen_set_msg_ctxid(config_word, val) \
262 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
263 #define netxen_set_msg_opcode(config_word, val) \
264 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
266 struct netxen_rcv_context {
267 __le64 rcv_ring_addr;
268 __le32 rcv_ring_size;
272 struct netxen_ring_ctx {
274 /* one command ring */
275 __le64 cmd_consumer_offset;
276 __le64 cmd_ring_addr;
277 __le32 cmd_ring_size;
280 /* three receive rings */
281 struct netxen_rcv_context rcv_ctx[3];
283 /* one status ring */
284 __le64 sts_ring_addr;
285 __le32 sts_ring_size;
288 } __attribute__ ((aligned(64)));
291 * Following data structures describe the descriptors that will be used.
292 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
293 * we are doing LSO (above the 1500 size packet) only.
297 * The size of reference handle been changed to 16 bits to pass the MSS fields
301 #define FLAGS_CHECKSUM_ENABLED 0x01
302 #define FLAGS_LSO_ENABLED 0x02
303 #define FLAGS_IPSEC_SA_ADD 0x04
304 #define FLAGS_IPSEC_SA_DELETE 0x08
305 #define FLAGS_VLAN_TAGGED 0x10
307 #define netxen_set_cmd_desc_port(cmd_desc, var) \
308 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
309 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
310 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
312 #define netxen_set_tx_port(_desc, _port) \
313 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
315 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
316 (_desc)->flags_opcode = \
317 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
319 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
320 (_desc)->num_of_buffers_total_length = \
321 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
323 struct cmd_desc_type0 {
324 u8 tcp_hdr_offset; /* For LSO only */
325 u8 ip_hdr_offset; /* For LSO only */
326 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
328 /* Bit pattern: 0-7 total number of segments,
329 8-31 Total size of the packet */
330 __le32 num_of_buffers_total_length;
333 __le32 addr_low_part2;
334 __le32 addr_high_part2;
339 __le16 reference_handle; /* changed to u16 to add mss */
340 __le16 mss; /* passed by NDIS_PACKET for LSO */
341 /* Bit pattern 0-3 port, 0-3 ctx id */
343 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
344 __le16 conn_id; /* IPSec offoad only */
348 __le32 addr_low_part3;
349 __le32 addr_high_part3;
355 __le32 addr_low_part1;
356 __le32 addr_high_part1;
361 __le16 buffer1_length;
362 __le16 buffer2_length;
363 __le16 buffer3_length;
364 __le16 buffer4_length;
368 __le32 addr_low_part4;
369 __le32 addr_high_part4;
376 } __attribute__ ((aligned(64)));
378 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
380 __le16 reference_handle;
382 __le32 buffer_length; /* allocated buffer length (usually 2K) */
386 /* opcode field in status_desc */
387 #define NETXEN_NIC_RXPKT_DESC 0x04
388 #define NETXEN_OLD_RXPKT_DESC 0x3f
390 /* for status field in status_desc */
391 #define STATUS_NEED_CKSUM (1)
392 #define STATUS_CKSUM_OK (2)
394 /* owner bits of status_desc */
395 #define STATUS_OWNER_HOST (0x1)
396 #define STATUS_OWNER_PHANTOM (0x2)
398 #define NETXEN_PROT_IP (1)
399 #define NETXEN_PROT_UNKNOWN (0)
401 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
403 #define netxen_get_sts_desc_lro_cnt(status_desc) \
404 ((status_desc)->lro & 0x7F)
405 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
406 (((status_desc)->lro & 0x80) >> 7)
408 #define netxen_get_sts_port(sts_data) \
410 #define netxen_get_sts_status(sts_data) \
411 (((sts_data) >> 4) & 0x0F)
412 #define netxen_get_sts_type(sts_data) \
413 (((sts_data) >> 8) & 0x0F)
414 #define netxen_get_sts_totallength(sts_data) \
415 (((sts_data) >> 12) & 0xFFFF)
416 #define netxen_get_sts_refhandle(sts_data) \
417 (((sts_data) >> 28) & 0xFFFF)
418 #define netxen_get_sts_prot(sts_data) \
419 (((sts_data) >> 44) & 0x0F)
420 #define netxen_get_sts_pkt_offset(sts_data) \
421 (((sts_data) >> 48) & 0x1F)
422 #define netxen_get_sts_opcode(sts_data) \
423 (((sts_data) >> 58) & 0x03F)
425 #define netxen_get_sts_owner(status_desc) \
426 ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
427 #define netxen_set_sts_owner(status_desc, val) { \
428 (status_desc)->status_desc_data = \
429 ((status_desc)->status_desc_data & \
430 ~cpu_to_le64(0x3ULL << 56)) | \
431 cpu_to_le64((u64)((val) & 0x3) << 56); \
435 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
436 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
437 53-55 desc_cnt, 56-57 owner, 58-63 opcode
439 __le64 status_desc_data;
447 /* Bit pattern: 0-6 lro_count indicates frag
448 * sequence, 7 last_frag indicates last frag
452 /* chained buffers */
457 __le16 frag_handles[4];
460 } __attribute__ ((aligned(16)));
463 NETXEN_RCV_PEG_0 = 0,
466 /* The version of the main data structure */
467 #define NETXEN_BDINFO_VERSION 1
469 /* Magic number to let user know flash is programmed */
470 #define NETXEN_BDINFO_MAGIC 0x12345678
472 /* Max number of Gig ports on a Phantom board */
473 #define NETXEN_MAX_PORTS 4
476 NETXEN_BRDTYPE_P1_BD = 0x0000,
477 NETXEN_BRDTYPE_P1_SB = 0x0001,
478 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
479 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
481 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
482 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
483 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
484 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
485 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
487 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
488 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
489 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
491 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
492 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
493 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
494 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
495 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
496 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
497 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
498 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
499 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
500 NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
501 NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
502 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
503 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032,
504 NETXEN_BRDTYPE_P3_10G_TP = 0x0080
509 NETXEN_BRDMFG_INVENTEC = 1
513 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
514 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
515 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
516 MEM_ORG_256Mbx4 = 0x3,
517 MEM_ORG_256Mbx8 = 0x4,
518 MEM_ORG_256Mbx16 = 0x5,
519 MEM_ORG_512Mbx4 = 0x6,
520 MEM_ORG_512Mbx8 = 0x7,
521 MEM_ORG_512Mbx16 = 0x8,
524 MEM_ORG_1Gbx16 = 0xb,
527 MEM_ORG_2Gbx16 = 0xe,
528 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
529 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
530 } netxen_mn_mem_org_t;
533 MEM_ORG_512Kx36 = 0x0,
536 } netxen_sn_mem_org_t;
541 MEM_DEPTH_16MB = 0x3,
542 MEM_DEPTH_32MB = 0x4,
543 MEM_DEPTH_64MB = 0x5,
544 MEM_DEPTH_128MB = 0x6,
545 MEM_DEPTH_256MB = 0x7,
546 MEM_DEPTH_512MB = 0x8,
551 MEM_DEPTH_16GB = 0xd,
553 } netxen_mem_depth_t;
555 struct netxen_board_info {
567 u32 port_mask; /* available niu ports */
568 u32 peg_mask; /* available pegs */
569 u32 icache_ok; /* can we run with icache? */
570 u32 dcache_ok; /* can we run with dcache? */
578 /* MN-related config */
579 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
580 u32 mn_sync_shift_cclk;
581 u32 mn_sync_shift_mclk;
583 u32 mn_crystal_freq; /* in MHz */
584 u32 mn_speed; /* in MHz */
587 u32 mn_ranks_0; /* ranks per slot */
588 u32 mn_ranks_1; /* ranks per slot */
599 u32 mn_mode_reg; /* MIU DDR Mode Register */
600 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
601 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
602 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
603 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
605 /* SN-related config */
606 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
607 u32 sn_pt_mode; /* pass through mode */
622 u32 magic; /* indicates flash has been initialized */
629 #define FLASH_NUM_PORTS (4)
631 struct netxen_flash_mac_addr {
635 struct netxen_user_old_info {
647 /* primary image status */
649 u32 secondary_present;
651 /* MAC address , 4 ports */
652 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
654 #define FLASH_NUM_MAC_PER_PORT 32
655 struct netxen_user_info {
656 u8 flash_md5[16 * 64];
663 /* primary image status */
665 u32 secondary_present;
667 /* MAC address , 4 ports, 32 address per port */
668 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
672 /* Any user defined data */
676 * Flash Layout - new format.
678 struct netxen_new_user_info {
679 u8 flash_md5[16 * 64];
686 /* primary image status */
688 u32 secondary_present;
690 /* MAC address , 4 ports, 32 address per port */
691 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
695 /* Any user defined data */
698 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
699 #define SECONDARY_IMAGE_ABSENT 0xffffffff
700 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
701 #define PRIMARY_IMAGE_BAD 0xffffffff
703 /* Flash memory map */
705 NETXEN_CRBINIT_START = 0, /* Crbinit section */
706 NETXEN_BRDCFG_START = 0x4000, /* board config */
707 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
708 NETXEN_BOOTLD_START = 0x10000, /* bootld */
709 NETXEN_IMAGE_START = 0x43000, /* compressed image */
710 NETXEN_SECONDARY_START = 0x200000, /* backup images */
711 NETXEN_PXE_START = 0x3E0000, /* user defined region */
712 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
713 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
714 } netxen_flash_map_t;
716 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
717 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
718 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
719 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
720 #define NX_FW_MIN_SIZE (0x3fffff)
721 #define NX_P2_MN_ROMIMAGE "nxromimg.bin"
722 #define NX_P3_CT_ROMIMAGE "nx3fwct.bin"
723 #define NX_P3_MN_ROMIMAGE "nx3fwmn.bin"
725 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
727 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
728 #define NETXEN_INIT_SECTOR (0)
729 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
730 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
731 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
732 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
733 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
734 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
735 #define NETXEN_NUM_CONFIG_SECTORS (1)
736 #define PFX "NetXen: "
737 extern char netxen_nic_driver_name[];
739 /* Note: Make sure to not call this before adapter->port is valid */
740 #if !defined(NETXEN_DEBUG)
741 #define DPRINTK(klevel, fmt, args...) do { \
744 #define DPRINTK(klevel, fmt, args...) do { \
745 printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
746 (adapter != NULL && adapter->netdev != NULL) ? \
747 adapter->netdev->name : NULL, \
751 /* Number of status descriptors to handle per interrupt */
752 #define MAX_STATUS_HANDLE (128)
755 * netxen_skb_frag{} is to contain mapping info for each SG list. This
756 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
758 struct netxen_skb_frag {
763 #define _netxen_set_bits(config_word, start, bits, val) {\
764 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
765 unsigned long long __tvalue = (val); \
766 (config_word) &= ~__tmask; \
767 (config_word) |= (((__tvalue) << (start)) & __tmask); \
770 #define _netxen_clear_bits(config_word, start, bits) {\
771 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
772 (config_word) &= ~__tmask; \
775 /* Following defines are for the state of the buffers */
776 #define NETXEN_BUFFER_FREE 0
777 #define NETXEN_BUFFER_BUSY 1
780 * There will be one netxen_buffer per skb packet. These will be
781 * used to save the dma info for pci_unmap_page()
783 struct netxen_cmd_buffer {
785 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
789 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
790 struct netxen_rx_buffer {
791 struct list_head list;
796 u32 lro_expected_frags;
797 u32 lro_current_frags;
802 #define NETXEN_NIC_GBE 0x01
803 #define NETXEN_NIC_XGBE 0x02
806 * One hardware_context{} per adapter
807 * contains interrupt info as well shared hardware info.
809 struct netxen_hardware_context {
810 void __iomem *pci_base0;
811 void __iomem *pci_base1;
812 void __iomem *pci_base2;
813 unsigned long first_page_group_end;
814 unsigned long first_page_group_start;
815 void __iomem *db_base;
816 unsigned long db_len;
817 unsigned long pci_len0;
822 unsigned long mn_win_crb;
823 unsigned long ms_win_crb;
827 struct netxen_board_info boardcfg;
829 /* Address of cmd ring in Phantom */
830 struct cmd_desc_type0 *cmd_desc_head;
831 dma_addr_t cmd_desc_phys_addr;
832 struct netxen_adapter *adapter;
836 #define RCV_RING_LRO RCV_DESC_LRO
838 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
839 #define ETHERNET_FCS_SIZE 4
841 struct netxen_adapter_stats {
859 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
860 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
862 struct nx_host_rds_ring {
865 dma_addr_t phys_addr;
866 u32 crb_rcv_producer; /* reg offset */
867 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
868 u32 max_rx_desc_count;
871 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
872 struct list_head free_list;
876 * Receive context. There is one such structure per instance of the
877 * receive processing. Any state information that is relevant to
878 * the receive, and is must be in this structure. The global data may be
881 struct netxen_recv_context {
886 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
887 u32 status_rx_consumer;
888 u32 crb_sts_consumer; /* reg offset */
889 dma_addr_t rcv_status_desc_phys_addr;
890 struct status_desc *rcv_status_desc_head;
893 /* New HW context creation */
895 #define NX_OS_CRB_RETRY_COUNT 4000
896 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
897 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
899 #define NX_CDRP_CLEAR 0x00000000
900 #define NX_CDRP_CMD_BIT 0x80000000
903 * All responses must have the NX_CDRP_CMD_BIT cleared
904 * in the crb NX_CDRP_CRB_OFFSET.
906 #define NX_CDRP_FORM_RSP(rsp) (rsp)
907 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
909 #define NX_CDRP_RSP_OK 0x00000001
910 #define NX_CDRP_RSP_FAIL 0x00000002
911 #define NX_CDRP_RSP_TIMEOUT 0x00000003
914 * All commands must have the NX_CDRP_CMD_BIT set in
915 * the crb NX_CDRP_CRB_OFFSET.
917 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
918 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
920 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
921 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
922 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
923 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
924 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
925 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
926 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
927 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
928 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
929 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
930 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
931 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
932 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
933 #define NX_CDRP_CMD_SET_MTU 0x00000012
934 #define NX_CDRP_CMD_MAX 0x00000013
936 #define NX_RCODE_SUCCESS 0
937 #define NX_RCODE_NO_HOST_MEM 1
938 #define NX_RCODE_NO_HOST_RESOURCE 2
939 #define NX_RCODE_NO_CARD_CRB 3
940 #define NX_RCODE_NO_CARD_MEM 4
941 #define NX_RCODE_NO_CARD_RESOURCE 5
942 #define NX_RCODE_INVALID_ARGS 6
943 #define NX_RCODE_INVALID_ACTION 7
944 #define NX_RCODE_INVALID_STATE 8
945 #define NX_RCODE_NOT_SUPPORTED 9
946 #define NX_RCODE_NOT_PERMITTED 10
947 #define NX_RCODE_NOT_READY 11
948 #define NX_RCODE_DOES_NOT_EXIST 12
949 #define NX_RCODE_ALREADY_EXISTS 13
950 #define NX_RCODE_BAD_SIGNATURE 14
951 #define NX_RCODE_CMD_NOT_IMPL 15
952 #define NX_RCODE_CMD_INVALID 16
953 #define NX_RCODE_TIMEOUT 17
954 #define NX_RCODE_CMD_FAILED 18
955 #define NX_RCODE_MAX_EXCEEDED 19
956 #define NX_RCODE_MAX 20
958 #define NX_DESTROY_CTX_RESET 0
959 #define NX_DESTROY_CTX_D3_RESET 1
960 #define NX_DESTROY_CTX_MAX 2
965 #define NX_CAP_BIT(class, bit) (1 << bit)
966 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
967 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
968 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
969 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
970 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
971 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
972 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
973 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
974 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
979 #define NX_HOST_CTX_STATE_FREED 0
980 #define NX_HOST_CTX_STATE_ALLOCATED 1
981 #define NX_HOST_CTX_STATE_ACTIVE 2
982 #define NX_HOST_CTX_STATE_DISABLED 3
983 #define NX_HOST_CTX_STATE_QUIESCED 4
984 #define NX_HOST_CTX_STATE_MAX 5
991 __le64 host_phys_addr; /* Ring base addr */
992 __le32 ring_size; /* Ring entries */
994 __le16 rsvd; /* Padding */
995 } nx_hostrq_sds_ring_t;
998 __le64 host_phys_addr; /* Ring base addr */
999 __le64 buff_size; /* Packet buffer size */
1000 __le32 ring_size; /* Ring entries */
1001 __le32 ring_kind; /* Class of ring */
1002 } nx_hostrq_rds_ring_t;
1005 __le64 host_rsp_dma_addr; /* Response dma'd here */
1006 __le32 capabilities[4]; /* Flag bit vector */
1007 __le32 host_int_crb_mode; /* Interrupt crb usage */
1008 __le32 host_rds_crb_mode; /* RDS crb usage */
1009 /* These ring offsets are relative to data[0] below */
1010 __le32 rds_ring_offset; /* Offset to RDS config */
1011 __le32 sds_ring_offset; /* Offset to SDS config */
1012 __le16 num_rds_rings; /* Count of RDS rings */
1013 __le16 num_sds_rings; /* Count of SDS rings */
1014 __le16 rsvd1; /* Padding */
1015 __le16 rsvd2; /* Padding */
1016 u8 reserved[128]; /* reserve space for future expansion*/
1017 /* MUST BE 64-bit aligned.
1018 The following is packed:
1019 - N hostrq_rds_rings
1020 - N hostrq_sds_rings */
1022 } nx_hostrq_rx_ctx_t;
1025 __le32 host_producer_crb; /* Crb to use */
1026 __le32 rsvd1; /* Padding */
1027 } nx_cardrsp_rds_ring_t;
1030 __le32 host_consumer_crb; /* Crb to use */
1031 __le32 interrupt_crb; /* Crb to use */
1032 } nx_cardrsp_sds_ring_t;
1035 /* These ring offsets are relative to data[0] below */
1036 __le32 rds_ring_offset; /* Offset to RDS config */
1037 __le32 sds_ring_offset; /* Offset to SDS config */
1038 __le32 host_ctx_state; /* Starting State */
1039 __le32 num_fn_per_port; /* How many PCI fn share the port */
1040 __le16 num_rds_rings; /* Count of RDS rings */
1041 __le16 num_sds_rings; /* Count of SDS rings */
1042 __le16 context_id; /* Handle for context */
1043 u8 phys_port; /* Physical id of port */
1044 u8 virt_port; /* Virtual/Logical id of port */
1045 u8 reserved[128]; /* save space for future expansion */
1046 /* MUST BE 64-bit aligned.
1047 The following is packed:
1048 - N cardrsp_rds_rings
1049 - N cardrs_sds_rings */
1051 } nx_cardrsp_rx_ctx_t;
1053 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
1054 (sizeof(HOSTRQ_RX) + \
1055 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
1056 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1058 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
1059 (sizeof(CARDRSP_RX) + \
1060 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
1061 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1068 __le64 host_phys_addr; /* Ring base addr */
1069 __le32 ring_size; /* Ring entries */
1070 __le32 rsvd; /* Padding */
1071 } nx_hostrq_cds_ring_t;
1074 __le64 host_rsp_dma_addr; /* Response dma'd here */
1075 __le64 cmd_cons_dma_addr; /* */
1076 __le64 dummy_dma_addr; /* */
1077 __le32 capabilities[4]; /* Flag bit vector */
1078 __le32 host_int_crb_mode; /* Interrupt crb usage */
1079 __le32 rsvd1; /* Padding */
1080 __le16 rsvd2; /* Padding */
1081 __le16 interrupt_ctl;
1083 __le16 rsvd3; /* Padding */
1084 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1085 u8 reserved[128]; /* future expansion */
1086 } nx_hostrq_tx_ctx_t;
1089 __le32 host_producer_crb; /* Crb to use */
1090 __le32 interrupt_crb; /* Crb to use */
1091 } nx_cardrsp_cds_ring_t;
1094 __le32 host_ctx_state; /* Starting state */
1095 __le16 context_id; /* Handle for context */
1096 u8 phys_port; /* Physical id of port */
1097 u8 virt_port; /* Virtual/Logical id of port */
1098 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1099 u8 reserved[128]; /* future expansion */
1100 } nx_cardrsp_tx_ctx_t;
1102 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
1103 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
1107 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1108 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1109 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1110 #define NX_HOST_RDS_CRB_MODE_MAX 3
1112 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1113 #define NX_HOST_INT_CRB_MODE_SHARED 1
1114 #define NX_HOST_INT_CRB_MODE_NORX 2
1115 #define NX_HOST_INT_CRB_MODE_NOTX 3
1116 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1121 #define MC_COUNT_P2 16
1122 #define MC_COUNT_P3 38
1124 #define NETXEN_MAC_NOOP 0
1125 #define NETXEN_MAC_ADD 1
1126 #define NETXEN_MAC_DEL 2
1128 typedef struct nx_mac_list_s {
1129 struct nx_mac_list_s *next;
1130 uint8_t mac_addr[MAX_ADDR_LEN];
1134 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1135 * adjusted based on configured MTU.
1137 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1138 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1139 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1140 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1142 #define NETXEN_NIC_INTR_DEFAULT 0x04
1146 uint16_t rx_packets;
1147 uint16_t rx_time_us;
1148 uint16_t tx_packets;
1149 uint16_t tx_time_us;
1152 } nx_nic_intr_coalesce_data_t;
1155 uint16_t stats_time_us;
1156 uint16_t rate_sample_time;
1159 uint32_t low_threshold;
1160 uint32_t high_threshold;
1161 nx_nic_intr_coalesce_data_t normal;
1162 nx_nic_intr_coalesce_data_t low;
1163 nx_nic_intr_coalesce_data_t high;
1164 nx_nic_intr_coalesce_data_t irq;
1165 } nx_nic_intr_coalesce_t;
1167 #define NX_HOST_REQUEST 0x13
1168 #define NX_NIC_REQUEST 0x14
1170 #define NX_MAC_EVENT 0x1
1173 NX_NIC_H2C_OPCODE_START = 0,
1174 NX_NIC_H2C_OPCODE_CONFIG_RSS,
1175 NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
1176 NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
1177 NX_NIC_H2C_OPCODE_CONFIG_LED,
1178 NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
1179 NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
1180 NX_NIC_H2C_OPCODE_LRO_REQUEST,
1181 NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
1182 NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
1183 NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
1184 NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
1185 NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
1186 NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
1187 NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
1188 NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
1189 NX_NIC_H2C_OPCODE_GET_NET_STATS,
1190 NX_NIC_H2C_OPCODE_LAST
1193 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1194 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1195 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1209 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1211 #define NETXEN_NIC_MSI_ENABLED 0x02
1212 #define NETXEN_NIC_MSIX_ENABLED 0x04
1213 #define NETXEN_IS_MSI_FAMILY(adapter) \
1214 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1216 #define MSIX_ENTRIES_PER_ADAPTER 1
1217 #define NETXEN_MSIX_TBL_SPACE 8192
1218 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1220 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1222 #define NETXEN_NETDEV_WEIGHT 120
1223 #define NETXEN_ADAPTER_UP_MAGIC 777
1224 #define NETXEN_NIC_PEG_TUNE 0
1226 struct netxen_dummy_dma {
1228 dma_addr_t phys_addr;
1231 struct netxen_adapter {
1232 struct netxen_hardware_context ahw;
1234 struct net_device *netdev;
1235 struct pci_dev *pdev;
1237 struct napi_struct napi;
1238 struct net_device_stats net_stats;
1245 uint8_t max_mc_count;
1246 nx_mac_list_t *mac_list;
1248 struct netxen_legacy_intr_set legacy_intr;
1251 struct work_struct watchdog_task;
1252 struct timer_list watchdog_timer;
1253 struct work_struct tx_timeout_task;
1257 rwlock_t adapter_lock;
1260 __le32 *cmd_consumer;
1261 u32 last_cmd_consumer;
1262 u32 crb_addr_cmd_producer;
1263 u32 crb_addr_cmd_consumer;
1265 u32 max_tx_desc_count;
1266 u32 max_rx_desc_count;
1267 u32 max_jumbo_rx_desc_count;
1268 u32 max_lro_rx_desc_count;
1274 int driver_mismatch;
1280 u8 max_possible_rss_rings;
1281 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1283 struct netxen_adapter_stats stats;
1292 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1295 * Receive instances. These can be either one per port,
1296 * or one per peg, etc.
1298 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
1301 struct netxen_dummy_dma dummy_dma;
1302 nx_nic_intr_coalesce_t coal;
1304 /* Context interface shared between card and host */
1305 struct netxen_ring_ctx *ctx_desc;
1306 dma_addr_t ctx_desc_phys_addr;
1309 int (*enable_phy_interrupts) (struct netxen_adapter *);
1310 int (*disable_phy_interrupts) (struct netxen_adapter *);
1311 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1312 int (*set_mtu) (struct netxen_adapter *, int);
1313 int (*set_promisc) (struct netxen_adapter *, u32);
1314 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1315 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1316 int (*init_port) (struct netxen_adapter *, int);
1317 int (*stop_port) (struct netxen_adapter *);
1319 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1320 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1321 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1322 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1323 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1324 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1325 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1326 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1327 unsigned long (*pci_set_window)(struct netxen_adapter *,
1328 unsigned long long);
1329 }; /* netxen_adapter structure */
1332 * NetXen dma watchdog control structure
1334 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1335 * Bit 1 : disable_request => 1 req disable dma watchdog
1336 * Bit 2 : enable_request => 1 req enable dma watchdog
1340 #define netxen_set_dma_watchdog_disable_req(config_word) \
1341 _netxen_set_bits(config_word, 1, 1, 1)
1342 #define netxen_set_dma_watchdog_enable_req(config_word) \
1343 _netxen_set_bits(config_word, 2, 1, 1)
1344 #define netxen_get_dma_watchdog_enabled(config_word) \
1345 ((config_word) & 0x1)
1346 #define netxen_get_dma_watchdog_disabled(config_word) \
1347 (((config_word) >> 1) & 0x1)
1349 /* Max number of xmit producer threads that can run simultaneously */
1350 #define MAX_XMIT_PRODUCERS 16
1352 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1353 ((adapter)->ahw.pci_base0 + (off))
1354 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1355 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1356 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1357 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1359 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1362 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1363 return (adapter->ahw.pci_base0 + off);
1364 } else if ((off < SECOND_PAGE_GROUP_END) &&
1365 (off >= SECOND_PAGE_GROUP_START)) {
1366 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1367 } else if ((off < THIRD_PAGE_GROUP_END) &&
1368 (off >= THIRD_PAGE_GROUP_START)) {
1369 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1374 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1377 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1378 return adapter->ahw.pci_base0;
1379 } else if ((off < SECOND_PAGE_GROUP_END) &&
1380 (off >= SECOND_PAGE_GROUP_START)) {
1381 return adapter->ahw.pci_base1;
1382 } else if ((off < THIRD_PAGE_GROUP_END) &&
1383 (off >= THIRD_PAGE_GROUP_START)) {
1384 return adapter->ahw.pci_base2;
1389 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1390 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1391 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1392 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1393 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1395 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1396 long reg, __u32 val);
1398 /* Functions available from netxen_nic_hw.c */
1399 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1400 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1401 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1402 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1403 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1404 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1405 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1406 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1408 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1410 int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1411 ulong off, void *data, int len);
1412 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1413 ulong off, void *data, int len);
1414 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1415 u64 off, void *data, int size);
1416 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1417 u64 off, void *data, int size);
1418 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1420 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1421 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1423 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1424 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1425 unsigned long long addr);
1426 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1429 int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1430 ulong off, void *data, int len);
1431 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1432 ulong off, void *data, int len);
1433 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1434 u64 off, void *data, int size);
1435 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1436 u64 off, void *data, int size);
1437 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1438 unsigned long off, int data);
1439 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1441 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1442 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1444 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1445 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1446 unsigned long long addr);
1448 /* Functions from netxen_nic_init.c */
1449 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1450 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1451 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1452 int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1453 int netxen_load_firmware(struct netxen_adapter *adapter);
1454 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1456 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1457 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1458 u8 *bytes, size_t size);
1459 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1460 u8 *bytes, size_t size);
1461 int netxen_flash_unlock(struct netxen_adapter *adapter);
1462 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1463 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1464 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1465 void netxen_halt_pegs(struct netxen_adapter *adapter);
1467 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1469 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1470 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1472 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1473 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1475 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1476 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1478 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1479 int netxen_init_firmware(struct netxen_adapter *adapter);
1480 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1481 void netxen_watchdog_task(struct work_struct *work);
1482 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1484 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1485 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1486 void netxen_p2_nic_set_multi(struct net_device *netdev);
1487 void netxen_p3_nic_set_multi(struct net_device *netdev);
1488 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1489 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1490 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1492 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1493 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1495 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1496 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1498 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1499 uint32_t crb_producer);
1502 * NetXen Board information
1505 #define NETXEN_MAX_SHORT_NAME 32
1506 struct netxen_brdinfo {
1507 netxen_brdtype_t brdtype; /* type of board */
1508 long ports; /* max no of physical ports */
1509 char short_name[NETXEN_MAX_SHORT_NAME];
1512 static const struct netxen_brdinfo netxen_boards[] = {
1513 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1514 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1515 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1516 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1517 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1518 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1519 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1520 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1521 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1522 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1523 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1524 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1525 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1526 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1527 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1528 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1529 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1530 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1531 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1534 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1536 static inline void get_brd_name_by_type(u32 type, char *name)
1539 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1540 if (netxen_boards[i].brdtype == type) {
1541 strcpy(name, netxen_boards[i].short_name);
1552 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1556 /* check if already inactive */
1557 if (adapter->hw_read_wx(adapter,
1558 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1559 printk(KERN_ERR "failed to read dma watchdog status\n");
1561 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1564 /* Send the disable request */
1565 netxen_set_dma_watchdog_disable_req(ctrl);
1566 netxen_crb_writelit_adapter(adapter,
1567 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1573 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1577 if (adapter->hw_read_wx(adapter,
1578 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1579 printk(KERN_ERR "failed to read dma watchdog status\n");
1581 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1585 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1589 if (adapter->hw_read_wx(adapter,
1590 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1591 printk(KERN_ERR "failed to read dma watchdog status\n");
1593 if (netxen_get_dma_watchdog_enabled(ctrl))
1596 /* send the wakeup request */
1597 netxen_set_dma_watchdog_enable_req(ctrl);
1599 netxen_crb_writelit_adapter(adapter,
1600 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1606 int netxen_is_flash_supported(struct netxen_adapter *adapter);
1607 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1608 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1609 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1610 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1613 extern struct ethtool_ops netxen_nic_ethtool_ops;
1615 #endif /* __NETXEN_NIC_H_ */