git.oblomov.eu Git - linux-2.6/blob - arch/ppc/syslib/open_pic.c

   1 /*
   2  *  Copyright (C) 1997 Geert Uytterhoeven
   3  *
   4  *  This file is subject to the terms and conditions of the GNU General Public
   5  *  License.  See the file COPYING in the main directory of this archive
   6  *  for more details.
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/sched.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/sysdev.h>
  16 #include <linux/errno.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/signal.h>
  19 #include <asm/io.h>
  20 #include <asm/irq.h>
  21 #include <asm/sections.h>
  22 #include <asm/open_pic.h>
  23 #include <asm/i8259.h>
  24 #include <asm/machdep.h>
  25
  26 #include "open_pic_defs.h"
  27
  28 #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)
  29 #define OPENPIC_BIG_ENDIAN
  30 #endif
  31
  32 void __iomem *OpenPIC_Addr;
  33 static volatile struct OpenPIC __iomem *OpenPIC = NULL;
  34
  35 /*
  36  * We define OpenPIC_InitSenses table thusly:
  37  * bit 0x1: sense, 0 for edge and 1 for level.
  38  * bit 0x2: polarity, 0 for negative, 1 for positive.
  39  */
  40 u_int OpenPIC_NumInitSenses __initdata = 0;
  41 u_char *OpenPIC_InitSenses __initdata = NULL;
  42 extern int use_of_interrupt_tree;
  43
  44 static u_int NumProcessors;
  45 static u_int NumSources;
  46 static int open_pic_irq_offset;
  47 static volatile OpenPIC_Source __iomem *ISR[NR_IRQS];
  48 static int openpic_cascade_irq = -1;
  49 static int (*openpic_cascade_fn)(struct pt_regs *);
  50
  51 /* Global Operations */
  52 static void openpic_disable_8259_pass_through(void);
  53 static void openpic_set_spurious(u_int vector);
  54
  55 #ifdef CONFIG_SMP
  56 /* Interprocessor Interrupts */
  57 static void openpic_initipi(u_int ipi, u_int pri, u_int vector);
  58 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *);
  59 #endif
  60
  61 /* Timer Interrupts */
  62 static void openpic_inittimer(u_int timer, u_int pri, u_int vector);
  63 static void openpic_maptimer(u_int timer, cpumask_t cpumask);
  64
  65 /* Interrupt Sources */
  66 static void openpic_enable_irq(u_int irq);
  67 static void openpic_disable_irq(u_int irq);
  68 static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
  69                             int is_level);
  70 static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
  71
  72 /*
  73  * These functions are not used but the code is kept here
  74  * for completeness and future reference.
  75  */
  76 #ifdef notused
  77 static void openpic_enable_8259_pass_through(void);
  78 static u_int openpic_get_spurious(void);
  79 static void openpic_set_sense(u_int irq, int sense);
  80 #endif /* notused */
  81
  82 /*
  83  * Description of the openpic for the higher-level irq code
  84  */
  85 static void openpic_end_irq(unsigned int irq_nr);
  86 static void openpic_ack_irq(unsigned int irq_nr);
  87 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask);
  88
  89 struct hw_interrupt_type open_pic = {
  90         .typename       = " OpenPIC  ",
  91         .enable         = openpic_enable_irq,
  92         .disable        = openpic_disable_irq,
  93         .ack            = openpic_ack_irq,
  94         .end            = openpic_end_irq,
  95         .set_affinity   = openpic_set_affinity,
  96 };
  97
  98 #ifdef CONFIG_SMP
  99 static void openpic_end_ipi(unsigned int irq_nr);
 100 static void openpic_ack_ipi(unsigned int irq_nr);
 101 static void openpic_enable_ipi(unsigned int irq_nr);
 102 static void openpic_disable_ipi(unsigned int irq_nr);
 103
 104 struct hw_interrupt_type open_pic_ipi = {
 105         .typename       = " OpenPIC  ",
 106         .enable         = openpic_enable_ipi,
 107         .disable        = openpic_disable_ipi,
 108         .ack            = openpic_ack_ipi,
 109         .end            = openpic_end_ipi,
 110 };
 111 #endif /* CONFIG_SMP */
 112
 113 /*
 114  *  Accesses to the current processor's openpic registers
 115  */
 116 #ifdef CONFIG_SMP
 117 #define THIS_CPU                Processor[cpu]
 118 #define DECL_THIS_CPU           int cpu = smp_hw_index[smp_processor_id()]
 119 #define CHECK_THIS_CPU          check_arg_cpu(cpu)
 120 #else
 121 #define THIS_CPU                Processor[0]
 122 #define DECL_THIS_CPU
 123 #define CHECK_THIS_CPU
 124 #endif /* CONFIG_SMP */
 125
 126 #if 1
 127 #define check_arg_ipi(ipi) \
 128     if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
 129         printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);
 130 #define check_arg_timer(timer) \
 131     if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
 132         printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);
 133 #define check_arg_vec(vec) \
 134     if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
 135         printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);
 136 #define check_arg_pri(pri) \
 137     if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
 138         printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);
 139 /*
 140  * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
 141  * data has probably been corrupted and we're going to panic or deadlock later
 142  * anyway --Troy
 143  */
 144 #define check_arg_irq(irq) \
 145     if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \
 146         || ISR[irq - open_pic_irq_offset] == 0) { \
 147       printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \
 148       dump_stack(); }
 149 #define check_arg_cpu(cpu) \
 150     if (cpu < 0 || cpu >= NumProcessors){ \
 151         printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \
 152         dump_stack(); }
 153 #else
 154 #define check_arg_ipi(ipi)      do {} while (0)
 155 #define check_arg_timer(timer)  do {} while (0)
 156 #define check_arg_vec(vec)      do {} while (0)
 157 #define check_arg_pri(pri)      do {} while (0)
 158 #define check_arg_irq(irq)      do {} while (0)
 159 #define check_arg_cpu(cpu)      do {} while (0)
 160 #endif
 161
 162 u_int openpic_read(volatile u_int __iomem *addr)
 163 {
 164         u_int val;
 165
 166 #ifdef OPENPIC_BIG_ENDIAN
 167         val = in_be32(addr);
 168 #else
 169         val = in_le32(addr);
 170 #endif
 171         return val;
 172 }
 173
 174 static inline void openpic_write(volatile u_int __iomem *addr, u_int val)
 175 {
 176 #ifdef OPENPIC_BIG_ENDIAN
 177         out_be32(addr, val);
 178 #else
 179         out_le32(addr, val);
 180 #endif
 181 }
 182
 183 static inline u_int openpic_readfield(volatile u_int __iomem *addr, u_int mask)
 184 {
 185         u_int val = openpic_read(addr);
 186         return val & mask;
 187 }
 188
 189 inline void openpic_writefield(volatile u_int __iomem *addr, u_int mask,
 190                                u_int field)
 191 {
 192         u_int val = openpic_read(addr);
 193         openpic_write(addr, (val & ~mask) | (field & mask));
 194 }
 195
 196 static inline void openpic_clearfield(volatile u_int __iomem *addr, u_int mask)
 197 {
 198         openpic_writefield(addr, mask, 0);
 199 }
 200
 201 static inline void openpic_setfield(volatile u_int __iomem *addr, u_int mask)
 202 {
 203         openpic_writefield(addr, mask, mask);
 204 }
 205
 206 static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask,
 207                                     u_int field)
 208 {
 209         openpic_setfield(addr, OPENPIC_MASK);
 210         while (openpic_read(addr) & OPENPIC_ACTIVITY);
 211         openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 212 }
 213
 214 #ifdef CONFIG_SMP
 215 /* yes this is right ... bug, feature, you decide! -- tgall */
 216 u_int openpic_read_IPI(volatile u_int __iomem * addr)
 217 {
 218          u_int val = 0;
 219 #if defined(OPENPIC_BIG_ENDIAN)
 220         val = in_be32(addr);
 221 #else
 222         val = in_le32(addr);
 223 #endif
 224         return val;
 225 }
 226
 227 /* because of the power3 be / le above, this is needed */
 228 inline void openpic_writefield_IPI(volatile u_int __iomem * addr, u_int mask, u_int field)
 229 {
 230         u_int  val = openpic_read_IPI(addr);
 231         openpic_write(addr, (val & ~mask) | (field & mask));
 232 }
 233
 234 static inline void openpic_clearfield_IPI(volatile u_int __iomem *addr, u_int mask)
 235 {
 236         openpic_writefield_IPI(addr, mask, 0);
 237 }
 238
 239 static inline void openpic_setfield_IPI(volatile u_int __iomem *addr, u_int mask)
 240 {
 241         openpic_writefield_IPI(addr, mask, mask);
 242 }
 243
 244 static void openpic_safe_writefield_IPI(volatile u_int __iomem *addr, u_int mask, u_int field)
 245 {
 246         openpic_setfield_IPI(addr, OPENPIC_MASK);
 247
 248         /* wait until it's not in use */
 249         /* BenH: Is this code really enough ? I would rather check the result
 250          *       and eventually retry ...
 251          */
 252         while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
 253
 254         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
 255 }
 256 #endif /* CONFIG_SMP */
 257
 258 #ifdef CONFIG_EPIC_SERIAL_MODE
 259 /* On platforms that may use EPIC serial mode, the default is enabled. */
 260 int epic_serial_mode = 1;
 261
 262 static void __init openpic_eicr_set_clk(u_int clkval)
 263 {
 264         openpic_writefield(&OpenPIC->Global.Global_Configuration1,
 265                         OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
 266 }
 267
 268 static void __init openpic_enable_sie(void)
 269 {
 270         openpic_setfield(&OpenPIC->Global.Global_Configuration1,
 271                         OPENPIC_EICR_SIE);
 272 }
 273 #endif
 274
 275 #if defined(CONFIG_EPIC_SERIAL_MODE)
 276 static void openpic_reset(void)
 277 {
 278         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 279                          OPENPIC_CONFIG_RESET);
 280         while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
 281                                  OPENPIC_CONFIG_RESET))
 282                 mb();
 283 }
 284 #endif
 285
 286 void __init openpic_set_sources(int first_irq, int num_irqs, void __iomem *first_ISR)
 287 {
 288         volatile OpenPIC_Source __iomem *src = first_ISR;
 289         int i, last_irq;
 290
 291         last_irq = first_irq + num_irqs;
 292         if (last_irq > NumSources)
 293                 NumSources = last_irq;
 294         if (src == 0)
 295                 src = &((struct OpenPIC __iomem *)OpenPIC_Addr)->Source[first_irq];
 296         for (i = first_irq; i < last_irq; ++i, ++src)
 297                 ISR[i] = src;
 298 }
 299
 300 /*
 301  * The `offset' parameter defines where the interrupts handled by the
 302  * OpenPIC start in the space of interrupt numbers that the kernel knows
 303  * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the
 304  * kernel's interrupt numbering scheme.
 305  * We assume there is only one OpenPIC.
 306  */
 307 void __init openpic_init(int offset)
 308 {
 309         u_int t, i;
 310         u_int timerfreq;
 311         const char *version;
 312
 313         if (!OpenPIC_Addr) {
 314                 printk("No OpenPIC found !\n");
 315                 return;
 316         }
 317         OpenPIC = (volatile struct OpenPIC __iomem *)OpenPIC_Addr;
 318
 319 #ifdef CONFIG_EPIC_SERIAL_MODE
 320         /* Have to start from ground zero.
 321         */
 322         openpic_reset();
 323 #endif
 324
 325         if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
 326
 327         t = openpic_read(&OpenPIC->Global.Feature_Reporting0);
 328         switch (t & OPENPIC_FEATURE_VERSION_MASK) {
 329         case 1:
 330                 version = "1.0";
 331                 break;
 332         case 2:
 333                 version = "1.2";
 334                 break;
 335         case 3:
 336                 version = "1.3";
 337                 break;
 338         default:
 339                 version = "?";
 340                 break;
 341         }
 342         NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
 343                          OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
 344         if (NumSources == 0)
 345                 openpic_set_sources(0,
 346                                     ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
 347                                      OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
 348                                     NULL);
 349         printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
 350                version, NumProcessors, NumSources, OpenPIC);
 351         timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
 352         if (timerfreq)
 353                 printk("OpenPIC timer frequency is %d.%06d MHz\n",
 354                        timerfreq / 1000000, timerfreq % 1000000);
 355
 356         open_pic_irq_offset = offset;
 357
 358         /* Initialize timer interrupts */
 359         if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
 360         for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
 361                 /* Disabled, Priority 0 */
 362                 openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
 363                 /* No processor */
 364                 openpic_maptimer(i, CPU_MASK_NONE);
 365         }
 366
 367 #ifdef CONFIG_SMP
 368         /* Initialize IPI interrupts */
 369         if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
 370         for (i = 0; i < OPENPIC_NUM_IPI; i++) {
 371                 /* Disabled, increased priorities 10..13 */
 372                 openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i,
 373                                 OPENPIC_VEC_IPI+i+offset);
 374                 /* IPIs are per-CPU */
 375                 irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
 376                 irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
 377         }
 378 #endif
 379
 380         /* Initialize external interrupts */
 381         if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc);
 382
 383         openpic_set_priority(0xf);
 384
 385         /* Init all external sources, including possibly the cascade. */
 386         for (i = 0; i < NumSources; i++) {
 387                 int sense;
 388
 389                 if (ISR[i] == 0)
 390                         continue;
 391
 392                 /* the bootloader may have left it enabled (bad !) */
 393                 openpic_disable_irq(i+offset);
 394
 395                 sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
 396                                 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
 397
 398                 if (sense & IRQ_SENSE_MASK)
 399                         irq_desc[i+offset].status = IRQ_LEVEL;
 400
 401                 /* Enabled, Default priority */
 402                 openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset,
 403                                 (sense & IRQ_POLARITY_MASK),
 404                                 (sense & IRQ_SENSE_MASK));
 405                 /* Processor 0 */
 406                 openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
 407         }
 408
 409         /* Init descriptors */
 410         for (i = offset; i < NumSources + offset; i++)
 411                 irq_desc[i].handler = &open_pic;
 412
 413         /* Initialize the spurious interrupt */
 414         if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
 415         openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
 416         openpic_disable_8259_pass_through();
 417 #ifdef CONFIG_EPIC_SERIAL_MODE
 418         if (epic_serial_mode) {
 419                 openpic_eicr_set_clk(7);        /* Slowest value until we know better */
 420                 openpic_enable_sie();
 421         }
 422 #endif
 423         openpic_set_priority(0);
 424
 425         if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);
 426 }
 427
 428 #ifdef notused
 429 static void openpic_enable_8259_pass_through(void)
 430 {
 431         openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
 432                            OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 433 }
 434 #endif /* notused */
 435
 436 static void openpic_disable_8259_pass_through(void)
 437 {
 438         openpic_setfield(&OpenPIC->Global.Global_Configuration0,
 439                          OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
 440 }
 441
 442 /*
 443  *  Find out the current interrupt
 444  */
 445 u_int openpic_irq(void)
 446 {
 447         u_int vec;
 448         DECL_THIS_CPU;
 449
 450         CHECK_THIS_CPU;
 451         vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
 452                                 OPENPIC_VECTOR_MASK);
 453         return vec;
 454 }
 455
 456 void openpic_eoi(void)
 457 {
 458         DECL_THIS_CPU;
 459
 460         CHECK_THIS_CPU;
 461         openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
 462         /* Handle PCI write posting */
 463         (void)openpic_read(&OpenPIC->THIS_CPU.EOI);
 464 }
 465
 466 u_int openpic_get_priority(void)
 467 {
 468         DECL_THIS_CPU;
 469
 470         CHECK_THIS_CPU;
 471         return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 472                                  OPENPIC_CURRENT_TASK_PRIORITY_MASK);
 473 }
 474
 475 void openpic_set_priority(u_int pri)
 476 {
 477         DECL_THIS_CPU;
 478
 479         CHECK_THIS_CPU;
 480         check_arg_pri(pri);
 481         openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
 482                            OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
 483 }
 484
 485 /*
 486  *  Get/set the spurious vector
 487  */
 488 #ifdef notused
 489 static u_int openpic_get_spurious(void)
 490 {
 491         return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
 492                                  OPENPIC_VECTOR_MASK);
 493 }
 494 #endif /* notused */
 495
 496 static void openpic_set_spurious(u_int vec)
 497 {
 498         check_arg_vec(vec);
 499         openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
 500                            vec);
 501 }
 502
 503 #ifdef CONFIG_SMP
 504 /*
 505  * Convert a cpu mask from logical to physical cpu numbers.
 506  */
 507 static inline cpumask_t physmask(cpumask_t cpumask)
 508 {
 509         int i;
 510         cpumask_t mask = CPU_MASK_NONE;
 511
 512         cpus_and(cpumask, cpu_online_map, cpumask);
 513
 514         for (i = 0; i < NR_CPUS; i++)
 515                 if (cpu_isset(i, cpumask))
 516                         cpu_set(smp_hw_index[i], mask);
 517
 518         return mask;
 519 }
 520 #else
 521 #define physmask(cpumask)       (cpumask)
 522 #endif
 523
 524 void openpic_reset_processor_phys(u_int mask)
 525 {
 526         openpic_write(&OpenPIC->Global.Processor_Initialization, mask);
 527 }
 528
 529 #if defined(CONFIG_SMP) || defined(CONFIG_PM)
 530 static DEFINE_SPINLOCK(openpic_setup_lock);
 531 #endif
 532
 533 #ifdef CONFIG_SMP
 534 /*
 535  *  Initialize an interprocessor interrupt (and disable it)
 536  *
 537  *  ipi: OpenPIC interprocessor interrupt number
 538  *  pri: interrupt source priority
 539  *  vec: the vector it will produce
 540  */
 541 static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
 542 {
 543         check_arg_ipi(ipi);
 544         check_arg_pri(pri);
 545         check_arg_vec(vec);
 546         openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
 547                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 548                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 549 }
 550
 551 /*
 552  *  Send an IPI to one or more CPUs
 553  *
 554  *  Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
 555  *  and not a system-wide interrupt number
 556  */
 557 void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
 558 {
 559         DECL_THIS_CPU;
 560
 561         CHECK_THIS_CPU;
 562         check_arg_ipi(ipi);
 563         openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
 564                       cpus_addr(physmask(cpumask))[0]);
 565 }
 566
 567 void openpic_request_IPIs(void)
 568 {
 569         int i;
 570
 571         /*
 572          * Make sure this matches what is defined in smp.c for
 573          * smp_message_{pass|recv}() or what shows up in
 574          * /proc/interrupts will be wrong!!! --Troy */
 575
 576         if (OpenPIC == NULL)
 577                 return;
 578
 579         /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */
 580         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
 581                     openpic_ipi_action, SA_INTERRUPT,
 582                     "IPI0 (call function)", NULL);
 583         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
 584                     openpic_ipi_action, SA_INTERRUPT,
 585                     "IPI1 (reschedule)", NULL);
 586         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
 587                     openpic_ipi_action, SA_INTERRUPT,
 588                     "IPI2 (invalidate tlb)", NULL);
 589         request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
 590                     openpic_ipi_action, SA_INTERRUPT,
 591                     "IPI3 (xmon break)", NULL);
 592
 593         for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
 594                 openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
 595 }
 596
 597 /*
 598  * Do per-cpu setup for SMP systems.
 599  *
 600  * Get IPI's working and start taking interrupts.
 601  *   -- Cort
 602  */
 603
 604 void __devinit do_openpic_setup_cpu(void)
 605 {
 606 #ifdef CONFIG_IRQ_ALL_CPUS
 607         int i;
 608         cpumask_t msk = CPU_MASK_NONE;
 609 #endif
 610         spin_lock(&openpic_setup_lock);
 611
 612 #ifdef CONFIG_IRQ_ALL_CPUS
 613         cpu_set(smp_hw_index[smp_processor_id()], msk);
 614
 615         /* let the openpic know we want intrs. default affinity
 616          * is 0xffffffff until changed via /proc
 617          * That's how it's done on x86. If we want it differently, then
 618          * we should make sure we also change the default values of irq_affinity
 619          * in irq.c.
 620          */
 621         for (i = 0; i < NumSources; i++)
 622                 openpic_mapirq(i, msk, CPU_MASK_ALL);
 623 #endif /* CONFIG_IRQ_ALL_CPUS */
 624         openpic_set_priority(0);
 625
 626         spin_unlock(&openpic_setup_lock);
 627 }
 628 #endif /* CONFIG_SMP */
 629
 630 /*
 631  *  Initialize a timer interrupt (and disable it)
 632  *
 633  *  timer: OpenPIC timer number
 634  *  pri: interrupt source priority
 635  *  vec: the vector it will produce
 636  */
 637 static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
 638 {
 639         check_arg_timer(timer);
 640         check_arg_pri(pri);
 641         check_arg_vec(vec);
 642         openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority,
 643                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
 644                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec);
 645 }
 646
 647 /*
 648  *  Map a timer interrupt to one or more CPUs
 649  */
 650 static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
 651 {
 652         cpumask_t phys = physmask(cpumask);
 653         check_arg_timer(timer);
 654         openpic_write(&OpenPIC->Global.Timer[timer].Destination,
 655                       cpus_addr(phys)[0]);
 656 }
 657
 658 /*
 659  * Change the priority of an interrupt
 660  */
 661 void __init
 662 openpic_set_irq_priority(u_int irq, u_int pri)
 663 {
 664         check_arg_irq(irq);
 665         openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
 666                                 OPENPIC_PRIORITY_MASK,
 667                                 pri << OPENPIC_PRIORITY_SHIFT);
 668 }
 669
 670 /*
 671  * Initalize the interrupt source which will generate an NMI.
 672  * This raises the interrupt's priority from 8 to 9.
 673  *
 674  * irq: The logical IRQ which generates an NMI.
 675  */
 676 void __init
 677 openpic_init_nmi_irq(u_int irq)
 678 {
 679         check_arg_irq(irq);
 680         openpic_set_irq_priority(irq, OPENPIC_PRIORITY_NMI);
 681 }
 682
 683 /*
 684  *
 685  * All functions below take an offset'ed irq argument
 686  *
 687  */
 688
 689 /*
 690  * Hookup a cascade to the OpenPIC.
 691  */
 692
 693 static struct irqaction openpic_cascade_irqaction = {
 694         .handler = no_action,
 695         .flags = SA_INTERRUPT,
 696         .mask = CPU_MASK_NONE,
 697 };
 698
 699 void __init
 700 openpic_hookup_cascade(u_int irq, char *name,
 701         int (*cascade_fn)(struct pt_regs *))
 702 {
 703         openpic_cascade_irq = irq;
 704         openpic_cascade_fn = cascade_fn;
 705
 706         if (setup_irq(irq, &openpic_cascade_irqaction))
 707                 printk("Unable to get OpenPIC IRQ %d for cascade\n",
 708                                 irq - open_pic_irq_offset);
 709 }
 710
 711 /*
 712  *  Enable/disable an external interrupt source
 713  *
 714  *  Externally called, irq is an offseted system-wide interrupt number
 715  */
 716 static void openpic_enable_irq(u_int irq)
 717 {
 718         volatile u_int __iomem *vpp;
 719
 720         check_arg_irq(irq);
 721         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 722         openpic_clearfield(vpp, OPENPIC_MASK);
 723         /* make sure mask gets to controller before we return to user */
 724         do {
 725                 mb(); /* sync is probably useless here */
 726         } while (openpic_readfield(vpp, OPENPIC_MASK));
 727 }
 728
 729 static void openpic_disable_irq(u_int irq)
 730 {
 731         volatile u_int __iomem *vpp;
 732         u32 vp;
 733
 734         check_arg_irq(irq);
 735         vpp = &ISR[irq - open_pic_irq_offset]->Vector_Priority;
 736         openpic_setfield(vpp, OPENPIC_MASK);
 737         /* make sure mask gets to controller before we return to user */
 738         do {
 739                 mb();  /* sync is probably useless here */
 740                 vp = openpic_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
 741         } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
 742 }
 743
 744 #ifdef CONFIG_SMP
 745 /*
 746  *  Enable/disable an IPI interrupt source
 747  *
 748  *  Externally called, irq is an offseted system-wide interrupt number
 749  */
 750 void openpic_enable_ipi(u_int irq)
 751 {
 752         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 753         check_arg_ipi(irq);
 754         openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 755
 756 }
 757
 758 void openpic_disable_ipi(u_int irq)
 759 {
 760         irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
 761         check_arg_ipi(irq);
 762         openpic_setfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
 763 }
 764 #endif
 765
 766 /*
 767  *  Initialize an interrupt source (and disable it!)
 768  *
 769  *  irq: OpenPIC interrupt number
 770  *  pri: interrupt source priority
 771  *  vec: the vector it will produce
 772  *  pol: polarity (1 for positive, 0 for negative)
 773  *  sense: 1 for level, 0 for edge
 774  */
 775 static void __init
 776 openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
 777 {
 778         openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 779                                 OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 780                                 OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
 781                                 (pri << OPENPIC_PRIORITY_SHIFT) | vec |
 782                                 (pol ? OPENPIC_POLARITY_POSITIVE :
 783                                         OPENPIC_POLARITY_NEGATIVE) |
 784                                 (sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
 785 }
 786
 787 /*
 788  *  Map an interrupt source to one or more CPUs
 789  */
 790 static void openpic_mapirq(u_int irq, cpumask_t physmask, cpumask_t keepmask)
 791 {
 792         if (ISR[irq] == 0)
 793                 return;
 794         if (!cpus_empty(keepmask)) {
 795                 cpumask_t irqdest = { .bits[0] = openpic_read(&ISR[irq]->Destination) };
 796                 cpus_and(irqdest, irqdest, keepmask);
 797                 cpus_or(physmask, physmask, irqdest);
 798         }
 799         openpic_write(&ISR[irq]->Destination, cpus_addr(physmask)[0]);
 800 }
 801
 802 #ifdef notused
 803 /*
 804  *  Set the sense for an interrupt source (and disable it!)
 805  *
 806  *  sense: 1 for level, 0 for edge
 807  */
 808 static void openpic_set_sense(u_int irq, int sense)
 809 {
 810         if (ISR[irq] != 0)
 811                 openpic_safe_writefield(&ISR[irq]->Vector_Priority,
 812                                         OPENPIC_SENSE_LEVEL,
 813                                         (sense ? OPENPIC_SENSE_LEVEL : 0));
 814 }
 815 #endif /* notused */
 816
 817 /* No spinlocks, should not be necessary with the OpenPIC
 818  * (1 register = 1 interrupt and we have the desc lock).
 819  */
 820 static void openpic_ack_irq(unsigned int irq_nr)
 821 {
 822 #ifdef __SLOW_VERSION__
 823         openpic_disable_irq(irq_nr);
 824         openpic_eoi();
 825 #else
 826         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
 827                 openpic_eoi();
 828 #endif
 829 }
 830
 831 static void openpic_end_irq(unsigned int irq_nr)
 832 {
 833 #ifdef __SLOW_VERSION__
 834         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
 835             && irq_desc[irq_nr].action)
 836                 openpic_enable_irq(irq_nr);
 837 #else
 838         if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
 839                 openpic_eoi();
 840 #endif
 841 }
 842
 843 static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask)
 844 {
 845         openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask), CPU_MASK_NONE);
 846 }
 847
 848 #ifdef CONFIG_SMP
 849 static void openpic_ack_ipi(unsigned int irq_nr)
 850 {
 851         openpic_eoi();
 852 }
 853
 854 static void openpic_end_ipi(unsigned int irq_nr)
 855 {
 856 }
 857
 858 static irqreturn_t openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 859 {
 860         smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
 861         return IRQ_HANDLED;
 862 }
 863
 864 #endif /* CONFIG_SMP */
 865
 866 int
 867 openpic_get_irq(struct pt_regs *regs)
 868 {
 869         int irq = openpic_irq();
 870
 871         /*
 872          * Check for the cascade interrupt and call the cascaded
 873          * interrupt controller function (usually i8259_irq) if so.
 874          * This should move to irq.c eventually.  -- paulus
 875          */
 876         if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
 877                 int cirq = openpic_cascade_fn(regs);
 878
 879                 /* Allow for the cascade being shared with other devices */
 880                 if (cirq != -1) {
 881                         irq = cirq;
 882                         openpic_eoi();
 883                 }
 884         } else if (irq == OPENPIC_VEC_SPURIOUS)
 885                 irq = -1;
 886         return irq;
 887 }
 888
 889 #ifdef CONFIG_SMP
 890 void
 891 smp_openpic_message_pass(int target, int msg)
 892 {
 893         cpumask_t mask = CPU_MASK_ALL;
 894         /* make sure we're sending something that translates to an IPI */
 895         if (msg > 0x3) {
 896                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
 897                        smp_processor_id(), msg);
 898                 return;
 899         }
 900         switch (target) {
 901         case MSG_ALL:
 902                 openpic_cause_IPI(msg, mask);
 903                 break;
 904         case MSG_ALL_BUT_SELF:
 905                 cpu_clear(smp_processor_id(), mask);
 906                 openpic_cause_IPI(msg, mask);
 907                 break;
 908         default:
 909                 openpic_cause_IPI(msg, cpumask_of_cpu(target));
 910                 break;
 911         }
 912 }
 913 #endif /* CONFIG_SMP */
 914
 915 #ifdef CONFIG_PM
 916
 917 /*
 918  * We implement the IRQ controller as a sysdev and put it
 919  * to sleep at powerdown stage (the callback is named suspend,
 920  * but it's old semantics, for the Device Model, it's really
 921  * powerdown). The possible problem is that another sysdev that
 922  * happens to be suspend after this one will have interrupts off,
 923  * that may be an issue... For now, this isn't an issue on pmac
 924  * though...
 925  */
 926
 927 static u32 save_ipi_vp[OPENPIC_NUM_IPI];
 928 static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
 929 static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
 930 static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
 931 static int openpic_suspend_count;
 932
 933 static void openpic_cached_enable_irq(u_int irq)
 934 {
 935         check_arg_irq(irq);
 936         save_irq_src_vp[irq - open_pic_irq_offset] &= ~OPENPIC_MASK;
 937 }
 938
 939 static void openpic_cached_disable_irq(u_int irq)
 940 {
 941         check_arg_irq(irq);
 942         save_irq_src_vp[irq - open_pic_irq_offset] |= OPENPIC_MASK;
 943 }
 944
 945 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 946  * we need something better to deal with that... Maybe switch to S1 for
 947  * cpufreq changes
 948  */
 949 int openpic_suspend(struct sys_device *sysdev, pm_message_t state)
 950 {
 951         int     i;
 952         unsigned long flags;
 953
 954         spin_lock_irqsave(&openpic_setup_lock, flags);
 955
 956         if (openpic_suspend_count++ > 0) {
 957                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
 958                 return 0;
 959         }
 960
 961         openpic_set_priority(0xf);
 962
 963         open_pic.enable = openpic_cached_enable_irq;
 964         open_pic.disable = openpic_cached_disable_irq;
 965
 966         for (i=0; i<NumProcessors; i++) {
 967                 save_cpu_task_pri[i] = openpic_read(&OpenPIC->Processor[i].Current_Task_Priority);
 968                 openpic_writefield(&OpenPIC->Processor[i].Current_Task_Priority,
 969                                    OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
 970         }
 971
 972         for (i=0; i<OPENPIC_NUM_IPI; i++)
 973                 save_ipi_vp[i] = openpic_read(&OpenPIC->Global.IPI_Vector_Priority(i));
 974         for (i=0; i<NumSources; i++) {
 975                 if (ISR[i] == 0)
 976                         continue;
 977                 save_irq_src_vp[i] = openpic_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
 978                 save_irq_src_dest[i] = openpic_read(&ISR[i]->Destination);
 979         }
 980
 981         spin_unlock_irqrestore(&openpic_setup_lock, flags);
 982
 983         return 0;
 984 }
 985
 986 /* WARNING: Can be called directly by the cpufreq code with NULL parameter,
 987  * we need something better to deal with that... Maybe switch to S1 for
 988  * cpufreq changes
 989  */
 990 int openpic_resume(struct sys_device *sysdev)
 991 {
 992         int             i;
 993         unsigned long   flags;
 994         u32             vppmask =       OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
 995                                         OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
 996                                         OPENPIC_MASK;
 997
 998         spin_lock_irqsave(&openpic_setup_lock, flags);
 999
1000         if ((--openpic_suspend_count) > 0) {
1001                 spin_unlock_irqrestore(&openpic_setup_lock, flags);
1002                 return 0;
1003         }
1004
1005         /* OpenPIC sometimes seem to need some time to be fully back up... */
1006         do {
1007                 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
1008         } while(openpic_readfield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
1009                         != OPENPIC_VEC_SPURIOUS);
1010
1011         openpic_disable_8259_pass_through();
1012
1013         for (i=0; i<OPENPIC_NUM_IPI; i++)
1014                 openpic_write(&OpenPIC->Global.IPI_Vector_Priority(i),
1015                               save_ipi_vp[i]);
1016         for (i=0; i<NumSources; i++) {
1017                 if (ISR[i] == 0)
1018                         continue;
1019                 openpic_write(&ISR[i]->Destination, save_irq_src_dest[i]);
1020                 openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1021                 /* make sure mask gets to controller before we return to user */
1022                 do {
1023                         openpic_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
1024                 } while (openpic_readfield(&ISR[i]->Vector_Priority, vppmask)
1025                          != (save_irq_src_vp[i] & vppmask));
1026         }
1027         for (i=0; i<NumProcessors; i++)
1028                 openpic_write(&OpenPIC->Processor[i].Current_Task_Priority,
1029                               save_cpu_task_pri[i]);
1030
1031         open_pic.enable = openpic_enable_irq;
1032         open_pic.disable = openpic_disable_irq;
1033
1034         openpic_set_priority(0);
1035
1036         spin_unlock_irqrestore(&openpic_setup_lock, flags);
1037
1038         return 0;
1039 }
1040
1041 #endif /* CONFIG_PM */
1042
1043 static struct sysdev_class openpic_sysclass = {
1044         set_kset_name("openpic"),
1045 };
1046
1047 static struct sys_device device_openpic = {
1048         .id             = 0,
1049         .cls            = &openpic_sysclass,
1050 };
1051
1052 static struct sysdev_driver driver_openpic = {
1053 #ifdef CONFIG_PM
1054         .suspend        = &openpic_suspend,
1055         .resume         = &openpic_resume,
1056 #endif /* CONFIG_PM */
1057 };
1058
1059 static int __init init_openpic_sysfs(void)
1060 {
1061         int rc;
1062
1063         if (!OpenPIC_Addr)
1064                 return -ENODEV;
1065         printk(KERN_DEBUG "Registering openpic with sysfs...\n");
1066         rc = sysdev_class_register(&openpic_sysclass);
1067         if (rc) {
1068                 printk(KERN_ERR "Failed registering openpic sys class\n");
1069                 return -ENODEV;
1070         }
1071         rc = sysdev_register(&device_openpic);
1072         if (rc) {
1073                 printk(KERN_ERR "Failed registering openpic sys device\n");
1074                 return -ENODEV;
1075         }
1076         rc = sysdev_driver_register(&openpic_sysclass, &driver_openpic);
1077         if (rc) {
1078                 printk(KERN_ERR "Failed registering openpic sys driver\n");
1079                 return -ENODEV;
1080         }
1081         return 0;
1082 }
1083
1084 subsys_initcall(init_openpic_sysfs);
1085