1 /* pci_iommu.c: UltraSparc PCI controller IOM/STC support.
3 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/delay.h>
14 #include "iommu_common.h"
16 #define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
17 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
19 /* Accessing IOMMU and Streaming Buffer registers.
20 * REG parameter is a physical address. All registers
21 * are 64-bits in size.
23 #define pci_iommu_read(__reg) \
25 __asm__ __volatile__("ldxa [%1] %2, %0" \
27 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
31 #define pci_iommu_write(__reg, __val) \
32 __asm__ __volatile__("stxa %0, [%1] %2" \
34 : "r" (__val), "r" (__reg), \
35 "i" (ASI_PHYS_BYPASS_EC_E))
37 /* Must be invoked under the IOMMU lock. */
38 static void __iommu_flushall(struct iommu *iommu)
43 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
44 for (entry = 0; entry < 16; entry++) {
45 pci_iommu_write(tag, 0);
49 /* Ensure completion of previous PIO writes. */
50 (void) pci_iommu_read(iommu->write_complete_reg);
53 #define IOPTE_CONSISTENT(CTX) \
54 (IOPTE_VALID | IOPTE_CACHE | \
55 (((CTX) << 47) & IOPTE_CONTEXT))
57 #define IOPTE_STREAMING(CTX) \
58 (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
60 /* Existing mappings are never marked invalid, instead they
61 * are pointed to a dummy page.
63 #define IOPTE_IS_DUMMY(iommu, iopte) \
64 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
66 static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
68 unsigned long val = iopte_val(*iopte);
71 val |= iommu->dummy_page_pa;
73 iopte_val(*iopte) = val;
76 /* Based largely upon the ppc64 iommu allocator. */
77 static long pci_arena_alloc(struct iommu *iommu, unsigned long npages)
79 struct iommu_arena *arena = &iommu->arena;
80 unsigned long n, i, start, end, limit;
88 n = find_next_zero_bit(arena->map, limit, start);
90 if (unlikely(end >= limit)) {
91 if (likely(pass < 1)) {
94 __iommu_flushall(iommu);
98 /* Scanned the whole thing, give up. */
103 for (i = n; i < end; i++) {
104 if (test_bit(i, arena->map)) {
110 for (i = n; i < end; i++)
111 __set_bit(i, arena->map);
118 static void pci_arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
122 for (i = base; i < (base + npages); i++)
123 __clear_bit(i, arena->map);
126 void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
128 unsigned long i, tsbbase, order, sz, num_tsb_entries;
130 num_tsb_entries = tsbsize / sizeof(iopte_t);
132 /* Setup initial software IOMMU state. */
133 spin_lock_init(&iommu->lock);
134 iommu->ctx_lowest_free = 1;
135 iommu->page_table_map_base = dma_offset;
136 iommu->dma_addr_mask = dma_addr_mask;
138 /* Allocate and initialize the free area map. */
139 sz = num_tsb_entries / 8;
140 sz = (sz + 7UL) & ~7UL;
141 iommu->arena.map = kzalloc(sz, GFP_KERNEL);
142 if (!iommu->arena.map) {
143 prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
146 iommu->arena.limit = num_tsb_entries;
148 /* Allocate and initialize the dummy page which we
149 * set inactive IO PTEs to point to.
151 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
152 if (!iommu->dummy_page) {
153 prom_printf("PCI_IOMMU: Error, gfp(dummy_page) failed.\n");
156 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
157 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
159 /* Now allocate and setup the IOMMU page table itself. */
160 order = get_order(tsbsize);
161 tsbbase = __get_free_pages(GFP_KERNEL, order);
163 prom_printf("PCI_IOMMU: Error, gfp(tsb) failed.\n");
166 iommu->page_table = (iopte_t *)tsbbase;
168 for (i = 0; i < num_tsb_entries; i++)
169 iopte_make_dummy(iommu, &iommu->page_table[i]);
172 static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages)
176 entry = pci_arena_alloc(iommu, npages);
177 if (unlikely(entry < 0))
180 return iommu->page_table + entry;
183 static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages)
185 pci_arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
188 static int iommu_alloc_ctx(struct iommu *iommu)
190 int lowest = iommu->ctx_lowest_free;
191 int sz = IOMMU_NUM_CTXS - lowest;
192 int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
194 if (unlikely(n == sz)) {
195 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
196 if (unlikely(n == lowest)) {
197 printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
202 __set_bit(n, iommu->ctx_bitmap);
207 static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
210 __clear_bit(ctx, iommu->ctx_bitmap);
211 if (ctx < iommu->ctx_lowest_free)
212 iommu->ctx_lowest_free = ctx;
216 /* Allocate and map kernel buffer of size SIZE using consistent mode
217 * DMA for PCI device PDEV. Return non-NULL cpu-side address if
218 * successful and set *DMA_ADDRP to the PCI side dma address.
220 static void *pci_4u_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp, gfp_t gfp)
224 unsigned long flags, order, first_page;
228 size = IO_PAGE_ALIGN(size);
229 order = get_order(size);
233 first_page = __get_free_pages(gfp, order);
234 if (first_page == 0UL)
236 memset((char *)first_page, 0, PAGE_SIZE << order);
238 iommu = pdev->dev.archdata.iommu;
240 spin_lock_irqsave(&iommu->lock, flags);
241 iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
242 spin_unlock_irqrestore(&iommu->lock, flags);
244 if (unlikely(iopte == NULL)) {
245 free_pages(first_page, order);
249 *dma_addrp = (iommu->page_table_map_base +
250 ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
251 ret = (void *) first_page;
252 npages = size >> IO_PAGE_SHIFT;
253 first_page = __pa(first_page);
255 iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
257 (first_page & IOPTE_PAGE));
259 first_page += IO_PAGE_SIZE;
265 /* Free and unmap a consistent DMA translation. */
266 static void pci_4u_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
270 unsigned long flags, order, npages;
272 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
273 iommu = pdev->dev.archdata.iommu;
274 iopte = iommu->page_table +
275 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
277 spin_lock_irqsave(&iommu->lock, flags);
279 free_npages(iommu, dvma - iommu->page_table_map_base, npages);
281 spin_unlock_irqrestore(&iommu->lock, flags);
283 order = get_order(size);
285 free_pages((unsigned long)cpu, order);
288 /* Map a single buffer at PTR of SZ bytes for PCI DMA
291 static dma_addr_t pci_4u_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
294 struct strbuf *strbuf;
296 unsigned long flags, npages, oaddr;
297 unsigned long i, base_paddr, ctx;
299 unsigned long iopte_protection;
301 iommu = pdev->dev.archdata.iommu;
302 strbuf = pdev->dev.archdata.stc;
304 if (unlikely(direction == PCI_DMA_NONE))
307 oaddr = (unsigned long)ptr;
308 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
309 npages >>= IO_PAGE_SHIFT;
311 spin_lock_irqsave(&iommu->lock, flags);
312 base = alloc_npages(iommu, npages);
314 if (iommu->iommu_ctxflush)
315 ctx = iommu_alloc_ctx(iommu);
316 spin_unlock_irqrestore(&iommu->lock, flags);
321 bus_addr = (iommu->page_table_map_base +
322 ((base - iommu->page_table) << IO_PAGE_SHIFT));
323 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
324 base_paddr = __pa(oaddr & IO_PAGE_MASK);
325 if (strbuf->strbuf_enabled)
326 iopte_protection = IOPTE_STREAMING(ctx);
328 iopte_protection = IOPTE_CONSISTENT(ctx);
329 if (direction != PCI_DMA_TODEVICE)
330 iopte_protection |= IOPTE_WRITE;
332 for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
333 iopte_val(*base) = iopte_protection | base_paddr;
338 iommu_free_ctx(iommu, ctx);
340 if (printk_ratelimit())
342 return PCI_DMA_ERROR_CODE;
345 static void pci_strbuf_flush(struct strbuf *strbuf, struct iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
349 if (strbuf->strbuf_ctxflush &&
350 iommu->iommu_ctxflush) {
351 unsigned long matchreg, flushreg;
354 flushreg = strbuf->strbuf_ctxflush;
355 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
357 pci_iommu_write(flushreg, ctx);
358 val = pci_iommu_read(matchreg);
365 pci_iommu_write(flushreg, ctx);
368 val = pci_iommu_read(matchreg);
370 printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
371 "timeout matchreg[%lx] ctx[%lx]\n",
379 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
380 pci_iommu_write(strbuf->strbuf_pflush, vaddr);
384 /* If the device could not have possibly put dirty data into
385 * the streaming cache, no flush-flag synchronization needs
388 if (direction == PCI_DMA_TODEVICE)
391 PCI_STC_FLUSHFLAG_INIT(strbuf);
392 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
393 (void) pci_iommu_read(iommu->write_complete_reg);
396 while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
404 printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout "
405 "vaddr[%08x] ctx[%lx] npages[%ld]\n",
409 /* Unmap a single streaming mode DMA translation. */
410 static void pci_4u_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
413 struct strbuf *strbuf;
415 unsigned long flags, npages, ctx, i;
417 if (unlikely(direction == PCI_DMA_NONE)) {
418 if (printk_ratelimit())
423 iommu = pdev->dev.archdata.iommu;
424 strbuf = pdev->dev.archdata.stc;
426 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
427 npages >>= IO_PAGE_SHIFT;
428 base = iommu->page_table +
429 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
430 #ifdef DEBUG_PCI_IOMMU
431 if (IOPTE_IS_DUMMY(iommu, base))
432 printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n",
433 bus_addr, sz, __builtin_return_address(0));
435 bus_addr &= IO_PAGE_MASK;
437 spin_lock_irqsave(&iommu->lock, flags);
439 /* Record the context, if any. */
441 if (iommu->iommu_ctxflush)
442 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
444 /* Step 1: Kick data out of streaming buffers if necessary. */
445 if (strbuf->strbuf_enabled)
446 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx,
449 /* Step 2: Clear out TSB entries. */
450 for (i = 0; i < npages; i++)
451 iopte_make_dummy(iommu, base + i);
453 free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
455 iommu_free_ctx(iommu, ctx);
457 spin_unlock_irqrestore(&iommu->lock, flags);
460 #define SG_ENT_PHYS_ADDRESS(SG) \
461 (__pa(page_address((SG)->page)) + (SG)->offset)
463 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
464 int nused, int nelems, unsigned long iopte_protection)
466 struct scatterlist *dma_sg = sg;
467 struct scatterlist *sg_end = sg + nelems;
470 for (i = 0; i < nused; i++) {
471 unsigned long pteval = ~0UL;
474 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
476 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
478 unsigned long offset;
481 /* If we are here, we know we have at least one
482 * more page to map. So walk forward until we
483 * hit a page crossing, and begin creating new
484 * mappings from that spot.
489 tmp = SG_ENT_PHYS_ADDRESS(sg);
491 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
492 pteval = tmp & IO_PAGE_MASK;
493 offset = tmp & (IO_PAGE_SIZE - 1UL);
496 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
497 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
499 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
505 pteval = iopte_protection | (pteval & IOPTE_PAGE);
507 *iopte++ = __iopte(pteval);
508 pteval += IO_PAGE_SIZE;
509 len -= (IO_PAGE_SIZE - offset);
514 pteval = (pteval & IOPTE_PAGE) + len;
517 /* Skip over any tail mappings we've fully mapped,
518 * adjusting pteval along the way. Stop when we
519 * detect a page crossing event.
521 while (sg < sg_end &&
522 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
523 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
525 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
526 pteval += sg->length;
529 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
531 } while (dma_npages != 0);
536 /* Map a set of buffers described by SGLIST with NELEMS array
537 * elements in streaming mode for PCI DMA.
538 * When making changes here, inspect the assembly output. I was having
539 * hard time to kepp this routine out of using stack slots for holding variables.
541 static int pci_4u_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
544 struct strbuf *strbuf;
545 unsigned long flags, ctx, npages, iopte_protection;
548 struct scatterlist *sgtmp;
551 /* Fast path single entry scatterlists. */
553 sglist->dma_address =
554 pci_4u_map_single(pdev,
555 (page_address(sglist->page) + sglist->offset),
556 sglist->length, direction);
557 if (unlikely(sglist->dma_address == PCI_DMA_ERROR_CODE))
559 sglist->dma_length = sglist->length;
563 iommu = pdev->dev.archdata.iommu;
564 strbuf = pdev->dev.archdata.stc;
566 if (unlikely(direction == PCI_DMA_NONE))
569 /* Step 1: Prepare scatter list. */
571 npages = prepare_sg(sglist, nelems);
573 /* Step 2: Allocate a cluster and context, if necessary. */
575 spin_lock_irqsave(&iommu->lock, flags);
577 base = alloc_npages(iommu, npages);
579 if (iommu->iommu_ctxflush)
580 ctx = iommu_alloc_ctx(iommu);
582 spin_unlock_irqrestore(&iommu->lock, flags);
587 dma_base = iommu->page_table_map_base +
588 ((base - iommu->page_table) << IO_PAGE_SHIFT);
590 /* Step 3: Normalize DMA addresses. */
594 while (used && sgtmp->dma_length) {
595 sgtmp->dma_address += dma_base;
599 used = nelems - used;
601 /* Step 4: Create the mappings. */
602 if (strbuf->strbuf_enabled)
603 iopte_protection = IOPTE_STREAMING(ctx);
605 iopte_protection = IOPTE_CONSISTENT(ctx);
606 if (direction != PCI_DMA_TODEVICE)
607 iopte_protection |= IOPTE_WRITE;
609 fill_sg(base, sglist, used, nelems, iopte_protection);
612 verify_sglist(sglist, nelems, base, npages);
618 iommu_free_ctx(iommu, ctx);
620 if (printk_ratelimit())
625 /* Unmap a set of streaming mode DMA translations. */
626 static void pci_4u_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
629 struct strbuf *strbuf;
631 unsigned long flags, ctx, i, npages;
634 if (unlikely(direction == PCI_DMA_NONE)) {
635 if (printk_ratelimit())
639 iommu = pdev->dev.archdata.iommu;
640 strbuf = pdev->dev.archdata.stc;
642 bus_addr = sglist->dma_address & IO_PAGE_MASK;
644 for (i = 1; i < nelems; i++)
645 if (sglist[i].dma_length == 0)
648 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) -
649 bus_addr) >> IO_PAGE_SHIFT;
651 base = iommu->page_table +
652 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
654 #ifdef DEBUG_PCI_IOMMU
655 if (IOPTE_IS_DUMMY(iommu, base))
656 printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0));
659 spin_lock_irqsave(&iommu->lock, flags);
661 /* Record the context, if any. */
663 if (iommu->iommu_ctxflush)
664 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
666 /* Step 1: Kick data out of streaming buffers if necessary. */
667 if (strbuf->strbuf_enabled)
668 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
670 /* Step 2: Clear out the TSB entries. */
671 for (i = 0; i < npages; i++)
672 iopte_make_dummy(iommu, base + i);
674 free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
676 iommu_free_ctx(iommu, ctx);
678 spin_unlock_irqrestore(&iommu->lock, flags);
681 /* Make physical memory consistent for a single
682 * streaming mode DMA translation after a transfer.
684 static void pci_4u_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
687 struct strbuf *strbuf;
688 unsigned long flags, ctx, npages;
690 iommu = pdev->dev.archdata.iommu;
691 strbuf = pdev->dev.archdata.stc;
693 if (!strbuf->strbuf_enabled)
696 spin_lock_irqsave(&iommu->lock, flags);
698 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
699 npages >>= IO_PAGE_SHIFT;
700 bus_addr &= IO_PAGE_MASK;
702 /* Step 1: Record the context, if any. */
704 if (iommu->iommu_ctxflush &&
705 strbuf->strbuf_ctxflush) {
708 iopte = iommu->page_table +
709 ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
710 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
713 /* Step 2: Kick data out of streaming buffers. */
714 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
716 spin_unlock_irqrestore(&iommu->lock, flags);
719 /* Make physical memory consistent for a set of streaming
720 * mode DMA translations after a transfer.
722 static void pci_4u_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
725 struct strbuf *strbuf;
726 unsigned long flags, ctx, npages, i;
729 iommu = pdev->dev.archdata.iommu;
730 strbuf = pdev->dev.archdata.stc;
732 if (!strbuf->strbuf_enabled)
735 spin_lock_irqsave(&iommu->lock, flags);
737 /* Step 1: Record the context, if any. */
739 if (iommu->iommu_ctxflush &&
740 strbuf->strbuf_ctxflush) {
743 iopte = iommu->page_table +
744 ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
745 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
748 /* Step 2: Kick data out of streaming buffers. */
749 bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
750 for(i = 1; i < nelems; i++)
751 if (!sglist[i].dma_length)
754 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
755 - bus_addr) >> IO_PAGE_SHIFT;
756 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
758 spin_unlock_irqrestore(&iommu->lock, flags);
761 const struct pci_iommu_ops pci_sun4u_iommu_ops = {
762 .alloc_consistent = pci_4u_alloc_consistent,
763 .free_consistent = pci_4u_free_consistent,
764 .map_single = pci_4u_map_single,
765 .unmap_single = pci_4u_unmap_single,
766 .map_sg = pci_4u_map_sg,
767 .unmap_sg = pci_4u_unmap_sg,
768 .dma_sync_single_for_cpu = pci_4u_dma_sync_single_for_cpu,
769 .dma_sync_sg_for_cpu = pci_4u_dma_sync_sg_for_cpu,
772 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
774 struct pci_dev *ali_isa_bridge;
777 /* ALI sound chips generate 31-bits of DMA, a special register
778 * determines what bit 31 is emitted as.
780 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
781 PCI_DEVICE_ID_AL_M1533,
784 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
789 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
790 pci_dev_put(ali_isa_bridge);
793 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
798 dma_addr_mask = 0xffffffff;
800 struct iommu *iommu = pdev->dev.archdata.iommu;
802 dma_addr_mask = iommu->dma_addr_mask;
804 if (pdev->vendor == PCI_VENDOR_ID_AL &&
805 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
806 device_mask == 0x7fffffff) {
807 ali_sound_dma_hack(pdev,
808 (dma_addr_mask & 0x80000000) != 0);
813 if (device_mask >= (1UL << 32UL))
816 return (device_mask & dma_addr_mask) == dma_addr_mask;