2 * (C) 2001 Dave Jones, Arjan van de ven.
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon reverse engineered information, and on Intel documentation
7 * for chipsets ICH2-M and ICH3-M.
9 * Many thanks to Ducrot Bruno for finding and fixing the last
10 * "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
11 * for extensive testing.
13 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
17 /*********************************************************************
18 * SPEEDSTEP - DEFINITIONS *
19 *********************************************************************/
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/cpufreq.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
29 #include "speedstep-lib.h"
33 * It is necessary to know which chipset is used. As accesses to
34 * this device occur at various places in this module, we need a
35 * static struct pci_dev * pointing to that device.
37 static struct pci_dev *speedstep_chipset_dev;
40 /* speedstep_processor
42 static unsigned int speedstep_processor = 0;
47 * There are only two frequency states for each processor. Values
48 * are in kHz for the time being.
50 static struct cpufreq_frequency_table speedstep_freqs[] = {
53 {0, CPUFREQ_TABLE_END},
57 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-ich", msg)
61 * speedstep_find_register - read the PMBASE address
63 * Returns: -ENODEV if no register could be found
65 static int speedstep_find_register (void)
67 if (!speedstep_chipset_dev)
71 pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
72 if (!(pmbase & 0x01)) {
73 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
79 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
83 dprintk("pmbase is 0x%x\n", pmbase);
88 * speedstep_set_state - set the SpeedStep state
89 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
91 * Tries to change the SpeedStep state.
93 static void speedstep_set_state (unsigned int state)
103 local_irq_save(flags);
106 value = inb(pmbase + 0x50);
108 dprintk("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
110 /* write new state */
114 dprintk("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
116 /* Disable bus master arbitration */
117 pm2_blk = inb(pmbase + 0x20);
119 outb(pm2_blk, (pmbase + 0x20));
121 /* Actual transition */
122 outb(value, (pmbase + 0x50));
124 /* Restore bus master arbitration */
126 outb(pm2_blk, (pmbase + 0x20));
128 /* check if transition was successful */
129 value = inb(pmbase + 0x50);
132 local_irq_restore(flags);
134 dprintk("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
136 if (state == (value & 0x1)) {
137 dprintk("change to %u MHz succeeded\n", (speedstep_get_processor_frequency(speedstep_processor) / 1000));
139 printk (KERN_ERR "cpufreq: change failed - I/O error\n");
147 * speedstep_activate - activate SpeedStep control in the chipset
149 * Tries to activate the SpeedStep status and control registers.
150 * Returns -EINVAL on an unsupported chipset, and zero on success.
152 static int speedstep_activate (void)
156 if (!speedstep_chipset_dev)
159 pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
160 if (!(value & 0x08)) {
162 dprintk("activating SpeedStep (TM) registers\n");
163 pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
171 * speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
173 * Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
174 * the LPC bridge / PM module which contains all power-management
175 * functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
176 * chipset, or zero on failure.
178 static unsigned int speedstep_detect_chipset (void)
180 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
181 PCI_DEVICE_ID_INTEL_82801DB_12,
185 if (speedstep_chipset_dev)
188 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
189 PCI_DEVICE_ID_INTEL_82801CA_12,
193 if (speedstep_chipset_dev)
197 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
198 PCI_DEVICE_ID_INTEL_82801BA_10,
202 if (speedstep_chipset_dev) {
203 /* speedstep.c causes lockups on Dell Inspirons 8000 and
204 * 8100 which use a pretty old revision of the 82815
205 * host brige. Abort on these systems.
207 static struct pci_dev *hostbridge;
209 hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
210 PCI_DEVICE_ID_INTEL_82815_MC,
218 if (hostbridge->revision < 5) {
219 dprintk("hostbridge does not support speedstep\n");
220 speedstep_chipset_dev = NULL;
221 pci_dev_put(hostbridge);
225 pci_dev_put(hostbridge);
232 static unsigned int _speedstep_get(const cpumask_t *cpus)
235 cpumask_t cpus_allowed;
237 cpus_allowed = current->cpus_allowed;
238 set_cpus_allowed_ptr(current, cpus);
239 speed = speedstep_get_processor_frequency(speedstep_processor);
240 set_cpus_allowed_ptr(current, &cpus_allowed);
241 dprintk("detected %u kHz as current frequency\n", speed);
245 static unsigned int speedstep_get(unsigned int cpu)
247 return _speedstep_get(&cpumask_of_cpu(cpu));
251 * speedstep_target - set a new CPUFreq policy
252 * @policy: new policy
253 * @target_freq: the target frequency
254 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
256 * Sets a new CPUFreq policy.
258 static int speedstep_target (struct cpufreq_policy *policy,
259 unsigned int target_freq,
260 unsigned int relation)
262 unsigned int newstate = 0;
263 struct cpufreq_freqs freqs;
264 cpumask_t cpus_allowed;
267 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], target_freq, relation, &newstate))
270 freqs.old = _speedstep_get(&policy->cpus);
271 freqs.new = speedstep_freqs[newstate].frequency;
272 freqs.cpu = policy->cpu;
274 dprintk("transiting from %u to %u kHz\n", freqs.old, freqs.new);
276 /* no transition necessary */
277 if (freqs.old == freqs.new)
280 cpus_allowed = current->cpus_allowed;
282 for_each_cpu_mask_nr(i, policy->cpus) {
284 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
287 /* switch to physical CPU where state is to be changed */
288 set_cpus_allowed_ptr(current, &policy->cpus);
290 speedstep_set_state(newstate);
292 /* allow to be run on all CPUs */
293 set_cpus_allowed_ptr(current, &cpus_allowed);
295 for_each_cpu_mask_nr(i, policy->cpus) {
297 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
305 * speedstep_verify - verifies a new CPUFreq policy
306 * @policy: new policy
308 * Limit must be within speedstep_low_freq and speedstep_high_freq, with
309 * at least one border included.
311 static int speedstep_verify (struct cpufreq_policy *policy)
313 return cpufreq_frequency_table_verify(policy, &speedstep_freqs[0]);
317 static int speedstep_cpu_init(struct cpufreq_policy *policy)
321 cpumask_t cpus_allowed;
323 /* only run on CPU to be set, or on its sibling */
325 policy->cpus = per_cpu(cpu_sibling_map, policy->cpu);
328 cpus_allowed = current->cpus_allowed;
329 set_cpus_allowed_ptr(current, &policy->cpus);
331 /* detect low and high frequency and transition latency */
332 result = speedstep_get_freqs(speedstep_processor,
333 &speedstep_freqs[SPEEDSTEP_LOW].frequency,
334 &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
335 &policy->cpuinfo.transition_latency,
336 &speedstep_set_state);
337 set_cpus_allowed_ptr(current, &cpus_allowed);
341 /* get current speed setting */
342 speed = _speedstep_get(&policy->cpus);
346 dprintk("currently at %s speed setting - %i MHz\n",
347 (speed == speedstep_freqs[SPEEDSTEP_LOW].frequency) ? "low" : "high",
350 /* cpuinfo and default policy values */
353 result = cpufreq_frequency_table_cpuinfo(policy, speedstep_freqs);
357 cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
363 static int speedstep_cpu_exit(struct cpufreq_policy *policy)
365 cpufreq_frequency_table_put_attr(policy->cpu);
369 static struct freq_attr* speedstep_attr[] = {
370 &cpufreq_freq_attr_scaling_available_freqs,
375 static struct cpufreq_driver speedstep_driver = {
376 .name = "speedstep-ich",
377 .verify = speedstep_verify,
378 .target = speedstep_target,
379 .init = speedstep_cpu_init,
380 .exit = speedstep_cpu_exit,
381 .get = speedstep_get,
382 .owner = THIS_MODULE,
383 .attr = speedstep_attr,
388 * speedstep_init - initializes the SpeedStep CPUFreq driver
390 * Initializes the SpeedStep support. Returns -ENODEV on unsupported
391 * devices, -EINVAL on problems during initiatization, and zero on
394 static int __init speedstep_init(void)
396 /* detect processor */
397 speedstep_processor = speedstep_detect_processor();
398 if (!speedstep_processor) {
399 dprintk("Intel(R) SpeedStep(TM) capable processor not found\n");
404 if (!speedstep_detect_chipset()) {
405 dprintk("Intel(R) SpeedStep(TM) for this chipset not (yet) available.\n");
409 /* activate speedstep support */
410 if (speedstep_activate()) {
411 pci_dev_put(speedstep_chipset_dev);
415 if (speedstep_find_register())
418 return cpufreq_register_driver(&speedstep_driver);
423 * speedstep_exit - unregisters SpeedStep support
425 * Unregisters SpeedStep support.
427 static void __exit speedstep_exit(void)
429 pci_dev_put(speedstep_chipset_dev);
430 cpufreq_unregister_driver(&speedstep_driver);
434 MODULE_AUTHOR ("Dave Jones <davej@redhat.com>, Dominik Brodowski <linux@brodo.de>");
435 MODULE_DESCRIPTION ("Speedstep driver for Intel mobile processors on chipsets with ICH-M southbridges.");
436 MODULE_LICENSE ("GPL");
438 module_init(speedstep_init);
439 module_exit(speedstep_exit);