Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes...
[linux-2.6] / drivers / i2c / busses / i2c-cpm.c
1 /*
2  * Freescale CPM1/CPM2 I2C interface.
3  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
4  *
5  * moved into proper i2c interface;
6  * Brad Parker (brad@heeltoe.com)
7  *
8  * Parts from dbox2_i2c.c (cvs.tuxbox.org)
9  * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
10  *
11  * (C) 2007 Montavista Software, Inc.
12  * Vitaly Bordug <vitb@kernel.crashing.org>
13  *
14  * Converted to of_platform_device. Renamed to i2c-cpm.c.
15  * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
16  *
17  *  This program is free software; you can redistribute it and/or modify
18  *  it under the terms of the GNU General Public License as published by
19  *  the Free Software Foundation; either version 2 of the License, or
20  *  (at your option) any later version.
21  *
22  *  This program is distributed in the hope that it will be useful,
23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25  *  GNU General Public License for more details.
26  *
27  *  You should have received a copy of the GNU General Public License
28  *  along with this program; if not, write to the Free Software
29  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
30  */
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/errno.h>
39 #include <linux/stddef.h>
40 #include <linux/i2c.h>
41 #include <linux/io.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/of_device.h>
44 #include <linux/of_platform.h>
45 #include <linux/of_i2c.h>
46 #include <sysdev/fsl_soc.h>
47 #include <asm/cpm.h>
48
49 /* Try to define this if you have an older CPU (earlier than rev D4) */
50 /* However, better use a GPIO based bitbang driver in this case :/   */
51 #undef  I2C_CHIP_ERRATA
52
53 #define CPM_MAX_READ    513
54 #define CPM_MAXBD       4
55
56 #define I2C_EB                  (0x10) /* Big endian mode */
57 #define I2C_EB_CPM2             (0x30) /* Big endian mode, memory snoop */
58
59 #define DPRAM_BASE              ((u8 __iomem __force *)cpm_muram_addr(0))
60
61 /* I2C parameter RAM. */
62 struct i2c_ram {
63         ushort  rbase;          /* Rx Buffer descriptor base address */
64         ushort  tbase;          /* Tx Buffer descriptor base address */
65         u_char  rfcr;           /* Rx function code */
66         u_char  tfcr;           /* Tx function code */
67         ushort  mrblr;          /* Max receive buffer length */
68         uint    rstate;         /* Internal */
69         uint    rdp;            /* Internal */
70         ushort  rbptr;          /* Rx Buffer descriptor pointer */
71         ushort  rbc;            /* Internal */
72         uint    rxtmp;          /* Internal */
73         uint    tstate;         /* Internal */
74         uint    tdp;            /* Internal */
75         ushort  tbptr;          /* Tx Buffer descriptor pointer */
76         ushort  tbc;            /* Internal */
77         uint    txtmp;          /* Internal */
78         char    res1[4];        /* Reserved */
79         ushort  rpbase;         /* Relocation pointer */
80         char    res2[2];        /* Reserved */
81 };
82
83 #define I2COM_START     0x80
84 #define I2COM_MASTER    0x01
85 #define I2CER_TXE       0x10
86 #define I2CER_BUSY      0x04
87 #define I2CER_TXB       0x02
88 #define I2CER_RXB       0x01
89 #define I2MOD_EN        0x01
90
91 /* I2C Registers */
92 struct i2c_reg {
93         u8      i2mod;
94         u8      res1[3];
95         u8      i2add;
96         u8      res2[3];
97         u8      i2brg;
98         u8      res3[3];
99         u8      i2com;
100         u8      res4[3];
101         u8      i2cer;
102         u8      res5[3];
103         u8      i2cmr;
104 };
105
106 struct cpm_i2c {
107         char *base;
108         struct of_device *ofdev;
109         struct i2c_adapter adap;
110         uint dp_addr;
111         int version; /* CPM1=1, CPM2=2 */
112         int irq;
113         int cp_command;
114         int freq;
115         struct i2c_reg __iomem *i2c_reg;
116         struct i2c_ram __iomem *i2c_ram;
117         u16 i2c_addr;
118         wait_queue_head_t i2c_wait;
119         cbd_t __iomem *tbase;
120         cbd_t __iomem *rbase;
121         u_char *txbuf[CPM_MAXBD];
122         u_char *rxbuf[CPM_MAXBD];
123         u32 txdma[CPM_MAXBD];
124         u32 rxdma[CPM_MAXBD];
125 };
126
127 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
128 {
129         struct cpm_i2c *cpm;
130         struct i2c_reg __iomem *i2c_reg;
131         struct i2c_adapter *adap = dev_id;
132         int i;
133
134         cpm = i2c_get_adapdata(dev_id);
135         i2c_reg = cpm->i2c_reg;
136
137         /* Clear interrupt. */
138         i = in_8(&i2c_reg->i2cer);
139         out_8(&i2c_reg->i2cer, i);
140
141         dev_dbg(&adap->dev, "Interrupt: %x\n", i);
142
143         wake_up_interruptible(&cpm->i2c_wait);
144
145         return i ? IRQ_HANDLED : IRQ_NONE;
146 }
147
148 static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
149 {
150         struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
151
152         /* Set up the I2C parameters in the parameter ram. */
153         out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
154         out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
155
156         if (cpm->version == 1) {
157                 out_8(&i2c_ram->tfcr, I2C_EB);
158                 out_8(&i2c_ram->rfcr, I2C_EB);
159         } else {
160                 out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
161                 out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
162         }
163
164         out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
165
166         out_be32(&i2c_ram->rstate, 0);
167         out_be32(&i2c_ram->rdp, 0);
168         out_be16(&i2c_ram->rbptr, 0);
169         out_be16(&i2c_ram->rbc, 0);
170         out_be32(&i2c_ram->rxtmp, 0);
171         out_be32(&i2c_ram->tstate, 0);
172         out_be32(&i2c_ram->tdp, 0);
173         out_be16(&i2c_ram->tbptr, 0);
174         out_be16(&i2c_ram->tbc, 0);
175         out_be32(&i2c_ram->txtmp, 0);
176 }
177
178 static void cpm_i2c_force_close(struct i2c_adapter *adap)
179 {
180         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
181         struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
182
183         dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
184
185         cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
186
187         out_8(&i2c_reg->i2cmr, 0x00);   /* Disable all interrupts */
188         out_8(&i2c_reg->i2cer, 0xff);
189 }
190
191 static void cpm_i2c_parse_message(struct i2c_adapter *adap,
192         struct i2c_msg *pmsg, int num, int tx, int rx)
193 {
194         cbd_t __iomem *tbdf;
195         cbd_t __iomem *rbdf;
196         u_char addr;
197         u_char *tb;
198         u_char *rb;
199         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
200
201         tbdf = cpm->tbase + tx;
202         rbdf = cpm->rbase + rx;
203
204         addr = pmsg->addr << 1;
205         if (pmsg->flags & I2C_M_RD)
206                 addr |= 1;
207
208         tb = cpm->txbuf[tx];
209         rb = cpm->rxbuf[rx];
210
211         /* Align read buffer */
212         rb = (u_char *) (((ulong) rb + 1) & ~1);
213
214         tb[0] = addr;           /* Device address byte w/rw flag */
215
216         out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
217         out_be16(&tbdf->cbd_sc, 0);
218
219         if (!(pmsg->flags & I2C_M_NOSTART))
220                 setbits16(&tbdf->cbd_sc, BD_I2C_START);
221
222         if (tx + 1 == num)
223                 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
224
225         if (pmsg->flags & I2C_M_RD) {
226                 /*
227                  * To read, we need an empty buffer of the proper length.
228                  * All that is used is the first byte for address, the remainder
229                  * is just used for timing (and doesn't really have to exist).
230                  */
231
232                 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
233
234                 out_be16(&rbdf->cbd_datlen, 0);
235                 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
236
237                 if (rx + 1 == CPM_MAXBD)
238                         setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
239
240                 eieio();
241                 setbits16(&tbdf->cbd_sc, BD_SC_READY);
242         } else {
243                 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
244
245                 memcpy(tb+1, pmsg->buf, pmsg->len);
246
247                 eieio();
248                 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
249         }
250 }
251
252 static int cpm_i2c_check_message(struct i2c_adapter *adap,
253         struct i2c_msg *pmsg, int tx, int rx)
254 {
255         cbd_t __iomem *tbdf;
256         cbd_t __iomem *rbdf;
257         u_char *tb;
258         u_char *rb;
259         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
260
261         tbdf = cpm->tbase + tx;
262         rbdf = cpm->rbase + rx;
263
264         tb = cpm->txbuf[tx];
265         rb = cpm->rxbuf[rx];
266
267         /* Align read buffer */
268         rb = (u_char *) (((uint) rb + 1) & ~1);
269
270         eieio();
271         if (pmsg->flags & I2C_M_RD) {
272                 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
273                         in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
274
275                 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
276                         dev_dbg(&adap->dev, "I2C read; No ack\n");
277                         return -ENXIO;
278                 }
279                 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
280                         dev_err(&adap->dev,
281                                 "I2C read; complete but rbuf empty\n");
282                         return -EREMOTEIO;
283                 }
284                 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
285                         dev_err(&adap->dev, "I2C read; Overrun\n");
286                         return -EREMOTEIO;
287                 }
288                 memcpy(pmsg->buf, rb, pmsg->len);
289         } else {
290                 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
291                         in_be16(&tbdf->cbd_sc));
292
293                 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
294                         dev_dbg(&adap->dev, "I2C write; No ack\n");
295                         return -ENXIO;
296                 }
297                 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
298                         dev_err(&adap->dev, "I2C write; Underrun\n");
299                         return -EIO;
300                 }
301                 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
302                         dev_err(&adap->dev, "I2C write; Collision\n");
303                         return -EIO;
304                 }
305         }
306         return 0;
307 }
308
309 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
310 {
311         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
312         struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
313         struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
314         struct i2c_msg *pmsg;
315         int ret, i;
316         int tptr;
317         int rptr;
318         cbd_t __iomem *tbdf;
319         cbd_t __iomem *rbdf;
320
321         if (num > CPM_MAXBD)
322                 return -EINVAL;
323
324         /* Check if we have any oversized READ requests */
325         for (i = 0; i < num; i++) {
326                 pmsg = &msgs[i];
327                 if (pmsg->len >= CPM_MAX_READ)
328                         return -EINVAL;
329         }
330
331         /* Reset to use first buffer */
332         out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
333         out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
334
335         tbdf = cpm->tbase;
336         rbdf = cpm->rbase;
337
338         tptr = 0;
339         rptr = 0;
340
341         while (tptr < num) {
342                 pmsg = &msgs[tptr];
343                 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
344
345                 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
346                 if (pmsg->flags & I2C_M_RD)
347                         rptr++;
348                 tptr++;
349         }
350         /* Start transfer now */
351         /* Enable RX/TX/Error interupts */
352         out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
353         out_8(&i2c_reg->i2cer, 0xff);   /* Clear interrupt status */
354         /* Chip bug, set enable here */
355         setbits8(&i2c_reg->i2mod, I2MOD_EN);    /* Enable */
356         /* Begin transmission */
357         setbits8(&i2c_reg->i2com, I2COM_START);
358
359         tptr = 0;
360         rptr = 0;
361
362         while (tptr < num) {
363                 /* Check for outstanding messages */
364                 dev_dbg(&adap->dev, "test ready.\n");
365                 pmsg = &msgs[tptr];
366                 if (pmsg->flags & I2C_M_RD)
367                         ret = wait_event_interruptible_timeout(cpm->i2c_wait,
368                                 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
369                                 1 * HZ);
370                 else
371                         ret = wait_event_interruptible_timeout(cpm->i2c_wait,
372                                 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
373                                 1 * HZ);
374                 if (ret == 0) {
375                         ret = -EREMOTEIO;
376                         dev_err(&adap->dev, "I2C transfer: timeout\n");
377                         goto out_err;
378                 }
379                 if (ret > 0) {
380                         dev_dbg(&adap->dev, "ready.\n");
381                         ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
382                         tptr++;
383                         if (pmsg->flags & I2C_M_RD)
384                                 rptr++;
385                         if (ret)
386                                 goto out_err;
387                 }
388         }
389 #ifdef I2C_CHIP_ERRATA
390         /*
391          * Chip errata, clear enable. This is not needed on rev D4 CPUs.
392          * Disabling I2C too early may cause too short stop condition
393          */
394         udelay(4);
395         clrbits8(&i2c_reg->i2mod, I2MOD_EN);
396 #endif
397         return (num);
398
399 out_err:
400         cpm_i2c_force_close(adap);
401 #ifdef I2C_CHIP_ERRATA
402         /*
403          * Chip errata, clear enable. This is not needed on rev D4 CPUs.
404          */
405         clrbits8(&i2c_reg->i2mod, I2MOD_EN);
406 #endif
407         return ret;
408 }
409
410 static u32 cpm_i2c_func(struct i2c_adapter *adap)
411 {
412         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
413 }
414
415 /* -----exported algorithm data: -------------------------------------  */
416
417 static const struct i2c_algorithm cpm_i2c_algo = {
418         .master_xfer = cpm_i2c_xfer,
419         .functionality = cpm_i2c_func,
420 };
421
422 static const struct i2c_adapter cpm_ops = {
423         .owner          = THIS_MODULE,
424         .name           = "i2c-cpm",
425         .algo           = &cpm_i2c_algo,
426 };
427
428 static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm)
429 {
430         struct of_device *ofdev = cpm->ofdev;
431         const u32 *data;
432         int len, ret, i;
433         void __iomem *i2c_base;
434         cbd_t __iomem *tbdf;
435         cbd_t __iomem *rbdf;
436         unsigned char brg;
437
438         dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
439
440         init_waitqueue_head(&cpm->i2c_wait);
441
442         cpm->irq = of_irq_to_resource(ofdev->node, 0, NULL);
443         if (cpm->irq == NO_IRQ)
444                 return -EINVAL;
445
446         /* Install interrupt handler. */
447         ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
448                           &cpm->adap);
449         if (ret)
450                 return ret;
451
452         /* I2C parameter RAM */
453         i2c_base = of_iomap(ofdev->node, 1);
454         if (i2c_base == NULL) {
455                 ret = -EINVAL;
456                 goto out_irq;
457         }
458
459         if (of_device_is_compatible(ofdev->node, "fsl,cpm1-i2c")) {
460
461                 /* Check for and use a microcode relocation patch. */
462                 cpm->i2c_ram = i2c_base;
463                 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
464
465                 /*
466                  * Maybe should use cpm_muram_alloc instead of hardcoding
467                  * this in micropatch.c
468                  */
469                 if (cpm->i2c_addr) {
470                         cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
471                         iounmap(i2c_base);
472                 }
473
474                 cpm->version = 1;
475
476         } else if (of_device_is_compatible(ofdev->node, "fsl,cpm2-i2c")) {
477                 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
478                 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
479                 out_be16(i2c_base, cpm->i2c_addr);
480                 iounmap(i2c_base);
481
482                 cpm->version = 2;
483
484         } else {
485                 iounmap(i2c_base);
486                 ret = -EINVAL;
487                 goto out_irq;
488         }
489
490         /* I2C control/status registers */
491         cpm->i2c_reg = of_iomap(ofdev->node, 0);
492         if (cpm->i2c_reg == NULL) {
493                 ret = -EINVAL;
494                 goto out_ram;
495         }
496
497         data = of_get_property(ofdev->node, "fsl,cpm-command", &len);
498         if (!data || len != 4) {
499                 ret = -EINVAL;
500                 goto out_reg;
501         }
502         cpm->cp_command = *data;
503
504         data = of_get_property(ofdev->node, "linux,i2c-class", &len);
505         if (data && len == 4)
506                 cpm->adap.class = *data;
507
508         data = of_get_property(ofdev->node, "clock-frequency", &len);
509         if (data && len == 4)
510                 cpm->freq = *data;
511         else
512                 cpm->freq = 60000; /* use 60kHz i2c clock by default */
513
514         /*
515          * Allocate space for CPM_MAXBD transmit and receive buffer
516          * descriptors in the DP ram.
517          */
518         cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
519         if (!cpm->dp_addr) {
520                 ret = -ENOMEM;
521                 goto out_reg;
522         }
523
524         cpm->tbase = cpm_muram_addr(cpm->dp_addr);
525         cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
526
527         /* Allocate TX and RX buffers */
528
529         tbdf = cpm->tbase;
530         rbdf = cpm->rbase;
531
532         for (i = 0; i < CPM_MAXBD; i++) {
533                 cpm->rxbuf[i] = dma_alloc_coherent(
534                         NULL, CPM_MAX_READ + 1, &cpm->rxdma[i], GFP_KERNEL);
535                 if (!cpm->rxbuf[i]) {
536                         ret = -ENOMEM;
537                         goto out_muram;
538                 }
539                 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
540
541                 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(
542                         NULL, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
543                 if (!cpm->txbuf[i]) {
544                         ret = -ENOMEM;
545                         goto out_muram;
546                 }
547                 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
548         }
549
550         /* Initialize Tx/Rx parameters. */
551
552         cpm_reset_i2c_params(cpm);
553
554         dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
555                 cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
556         dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
557                 (u8 __iomem *)cpm->tbase - DPRAM_BASE,
558                 (u8 __iomem *)cpm->rbase - DPRAM_BASE);
559
560         cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
561
562         /*
563          * Select an invalid address. Just make sure we don't use loopback mode
564          */
565         out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
566
567         /*
568          * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
569          * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
570          * the actual i2c bus frequency.
571          */
572         brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
573         out_8(&cpm->i2c_reg->i2brg, brg);
574
575         out_8(&cpm->i2c_reg->i2mod, 0x00);
576         out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);      /* Master mode */
577
578         /* Disable interrupts. */
579         out_8(&cpm->i2c_reg->i2cmr, 0);
580         out_8(&cpm->i2c_reg->i2cer, 0xff);
581
582         return 0;
583
584 out_muram:
585         for (i = 0; i < CPM_MAXBD; i++) {
586                 if (cpm->rxbuf[i])
587                         dma_free_coherent(NULL, CPM_MAX_READ + 1,
588                                 cpm->rxbuf[i], cpm->rxdma[i]);
589                 if (cpm->txbuf[i])
590                         dma_free_coherent(NULL, CPM_MAX_READ + 1,
591                                 cpm->txbuf[i], cpm->txdma[i]);
592         }
593         cpm_muram_free(cpm->dp_addr);
594 out_reg:
595         iounmap(cpm->i2c_reg);
596 out_ram:
597         if ((cpm->version == 1) && (!cpm->i2c_addr))
598                 iounmap(cpm->i2c_ram);
599         if (cpm->version == 2)
600                 cpm_muram_free(cpm->i2c_addr);
601 out_irq:
602         free_irq(cpm->irq, &cpm->adap);
603         return ret;
604 }
605
606 static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
607 {
608         int i;
609
610         /* Shut down I2C. */
611         clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
612
613         /* Disable interrupts */
614         out_8(&cpm->i2c_reg->i2cmr, 0);
615         out_8(&cpm->i2c_reg->i2cer, 0xff);
616
617         free_irq(cpm->irq, &cpm->adap);
618
619         /* Free all memory */
620         for (i = 0; i < CPM_MAXBD; i++) {
621                 dma_free_coherent(NULL, CPM_MAX_READ + 1,
622                         cpm->rxbuf[i], cpm->rxdma[i]);
623                 dma_free_coherent(NULL, CPM_MAX_READ + 1,
624                         cpm->txbuf[i], cpm->txdma[i]);
625         }
626
627         cpm_muram_free(cpm->dp_addr);
628         iounmap(cpm->i2c_reg);
629
630         if ((cpm->version == 1) && (!cpm->i2c_addr))
631                 iounmap(cpm->i2c_ram);
632         if (cpm->version == 2)
633                 cpm_muram_free(cpm->i2c_addr);
634 }
635
636 static int __devinit cpm_i2c_probe(struct of_device *ofdev,
637                          const struct of_device_id *match)
638 {
639         int result, len;
640         struct cpm_i2c *cpm;
641         const u32 *data;
642
643         cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
644         if (!cpm)
645                 return -ENOMEM;
646
647         cpm->ofdev = ofdev;
648
649         dev_set_drvdata(&ofdev->dev, cpm);
650
651         cpm->adap = cpm_ops;
652         i2c_set_adapdata(&cpm->adap, cpm);
653         cpm->adap.dev.parent = &ofdev->dev;
654
655         result = cpm_i2c_setup(cpm);
656         if (result) {
657                 dev_err(&ofdev->dev, "Unable to init hardware\n");
658                 goto out_free;
659         }
660
661         /* register new adapter to i2c module... */
662
663         data = of_get_property(ofdev->node, "linux,i2c-index", &len);
664         if (data && len == 4) {
665                 cpm->adap.nr = *data;
666                 result = i2c_add_numbered_adapter(&cpm->adap);
667         } else
668                 result = i2c_add_adapter(&cpm->adap);
669
670         if (result < 0) {
671                 dev_err(&ofdev->dev, "Unable to register with I2C\n");
672                 goto out_shut;
673         }
674
675         dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
676                 cpm->adap.name);
677
678         /*
679          * register OF I2C devices
680          */
681         of_register_i2c_devices(&cpm->adap, ofdev->node);
682
683         return 0;
684 out_shut:
685         cpm_i2c_shutdown(cpm);
686 out_free:
687         dev_set_drvdata(&ofdev->dev, NULL);
688         kfree(cpm);
689
690         return result;
691 }
692
693 static int __devexit cpm_i2c_remove(struct of_device *ofdev)
694 {
695         struct cpm_i2c *cpm = dev_get_drvdata(&ofdev->dev);
696
697         i2c_del_adapter(&cpm->adap);
698
699         cpm_i2c_shutdown(cpm);
700
701         dev_set_drvdata(&ofdev->dev, NULL);
702         kfree(cpm);
703
704         return 0;
705 }
706
707 static const struct of_device_id cpm_i2c_match[] = {
708         {
709                 .compatible = "fsl,cpm1-i2c",
710         },
711         {
712                 .compatible = "fsl,cpm2-i2c",
713         },
714         {},
715 };
716
717 MODULE_DEVICE_TABLE(of, cpm_i2c_match);
718
719 static struct of_platform_driver cpm_i2c_driver = {
720         .match_table    = cpm_i2c_match,
721         .probe          = cpm_i2c_probe,
722         .remove         = __devexit_p(cpm_i2c_remove),
723         .driver         = {
724                 .name   = "fsl-i2c-cpm",
725                 .owner  = THIS_MODULE,
726         }
727 };
728
729 static int __init cpm_i2c_init(void)
730 {
731         return of_register_platform_driver(&cpm_i2c_driver);
732 }
733
734 static void __exit cpm_i2c_exit(void)
735 {
736         of_unregister_platform_driver(&cpm_i2c_driver);
737 }
738
739 module_init(cpm_i2c_init);
740 module_exit(cpm_i2c_exit);
741
742 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
743 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
744 MODULE_LICENSE("GPL");