2 * include/asm-arm/arch-pnx4008/entry-macro.S
4 * Low-level IRQ helper macros for PNX4008-based platforms
6 * 2005-2006 (c) MontaVista Software, Inc.
7 * Author: Vitaly Wool <vwool@ru.mvista.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
15 #define IO_BASE 0xF0000000
16 #define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
18 #define INTRC_MASK 0x00
19 #define INTRC_RAW_STAT 0x04
20 #define INTRC_STAT 0x08
21 #define INTRC_POLAR 0x0C
22 #define INTRC_ACT_TYPE 0x10
23 #define INTRC_TYPE 0x14
25 #define SIC1_BASE_INT 32
26 #define SIC2_BASE_INT 64
31 .macro get_irqnr_preamble, base, tmp
34 .macro arch_ret_to_user, tmp1, tmp2
37 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
38 /* decode the MIC interrupt numbers */
39 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
40 ldr \irqstat, [\base, #INTRC_STAT]
45 movhs \irqstat,\irqstat,lsr#16
47 addhs \irqnr,\irqnr,#8
48 movhs \irqstat,\irqstat,lsr#8
50 addhs \irqnr,\irqnr,#4
51 movhs \irqstat,\irqstat,lsr#4
53 addhs \irqnr,\irqnr,#2
54 movhs \irqstat,\irqstat,lsr#2
56 addhs \irqnr,\irqnr,#1
58 /* was there an interrupt ? if not then drop out with EQ status */
62 /* and now check for extended IRQ reasons */
68 /* IRQ 31,30 : High priority cascade IRQ handle */
69 /* read the correct SIC */
70 /* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
71 /* set the base IRQ number */
72 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
73 moveq \irqnr,#SIC1_BASE_INT
74 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
75 movne \irqnr,#SIC2_BASE_INT
76 ldr \irqstat, [\base, #INTRC_STAT]
77 ldr \tmp, [\base, #INTRC_TYPE]
78 /* and with inverted mask : low priority interrupts */
79 and \irqstat,\irqstat,\tmp
83 /* IRQ 1,0 : Low priority cascade IRQ handle */
84 /* read the correct SIC */
85 /* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
86 /* read the correct SIC */
87 /* set the base IRQ number */
88 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
89 movne \irqnr,#SIC1_BASE_INT
90 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
91 moveq \irqnr,#SIC2_BASE_INT
92 ldr \irqstat, [\base, #INTRC_STAT]
93 ldr \tmp, [\base, #INTRC_TYPE]
94 /* and with inverted mask : low priority interrupts */
95 bic \irqstat,\irqstat,\tmp
100 addhs \irqnr,\irqnr,#16
101 movhs \irqstat,\irqstat,lsr#16
103 addhs \irqnr,\irqnr,#8
104 movhs \irqstat,\irqstat,lsr#8
106 addhs \irqnr,\irqnr,#4
107 movhs \irqstat,\irqstat,lsr#4
109 addhs \irqnr,\irqnr,#2
110 movhs \irqstat,\irqstat,lsr#2
112 addhs \irqnr,\irqnr,#1
115 /* is irqstat not zero */
118 /* we assert that irqstat is not equal to zero and return ne status if true*/
124 .macro irq_prio_table