2 * MPC8378E RDB Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "fsl,mpc8378rdb";
36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>;
38 d-cache-size = <32768>;
39 i-cache-size = <32768>;
40 timebase-frequency = <0>;
42 clock-frequency = <0>;
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; // 256MB at 0
54 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
55 reg = <0xe0005000 0x1000>;
56 interrupts = <77 0x8>;
57 interrupt-parent = <&ipic>;
59 // CS0 and CS1 are swapped when
60 // booting from nand, but the
61 // addresses are the same.
62 ranges = <0x0 0x0 0xfe000000 0x00800000
63 0x1 0x0 0xe0600000 0x00008000
64 0x2 0x0 0xf0000000 0x00020000
65 0x3 0x0 0xfa000000 0x00008000>;
70 compatible = "cfi-flash";
71 reg = <0x0 0x0 0x800000>;
79 compatible = "fsl,mpc8378-fcm-nand",
81 reg = <0x1 0x0 0x8000>;
89 reg = <0x100000 0x300000>;
92 reg = <0x400000 0x1c00000>;
101 compatible = "simple-bus";
102 ranges = <0x0 0xe0000000 0x00100000>;
103 reg = <0xe0000000 0x00000200>;
107 device_type = "watchdog";
108 compatible = "mpc83xx_wdt";
112 gpio1: gpio-controller@c00 {
114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
121 gpio2: gpio-controller@d00 {
123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
131 #address-cells = <1>;
134 compatible = "fsl-i2c";
135 reg = <0x3000 0x100>;
136 interrupts = <14 0x8>;
137 interrupt-parent = <&ipic>;
141 compatible = "national,lm75";
146 compatible = "at24,24c256";
151 compatible = "dallas,ds1339";
157 compatible = "fsl,mc9s08qg8-mpc8378erdb",
158 "fsl,mcu-mpc8349emitx";
165 #address-cells = <1>;
168 compatible = "fsl-i2c";
169 reg = <0x3100 0x100>;
170 interrupts = <15 0x8>;
171 interrupt-parent = <&ipic>;
177 compatible = "fsl,spi";
178 reg = <0x7000 0x1000>;
179 interrupts = <16 0x8>;
180 interrupt-parent = <&ipic>;
185 #address-cells = <1>;
187 compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
189 ranges = <0 0x8100 0x1a8>;
190 interrupt-parent = <&ipic>;
194 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
197 interrupt-parent = <&ipic>;
201 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
204 interrupt-parent = <&ipic>;
208 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
211 interrupt-parent = <&ipic>;
215 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
218 interrupt-parent = <&ipic>;
224 compatible = "fsl-usb2-dr";
225 reg = <0x23000 0x1000>;
226 #address-cells = <1>;
228 interrupt-parent = <&ipic>;
229 interrupts = <38 0x8>;
234 #address-cells = <1>;
236 compatible = "fsl,gianfar-mdio";
237 reg = <0x24520 0x20>;
238 phy2: ethernet-phy@2 {
239 interrupt-parent = <&ipic>;
240 interrupts = <17 0x8>;
242 device_type = "ethernet-phy";
246 device_type = "tbi-phy";
251 #address-cells = <1>;
253 compatible = "fsl,gianfar-tbi";
254 reg = <0x25520 0x20>;
258 device_type = "tbi-phy";
263 enet0: ethernet@24000 {
265 device_type = "network";
267 compatible = "gianfar";
268 reg = <0x24000 0x1000>;
269 local-mac-address = [ 00 00 00 00 00 00 ];
270 interrupts = <32 0x8 33 0x8 34 0x8>;
271 phy-connection-type = "mii";
272 interrupt-parent = <&ipic>;
273 phy-handle = <&phy2>;
276 enet1: ethernet@25000 {
278 device_type = "network";
280 compatible = "gianfar";
281 reg = <0x25000 0x1000>;
282 local-mac-address = [ 00 00 00 00 00 00 ];
283 interrupts = <35 0x8 36 0x8 37 0x8>;
284 phy-connection-type = "mii";
285 interrupt-parent = <&ipic>;
286 fixed-link = <1 1 1000 0 0>;
289 serial0: serial@4500 {
291 device_type = "serial";
292 compatible = "ns16550";
293 reg = <0x4500 0x100>;
294 clock-frequency = <0>;
295 interrupts = <9 0x8>;
296 interrupt-parent = <&ipic>;
299 serial1: serial@4600 {
301 device_type = "serial";
302 compatible = "ns16550";
303 reg = <0x4600 0x100>;
304 clock-frequency = <0>;
305 interrupts = <10 0x8>;
306 interrupt-parent = <&ipic>;
310 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
311 "fsl,sec2.1", "fsl,sec2.0";
312 reg = <0x30000 0x10000>;
313 interrupts = <11 0x8>;
314 interrupt-parent = <&ipic>;
315 fsl,num-channels = <4>;
316 fsl,channel-fifo-len = <24>;
317 fsl,exec-units-mask = <0x9fe>;
318 fsl,descriptor-types-mask = <0x3ab0ebf>;
322 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
323 reg = <0x2e000 0x1000>;
324 interrupts = <42 0x8>;
325 interrupt-parent = <&ipic>;
326 /* Filled in by U-Boot */
327 clock-frequency = <0>;
331 * interrupts cell = <intr #, sense>
332 * sense values match linux IORESOURCE_IRQ_* defines:
333 * sense == 8: Level, low assertion
334 * sense == 2: Edge, high-to-low change
336 ipic: interrupt-controller@700 {
337 compatible = "fsl,ipic";
338 interrupt-controller;
339 #address-cells = <0>;
340 #interrupt-cells = <2>;
346 interrupt-map-mask = <0xf800 0 0 7>;
348 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
350 /* IDSEL AD14 IRQ6 inta */
351 0x7000 0x0 0x0 0x1 &ipic 22 0x8
353 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
354 0x7800 0x0 0x0 0x1 &ipic 21 0x8
355 0x7800 0x0 0x0 0x2 &ipic 22 0x8
356 0x7800 0x0 0x0 0x4 &ipic 23 0x8
358 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
359 0xE000 0x0 0x0 0x1 &ipic 23 0x8
360 0xE000 0x0 0x0 0x2 &ipic 21 0x8
361 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
362 interrupt-parent = <&ipic>;
363 interrupts = <66 0x8>;
365 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
366 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
367 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
368 clock-frequency = <66666666>;
369 #interrupt-cells = <1>;
371 #address-cells = <3>;
372 reg = <0xe0008500 0x100 /* internal registers */
373 0xe0008300 0x8>; /* config space access registers */
374 compatible = "fsl,mpc8349-pci";
378 pci1: pcie@e0009000 {
379 #address-cells = <3>;
381 #interrupt-cells = <1>;
383 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
384 reg = <0xe0009000 0x00001000>;
385 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
386 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
388 interrupt-map-mask = <0xf800 0 0 7>;
389 interrupt-map = <0 0 0 1 &ipic 1 8
393 clock-frequency = <0>;
396 #address-cells = <3>;
400 ranges = <0x02000000 0 0xa8000000
401 0x02000000 0 0xa8000000
403 0x01000000 0 0x00000000
404 0x01000000 0 0x00000000
409 pci2: pcie@e000a000 {
410 #address-cells = <3>;
412 #interrupt-cells = <1>;
414 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
415 reg = <0xe000a000 0x00001000>;
416 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
417 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
419 interrupt-map-mask = <0xf800 0 0 7>;
420 interrupt-map = <0 0 0 1 &ipic 2 8
424 clock-frequency = <0>;
427 #address-cells = <3>;
431 ranges = <0x02000000 0 0xc8000000
432 0x02000000 0 0xc8000000
434 0x01000000 0 0x00000000
435 0x01000000 0 0x00000000