git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/pci.h>
  23 #include <linux/delay.h>
  24 #include <linux/crc32.h>
  25 #include <linux/eeprom_93cx6.h>
  26 #include <net/mac80211.h>
  27
  28 #include "adm8211.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  33 MODULE_SUPPORTED_DEVICE("ADM8211");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int tx_ring_size __read_mostly = 16;
  37 static unsigned int rx_ring_size __read_mostly = 16;
  38
  39 module_param(tx_ring_size, uint, 0);
  40 module_param(rx_ring_size, uint, 0);
  41
  42 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
  43         /* ADMtek ADM8211 */
  44         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  45         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  46         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  47         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  48         { 0 }
  49 };
  50
  51 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  52 {
  53         struct adm8211_priv *priv = eeprom->data;
  54         u32 reg = ADM8211_CSR_READ(SPR);
  55
  56         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  57         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  58         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  59         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  60 }
  61
  62 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  63 {
  64         struct adm8211_priv *priv = eeprom->data;
  65         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  66
  67         if (eeprom->reg_data_in)
  68                 reg |= ADM8211_SPR_SDI;
  69         if (eeprom->reg_data_out)
  70                 reg |= ADM8211_SPR_SDO;
  71         if (eeprom->reg_data_clock)
  72                 reg |= ADM8211_SPR_SCLK;
  73         if (eeprom->reg_chip_select)
  74                 reg |= ADM8211_SPR_SCS;
  75
  76         ADM8211_CSR_WRITE(SPR, reg);
  77         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
  78 }
  79
  80 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
  81 {
  82         struct adm8211_priv *priv = dev->priv;
  83         unsigned int words, i;
  84         struct ieee80211_chan_range chan_range;
  85         u16 cr49;
  86         struct eeprom_93cx6 eeprom = {
  87                 .data           = priv,
  88                 .register_read  = adm8211_eeprom_register_read,
  89                 .register_write = adm8211_eeprom_register_write
  90         };
  91
  92         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
  93                 /* 256 * 16-bit = 512 bytes */
  94                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
  95                 words = 256;
  96         } else {
  97                 /* 64 * 16-bit = 128 bytes */
  98                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
  99                 words = 64;
 100         }
 101
 102         priv->eeprom_len = words * 2;
 103         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 104         if (!priv->eeprom)
 105                 return -ENOMEM;
 106
 107         eeprom_93cx6_multiread(&eeprom, 0, (__le16 __force *)priv->eeprom, words);
 108
 109         cr49 = le16_to_cpu(priv->eeprom->cr49);
 110         priv->rf_type = (cr49 >> 3) & 0x7;
 111         switch (priv->rf_type) {
 112         case ADM8211_TYPE_INTERSIL:
 113         case ADM8211_TYPE_RFMD:
 114         case ADM8211_TYPE_MARVEL:
 115         case ADM8211_TYPE_AIROHA:
 116         case ADM8211_TYPE_ADMTEK:
 117                 break;
 118
 119         default:
 120                 if (priv->pdev->revision < ADM8211_REV_CA)
 121                         priv->rf_type = ADM8211_TYPE_RFMD;
 122                 else
 123                         priv->rf_type = ADM8211_TYPE_AIROHA;
 124
 125                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 126                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 127         }
 128
 129         priv->bbp_type = cr49 & 0x7;
 130         switch (priv->bbp_type) {
 131         case ADM8211_TYPE_INTERSIL:
 132         case ADM8211_TYPE_RFMD:
 133         case ADM8211_TYPE_MARVEL:
 134         case ADM8211_TYPE_AIROHA:
 135         case ADM8211_TYPE_ADMTEK:
 136                 break;
 137         default:
 138                 if (priv->pdev->revision < ADM8211_REV_CA)
 139                         priv->bbp_type = ADM8211_TYPE_RFMD;
 140                 else
 141                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 142
 143                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 144                        pci_name(priv->pdev), cr49 >> 3);
 145         }
 146
 147         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 148                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 149                        pci_name(priv->pdev), priv->eeprom->country_code);
 150
 151                 chan_range = cranges[2];
 152         } else
 153                 chan_range = cranges[priv->eeprom->country_code];
 154
 155         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 156                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 157
 158         priv->modes[0].num_channels = chan_range.max - chan_range.min + 1;
 159         priv->modes[0].channels = priv->channels;
 160
 161         memcpy(priv->channels, adm8211_channels, sizeof(adm8211_channels));
 162
 163         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 164                 if (i >= chan_range.min && i <= chan_range.max)
 165                         priv->channels[i - 1].flag =
 166                                 IEEE80211_CHAN_W_SCAN |
 167                                 IEEE80211_CHAN_W_ACTIVE_SCAN |
 168                                 IEEE80211_CHAN_W_IBSS;
 169
 170         switch (priv->eeprom->specific_bbptype) {
 171         case ADM8211_BBP_RFMD3000:
 172         case ADM8211_BBP_RFMD3002:
 173         case ADM8211_BBP_ADM8011:
 174                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 175                 break;
 176
 177         default:
 178                 if (priv->pdev->revision < ADM8211_REV_CA)
 179                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 180                 else
 181                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 182
 183                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 184                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 185         }
 186
 187         switch (priv->eeprom->specific_rftype) {
 188         case ADM8211_RFMD2948:
 189         case ADM8211_RFMD2958:
 190         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 191         case ADM8211_MAX2820:
 192         case ADM8211_AL2210L:
 193                 priv->transceiver_type = priv->eeprom->specific_rftype;
 194                 break;
 195
 196         default:
 197                 if (priv->pdev->revision == ADM8211_REV_BA)
 198                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 199                 else if (priv->pdev->revision == ADM8211_REV_CA)
 200                         priv->transceiver_type = ADM8211_AL2210L;
 201                 else if (priv->pdev->revision == ADM8211_REV_AB)
 202                         priv->transceiver_type = ADM8211_RFMD2948;
 203
 204                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 205                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 206
 207                 break;
 208         }
 209
 210         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 211                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 212                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 213
 214         return 0;
 215 }
 216
 217 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 218                                       u32 addr, u32 data)
 219 {
 220         struct adm8211_priv *priv = dev->priv;
 221
 222         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 223                           (priv->pdev->revision < ADM8211_REV_BA ?
 224                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 225         ADM8211_CSR_READ(WEPCTL);
 226         msleep(1);
 227
 228         ADM8211_CSR_WRITE(WESK, data);
 229         ADM8211_CSR_READ(WESK);
 230         msleep(1);
 231 }
 232
 233 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 234                                      unsigned int addr, u8 *buf,
 235                                      unsigned int len)
 236 {
 237         struct adm8211_priv *priv = dev->priv;
 238         u32 reg = ADM8211_CSR_READ(WEPCTL);
 239         unsigned int i;
 240
 241         if (priv->pdev->revision < ADM8211_REV_BA) {
 242                 for (i = 0; i < len; i += 2) {
 243                         u16 val = buf[i] | (buf[i + 1] << 8);
 244                         adm8211_write_sram(dev, addr + i / 2, val);
 245                 }
 246         } else {
 247                 for (i = 0; i < len; i += 4) {
 248                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 249                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 250                         adm8211_write_sram(dev, addr + i / 4, val);
 251                 }
 252         }
 253
 254         ADM8211_CSR_WRITE(WEPCTL, reg);
 255 }
 256
 257 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 258 {
 259         struct adm8211_priv *priv = dev->priv;
 260         u32 reg = ADM8211_CSR_READ(WEPCTL);
 261         unsigned int addr;
 262
 263         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 264                 adm8211_write_sram(dev, addr, 0);
 265
 266         ADM8211_CSR_WRITE(WEPCTL, reg);
 267 }
 268
 269 static int adm8211_get_stats(struct ieee80211_hw *dev,
 270                              struct ieee80211_low_level_stats *stats)
 271 {
 272         struct adm8211_priv *priv = dev->priv;
 273
 274         memcpy(stats, &priv->stats, sizeof(*stats));
 275
 276         return 0;
 277 }
 278
 279 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
 280                                 struct ieee80211_tx_queue_stats *stats)
 281 {
 282         struct adm8211_priv *priv = dev->priv;
 283         struct ieee80211_tx_queue_stats_data *data = &stats->data[0];
 284
 285         data->len = priv->cur_tx - priv->dirty_tx;
 286         data->limit = priv->tx_ring_size - 2;
 287         data->count = priv->dirty_tx;
 288
 289         return 0;
 290 }
 291
 292 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 293 {
 294         struct adm8211_priv *priv = dev->priv;
 295         unsigned int dirty_tx;
 296
 297         spin_lock(&priv->lock);
 298
 299         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 300                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 301                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 302                 struct ieee80211_tx_status tx_status;
 303                 struct adm8211_tx_ring_info *info;
 304                 struct sk_buff *skb;
 305
 306                 if (status & TDES0_CONTROL_OWN ||
 307                     !(status & TDES0_CONTROL_DONE))
 308                         break;
 309
 310                 info = &priv->tx_buffers[entry];
 311                 skb = info->skb;
 312
 313                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 314
 315                 pci_unmap_single(priv->pdev, info->mapping,
 316                                  info->skb->len, PCI_DMA_TODEVICE);
 317
 318                 memset(&tx_status, 0, sizeof(tx_status));
 319                 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 320                 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
 321                 memcpy(&tx_status.control, &info->tx_control,
 322                        sizeof(tx_status.control));
 323                 if (!(tx_status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
 324                         if (status & TDES0_STATUS_ES)
 325                                 tx_status.excessive_retries = 1;
 326                         else
 327                                 tx_status.flags |= IEEE80211_TX_STATUS_ACK;
 328                 }
 329                 ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
 330
 331                 info->skb = NULL;
 332         }
 333
 334         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 335                 ieee80211_wake_queue(dev, 0);
 336
 337         priv->dirty_tx = dirty_tx;
 338         spin_unlock(&priv->lock);
 339 }
 340
 341
 342 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 343 {
 344         struct adm8211_priv *priv = dev->priv;
 345         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 346         u32 status;
 347         unsigned int pktlen;
 348         struct sk_buff *skb, *newskb;
 349         unsigned int limit = priv->rx_ring_size;
 350         static const u8 rate_tbl[] = {10, 20, 55, 110, 220};
 351         u8 rssi, rate;
 352
 353         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 354                 if (!limit--)
 355                         break;
 356
 357                 status = le32_to_cpu(priv->rx_ring[entry].status);
 358                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 359                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 360                         RDES1_STATUS_RSSI;
 361
 362                 pktlen = status & RDES0_STATUS_FL;
 363                 if (pktlen > RX_PKT_SIZE) {
 364                         if (net_ratelimit())
 365                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 366                                        wiphy_name(dev->wiphy), pktlen);
 367                         pktlen = RX_PKT_SIZE;
 368                 }
 369
 370                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 371                         skb = NULL; /* old buffer will be reused */
 372                         /* TODO: update RX error stats */
 373                         /* TODO: check RDES0_STATUS_CRC*E */
 374                 } else if (pktlen < RX_COPY_BREAK) {
 375                         skb = dev_alloc_skb(pktlen);
 376                         if (skb) {
 377                                 pci_dma_sync_single_for_cpu(
 378                                         priv->pdev,
 379                                         priv->rx_buffers[entry].mapping,
 380                                         pktlen, PCI_DMA_FROMDEVICE);
 381                                 memcpy(skb_put(skb, pktlen),
 382                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 383                                        pktlen);
 384                                 pci_dma_sync_single_for_device(
 385                                         priv->pdev,
 386                                         priv->rx_buffers[entry].mapping,
 387                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 388                         }
 389                 } else {
 390                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 391                         if (newskb) {
 392                                 skb = priv->rx_buffers[entry].skb;
 393                                 skb_put(skb, pktlen);
 394                                 pci_unmap_single(
 395                                         priv->pdev,
 396                                         priv->rx_buffers[entry].mapping,
 397                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 398                                 priv->rx_buffers[entry].skb = newskb;
 399                                 priv->rx_buffers[entry].mapping =
 400                                         pci_map_single(priv->pdev,
 401                                                        skb_tail_pointer(newskb),
 402                                                        RX_PKT_SIZE,
 403                                                        PCI_DMA_FROMDEVICE);
 404                         } else {
 405                                 skb = NULL;
 406                                 /* TODO: update rx dropped stats */
 407                         }
 408
 409                         priv->rx_ring[entry].buffer1 =
 410                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 411                 }
 412
 413                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 414                                                           RDES0_STATUS_SQL);
 415                 priv->rx_ring[entry].length =
 416                         cpu_to_le32(RX_PKT_SIZE |
 417                                     (entry == priv->rx_ring_size - 1 ?
 418                                      RDES1_CONTROL_RER : 0));
 419
 420                 if (skb) {
 421                         struct ieee80211_rx_status rx_status = {0};
 422
 423                         if (priv->pdev->revision < ADM8211_REV_CA)
 424                                 rx_status.ssi = rssi;
 425                         else
 426                                 rx_status.ssi = 100 - rssi;
 427
 428                         if (rate <= 4)
 429                                 rx_status.rate = rate_tbl[rate];
 430
 431                         rx_status.channel = priv->channel;
 432                         rx_status.freq = adm8211_channels[priv->channel - 1].freq;
 433                         rx_status.phymode = MODE_IEEE80211B;
 434
 435                         ieee80211_rx_irqsafe(dev, skb, &rx_status);
 436                 }
 437
 438                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 439         }
 440
 441         /* TODO: check LPC and update stats? */
 442 }
 443
 444
 445 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 446 {
 447 #define ADM8211_INT(x)                                                     \
 448 do {                                                                       \
 449         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 450                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 451 } while (0)
 452
 453         struct ieee80211_hw *dev = dev_id;
 454         struct adm8211_priv *priv = dev->priv;
 455         u32 stsr = ADM8211_CSR_READ(STSR);
 456         ADM8211_CSR_WRITE(STSR, stsr);
 457         if (stsr == 0xffffffff)
 458                 return IRQ_HANDLED;
 459
 460         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 461                 return IRQ_HANDLED;
 462
 463         if (stsr & ADM8211_STSR_RCI)
 464                 adm8211_interrupt_rci(dev);
 465         if (stsr & ADM8211_STSR_TCI)
 466                 adm8211_interrupt_tci(dev);
 467
 468         /*ADM8211_INT(LinkOn);*/
 469         /*ADM8211_INT(LinkOff);*/
 470
 471         ADM8211_INT(PCF);
 472         ADM8211_INT(BCNTC);
 473         ADM8211_INT(GPINT);
 474         ADM8211_INT(ATIMTC);
 475         ADM8211_INT(TSFTF);
 476         ADM8211_INT(TSCZ);
 477         ADM8211_INT(SQL);
 478         ADM8211_INT(WEPTD);
 479         ADM8211_INT(ATIME);
 480         /*ADM8211_INT(TBTT);*/
 481         ADM8211_INT(TEIS);
 482         ADM8211_INT(FBE);
 483         ADM8211_INT(REIS);
 484         ADM8211_INT(GPTT);
 485         ADM8211_INT(RPS);
 486         ADM8211_INT(RDU);
 487         ADM8211_INT(TUF);
 488         /*ADM8211_INT(TRT);*/
 489         /*ADM8211_INT(TLT);*/
 490         /*ADM8211_INT(TDU);*/
 491         ADM8211_INT(TPS);
 492
 493         return IRQ_HANDLED;
 494
 495 #undef ADM8211_INT
 496 }
 497
 498 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 499 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 500                                            u16 addr, u32 value) {            \
 501         struct adm8211_priv *priv = dev->priv;                               \
 502         unsigned int i;                                                      \
 503         u32 reg, bitbuf;                                                     \
 504                                                                              \
 505         value &= v_mask;                                                     \
 506         addr &= a_mask;                                                      \
 507         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 508                                                                              \
 509         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 510         ADM8211_CSR_READ(SYNRF);                                             \
 511         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 512         ADM8211_CSR_READ(SYNRF);                                             \
 513                                                                              \
 514         if (prewrite) {                                                      \
 515                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 516                 ADM8211_CSR_READ(SYNRF);                                     \
 517         }                                                                    \
 518                                                                              \
 519         for (i = 0; i <= bits; i++) {                                        \
 520                 if (bitbuf & (1 << (bits - i)))                              \
 521                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 522                 else                                                         \
 523                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 524                                                                              \
 525                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 526                 ADM8211_CSR_READ(SYNRF);                                     \
 527                                                                              \
 528                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 529                 ADM8211_CSR_READ(SYNRF);                                     \
 530                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 531                 ADM8211_CSR_READ(SYNRF);                                     \
 532         }                                                                    \
 533                                                                              \
 534         if (postwrite == 1) {                                                \
 535                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 536                 ADM8211_CSR_READ(SYNRF);                                     \
 537         }                                                                    \
 538         if (postwrite == 2) {                                                \
 539                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 540                 ADM8211_CSR_READ(SYNRF);                                     \
 541         }                                                                    \
 542                                                                              \
 543         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 544         ADM8211_CSR_READ(SYNRF);                                             \
 545 }
 546
 547 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 548 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 549 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 550 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 551
 552 #undef WRITE_SYN
 553
 554 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 555 {
 556         struct adm8211_priv *priv = dev->priv;
 557         unsigned int timeout;
 558         u32 reg;
 559
 560         timeout = 10;
 561         while (timeout > 0) {
 562                 reg = ADM8211_CSR_READ(BBPCTL);
 563                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 564                         break;
 565                 timeout--;
 566                 msleep(2);
 567         }
 568
 569         if (timeout == 0) {
 570                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 571                        " prewrite (reg=0x%08x)\n",
 572                        wiphy_name(dev->wiphy), addr, data, reg);
 573                 return -ETIMEDOUT;
 574         }
 575
 576         switch (priv->bbp_type) {
 577         case ADM8211_TYPE_INTERSIL:
 578                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 579                 break;
 580         case ADM8211_TYPE_RFMD:
 581                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 582                       (0x01 << 18);
 583                 break;
 584         case ADM8211_TYPE_ADMTEK:
 585                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 586                       (0x05 << 18);
 587                 break;
 588         }
 589         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 590
 591         ADM8211_CSR_WRITE(BBPCTL, reg);
 592
 593         timeout = 10;
 594         while (timeout > 0) {
 595                 reg = ADM8211_CSR_READ(BBPCTL);
 596                 if (!(reg & ADM8211_BBPCTL_WR))
 597                         break;
 598                 timeout--;
 599                 msleep(2);
 600         }
 601
 602         if (timeout == 0) {
 603                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 604                                   ~ADM8211_BBPCTL_WR);
 605                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 606                        " postwrite (reg=0x%08x)\n",
 607                        wiphy_name(dev->wiphy), addr, data, reg);
 608                 return -ETIMEDOUT;
 609         }
 610
 611         return 0;
 612 }
 613
 614 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 615 {
 616         static const u32 adm8211_rfmd2958_reg5[] =
 617                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 618                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 619         static const u32 adm8211_rfmd2958_reg6[] =
 620                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 621                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 622
 623         struct adm8211_priv *priv = dev->priv;
 624         u8 ant_power = priv->ant_power > 0x3F ?
 625                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 626         u8 tx_power = priv->tx_power > 0x3F ?
 627                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 628         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 629                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 630         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 631                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 632         u32 reg;
 633
 634         ADM8211_IDLE();
 635
 636         /* Program synthesizer to new channel */
 637         switch (priv->transceiver_type) {
 638         case ADM8211_RFMD2958:
 639         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 640                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 641                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 642
 643                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 644                         adm8211_rfmd2958_reg5[chan - 1]);
 645                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 646                         adm8211_rfmd2958_reg6[chan - 1]);
 647                 break;
 648
 649         case ADM8211_RFMD2948:
 650                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 651                                               SI4126_MAIN_XINDIV2);
 652                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 653                                               SI4126_POWERDOWN_PDIB |
 654                                               SI4126_POWERDOWN_PDRB);
 655                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 656                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 657                                               (chan == 14 ?
 658                                                2110 : (2033 + (chan * 5))));
 659                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 660                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 661                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 662                 break;
 663
 664         case ADM8211_MAX2820:
 665                 adm8211_rf_write_syn_max2820(dev, 0x3,
 666                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 667                 break;
 668
 669         case ADM8211_AL2210L:
 670                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 671                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 672                 break;
 673
 674         default:
 675                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 676                        wiphy_name(dev->wiphy), priv->transceiver_type);
 677                 break;
 678         }
 679
 680         /* write BBP regs */
 681         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 682
 683         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 684         /* TODO: remove if SMC 2635W doesn't need this */
 685         if (priv->transceiver_type == ADM8211_RFMD2948) {
 686                 reg = ADM8211_CSR_READ(GPIO);
 687                 reg &= 0xfffc0000;
 688                 reg |= ADM8211_CSR_GPIO_EN0;
 689                 if (chan != 14)
 690                         reg |= ADM8211_CSR_GPIO_O0;
 691                 ADM8211_CSR_WRITE(GPIO, reg);
 692         }
 693
 694         if (priv->transceiver_type == ADM8211_RFMD2958) {
 695                 /* set PCNT2 */
 696                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 697                 /* set PCNT1 P_DESIRED/MID_BIAS */
 698                 reg = le16_to_cpu(priv->eeprom->cr49);
 699                 reg >>= 13;
 700                 reg <<= 15;
 701                 reg |= ant_power << 9;
 702                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 703                 /* set TXRX TX_GAIN */
 704                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 705                         (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
 706         } else {
 707                 reg = ADM8211_CSR_READ(PLCPHD);
 708                 reg &= 0xff00ffff;
 709                 reg |= tx_power << 18;
 710                 ADM8211_CSR_WRITE(PLCPHD, reg);
 711         }
 712
 713         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 714                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 715         ADM8211_CSR_READ(SYNRF);
 716         msleep(30);
 717
 718         /* RF3000 BBP */
 719         if (priv->transceiver_type != ADM8211_RFMD2958)
 720                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 721                                   tx_power<<2);
 722         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 723         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 724         adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
 725                                      priv->eeprom->cr28 : 0);
 726         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 727
 728         ADM8211_CSR_WRITE(SYNRF, 0);
 729
 730         /* Nothing to do for ADMtek BBP */
 731         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 732                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 733                        wiphy_name(dev->wiphy), priv->bbp_type);
 734
 735         ADM8211_RESTORE();
 736
 737         /* update current channel for adhoc (and maybe AP mode) */
 738         reg = ADM8211_CSR_READ(CAP0);
 739         reg &= ~0xF;
 740         reg |= chan;
 741         ADM8211_CSR_WRITE(CAP0, reg);
 742
 743         return 0;
 744 }
 745
 746 static void adm8211_update_mode(struct ieee80211_hw *dev)
 747 {
 748         struct adm8211_priv *priv = dev->priv;
 749
 750         ADM8211_IDLE();
 751
 752         priv->soft_rx_crc = 0;
 753         switch (priv->mode) {
 754         case IEEE80211_IF_TYPE_STA:
 755                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 756                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 757                 break;
 758         case IEEE80211_IF_TYPE_IBSS:
 759                 priv->nar &= ~ADM8211_NAR_PR;
 760                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 761
 762                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 763                 if (priv->pdev->revision >= ADM8211_REV_BA)
 764                         priv->soft_rx_crc = 1;
 765                 break;
 766         case IEEE80211_IF_TYPE_MNTR:
 767                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 768                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 769                 break;
 770         }
 771
 772         ADM8211_RESTORE();
 773 }
 774
 775 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 776 {
 777         struct adm8211_priv *priv = dev->priv;
 778
 779         switch (priv->transceiver_type) {
 780         case ADM8211_RFMD2958:
 781         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 782                 /* comments taken from ADMtek vendor driver */
 783
 784                 /* Reset RF2958 after power on */
 785                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 786                 /* Initialize RF VCO Core Bias to maximum */
 787                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 788                 /* Initialize IF PLL */
 789                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 790                 /* Initialize IF PLL Coarse Tuning */
 791                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 792                 /* Initialize RF PLL */
 793                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 794                 /* Initialize RF PLL Coarse Tuning */
 795                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 796                 /* Initialize TX gain and filter BW (R9) */
 797                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 798                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 799                          0x10050 : 0x00050));
 800                 /* Initialize CAL register */
 801                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 802                 break;
 803
 804         case ADM8211_MAX2820:
 805                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 806                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 807                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 808                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 809                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 810                 break;
 811
 812         case ADM8211_AL2210L:
 813                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 814                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 815                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 816                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 817                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 818                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 819                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 820                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 821                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 822                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 823                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 824                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 825                 break;
 826
 827         case ADM8211_RFMD2948:
 828         default:
 829                 break;
 830         }
 831 }
 832
 833 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 834 {
 835         struct adm8211_priv *priv = dev->priv;
 836         u32 reg;
 837
 838         /* write addresses */
 839         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 840                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 841                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 842                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 843         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 844                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 845                 /* check specific BBP type */
 846                 switch (priv->specific_bbptype) {
 847                 case ADM8211_BBP_RFMD3000:
 848                 case ADM8211_BBP_RFMD3002:
 849                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 850                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 851                         break;
 852
 853                 case ADM8211_BBP_ADM8011:
 854                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 855                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 856
 857                         reg = ADM8211_CSR_READ(BBPCTL);
 858                         reg &= ~ADM8211_BBPCTL_TYPE;
 859                         reg |= 0x5 << 18;
 860                         ADM8211_CSR_WRITE(BBPCTL, reg);
 861                         break;
 862                 }
 863
 864                 switch (priv->pdev->revision) {
 865                 case ADM8211_REV_CA:
 866                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 867                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 868                             priv->transceiver_type == ADM8211_RFMD2948)
 869                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 870                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 871                                  priv->transceiver_type == ADM8211_AL2210L)
 872                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 873                         break;
 874
 875                 case ADM8211_REV_BA:
 876                         reg  = ADM8211_CSR_READ(MMIRD1);
 877                         reg &= 0x0000FFFF;
 878                         reg |= 0x7e100000;
 879                         ADM8211_CSR_WRITE(MMIRD1, reg);
 880                         break;
 881
 882                 case ADM8211_REV_AB:
 883                 case ADM8211_REV_AF:
 884                 default:
 885                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 886                         break;
 887                 }
 888
 889                 /* For RFMD */
 890                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 891         }
 892
 893         adm8211_hw_init_syn(dev);
 894
 895         /* Set RF Power control IF pin to PE1+PHYRST# */
 896         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 897                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 898         ADM8211_CSR_READ(SYNRF);
 899         msleep(20);
 900
 901         /* write BBP regs */
 902         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 903                 /* RF3000 BBP */
 904                 /* another set:
 905                  * 11: c8
 906                  * 14: 14
 907                  * 15: 50 (chan 1..13; chan 14: d0)
 908                  * 1c: 00
 909                  * 1d: 84
 910                  */
 911                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 912                 /* antenna selection: diversity */
 913                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 914                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 915                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 916                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 917
 918                 if (priv->eeprom->major_version < 2) {
 919                         adm8211_write_bbp(dev, 0x1c, 0x00);
 920                         adm8211_write_bbp(dev, 0x1d, 0x80);
 921                 } else {
 922                         if (priv->pdev->revision == ADM8211_REV_BA)
 923                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 924                         else
 925                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 926
 927                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 928                 }
 929         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 930                 /* reset baseband */
 931                 adm8211_write_bbp(dev, 0x00, 0xFF);
 932                 /* antenna selection: diversity */
 933                 adm8211_write_bbp(dev, 0x07, 0x0A);
 934
 935                 /* TODO: find documentation for this */
 936                 switch (priv->transceiver_type) {
 937                 case ADM8211_RFMD2958:
 938                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 939                         adm8211_write_bbp(dev, 0x00, 0x00);
 940                         adm8211_write_bbp(dev, 0x01, 0x00);
 941                         adm8211_write_bbp(dev, 0x02, 0x00);
 942                         adm8211_write_bbp(dev, 0x03, 0x00);
 943                         adm8211_write_bbp(dev, 0x06, 0x0f);
 944                         adm8211_write_bbp(dev, 0x09, 0x00);
 945                         adm8211_write_bbp(dev, 0x0a, 0x00);
 946                         adm8211_write_bbp(dev, 0x0b, 0x00);
 947                         adm8211_write_bbp(dev, 0x0c, 0x00);
 948                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 949                         adm8211_write_bbp(dev, 0x10, 0x8c);
 950                         adm8211_write_bbp(dev, 0x11, 0x43);
 951                         adm8211_write_bbp(dev, 0x18, 0x40);
 952                         adm8211_write_bbp(dev, 0x20, 0x23);
 953                         adm8211_write_bbp(dev, 0x21, 0x02);
 954                         adm8211_write_bbp(dev, 0x22, 0x28);
 955                         adm8211_write_bbp(dev, 0x23, 0x30);
 956                         adm8211_write_bbp(dev, 0x24, 0x2d);
 957                         adm8211_write_bbp(dev, 0x28, 0x35);
 958                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 959                         adm8211_write_bbp(dev, 0x2b, 0x81);
 960                         adm8211_write_bbp(dev, 0x2c, 0x44);
 961                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 962                         adm8211_write_bbp(dev, 0x29, 0x40);
 963                         adm8211_write_bbp(dev, 0x60, 0x08);
 964                         adm8211_write_bbp(dev, 0x64, 0x01);
 965                         break;
 966
 967                 case ADM8211_MAX2820:
 968                         adm8211_write_bbp(dev, 0x00, 0x00);
 969                         adm8211_write_bbp(dev, 0x01, 0x00);
 970                         adm8211_write_bbp(dev, 0x02, 0x00);
 971                         adm8211_write_bbp(dev, 0x03, 0x00);
 972                         adm8211_write_bbp(dev, 0x06, 0x0f);
 973                         adm8211_write_bbp(dev, 0x09, 0x05);
 974                         adm8211_write_bbp(dev, 0x0a, 0x02);
 975                         adm8211_write_bbp(dev, 0x0b, 0x00);
 976                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 977                         adm8211_write_bbp(dev, 0x0f, 0x55);
 978                         adm8211_write_bbp(dev, 0x10, 0x8d);
 979                         adm8211_write_bbp(dev, 0x11, 0x43);
 980                         adm8211_write_bbp(dev, 0x18, 0x4a);
 981                         adm8211_write_bbp(dev, 0x20, 0x20);
 982                         adm8211_write_bbp(dev, 0x21, 0x02);
 983                         adm8211_write_bbp(dev, 0x22, 0x23);
 984                         adm8211_write_bbp(dev, 0x23, 0x30);
 985                         adm8211_write_bbp(dev, 0x24, 0x2d);
 986                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 987                         adm8211_write_bbp(dev, 0x2b, 0x81);
 988                         adm8211_write_bbp(dev, 0x2c, 0x44);
 989                         adm8211_write_bbp(dev, 0x29, 0x4a);
 990                         adm8211_write_bbp(dev, 0x60, 0x2b);
 991                         adm8211_write_bbp(dev, 0x64, 0x01);
 992                         break;
 993
 994                 case ADM8211_AL2210L:
 995                         adm8211_write_bbp(dev, 0x00, 0x00);
 996                         adm8211_write_bbp(dev, 0x01, 0x00);
 997                         adm8211_write_bbp(dev, 0x02, 0x00);
 998                         adm8211_write_bbp(dev, 0x03, 0x00);
 999                         adm8211_write_bbp(dev, 0x06, 0x0f);
1000                         adm8211_write_bbp(dev, 0x07, 0x05);
1001                         adm8211_write_bbp(dev, 0x08, 0x03);
1002                         adm8211_write_bbp(dev, 0x09, 0x00);
1003                         adm8211_write_bbp(dev, 0x0a, 0x00);
1004                         adm8211_write_bbp(dev, 0x0b, 0x00);
1005                         adm8211_write_bbp(dev, 0x0c, 0x10);
1006                         adm8211_write_bbp(dev, 0x0f, 0x55);
1007                         adm8211_write_bbp(dev, 0x10, 0x8d);
1008                         adm8211_write_bbp(dev, 0x11, 0x43);
1009                         adm8211_write_bbp(dev, 0x18, 0x4a);
1010                         adm8211_write_bbp(dev, 0x20, 0x20);
1011                         adm8211_write_bbp(dev, 0x21, 0x02);
1012                         adm8211_write_bbp(dev, 0x22, 0x23);
1013                         adm8211_write_bbp(dev, 0x23, 0x30);
1014                         adm8211_write_bbp(dev, 0x24, 0x2d);
1015                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1016                         adm8211_write_bbp(dev, 0x2b, 0x81);
1017                         adm8211_write_bbp(dev, 0x2c, 0x44);
1018                         adm8211_write_bbp(dev, 0x29, 0xfa);
1019                         adm8211_write_bbp(dev, 0x60, 0x2d);
1020                         adm8211_write_bbp(dev, 0x64, 0x01);
1021                         break;
1022
1023                 case ADM8211_RFMD2948:
1024                         break;
1025
1026                 default:
1027                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1028                                wiphy_name(dev->wiphy), priv->transceiver_type);
1029                         break;
1030                 }
1031         } else
1032                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1033                        wiphy_name(dev->wiphy), priv->bbp_type);
1034
1035         ADM8211_CSR_WRITE(SYNRF, 0);
1036
1037         /* Set RF CAL control source to MAC control */
1038         reg = ADM8211_CSR_READ(SYNCTL);
1039         reg |= ADM8211_SYNCTL_SELCAL;
1040         ADM8211_CSR_WRITE(SYNCTL, reg);
1041
1042         return 0;
1043 }
1044
1045 /* configures hw beacons/probe responses */
1046 static int adm8211_set_rate(struct ieee80211_hw *dev)
1047 {
1048         struct adm8211_priv *priv = dev->priv;
1049         u32 reg;
1050         int i = 0;
1051         u8 rate_buf[12] = {0};
1052
1053         /* write supported rates */
1054         if (priv->pdev->revision != ADM8211_REV_BA) {
1055                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1056                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1057                         rate_buf[i + 1] = (adm8211_rates[i].rate / 5) | 0x80;
1058         } else {
1059                 /* workaround for rev BA specific bug */
1060                 rate_buf[0] = 0x04;
1061                 rate_buf[1] = 0x82;
1062                 rate_buf[2] = 0x04;
1063                 rate_buf[3] = 0x0b;
1064                 rate_buf[4] = 0x16;
1065         }
1066
1067         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1068                                  ARRAY_SIZE(adm8211_rates) + 1);
1069
1070         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1071         reg |= 1 << 15; /* short preamble */
1072         reg |= 110 << 24;
1073         ADM8211_CSR_WRITE(PLCPHD, reg);
1074
1075         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1076          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1077          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1078         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1079
1080         return 0;
1081 }
1082
1083 static void adm8211_hw_init(struct ieee80211_hw *dev)
1084 {
1085         struct adm8211_priv *priv = dev->priv;
1086         u32 reg;
1087         u8 cline;
1088
1089         reg = le32_to_cpu(ADM8211_CSR_READ(PAR));
1090         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1091         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1092
1093         if (!pci_set_mwi(priv->pdev)) {
1094                 reg |= 0x1 << 24;
1095                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1096
1097                 switch (cline) {
1098                 case  0x8: reg |= (0x1 << 14);
1099                            break;
1100                 case 0x16: reg |= (0x2 << 14);
1101                            break;
1102                 case 0x32: reg |= (0x3 << 14);
1103                            break;
1104                   default: reg |= (0x0 << 14);
1105                            break;
1106                 }
1107         }
1108
1109         ADM8211_CSR_WRITE(PAR, reg);
1110
1111         reg = ADM8211_CSR_READ(CSR_TEST1);
1112         reg &= ~(0xF << 28);
1113         reg |= (1 << 28) | (1 << 31);
1114         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1115
1116         /* lose link after 4 lost beacons */
1117         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1118         ADM8211_CSR_WRITE(WCSR, reg);
1119
1120         /* Disable APM, enable receive FIFO threshold, and set drain receive
1121          * threshold to store-and-forward */
1122         reg = ADM8211_CSR_READ(CMDR);
1123         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1124         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1125         ADM8211_CSR_WRITE(CMDR, reg);
1126
1127         adm8211_set_rate(dev);
1128
1129         /* 4-bit values:
1130          * PWR1UP   = 8 * 2 ms
1131          * PWR0PAPE = 8 us or 5 us
1132          * PWR1PAPE = 1 us or 3 us
1133          * PWR0TRSW = 5 us
1134          * PWR1TRSW = 12 us
1135          * PWR0PE2  = 13 us
1136          * PWR1PE2  = 1 us
1137          * PWR0TXPE = 8 or 6 */
1138         if (priv->pdev->revision < ADM8211_REV_CA)
1139                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1140         else
1141                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1142
1143         /* Enable store and forward for transmit */
1144         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1145         ADM8211_CSR_WRITE(NAR, priv->nar);
1146
1147         /* Reset RF */
1148         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1149         ADM8211_CSR_READ(SYNRF);
1150         msleep(10);
1151         ADM8211_CSR_WRITE(SYNRF, 0);
1152         ADM8211_CSR_READ(SYNRF);
1153         msleep(5);
1154
1155         /* Set CFP Max Duration to 0x10 TU */
1156         reg = ADM8211_CSR_READ(CFPP);
1157         reg &= ~(0xffff << 8);
1158         reg |= 0x0010 << 8;
1159         ADM8211_CSR_WRITE(CFPP, reg);
1160
1161         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1162          * TUCNT = 0x3ff - Tu counter 1024 us  */
1163         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1164
1165         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1166          * DIFS=50 us, EIFS=100 us */
1167         if (priv->pdev->revision < ADM8211_REV_CA)
1168                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1169                                         (50 << 9)  | 100);
1170         else
1171                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1172                                         (50 << 9)  | 100);
1173
1174         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1175          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1176         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1177
1178         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1179         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1180
1181         /* Initialize BBP (and SYN) */
1182         adm8211_hw_init_bbp(dev);
1183
1184         /* make sure interrupts are off */
1185         ADM8211_CSR_WRITE(IER, 0);
1186
1187         /* ACK interrupts */
1188         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1189
1190         /* Setup WEP (turns it off for now) */
1191         reg = ADM8211_CSR_READ(MACTEST);
1192         reg &= ~(7 << 20);
1193         ADM8211_CSR_WRITE(MACTEST, reg);
1194
1195         reg = ADM8211_CSR_READ(WEPCTL);
1196         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1197         reg |= ADM8211_WEPCTL_WEPRXBYP;
1198         ADM8211_CSR_WRITE(WEPCTL, reg);
1199
1200         /* Clear the missed-packet counter. */
1201         ADM8211_CSR_READ(LPC);
1202 }
1203
1204 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1205 {
1206         struct adm8211_priv *priv = dev->priv;
1207         u32 reg, tmp;
1208         int timeout = 100;
1209
1210         /* Power-on issue */
1211         /* TODO: check if this is necessary */
1212         ADM8211_CSR_WRITE(FRCTL, 0);
1213
1214         /* Reset the chip */
1215         tmp = ADM8211_CSR_READ(PAR);
1216         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1217
1218         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1219                 msleep(50);
1220
1221         if (timeout <= 0)
1222                 return -ETIMEDOUT;
1223
1224         ADM8211_CSR_WRITE(PAR, tmp);
1225
1226         if (priv->pdev->revision == ADM8211_REV_BA &&
1227             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1228              priv->transceiver_type == ADM8211_RFMD2958)) {
1229                 reg = ADM8211_CSR_READ(CSR_TEST1);
1230                 reg |= (1 << 4) | (1 << 5);
1231                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1232         } else if (priv->pdev->revision == ADM8211_REV_CA) {
1233                 reg = ADM8211_CSR_READ(CSR_TEST1);
1234                 reg &= ~((1 << 4) | (1 << 5));
1235                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1236         }
1237
1238         ADM8211_CSR_WRITE(FRCTL, 0);
1239
1240         reg = ADM8211_CSR_READ(CSR_TEST0);
1241         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1242         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1243
1244         adm8211_clear_sram(dev);
1245
1246         return 0;
1247 }
1248
1249 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1250 {
1251         struct adm8211_priv *priv = dev->priv;
1252         u32 tsftl;
1253         u64 tsft;
1254
1255         tsftl = ADM8211_CSR_READ(TSFTL);
1256         tsft = ADM8211_CSR_READ(TSFTH);
1257         tsft <<= 32;
1258         tsft |= tsftl;
1259
1260         return tsft;
1261 }
1262
1263 static void adm8211_set_interval(struct ieee80211_hw *dev,
1264                                  unsigned short bi, unsigned short li)
1265 {
1266         struct adm8211_priv *priv = dev->priv;
1267         u32 reg;
1268
1269         /* BP (beacon interval) = data->beacon_interval
1270          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1271         reg = (bi << 16) | li;
1272         ADM8211_CSR_WRITE(BPLI, reg);
1273 }
1274
1275 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1276 {
1277         struct adm8211_priv *priv = dev->priv;
1278         u32 reg;
1279
1280         ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1281         reg = ADM8211_CSR_READ(ABDA1);
1282         reg &= 0x0000ffff;
1283         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1284         ADM8211_CSR_WRITE(ABDA1, reg);
1285 }
1286
1287 static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
1288 {
1289         struct adm8211_priv *priv = dev->priv;
1290         u8 buf[36];
1291
1292         if (ssid_len > 32)
1293                 return -EINVAL;
1294
1295         memset(buf, 0, sizeof(buf));
1296         buf[0] = ssid_len;
1297         memcpy(buf + 1, ssid, ssid_len);
1298         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
1299         /* TODO: configure beacon for adhoc? */
1300         return 0;
1301 }
1302
1303 static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1304 {
1305         struct adm8211_priv *priv = dev->priv;
1306
1307         if (conf->channel != priv->channel) {
1308                 priv->channel = conf->channel;
1309                 adm8211_rf_set_channel(dev, priv->channel);
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int adm8211_config_interface(struct ieee80211_hw *dev, int if_id,
1316                                     struct ieee80211_if_conf *conf)
1317 {
1318         struct adm8211_priv *priv = dev->priv;
1319
1320         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1321                 adm8211_set_bssid(dev, conf->bssid);
1322                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1323         }
1324
1325         if (conf->ssid_len != priv->ssid_len ||
1326             memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
1327                 adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
1328                 priv->ssid_len = conf->ssid_len;
1329                 memcpy(priv->ssid, conf->ssid, conf->ssid_len);
1330         }
1331
1332         return 0;
1333 }
1334
1335 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1336                                      unsigned int changed_flags,
1337                                      unsigned int *total_flags,
1338                                      int mc_count, struct dev_mc_list *mclist)
1339 {
1340         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1341         struct adm8211_priv *priv = dev->priv;
1342         unsigned int bit_nr, new_flags;
1343         u32 mc_filter[2];
1344         int i;
1345
1346         new_flags = 0;
1347
1348         if (*total_flags & FIF_PROMISC_IN_BSS) {
1349                 new_flags |= FIF_PROMISC_IN_BSS;
1350                 priv->nar |= ADM8211_NAR_PR;
1351                 priv->nar &= ~ADM8211_NAR_MM;
1352                 mc_filter[1] = mc_filter[0] = ~0;
1353         } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1354                 new_flags |= FIF_ALLMULTI;
1355                 priv->nar &= ~ADM8211_NAR_PR;
1356                 priv->nar |= ADM8211_NAR_MM;
1357                 mc_filter[1] = mc_filter[0] = ~0;
1358         } else {
1359                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1360                 mc_filter[1] = mc_filter[0] = 0;
1361                 for (i = 0; i < mc_count; i++) {
1362                         if (!mclist)
1363                                 break;
1364                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1365
1366                         bit_nr &= 0x3F;
1367                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1368                         mclist = mclist->next;
1369                 }
1370         }
1371
1372         ADM8211_IDLE_RX();
1373
1374         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1375         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1376         ADM8211_CSR_READ(NAR);
1377
1378         if (priv->nar & ADM8211_NAR_PR)
1379                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1380         else
1381                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1382
1383         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1384                 adm8211_set_bssid(dev, bcast);
1385         else
1386                 adm8211_set_bssid(dev, priv->bssid);
1387
1388         ADM8211_RESTORE();
1389
1390         *total_flags = new_flags;
1391 }
1392
1393 static int adm8211_add_interface(struct ieee80211_hw *dev,
1394                                  struct ieee80211_if_init_conf *conf)
1395 {
1396         struct adm8211_priv *priv = dev->priv;
1397         if (priv->mode != IEEE80211_IF_TYPE_MNTR)
1398                 return -EOPNOTSUPP;
1399
1400         switch (conf->type) {
1401         case IEEE80211_IF_TYPE_STA:
1402                 priv->mode = conf->type;
1403                 break;
1404         default:
1405                 return -EOPNOTSUPP;
1406         }
1407
1408         ADM8211_IDLE();
1409
1410         ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)conf->mac_addr));
1411         ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
1412
1413         adm8211_update_mode(dev);
1414
1415         ADM8211_RESTORE();
1416
1417         return 0;
1418 }
1419
1420 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1421                                      struct ieee80211_if_init_conf *conf)
1422 {
1423         struct adm8211_priv *priv = dev->priv;
1424         priv->mode = IEEE80211_IF_TYPE_MNTR;
1425 }
1426
1427 static int adm8211_init_rings(struct ieee80211_hw *dev)
1428 {
1429         struct adm8211_priv *priv = dev->priv;
1430         struct adm8211_desc *desc = NULL;
1431         struct adm8211_rx_ring_info *rx_info;
1432         struct adm8211_tx_ring_info *tx_info;
1433         unsigned int i;
1434
1435         for (i = 0; i < priv->rx_ring_size; i++) {
1436                 desc = &priv->rx_ring[i];
1437                 desc->status = 0;
1438                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1439                 priv->rx_buffers[i].skb = NULL;
1440         }
1441         /* Mark the end of RX ring; hw returns to base address after this
1442          * descriptor */
1443         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1444
1445         for (i = 0; i < priv->rx_ring_size; i++) {
1446                 desc = &priv->rx_ring[i];
1447                 rx_info = &priv->rx_buffers[i];
1448
1449                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1450                 if (rx_info->skb == NULL)
1451                         break;
1452                 rx_info->mapping = pci_map_single(priv->pdev,
1453                                                   skb_tail_pointer(rx_info->skb),
1454                                                   RX_PKT_SIZE,
1455                                                   PCI_DMA_FROMDEVICE);
1456                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1457                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1458         }
1459
1460         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1461         for (i = 0; i < priv->tx_ring_size; i++) {
1462                 desc = &priv->tx_ring[i];
1463                 tx_info = &priv->tx_buffers[i];
1464
1465                 tx_info->skb = NULL;
1466                 tx_info->mapping = 0;
1467                 desc->status = 0;
1468         }
1469         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1470
1471         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1472         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1473         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1474
1475         return 0;
1476 }
1477
1478 static void adm8211_free_rings(struct ieee80211_hw *dev)
1479 {
1480         struct adm8211_priv *priv = dev->priv;
1481         unsigned int i;
1482
1483         for (i = 0; i < priv->rx_ring_size; i++) {
1484                 if (!priv->rx_buffers[i].skb)
1485                         continue;
1486
1487                 pci_unmap_single(
1488                         priv->pdev,
1489                         priv->rx_buffers[i].mapping,
1490                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1491
1492                 dev_kfree_skb(priv->rx_buffers[i].skb);
1493         }
1494
1495         for (i = 0; i < priv->tx_ring_size; i++) {
1496                 if (!priv->tx_buffers[i].skb)
1497                         continue;
1498
1499                 pci_unmap_single(priv->pdev,
1500                                  priv->tx_buffers[i].mapping,
1501                                  priv->tx_buffers[i].skb->len,
1502                                  PCI_DMA_TODEVICE);
1503
1504                 dev_kfree_skb(priv->tx_buffers[i].skb);
1505         }
1506 }
1507
1508 static int adm8211_start(struct ieee80211_hw *dev)
1509 {
1510         struct adm8211_priv *priv = dev->priv;
1511         int retval;
1512
1513         /* Power up MAC and RF chips */
1514         retval = adm8211_hw_reset(dev);
1515         if (retval) {
1516                 printk(KERN_ERR "%s: hardware reset failed\n",
1517                        wiphy_name(dev->wiphy));
1518                 goto fail;
1519         }
1520
1521         retval = adm8211_init_rings(dev);
1522         if (retval) {
1523                 printk(KERN_ERR "%s: failed to initialize rings\n",
1524                        wiphy_name(dev->wiphy));
1525                 goto fail;
1526         }
1527
1528         /* Init hardware */
1529         adm8211_hw_init(dev);
1530         adm8211_rf_set_channel(dev, priv->channel);
1531
1532         retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1533                              IRQF_SHARED, "adm8211", dev);
1534         if (retval) {
1535                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1536                        wiphy_name(dev->wiphy));
1537                 goto fail;
1538         }
1539
1540         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1541                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1542                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1543         adm8211_update_mode(dev);
1544         ADM8211_CSR_WRITE(RDR, 0);
1545
1546         adm8211_set_interval(dev, 100, 10);
1547         return 0;
1548
1549 fail:
1550         return retval;
1551 }
1552
1553 static void adm8211_stop(struct ieee80211_hw *dev)
1554 {
1555         struct adm8211_priv *priv = dev->priv;
1556
1557         priv->nar = 0;
1558         ADM8211_CSR_WRITE(NAR, 0);
1559         ADM8211_CSR_WRITE(IER, 0);
1560         ADM8211_CSR_READ(NAR);
1561
1562         free_irq(priv->pdev->irq, dev);
1563
1564         adm8211_free_rings(dev);
1565 }
1566
1567 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1568                                    int plcp_signal, int short_preamble)
1569 {
1570         /* Alternative calculation from NetBSD: */
1571
1572 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1573 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1574 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1575 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1576 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1577 #define IEEE80211_DUR_DS_SLOW_ACK       112
1578 #define IEEE80211_DUR_DS_FAST_ACK       56
1579 #define IEEE80211_DUR_DS_SLOW_CTS       112
1580 #define IEEE80211_DUR_DS_FAST_CTS       56
1581 #define IEEE80211_DUR_DS_SLOT           20
1582 #define IEEE80211_DUR_DS_SIFS           10
1583
1584         int remainder;
1585
1586         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1587                 / plcp_signal;
1588
1589         if (plcp_signal <= PLCP_SIGNAL_2M)
1590                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1591                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1592                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1593                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1594                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1595         else
1596                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1597                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1598                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1599                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1600                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1601
1602         /* lengthen duration if long preamble */
1603         if (!short_preamble)
1604                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1605                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1606                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1607                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1608
1609
1610         *plcp = (80 * len) / plcp_signal;
1611         remainder = (80 * len) % plcp_signal;
1612         if (plcp_signal == PLCP_SIGNAL_11M &&
1613             remainder <= 30 && remainder > 0)
1614                 *plcp = (*plcp | 0x8000) + 1;
1615         else if (remainder)
1616                 (*plcp)++;
1617 }
1618
1619 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1620 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1621                            u16 plcp_signal,
1622                            struct ieee80211_tx_control *control,
1623                            size_t hdrlen)
1624 {
1625         struct adm8211_priv *priv = dev->priv;
1626         unsigned long flags;
1627         dma_addr_t mapping;
1628         unsigned int entry;
1629         u32 flag;
1630
1631         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1632                                  PCI_DMA_TODEVICE);
1633
1634         spin_lock_irqsave(&priv->lock, flags);
1635
1636         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1637                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1638         else
1639                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1640
1641         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1642                 ieee80211_stop_queue(dev, 0);
1643
1644         entry = priv->cur_tx % priv->tx_ring_size;
1645
1646         priv->tx_buffers[entry].skb = skb;
1647         priv->tx_buffers[entry].mapping = mapping;
1648         memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1649         priv->tx_buffers[entry].hdrlen = hdrlen;
1650         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1651
1652         if (entry == priv->tx_ring_size - 1)
1653                 flag |= TDES1_CONTROL_TER;
1654         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1655
1656         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1657         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1658         priv->tx_ring[entry].status = cpu_to_le32(flag);
1659
1660         priv->cur_tx++;
1661
1662         spin_unlock_irqrestore(&priv->lock, flags);
1663
1664         /* Trigger transmit poll */
1665         ADM8211_CSR_WRITE(TDR, 0);
1666 }
1667
1668 /* Put adm8211_tx_hdr on skb and transmit */
1669 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1670                       struct ieee80211_tx_control *control)
1671 {
1672         struct adm8211_tx_hdr *txhdr;
1673         u16 fc;
1674         size_t payload_len, hdrlen;
1675         int plcp, dur, len, plcp_signal, short_preamble;
1676         struct ieee80211_hdr *hdr;
1677
1678         if (control->tx_rate < 0) {
1679                 short_preamble = 1;
1680                 plcp_signal = -control->tx_rate;
1681         } else {
1682                 short_preamble = 0;
1683                 plcp_signal = control->tx_rate;
1684         }
1685
1686         hdr = (struct ieee80211_hdr *)skb->data;
1687         fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
1688         hdrlen = ieee80211_get_hdrlen(fc);
1689         memcpy(skb->cb, skb->data, hdrlen);
1690         hdr = (struct ieee80211_hdr *)skb->cb;
1691         skb_pull(skb, hdrlen);
1692         payload_len = skb->len;
1693
1694         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1695         memset(txhdr, 0, sizeof(*txhdr));
1696         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1697         txhdr->signal = plcp_signal;
1698         txhdr->frame_body_size = cpu_to_le16(payload_len);
1699         txhdr->frame_control = hdr->frame_control;
1700
1701         len = hdrlen + payload_len + FCS_LEN;
1702         if (fc & IEEE80211_FCTL_PROTECTED)
1703                 len += 8;
1704
1705         txhdr->frag = cpu_to_le16(0x0FFF);
1706         adm8211_calc_durations(&dur, &plcp, payload_len,
1707                                len, plcp_signal, short_preamble);
1708         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1709         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1710         txhdr->dur_frag_head = cpu_to_le16(dur);
1711         txhdr->dur_frag_tail = cpu_to_le16(dur);
1712
1713         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1714
1715         if (short_preamble)
1716                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1717
1718         if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
1719                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1720
1721         if (fc & IEEE80211_FCTL_PROTECTED)
1722                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1723
1724         txhdr->retry_limit = control->retry_limit;
1725
1726         adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1727
1728         return NETDEV_TX_OK;
1729 }
1730
1731 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1732 {
1733         struct adm8211_priv *priv = dev->priv;
1734         unsigned int ring_size;
1735
1736         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1737                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1738         if (!priv->rx_buffers)
1739                 return -ENOMEM;
1740
1741         priv->tx_buffers = (void *)priv->rx_buffers +
1742                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1743
1744         /* Allocate TX/RX descriptors */
1745         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1746                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1747         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1748                                              &priv->rx_ring_dma);
1749
1750         if (!priv->rx_ring) {
1751                 kfree(priv->rx_buffers);
1752                 priv->rx_buffers = NULL;
1753                 priv->tx_buffers = NULL;
1754                 return -ENOMEM;
1755         }
1756
1757         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1758                                                 priv->rx_ring_size);
1759         priv->tx_ring_dma = priv->rx_ring_dma +
1760                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1761
1762         return 0;
1763 }
1764
1765 static const struct ieee80211_ops adm8211_ops = {
1766         .tx                     = adm8211_tx,
1767         .start                  = adm8211_start,
1768         .stop                   = adm8211_stop,
1769         .add_interface          = adm8211_add_interface,
1770         .remove_interface       = adm8211_remove_interface,
1771         .config                 = adm8211_config,
1772         .config_interface       = adm8211_config_interface,
1773         .configure_filter       = adm8211_configure_filter,
1774         .get_stats              = adm8211_get_stats,
1775         .get_tx_stats           = adm8211_get_tx_stats,
1776         .get_tsf                = adm8211_get_tsft
1777 };
1778
1779 static int __devinit adm8211_probe(struct pci_dev *pdev,
1780                                    const struct pci_device_id *id)
1781 {
1782         struct ieee80211_hw *dev;
1783         struct adm8211_priv *priv;
1784         unsigned long mem_addr, mem_len;
1785         unsigned int io_addr, io_len;
1786         int err;
1787         u32 reg;
1788         u8 perm_addr[ETH_ALEN];
1789         DECLARE_MAC_BUF(mac);
1790
1791         err = pci_enable_device(pdev);
1792         if (err) {
1793                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1794                        pci_name(pdev));
1795                 return err;
1796         }
1797
1798         io_addr = pci_resource_start(pdev, 0);
1799         io_len = pci_resource_len(pdev, 0);
1800         mem_addr = pci_resource_start(pdev, 1);
1801         mem_len = pci_resource_len(pdev, 1);
1802         if (io_len < 256 || mem_len < 1024) {
1803                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1804                        pci_name(pdev));
1805                 goto err_disable_pdev;
1806         }
1807
1808
1809         /* check signature */
1810         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1811         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1812                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1813                        pci_name(pdev), reg);
1814                 goto err_disable_pdev;
1815         }
1816
1817         err = pci_request_regions(pdev, "adm8211");
1818         if (err) {
1819                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1820                        pci_name(pdev));
1821                 return err; /* someone else grabbed it? don't disable it */
1822         }
1823
1824         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
1825             pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1826                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1827                        pci_name(pdev));
1828                 goto err_free_reg;
1829         }
1830
1831         pci_set_master(pdev);
1832
1833         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1834         if (!dev) {
1835                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1836                        pci_name(pdev));
1837                 err = -ENOMEM;
1838                 goto err_free_reg;
1839         }
1840         priv = dev->priv;
1841         priv->pdev = pdev;
1842
1843         spin_lock_init(&priv->lock);
1844
1845         SET_IEEE80211_DEV(dev, &pdev->dev);
1846
1847         pci_set_drvdata(pdev, dev);
1848
1849         priv->map = pci_iomap(pdev, 1, mem_len);
1850         if (!priv->map)
1851                 priv->map = pci_iomap(pdev, 0, io_len);
1852
1853         if (!priv->map) {
1854                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1855                        pci_name(pdev));
1856                 goto err_free_dev;
1857         }
1858
1859         priv->rx_ring_size = rx_ring_size;
1860         priv->tx_ring_size = tx_ring_size;
1861
1862         if (adm8211_alloc_rings(dev)) {
1863                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1864                        pci_name(pdev));
1865                 goto err_iounmap;
1866         }
1867
1868         *(u32 *)perm_addr = le32_to_cpu((__force __le32)ADM8211_CSR_READ(PAR0));
1869         *(u16 *)&perm_addr[4] =
1870                 le16_to_cpu((__force __le16)ADM8211_CSR_READ(PAR1) & 0xFFFF);
1871
1872         if (!is_valid_ether_addr(perm_addr)) {
1873                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1874                        pci_name(pdev));
1875                 random_ether_addr(perm_addr);
1876         }
1877         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1878
1879         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1880         dev->flags = IEEE80211_HW_DEFAULT_REG_DOMAIN_CONFIGURED;
1881         /* IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1882
1883         dev->channel_change_time = 1000;
1884         dev->max_rssi = 100;    /* FIXME: find better value */
1885
1886         priv->modes[0].mode = MODE_IEEE80211B;
1887         /* channel info filled in by adm8211_read_eeprom */
1888         memcpy(priv->rates, adm8211_rates, sizeof(adm8211_rates));
1889         priv->modes[0].num_rates = ARRAY_SIZE(adm8211_rates);
1890         priv->modes[0].rates = priv->rates;
1891
1892         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1893
1894         priv->retry_limit = 3;
1895         priv->ant_power = 0x40;
1896         priv->tx_power = 0x40;
1897         priv->lpf_cutoff = 0xFF;
1898         priv->lnags_threshold = 0xFF;
1899         priv->mode = IEEE80211_IF_TYPE_MNTR;
1900
1901         /* Power-on issue. EEPROM won't read correctly without */
1902         if (pdev->revision >= ADM8211_REV_BA) {
1903                 ADM8211_CSR_WRITE(FRCTL, 0);
1904                 ADM8211_CSR_READ(FRCTL);
1905                 ADM8211_CSR_WRITE(FRCTL, 1);
1906                 ADM8211_CSR_READ(FRCTL);
1907                 msleep(100);
1908         }
1909
1910         err = adm8211_read_eeprom(dev);
1911         if (err) {
1912                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1913                        pci_name(pdev));
1914                 goto err_free_desc;
1915         }
1916
1917         priv->channel = priv->modes[0].channels[0].chan;
1918
1919         err = ieee80211_register_hwmode(dev, &priv->modes[0]);
1920         if (err) {
1921                 printk(KERN_ERR "%s (adm8211): Can't register hwmode\n",
1922                        pci_name(pdev));
1923                 goto err_free_desc;
1924         }
1925
1926         err = ieee80211_register_hw(dev);
1927         if (err) {
1928                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1929                        pci_name(pdev));
1930                 goto err_free_desc;
1931         }
1932
1933         printk(KERN_INFO "%s: hwaddr %s, Rev 0x%02x\n",
1934                wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
1935                pdev->revision);
1936
1937         return 0;
1938
1939  err_free_desc:
1940         pci_free_consistent(pdev,
1941                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1942                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1943                             priv->rx_ring, priv->rx_ring_dma);
1944         kfree(priv->rx_buffers);
1945
1946  err_iounmap:
1947         pci_iounmap(pdev, priv->map);
1948
1949  err_free_dev:
1950         pci_set_drvdata(pdev, NULL);
1951         ieee80211_free_hw(dev);
1952
1953  err_free_reg:
1954         pci_release_regions(pdev);
1955
1956  err_disable_pdev:
1957         pci_disable_device(pdev);
1958         return err;
1959 }
1960
1961
1962 static void __devexit adm8211_remove(struct pci_dev *pdev)
1963 {
1964         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1965         struct adm8211_priv *priv;
1966
1967         if (!dev)
1968                 return;
1969
1970         ieee80211_unregister_hw(dev);
1971
1972         priv = dev->priv;
1973
1974         pci_free_consistent(pdev,
1975                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1976                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1977                             priv->rx_ring, priv->rx_ring_dma);
1978
1979         kfree(priv->rx_buffers);
1980         kfree(priv->eeprom);
1981         pci_iounmap(pdev, priv->map);
1982         pci_release_regions(pdev);
1983         pci_disable_device(pdev);
1984         ieee80211_free_hw(dev);
1985 }
1986
1987
1988 #ifdef CONFIG_PM
1989 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1990 {
1991         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1992         struct adm8211_priv *priv = dev->priv;
1993
1994         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
1995                 ieee80211_stop_queues(dev);
1996                 adm8211_stop(dev);
1997         }
1998
1999         pci_save_state(pdev);
2000         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2001         return 0;
2002 }
2003
2004 static int adm8211_resume(struct pci_dev *pdev)
2005 {
2006         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2007         struct adm8211_priv *priv = dev->priv;
2008
2009         pci_set_power_state(pdev, PCI_D0);
2010         pci_restore_state(pdev);
2011
2012         if (priv->mode != IEEE80211_IF_TYPE_MNTR) {
2013                 adm8211_start(dev);
2014                 ieee80211_start_queues(dev);
2015         }
2016
2017         return 0;
2018 }
2019 #endif /* CONFIG_PM */
2020
2021
2022 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2023
2024 /* TODO: implement enable_wake */
2025 static struct pci_driver adm8211_driver = {
2026         .name           = "adm8211",
2027         .id_table       = adm8211_pci_id_table,
2028         .probe          = adm8211_probe,
2029         .remove         = __devexit_p(adm8211_remove),
2030 #ifdef CONFIG_PM
2031         .suspend        = adm8211_suspend,
2032         .resume         = adm8211_resume,
2033 #endif /* CONFIG_PM */
2034 };
2035
2036
2037
2038 static int __init adm8211_init(void)
2039 {
2040         return pci_register_driver(&adm8211_driver);
2041 }
2042
2043
2044 static void __exit adm8211_exit(void)
2045 {
2046         pci_unregister_driver(&adm8211_driver);
2047 }
2048
2049
2050 module_init(adm8211_init);
2051 module_exit(adm8211_exit);