Merge branch 'linus' into tracing/mmiotrace
[linux-2.6] / drivers / infiniband / hw / ipath / ipath_driver.c
1 /*
2  * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33
34 #include <linux/spinlock.h>
35 #include <linux/idr.h>
36 #include <linux/pci.h>
37 #include <linux/io.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/vmalloc.h>
41
42 #include "ipath_kernel.h"
43 #include "ipath_verbs.h"
44
45 static void ipath_update_pio_bufs(struct ipath_devdata *);
46
47 const char *ipath_get_unit_name(int unit)
48 {
49         static char iname[16];
50         snprintf(iname, sizeof iname, "infinipath%u", unit);
51         return iname;
52 }
53
54 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
55 #define PFX IPATH_DRV_NAME ": "
56
57 /*
58  * The size has to be longer than this string, so we can append
59  * board/chip information to it in the init code.
60  */
61 const char ib_ipath_version[] = IPATH_IDSTR "\n";
62
63 static struct idr unit_table;
64 DEFINE_SPINLOCK(ipath_devs_lock);
65 LIST_HEAD(ipath_dev_list);
66
67 wait_queue_head_t ipath_state_wait;
68
69 unsigned ipath_debug = __IPATH_INFO;
70
71 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
72 MODULE_PARM_DESC(debug, "mask for debug prints");
73 EXPORT_SYMBOL_GPL(ipath_debug);
74
75 unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
76 module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
77 MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
78
79 static unsigned ipath_hol_timeout_ms = 13000;
80 module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
81 MODULE_PARM_DESC(hol_timeout_ms,
82         "duration of user app suspension after link failure");
83
84 unsigned ipath_linkrecovery = 1;
85 module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
86 MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
87
88 MODULE_LICENSE("GPL");
89 MODULE_AUTHOR("QLogic <support@qlogic.com>");
90 MODULE_DESCRIPTION("QLogic InfiniPath driver");
91
92 /*
93  * Table to translate the LINKTRAININGSTATE portion of
94  * IBCStatus to a human-readable form.
95  */
96 const char *ipath_ibcstatus_str[] = {
97         "Disabled",
98         "LinkUp",
99         "PollActive",
100         "PollQuiet",
101         "SleepDelay",
102         "SleepQuiet",
103         "LState6",              /* unused */
104         "LState7",              /* unused */
105         "CfgDebounce",
106         "CfgRcvfCfg",
107         "CfgWaitRmt",
108         "CfgIdle",
109         "RecovRetrain",
110         "CfgTxRevLane",         /* unused before IBA7220 */
111         "RecovWaitRmt",
112         "RecovIdle",
113         /* below were added for IBA7220 */
114         "CfgEnhanced",
115         "CfgTest",
116         "CfgWaitRmtTest",
117         "CfgWaitCfgEnhanced",
118         "SendTS_T",
119         "SendTstIdles",
120         "RcvTS_T",
121         "SendTst_TS1s",
122         "LTState18", "LTState19", "LTState1A", "LTState1B",
123         "LTState1C", "LTState1D", "LTState1E", "LTState1F"
124 };
125
126 static void __devexit ipath_remove_one(struct pci_dev *);
127 static int __devinit ipath_init_one(struct pci_dev *,
128                                     const struct pci_device_id *);
129
130 /* Only needed for registration, nothing else needs this info */
131 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
132 #define PCI_VENDOR_ID_QLOGIC 0x1077
133 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
134 #define PCI_DEVICE_ID_INFINIPATH_PE800 0x10
135 #define PCI_DEVICE_ID_INFINIPATH_7220 0x7220
136
137 /* Number of seconds before our card status check...  */
138 #define STATUS_TIMEOUT 60
139
140 static const struct pci_device_id ipath_pci_tbl[] = {
141         { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
142         { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_PE800) },
143         { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_INFINIPATH_7220) },
144         { 0, }
145 };
146
147 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
148
149 static struct pci_driver ipath_driver = {
150         .name = IPATH_DRV_NAME,
151         .probe = ipath_init_one,
152         .remove = __devexit_p(ipath_remove_one),
153         .id_table = ipath_pci_tbl,
154         .driver = {
155                 .groups = ipath_driver_attr_groups,
156         },
157 };
158
159 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
160                              u32 *bar0, u32 *bar1)
161 {
162         int ret;
163
164         ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
165         if (ret)
166                 ipath_dev_err(dd, "failed to read bar0 before enable: "
167                               "error %d\n", -ret);
168
169         ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
170         if (ret)
171                 ipath_dev_err(dd, "failed to read bar1 before enable: "
172                               "error %d\n", -ret);
173
174         ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
175 }
176
177 static void ipath_free_devdata(struct pci_dev *pdev,
178                                struct ipath_devdata *dd)
179 {
180         unsigned long flags;
181
182         pci_set_drvdata(pdev, NULL);
183
184         if (dd->ipath_unit != -1) {
185                 spin_lock_irqsave(&ipath_devs_lock, flags);
186                 idr_remove(&unit_table, dd->ipath_unit);
187                 list_del(&dd->ipath_list);
188                 spin_unlock_irqrestore(&ipath_devs_lock, flags);
189         }
190         vfree(dd);
191 }
192
193 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
194 {
195         unsigned long flags;
196         struct ipath_devdata *dd;
197         int ret;
198
199         if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
200                 dd = ERR_PTR(-ENOMEM);
201                 goto bail;
202         }
203
204         dd = vmalloc(sizeof(*dd));
205         if (!dd) {
206                 dd = ERR_PTR(-ENOMEM);
207                 goto bail;
208         }
209         memset(dd, 0, sizeof(*dd));
210         dd->ipath_unit = -1;
211
212         spin_lock_irqsave(&ipath_devs_lock, flags);
213
214         ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
215         if (ret < 0) {
216                 printk(KERN_ERR IPATH_DRV_NAME
217                        ": Could not allocate unit ID: error %d\n", -ret);
218                 ipath_free_devdata(pdev, dd);
219                 dd = ERR_PTR(ret);
220                 goto bail_unlock;
221         }
222
223         dd->pcidev = pdev;
224         pci_set_drvdata(pdev, dd);
225
226         list_add(&dd->ipath_list, &ipath_dev_list);
227
228 bail_unlock:
229         spin_unlock_irqrestore(&ipath_devs_lock, flags);
230
231 bail:
232         return dd;
233 }
234
235 static inline struct ipath_devdata *__ipath_lookup(int unit)
236 {
237         return idr_find(&unit_table, unit);
238 }
239
240 struct ipath_devdata *ipath_lookup(int unit)
241 {
242         struct ipath_devdata *dd;
243         unsigned long flags;
244
245         spin_lock_irqsave(&ipath_devs_lock, flags);
246         dd = __ipath_lookup(unit);
247         spin_unlock_irqrestore(&ipath_devs_lock, flags);
248
249         return dd;
250 }
251
252 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
253 {
254         int nunits, npresent, nup;
255         struct ipath_devdata *dd;
256         unsigned long flags;
257         int maxports;
258
259         nunits = npresent = nup = maxports = 0;
260
261         spin_lock_irqsave(&ipath_devs_lock, flags);
262
263         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
264                 nunits++;
265                 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
266                         npresent++;
267                 if (dd->ipath_lid &&
268                     !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
269                                          | IPATH_LINKUNK)))
270                         nup++;
271                 if (dd->ipath_cfgports > maxports)
272                         maxports = dd->ipath_cfgports;
273         }
274
275         spin_unlock_irqrestore(&ipath_devs_lock, flags);
276
277         if (npresentp)
278                 *npresentp = npresent;
279         if (nupp)
280                 *nupp = nup;
281         if (maxportsp)
282                 *maxportsp = maxports;
283
284         return nunits;
285 }
286
287 /*
288  * These next two routines are placeholders in case we don't have per-arch
289  * code for controlling write combining.  If explicit control of write
290  * combining is not available, performance will probably be awful.
291  */
292
293 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
294 {
295         return -EOPNOTSUPP;
296 }
297
298 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
299 {
300 }
301
302 /*
303  * Perform a PIO buffer bandwidth write test, to verify proper system
304  * configuration.  Even when all the setup calls work, occasionally
305  * BIOS or other issues can prevent write combining from working, or
306  * can cause other bandwidth problems to the chip.
307  *
308  * This test simply writes the same buffer over and over again, and
309  * measures close to the peak bandwidth to the chip (not testing
310  * data bandwidth to the wire).   On chips that use an address-based
311  * trigger to send packets to the wire, this is easy.  On chips that
312  * use a count to trigger, we want to make sure that the packet doesn't
313  * go out on the wire, or trigger flow control checks.
314  */
315 static void ipath_verify_pioperf(struct ipath_devdata *dd)
316 {
317         u32 pbnum, cnt, lcnt;
318         u32 __iomem *piobuf;
319         u32 *addr;
320         u64 msecs, emsecs;
321
322         piobuf = ipath_getpiobuf(dd, 0, &pbnum);
323         if (!piobuf) {
324                 dev_info(&dd->pcidev->dev,
325                         "No PIObufs for checking perf, skipping\n");
326                 return;
327         }
328
329         /*
330          * Enough to give us a reasonable test, less than piobuf size, and
331          * likely multiple of store buffer length.
332          */
333         cnt = 1024;
334
335         addr = vmalloc(cnt);
336         if (!addr) {
337                 dev_info(&dd->pcidev->dev,
338                         "Couldn't get memory for checking PIO perf,"
339                         " skipping\n");
340                 goto done;
341         }
342
343         preempt_disable();  /* we want reasonably accurate elapsed time */
344         msecs = 1 + jiffies_to_msecs(jiffies);
345         for (lcnt = 0; lcnt < 10000U; lcnt++) {
346                 /* wait until we cross msec boundary */
347                 if (jiffies_to_msecs(jiffies) >= msecs)
348                         break;
349                 udelay(1);
350         }
351
352         ipath_disable_armlaunch(dd);
353
354         /*
355          * length 0, no dwords actually sent, and mark as VL15
356          * on chips where that may matter (due to IB flowcontrol)
357          */
358         if ((dd->ipath_flags & IPATH_HAS_PBC_CNT))
359                 writeq(1UL << 63, piobuf);
360         else
361                 writeq(0, piobuf);
362         ipath_flush_wc();
363
364         /*
365          * this is only roughly accurate, since even with preempt we
366          * still take interrupts that could take a while.   Running for
367          * >= 5 msec seems to get us "close enough" to accurate values
368          */
369         msecs = jiffies_to_msecs(jiffies);
370         for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
371                 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
372                 emsecs = jiffies_to_msecs(jiffies) - msecs;
373         }
374
375         /* 1 GiB/sec, slightly over IB SDR line rate */
376         if (lcnt < (emsecs * 1024U))
377                 ipath_dev_err(dd,
378                         "Performance problem: bandwidth to PIO buffers is "
379                         "only %u MiB/sec\n",
380                         lcnt / (u32) emsecs);
381         else
382                 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
383                         lcnt / (u32) emsecs);
384
385         preempt_enable();
386
387         vfree(addr);
388
389 done:
390         /* disarm piobuf, so it's available again */
391         ipath_disarm_piobufs(dd, pbnum, 1);
392         ipath_enable_armlaunch(dd);
393 }
394
395 static int __devinit ipath_init_one(struct pci_dev *pdev,
396                                     const struct pci_device_id *ent)
397 {
398         int ret, len, j;
399         struct ipath_devdata *dd;
400         unsigned long long addr;
401         u32 bar0 = 0, bar1 = 0;
402         u8 rev;
403
404         dd = ipath_alloc_devdata(pdev);
405         if (IS_ERR(dd)) {
406                 ret = PTR_ERR(dd);
407                 printk(KERN_ERR IPATH_DRV_NAME
408                        ": Could not allocate devdata: error %d\n", -ret);
409                 goto bail;
410         }
411
412         ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
413
414         ret = pci_enable_device(pdev);
415         if (ret) {
416                 /* This can happen iff:
417                  *
418                  * We did a chip reset, and then failed to reprogram the
419                  * BAR, or the chip reset due to an internal error.  We then
420                  * unloaded the driver and reloaded it.
421                  *
422                  * Both reset cases set the BAR back to initial state.  For
423                  * the latter case, the AER sticky error bit at offset 0x718
424                  * should be set, but the Linux kernel doesn't yet know
425                  * about that, it appears.  If the original BAR was retained
426                  * in the kernel data structures, this may be OK.
427                  */
428                 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
429                               dd->ipath_unit, -ret);
430                 goto bail_devdata;
431         }
432         addr = pci_resource_start(pdev, 0);
433         len = pci_resource_len(pdev, 0);
434         ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %d, vend %x/%x "
435                    "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
436                    ent->device, ent->driver_data);
437
438         read_bars(dd, pdev, &bar0, &bar1);
439
440         if (!bar1 && !(bar0 & ~0xf)) {
441                 if (addr) {
442                         dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
443                                  "rewriting as %llx\n", addr);
444                         ret = pci_write_config_dword(
445                                 pdev, PCI_BASE_ADDRESS_0, addr);
446                         if (ret) {
447                                 ipath_dev_err(dd, "rewrite of BAR0 "
448                                               "failed: err %d\n", -ret);
449                                 goto bail_disable;
450                         }
451                         ret = pci_write_config_dword(
452                                 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
453                         if (ret) {
454                                 ipath_dev_err(dd, "rewrite of BAR1 "
455                                               "failed: err %d\n", -ret);
456                                 goto bail_disable;
457                         }
458                 } else {
459                         ipath_dev_err(dd, "BAR is 0 (probable RESET), "
460                                       "not usable until reboot\n");
461                         ret = -ENODEV;
462                         goto bail_disable;
463                 }
464         }
465
466         ret = pci_request_regions(pdev, IPATH_DRV_NAME);
467         if (ret) {
468                 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
469                          "err %d\n", dd->ipath_unit, -ret);
470                 goto bail_disable;
471         }
472
473         ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
474         if (ret) {
475                 /*
476                  * if the 64 bit setup fails, try 32 bit.  Some systems
477                  * do not setup 64 bit maps on systems with 2GB or less
478                  * memory installed.
479                  */
480                 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
481                 if (ret) {
482                         dev_info(&pdev->dev,
483                                 "Unable to set DMA mask for unit %u: %d\n",
484                                 dd->ipath_unit, ret);
485                         goto bail_regions;
486                 }
487                 else {
488                         ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
489                         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
490                         if (ret)
491                                 dev_info(&pdev->dev,
492                                         "Unable to set DMA consistent mask "
493                                         "for unit %u: %d\n",
494                                         dd->ipath_unit, ret);
495
496                 }
497         }
498         else {
499                 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
500                 if (ret)
501                         dev_info(&pdev->dev,
502                                 "Unable to set DMA consistent mask "
503                                 "for unit %u: %d\n",
504                                 dd->ipath_unit, ret);
505         }
506
507         pci_set_master(pdev);
508
509         /*
510          * Save BARs to rewrite after device reset.  Save all 64 bits of
511          * BAR, just in case.
512          */
513         dd->ipath_pcibar0 = addr;
514         dd->ipath_pcibar1 = addr >> 32;
515         dd->ipath_deviceid = ent->device;       /* save for later use */
516         dd->ipath_vendorid = ent->vendor;
517
518         /* setup the chip-specific functions, as early as possible. */
519         switch (ent->device) {
520         case PCI_DEVICE_ID_INFINIPATH_HT:
521 #ifdef CONFIG_HT_IRQ
522                 ipath_init_iba6110_funcs(dd);
523                 break;
524 #else
525                 ipath_dev_err(dd, "QLogic HT device 0x%x cannot work if "
526                               "CONFIG_HT_IRQ is not enabled\n", ent->device);
527                 return -ENODEV;
528 #endif
529         case PCI_DEVICE_ID_INFINIPATH_PE800:
530 #ifdef CONFIG_PCI_MSI
531                 ipath_init_iba6120_funcs(dd);
532                 break;
533 #else
534                 ipath_dev_err(dd, "QLogic PCIE device 0x%x cannot work if "
535                               "CONFIG_PCI_MSI is not enabled\n", ent->device);
536                 return -ENODEV;
537 #endif
538         case PCI_DEVICE_ID_INFINIPATH_7220:
539 #ifndef CONFIG_PCI_MSI
540                 ipath_dbg("CONFIG_PCI_MSI is not enabled, "
541                           "using INTx for unit %u\n", dd->ipath_unit);
542 #endif
543                 ipath_init_iba7220_funcs(dd);
544                 break;
545         default:
546                 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
547                               "failing\n", ent->device);
548                 return -ENODEV;
549         }
550
551         for (j = 0; j < 6; j++) {
552                 if (!pdev->resource[j].start)
553                         continue;
554                 ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
555                            j, (unsigned long long)pdev->resource[j].start,
556                            (unsigned long long)pdev->resource[j].end,
557                            (unsigned long long)pci_resource_len(pdev, j));
558         }
559
560         if (!addr) {
561                 ipath_dev_err(dd, "No valid address in BAR 0!\n");
562                 ret = -ENODEV;
563                 goto bail_regions;
564         }
565
566         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
567         if (ret) {
568                 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
569                               "%u: err %d\n", dd->ipath_unit, -ret);
570                 goto bail_regions;      /* shouldn't ever happen */
571         }
572         dd->ipath_pcirev = rev;
573
574 #if defined(__powerpc__)
575         /* There isn't a generic way to specify writethrough mappings */
576         dd->ipath_kregbase = __ioremap(addr, len,
577                 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
578 #else
579         dd->ipath_kregbase = ioremap_nocache(addr, len);
580 #endif
581
582         if (!dd->ipath_kregbase) {
583                 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
584                           addr);
585                 ret = -ENOMEM;
586                 goto bail_iounmap;
587         }
588         dd->ipath_kregend = (u64 __iomem *)
589                 ((void __iomem *)dd->ipath_kregbase + len);
590         dd->ipath_physaddr = addr;      /* used for io_remap, etc. */
591         /* for user mmap */
592         ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
593                    addr, dd->ipath_kregbase);
594
595         if (dd->ipath_f_bus(dd, pdev))
596                 ipath_dev_err(dd, "Failed to setup config space; "
597                               "continuing anyway\n");
598
599         /*
600          * set up our interrupt handler; IRQF_SHARED probably not needed,
601          * since MSI interrupts shouldn't be shared but won't  hurt for now.
602          * check 0 irq after we return from chip-specific bus setup, since
603          * that can affect this due to setup
604          */
605         if (!dd->ipath_irq)
606                 ipath_dev_err(dd, "irq is 0, BIOS error?  Interrupts won't "
607                               "work\n");
608         else {
609                 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
610                                   IPATH_DRV_NAME, dd);
611                 if (ret) {
612                         ipath_dev_err(dd, "Couldn't setup irq handler, "
613                                       "irq=%d: %d\n", dd->ipath_irq, ret);
614                         goto bail_iounmap;
615                 }
616         }
617
618         ret = ipath_init_chip(dd, 0);   /* do the chip-specific init */
619         if (ret)
620                 goto bail_irqsetup;
621
622         ret = ipath_enable_wc(dd);
623
624         if (ret) {
625                 ipath_dev_err(dd, "Write combining not enabled "
626                               "(err %d): performance may be poor\n",
627                               -ret);
628                 ret = 0;
629         }
630
631         ipath_verify_pioperf(dd);
632
633         ipath_device_create_group(&pdev->dev, dd);
634         ipathfs_add_device(dd);
635         ipath_user_add(dd);
636         ipath_diag_add(dd);
637         ipath_register_ib_device(dd);
638
639         goto bail;
640
641 bail_irqsetup:
642         if (pdev->irq)
643                 free_irq(pdev->irq, dd);
644
645 bail_iounmap:
646         iounmap((volatile void __iomem *) dd->ipath_kregbase);
647
648 bail_regions:
649         pci_release_regions(pdev);
650
651 bail_disable:
652         pci_disable_device(pdev);
653
654 bail_devdata:
655         ipath_free_devdata(pdev, dd);
656
657 bail:
658         return ret;
659 }
660
661 static void __devexit cleanup_device(struct ipath_devdata *dd)
662 {
663         int port;
664
665         if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
666                 /* can't do anything more with chip; needs re-init */
667                 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
668                 if (dd->ipath_kregbase) {
669                         /*
670                          * if we haven't already cleaned up before these are
671                          * to ensure any register reads/writes "fail" until
672                          * re-init
673                          */
674                         dd->ipath_kregbase = NULL;
675                         dd->ipath_uregbase = 0;
676                         dd->ipath_sregbase = 0;
677                         dd->ipath_cregbase = 0;
678                         dd->ipath_kregsize = 0;
679                 }
680                 ipath_disable_wc(dd);
681         }
682
683         if (dd->ipath_spectriggerhit)
684                 dev_info(&dd->pcidev->dev, "%lu special trigger hits\n",
685                          dd->ipath_spectriggerhit);
686
687         if (dd->ipath_pioavailregs_dma) {
688                 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
689                                   (void *) dd->ipath_pioavailregs_dma,
690                                   dd->ipath_pioavailregs_phys);
691                 dd->ipath_pioavailregs_dma = NULL;
692         }
693         if (dd->ipath_dummy_hdrq) {
694                 dma_free_coherent(&dd->pcidev->dev,
695                         dd->ipath_pd[0]->port_rcvhdrq_size,
696                         dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
697                 dd->ipath_dummy_hdrq = NULL;
698         }
699
700         if (dd->ipath_pageshadow) {
701                 struct page **tmpp = dd->ipath_pageshadow;
702                 dma_addr_t *tmpd = dd->ipath_physshadow;
703                 int i, cnt = 0;
704
705                 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
706                            "locked\n");
707                 for (port = 0; port < dd->ipath_cfgports; port++) {
708                         int port_tidbase = port * dd->ipath_rcvtidcnt;
709                         int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
710                         for (i = port_tidbase; i < maxtid; i++) {
711                                 if (!tmpp[i])
712                                         continue;
713                                 pci_unmap_page(dd->pcidev, tmpd[i],
714                                         PAGE_SIZE, PCI_DMA_FROMDEVICE);
715                                 ipath_release_user_pages(&tmpp[i], 1);
716                                 tmpp[i] = NULL;
717                                 cnt++;
718                         }
719                 }
720                 if (cnt) {
721                         ipath_stats.sps_pageunlocks += cnt;
722                         ipath_cdbg(VERBOSE, "There were still %u expTID "
723                                    "entries locked\n", cnt);
724                 }
725                 if (ipath_stats.sps_pagelocks ||
726                     ipath_stats.sps_pageunlocks)
727                         ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
728                                    "unlocked via ipath_m{un}lock\n",
729                                    (unsigned long long)
730                                    ipath_stats.sps_pagelocks,
731                                    (unsigned long long)
732                                    ipath_stats.sps_pageunlocks);
733
734                 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
735                            dd->ipath_pageshadow);
736                 tmpp = dd->ipath_pageshadow;
737                 dd->ipath_pageshadow = NULL;
738                 vfree(tmpp);
739
740                 dd->ipath_egrtidbase = NULL;
741         }
742
743         /*
744          * free any resources still in use (usually just kernel ports)
745          * at unload; we do for portcnt, not cfgports, because cfgports
746          * could have changed while we were loaded.
747          */
748         for (port = 0; port < dd->ipath_portcnt; port++) {
749                 struct ipath_portdata *pd = dd->ipath_pd[port];
750                 dd->ipath_pd[port] = NULL;
751                 ipath_free_pddata(dd, pd);
752         }
753         kfree(dd->ipath_pd);
754         /*
755          * debuggability, in case some cleanup path tries to use it
756          * after this
757          */
758         dd->ipath_pd = NULL;
759 }
760
761 static void __devexit ipath_remove_one(struct pci_dev *pdev)
762 {
763         struct ipath_devdata *dd = pci_get_drvdata(pdev);
764
765         ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
766
767         /*
768          * disable the IB link early, to be sure no new packets arrive, which
769          * complicates the shutdown process
770          */
771         ipath_shutdown_device(dd);
772
773         flush_scheduled_work();
774
775         if (dd->verbs_dev)
776                 ipath_unregister_ib_device(dd->verbs_dev);
777
778         ipath_diag_remove(dd);
779         ipath_user_remove(dd);
780         ipathfs_remove_device(dd);
781         ipath_device_remove_group(&pdev->dev, dd);
782
783         ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
784                    "unit %u\n", dd, (u32) dd->ipath_unit);
785
786         cleanup_device(dd);
787
788         /*
789          * turn off rcv, send, and interrupts for all ports, all drivers
790          * should also hard reset the chip here?
791          * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
792          * for all versions of the driver, if they were allocated
793          */
794         if (dd->ipath_irq) {
795                 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
796                            dd->ipath_unit, dd->ipath_irq);
797                 dd->ipath_f_free_irq(dd);
798         } else
799                 ipath_dbg("irq is 0, not doing free_irq "
800                           "for unit %u\n", dd->ipath_unit);
801         /*
802          * we check for NULL here, because it's outside
803          * the kregbase check, and we need to call it
804          * after the free_irq.  Thus it's possible that
805          * the function pointers were never initialized.
806          */
807         if (dd->ipath_f_cleanup)
808                 /* clean up chip-specific stuff */
809                 dd->ipath_f_cleanup(dd);
810
811         ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
812         iounmap((volatile void __iomem *) dd->ipath_kregbase);
813         pci_release_regions(pdev);
814         ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
815         pci_disable_device(pdev);
816
817         ipath_free_devdata(pdev, dd);
818 }
819
820 /* general driver use */
821 DEFINE_MUTEX(ipath_mutex);
822
823 static DEFINE_SPINLOCK(ipath_pioavail_lock);
824
825 /**
826  * ipath_disarm_piobufs - cancel a range of PIO buffers
827  * @dd: the infinipath device
828  * @first: the first PIO buffer to cancel
829  * @cnt: the number of PIO buffers to cancel
830  *
831  * cancel a range of PIO buffers, used when they might be armed, but
832  * not triggered.  Used at init to ensure buffer state, and also user
833  * process close, in case it died while writing to a PIO buffer
834  * Also after errors.
835  */
836 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
837                           unsigned cnt)
838 {
839         unsigned i, last = first + cnt;
840         unsigned long flags;
841
842         ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
843         for (i = first; i < last; i++) {
844                 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
845                 /*
846                  * The disarm-related bits are write-only, so it
847                  * is ok to OR them in with our copy of sendctrl
848                  * while we hold the lock.
849                  */
850                 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
851                         dd->ipath_sendctrl | INFINIPATH_S_DISARM |
852                         (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
853                 /* can't disarm bufs back-to-back per iba7220 spec */
854                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
855                 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
856         }
857         /* on some older chips, update may not happen after cancel */
858         ipath_force_pio_avail_update(dd);
859 }
860
861 /**
862  * ipath_wait_linkstate - wait for an IB link state change to occur
863  * @dd: the infinipath device
864  * @state: the state to wait for
865  * @msecs: the number of milliseconds to wait
866  *
867  * wait up to msecs milliseconds for IB link state change to occur for
868  * now, take the easy polling route.  Currently used only by
869  * ipath_set_linkstate.  Returns 0 if state reached, otherwise
870  * -ETIMEDOUT state can have multiple states set, for any of several
871  * transitions.
872  */
873 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
874 {
875         dd->ipath_state_wanted = state;
876         wait_event_interruptible_timeout(ipath_state_wait,
877                                          (dd->ipath_flags & state),
878                                          msecs_to_jiffies(msecs));
879         dd->ipath_state_wanted = 0;
880
881         if (!(dd->ipath_flags & state)) {
882                 u64 val;
883                 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
884                            " ms\n",
885                            /* test INIT ahead of DOWN, both can be set */
886                            (state & IPATH_LINKINIT) ? "INIT" :
887                            ((state & IPATH_LINKDOWN) ? "DOWN" :
888                             ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
889                            msecs);
890                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
891                 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
892                            (unsigned long long) ipath_read_kreg64(
893                                    dd, dd->ipath_kregs->kr_ibcctrl),
894                            (unsigned long long) val,
895                            ipath_ibcstatus_str[val & dd->ibcs_lts_mask]);
896         }
897         return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
898 }
899
900 static void decode_sdma_errs(struct ipath_devdata *dd, ipath_err_t err,
901         char *buf, size_t blen)
902 {
903         static const struct {
904                 ipath_err_t err;
905                 const char *msg;
906         } errs[] = {
907                 { INFINIPATH_E_SDMAGENMISMATCH, "SDmaGenMismatch" },
908                 { INFINIPATH_E_SDMAOUTOFBOUND, "SDmaOutOfBound" },
909                 { INFINIPATH_E_SDMATAILOUTOFBOUND, "SDmaTailOutOfBound" },
910                 { INFINIPATH_E_SDMABASE, "SDmaBase" },
911                 { INFINIPATH_E_SDMA1STDESC, "SDma1stDesc" },
912                 { INFINIPATH_E_SDMARPYTAG, "SDmaRpyTag" },
913                 { INFINIPATH_E_SDMADWEN, "SDmaDwEn" },
914                 { INFINIPATH_E_SDMAMISSINGDW, "SDmaMissingDw" },
915                 { INFINIPATH_E_SDMAUNEXPDATA, "SDmaUnexpData" },
916                 { INFINIPATH_E_SDMADESCADDRMISALIGN, "SDmaDescAddrMisalign" },
917                 { INFINIPATH_E_SENDBUFMISUSE, "SendBufMisuse" },
918                 { INFINIPATH_E_SDMADISABLED, "SDmaDisabled" },
919         };
920         int i;
921         int expected;
922         size_t bidx = 0;
923
924         for (i = 0; i < ARRAY_SIZE(errs); i++) {
925                 expected = (errs[i].err != INFINIPATH_E_SDMADISABLED) ? 0 :
926                         test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status);
927                 if ((err & errs[i].err) && !expected)
928                         bidx += snprintf(buf + bidx, blen - bidx,
929                                          "%s ", errs[i].msg);
930         }
931 }
932
933 /*
934  * Decode the error status into strings, deciding whether to always
935  * print * it or not depending on "normal packet errors" vs everything
936  * else.   Return 1 if "real" errors, otherwise 0 if only packet
937  * errors, so caller can decide what to print with the string.
938  */
939 int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen,
940         ipath_err_t err)
941 {
942         int iserr = 1;
943         *buf = '\0';
944         if (err & INFINIPATH_E_PKTERRS) {
945                 if (!(err & ~INFINIPATH_E_PKTERRS))
946                         iserr = 0; // if only packet errors.
947                 if (ipath_debug & __IPATH_ERRPKTDBG) {
948                         if (err & INFINIPATH_E_REBP)
949                                 strlcat(buf, "EBP ", blen);
950                         if (err & INFINIPATH_E_RVCRC)
951                                 strlcat(buf, "VCRC ", blen);
952                         if (err & INFINIPATH_E_RICRC) {
953                                 strlcat(buf, "CRC ", blen);
954                                 // clear for check below, so only once
955                                 err &= INFINIPATH_E_RICRC;
956                         }
957                         if (err & INFINIPATH_E_RSHORTPKTLEN)
958                                 strlcat(buf, "rshortpktlen ", blen);
959                         if (err & INFINIPATH_E_SDROPPEDDATAPKT)
960                                 strlcat(buf, "sdroppeddatapkt ", blen);
961                         if (err & INFINIPATH_E_SPKTLEN)
962                                 strlcat(buf, "spktlen ", blen);
963                 }
964                 if ((err & INFINIPATH_E_RICRC) &&
965                         !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
966                         strlcat(buf, "CRC ", blen);
967                 if (!iserr)
968                         goto done;
969         }
970         if (err & INFINIPATH_E_RHDRLEN)
971                 strlcat(buf, "rhdrlen ", blen);
972         if (err & INFINIPATH_E_RBADTID)
973                 strlcat(buf, "rbadtid ", blen);
974         if (err & INFINIPATH_E_RBADVERSION)
975                 strlcat(buf, "rbadversion ", blen);
976         if (err & INFINIPATH_E_RHDR)
977                 strlcat(buf, "rhdr ", blen);
978         if (err & INFINIPATH_E_SENDSPECIALTRIGGER)
979                 strlcat(buf, "sendspecialtrigger ", blen);
980         if (err & INFINIPATH_E_RLONGPKTLEN)
981                 strlcat(buf, "rlongpktlen ", blen);
982         if (err & INFINIPATH_E_RMAXPKTLEN)
983                 strlcat(buf, "rmaxpktlen ", blen);
984         if (err & INFINIPATH_E_RMINPKTLEN)
985                 strlcat(buf, "rminpktlen ", blen);
986         if (err & INFINIPATH_E_SMINPKTLEN)
987                 strlcat(buf, "sminpktlen ", blen);
988         if (err & INFINIPATH_E_RFORMATERR)
989                 strlcat(buf, "rformaterr ", blen);
990         if (err & INFINIPATH_E_RUNSUPVL)
991                 strlcat(buf, "runsupvl ", blen);
992         if (err & INFINIPATH_E_RUNEXPCHAR)
993                 strlcat(buf, "runexpchar ", blen);
994         if (err & INFINIPATH_E_RIBFLOW)
995                 strlcat(buf, "ribflow ", blen);
996         if (err & INFINIPATH_E_SUNDERRUN)
997                 strlcat(buf, "sunderrun ", blen);
998         if (err & INFINIPATH_E_SPIOARMLAUNCH)
999                 strlcat(buf, "spioarmlaunch ", blen);
1000         if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
1001                 strlcat(buf, "sunexperrpktnum ", blen);
1002         if (err & INFINIPATH_E_SDROPPEDSMPPKT)
1003                 strlcat(buf, "sdroppedsmppkt ", blen);
1004         if (err & INFINIPATH_E_SMAXPKTLEN)
1005                 strlcat(buf, "smaxpktlen ", blen);
1006         if (err & INFINIPATH_E_SUNSUPVL)
1007                 strlcat(buf, "sunsupVL ", blen);
1008         if (err & INFINIPATH_E_INVALIDADDR)
1009                 strlcat(buf, "invalidaddr ", blen);
1010         if (err & INFINIPATH_E_RRCVEGRFULL)
1011                 strlcat(buf, "rcvegrfull ", blen);
1012         if (err & INFINIPATH_E_RRCVHDRFULL)
1013                 strlcat(buf, "rcvhdrfull ", blen);
1014         if (err & INFINIPATH_E_IBSTATUSCHANGED)
1015                 strlcat(buf, "ibcstatuschg ", blen);
1016         if (err & INFINIPATH_E_RIBLOSTLINK)
1017                 strlcat(buf, "riblostlink ", blen);
1018         if (err & INFINIPATH_E_HARDWARE)
1019                 strlcat(buf, "hardware ", blen);
1020         if (err & INFINIPATH_E_RESET)
1021                 strlcat(buf, "reset ", blen);
1022         if (err & INFINIPATH_E_SDMAERRS)
1023                 decode_sdma_errs(dd, err, buf, blen);
1024         if (err & INFINIPATH_E_INVALIDEEPCMD)
1025                 strlcat(buf, "invalideepromcmd ", blen);
1026 done:
1027         return iserr;
1028 }
1029
1030 /**
1031  * get_rhf_errstring - decode RHF errors
1032  * @err: the err number
1033  * @msg: the output buffer
1034  * @len: the length of the output buffer
1035  *
1036  * only used one place now, may want more later
1037  */
1038 static void get_rhf_errstring(u32 err, char *msg, size_t len)
1039 {
1040         /* if no errors, and so don't need to check what's first */
1041         *msg = '\0';
1042
1043         if (err & INFINIPATH_RHF_H_ICRCERR)
1044                 strlcat(msg, "icrcerr ", len);
1045         if (err & INFINIPATH_RHF_H_VCRCERR)
1046                 strlcat(msg, "vcrcerr ", len);
1047         if (err & INFINIPATH_RHF_H_PARITYERR)
1048                 strlcat(msg, "parityerr ", len);
1049         if (err & INFINIPATH_RHF_H_LENERR)
1050                 strlcat(msg, "lenerr ", len);
1051         if (err & INFINIPATH_RHF_H_MTUERR)
1052                 strlcat(msg, "mtuerr ", len);
1053         if (err & INFINIPATH_RHF_H_IHDRERR)
1054                 /* infinipath hdr checksum error */
1055                 strlcat(msg, "ipathhdrerr ", len);
1056         if (err & INFINIPATH_RHF_H_TIDERR)
1057                 strlcat(msg, "tiderr ", len);
1058         if (err & INFINIPATH_RHF_H_MKERR)
1059                 /* bad port, offset, etc. */
1060                 strlcat(msg, "invalid ipathhdr ", len);
1061         if (err & INFINIPATH_RHF_H_IBERR)
1062                 strlcat(msg, "iberr ", len);
1063         if (err & INFINIPATH_RHF_L_SWA)
1064                 strlcat(msg, "swA ", len);
1065         if (err & INFINIPATH_RHF_L_SWB)
1066                 strlcat(msg, "swB ", len);
1067 }
1068
1069 /**
1070  * ipath_get_egrbuf - get an eager buffer
1071  * @dd: the infinipath device
1072  * @bufnum: the eager buffer to get
1073  *
1074  * must only be called if ipath_pd[port] is known to be allocated
1075  */
1076 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
1077 {
1078         return dd->ipath_port0_skbinfo ?
1079                 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
1080 }
1081
1082 /**
1083  * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1084  * @dd: the infinipath device
1085  * @gfp_mask: the sk_buff SFP mask
1086  */
1087 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1088                                 gfp_t gfp_mask)
1089 {
1090         struct sk_buff *skb;
1091         u32 len;
1092
1093         /*
1094          * Only fully supported way to handle this is to allocate lots
1095          * extra, align as needed, and then do skb_reserve().  That wastes
1096          * a lot of memory...  I'll have to hack this into infinipath_copy
1097          * also.
1098          */
1099
1100         /*
1101          * We need 2 extra bytes for ipath_ether data sent in the
1102          * key header.  In order to keep everything dword aligned,
1103          * we'll reserve 4 bytes.
1104          */
1105         len = dd->ipath_ibmaxlen + 4;
1106
1107         if (dd->ipath_flags & IPATH_4BYTE_TID) {
1108                 /* We need a 2KB multiple alignment, and there is no way
1109                  * to do it except to allocate extra and then skb_reserve
1110                  * enough to bring it up to the right alignment.
1111                  */
1112                 len += 2047;
1113         }
1114
1115         skb = __dev_alloc_skb(len, gfp_mask);
1116         if (!skb) {
1117                 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1118                               len);
1119                 goto bail;
1120         }
1121
1122         skb_reserve(skb, 4);
1123
1124         if (dd->ipath_flags & IPATH_4BYTE_TID) {
1125                 u32 una = (unsigned long)skb->data & 2047;
1126                 if (una)
1127                         skb_reserve(skb, 2048 - una);
1128         }
1129
1130 bail:
1131         return skb;
1132 }
1133
1134 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1135                              u32 eflags,
1136                              u32 l,
1137                              u32 etail,
1138                              __le32 *rhf_addr,
1139                              struct ipath_message_header *hdr)
1140 {
1141         char emsg[128];
1142
1143         get_rhf_errstring(eflags, emsg, sizeof emsg);
1144         ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1145                    "tlen=%x opcode=%x egridx=%x: %s\n",
1146                    eflags, l,
1147                    ipath_hdrget_rcv_type(rhf_addr),
1148                    ipath_hdrget_length_in_bytes(rhf_addr),
1149                    be32_to_cpu(hdr->bth[0]) >> 24,
1150                    etail, emsg);
1151
1152         /* Count local link integrity errors. */
1153         if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1154                 u8 n = (dd->ipath_ibcctrl >>
1155                         INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1156                         INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1157
1158                 if (++dd->ipath_lli_counter > n) {
1159                         dd->ipath_lli_counter = 0;
1160                         dd->ipath_lli_errors++;
1161                 }
1162         }
1163 }
1164
1165 /*
1166  * ipath_kreceive - receive a packet
1167  * @pd: the infinipath port
1168  *
1169  * called from interrupt handler for errors or receive interrupt
1170  */
1171 void ipath_kreceive(struct ipath_portdata *pd)
1172 {
1173         struct ipath_devdata *dd = pd->port_dd;
1174         __le32 *rhf_addr;
1175         void *ebuf;
1176         const u32 rsize = dd->ipath_rcvhdrentsize;      /* words */
1177         const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1178         u32 etail = -1, l, hdrqtail;
1179         struct ipath_message_header *hdr;
1180         u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
1181         static u64 totcalls;    /* stats, may eventually remove */
1182         int last;
1183
1184         l = pd->port_head;
1185         rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1186         if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1187                 u32 seq = ipath_hdrget_seq(rhf_addr);
1188
1189                 if (seq != pd->port_seq_cnt)
1190                         goto bail;
1191                 hdrqtail = 0;
1192         } else {
1193                 hdrqtail = ipath_get_rcvhdrtail(pd);
1194                 if (l == hdrqtail)
1195                         goto bail;
1196                 smp_rmb();
1197         }
1198
1199 reloop:
1200         for (last = 0, i = 1; !last; i += !last) {
1201                 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1202                 eflags = ipath_hdrget_err_flags(rhf_addr);
1203                 etype = ipath_hdrget_rcv_type(rhf_addr);
1204                 /* total length */
1205                 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
1206                 ebuf = NULL;
1207                 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1208                     ipath_hdrget_use_egr_buf(rhf_addr) :
1209                     (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
1210                         /*
1211                          * It turns out that the chip uses an eager buffer
1212                          * for all non-expected packets, whether it "needs"
1213                          * one or not.  So always get the index, but don't
1214                          * set ebuf (so we try to copy data) unless the
1215                          * length requires it.
1216                          */
1217                         etail = ipath_hdrget_index(rhf_addr);
1218                         updegr = 1;
1219                         if (tlen > sizeof(*hdr) ||
1220                             etype == RCVHQ_RCV_TYPE_NON_KD)
1221                                 ebuf = ipath_get_egrbuf(dd, etail);
1222                 }
1223
1224                 /*
1225                  * both tiderr and ipathhdrerr are set for all plain IB
1226                  * packets; only ipathhdrerr should be set.
1227                  */
1228
1229                 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1230                     etype != RCVHQ_RCV_TYPE_ERROR &&
1231                     ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1232                     IPS_PROTO_VERSION)
1233                         ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1234                                    "%x\n", etype);
1235
1236                 if (unlikely(eflags))
1237                         ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
1238                 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1239                         ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
1240                         if (dd->ipath_lli_counter)
1241                                 dd->ipath_lli_counter--;
1242                 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1243                         u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1244                         u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
1245                         ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1246                                    "qp=%x), len %x; ignored\n",
1247                                    etype, opcode, qp, tlen);
1248                 }
1249                 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1250                         ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1251                                   be32_to_cpu(hdr->bth[0]) >> 24);
1252                 else {
1253                         /*
1254                          * error packet, type of error unknown.
1255                          * Probably type 3, but we don't know, so don't
1256                          * even try to print the opcode, etc.
1257                          * Usually caused by a "bad packet", that has no
1258                          * BTH, when the LRH says it should.
1259                          */
1260                         ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1261                                   " %x, len %x hdrq+%x rhf: %Lx\n",
1262                                   etail, tlen, l,
1263                                   le64_to_cpu(*(__le64 *) rhf_addr));
1264                         if (ipath_debug & __IPATH_ERRPKTDBG) {
1265                                 u32 j, *d, dw = rsize-2;
1266                                 if (rsize > (tlen>>2))
1267                                         dw = tlen>>2;
1268                                 d = (u32 *)hdr;
1269                                 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1270                                         dw);
1271                                 for (j = 0; j < dw; j++)
1272                                         printk(KERN_DEBUG "%8x%s", d[j],
1273                                                 (j%8) == 7 ? "\n" : " ");
1274                                 printk(KERN_DEBUG ".\n");
1275                         }
1276                 }
1277                 l += rsize;
1278                 if (l >= maxcnt)
1279                         l = 0;
1280                 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1281                         l + dd->ipath_rhf_offset;
1282                 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1283                         u32 seq = ipath_hdrget_seq(rhf_addr);
1284
1285                         if (++pd->port_seq_cnt > 13)
1286                                 pd->port_seq_cnt = 1;
1287                         if (seq != pd->port_seq_cnt)
1288                                 last = 1;
1289                 } else if (l == hdrqtail)
1290                         last = 1;
1291                 /*
1292                  * update head regs on last packet, and every 16 packets.
1293                  * Reduce bus traffic, while still trying to prevent
1294                  * rcvhdrq overflows, for when the queue is nearly full
1295                  */
1296                 if (last || !(i & 0xf)) {
1297                         u64 lval = l;
1298
1299                         /* request IBA6120 and 7220 interrupt only on last */
1300                         if (last)
1301                                 lval |= dd->ipath_rhdrhead_intr_off;
1302                         ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1303                                 pd->port_port);
1304                         if (updegr) {
1305                                 ipath_write_ureg(dd, ur_rcvegrindexhead,
1306                                                  etail, pd->port_port);
1307                                 updegr = 0;
1308                         }
1309                 }
1310         }
1311
1312         if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1313             !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1314                 /* IBA6110 workaround; we can have a race clearing chip
1315                  * interrupt with another interrupt about to be delivered,
1316                  * and can clear it before it is delivered on the GPIO
1317                  * workaround.  By doing the extra check here for the
1318                  * in-memory tail register updating while we were doing
1319                  * earlier packets, we "almost" guarantee we have covered
1320                  * that case.
1321                  */
1322                 u32 hqtail = ipath_get_rcvhdrtail(pd);
1323                 if (hqtail != hdrqtail) {
1324                         hdrqtail = hqtail;
1325                         reloop = 1; /* loop 1 extra time at most */
1326                         goto reloop;
1327                 }
1328         }
1329
1330         pkttot += i;
1331
1332         pd->port_head = l;
1333
1334         if (pkttot > ipath_stats.sps_maxpkts_call)
1335                 ipath_stats.sps_maxpkts_call = pkttot;
1336         ipath_stats.sps_port0pkts += pkttot;
1337         ipath_stats.sps_avgpkts_call =
1338                 ipath_stats.sps_port0pkts / ++totcalls;
1339
1340 bail:;
1341 }
1342
1343 /**
1344  * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1345  * @dd: the infinipath device
1346  *
1347  * called whenever our local copy indicates we have run out of send buffers
1348  * NOTE: This can be called from interrupt context by some code
1349  * and from non-interrupt context by ipath_getpiobuf().
1350  */
1351
1352 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1353 {
1354         unsigned long flags;
1355         int i;
1356         const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1357
1358         /* If the generation (check) bits have changed, then we update the
1359          * busy bit for the corresponding PIO buffer.  This algorithm will
1360          * modify positions to the value they already have in some cases
1361          * (i.e., no change), but it's faster than changing only the bits
1362          * that have changed.
1363          *
1364          * We would like to do this atomicly, to avoid spinlocks in the
1365          * critical send path, but that's not really possible, given the
1366          * type of changes, and that this routine could be called on
1367          * multiple cpu's simultaneously, so we lock in this routine only,
1368          * to avoid conflicting updates; all we change is the shadow, and
1369          * it's a single 64 bit memory location, so by definition the update
1370          * is atomic in terms of what other cpu's can see in testing the
1371          * bits.  The spin_lock overhead isn't too bad, since it only
1372          * happens when all buffers are in use, so only cpu overhead, not
1373          * latency or bandwidth is affected.
1374          */
1375         if (!dd->ipath_pioavailregs_dma) {
1376                 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1377                 return;
1378         }
1379         if (ipath_debug & __IPATH_VERBDBG) {
1380                 /* only if packet debug and verbose */
1381                 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1382                 unsigned long *shadow = dd->ipath_pioavailshadow;
1383
1384                 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1385                            "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1386                            "s3=%lx\n",
1387                            (unsigned long long) le64_to_cpu(dma[0]),
1388                            shadow[0],
1389                            (unsigned long long) le64_to_cpu(dma[1]),
1390                            shadow[1],
1391                            (unsigned long long) le64_to_cpu(dma[2]),
1392                            shadow[2],
1393                            (unsigned long long) le64_to_cpu(dma[3]),
1394                            shadow[3]);
1395                 if (piobregs > 4)
1396                         ipath_cdbg(
1397                                 PKT, "2nd group, dma4=%llx shad4=%lx, "
1398                                 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1399                                 "d7=%llx s7=%lx\n",
1400                                 (unsigned long long) le64_to_cpu(dma[4]),
1401                                 shadow[4],
1402                                 (unsigned long long) le64_to_cpu(dma[5]),
1403                                 shadow[5],
1404                                 (unsigned long long) le64_to_cpu(dma[6]),
1405                                 shadow[6],
1406                                 (unsigned long long) le64_to_cpu(dma[7]),
1407                                 shadow[7]);
1408         }
1409         spin_lock_irqsave(&ipath_pioavail_lock, flags);
1410         for (i = 0; i < piobregs; i++) {
1411                 u64 pchbusy, pchg, piov, pnew;
1412                 /*
1413                  * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1414                  */
1415                 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1416                         piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1417                 else
1418                         piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1419                 pchg = dd->ipath_pioavailkernel[i] &
1420                         ~(dd->ipath_pioavailshadow[i] ^ piov);
1421                 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1422                 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1423                         pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1424                         pnew |= piov & pchbusy;
1425                         dd->ipath_pioavailshadow[i] = pnew;
1426                 }
1427         }
1428         spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1429 }
1430
1431 /*
1432  * used to force update of pioavailshadow if we can't get a pio buffer.
1433  * Needed primarily due to exitting freeze mode after recovering
1434  * from errors.  Done lazily, because it's safer (known to not
1435  * be writing pio buffers).
1436  */
1437 static void ipath_reset_availshadow(struct ipath_devdata *dd)
1438 {
1439         int i, im;
1440         unsigned long flags;
1441
1442         spin_lock_irqsave(&ipath_pioavail_lock, flags);
1443         for (i = 0; i < dd->ipath_pioavregs; i++) {
1444                 u64 val, oldval;
1445                 /* deal with 6110 chip bug on high register #s */
1446                 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1447                         i ^ 1 : i;
1448                 val = le64_to_cpu(dd->ipath_pioavailregs_dma[im]);
1449                 /*
1450                  * busy out the buffers not in the kernel avail list,
1451                  * without changing the generation bits.
1452                  */
1453                 oldval = dd->ipath_pioavailshadow[i];
1454                 dd->ipath_pioavailshadow[i] = val |
1455                         ((~dd->ipath_pioavailkernel[i] <<
1456                         INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT) &
1457                         0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
1458                 if (oldval != dd->ipath_pioavailshadow[i])
1459                         ipath_dbg("shadow[%d] was %Lx, now %lx\n",
1460                                 i, oldval, dd->ipath_pioavailshadow[i]);
1461         }
1462         spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1463 }
1464
1465 /**
1466  * ipath_setrcvhdrsize - set the receive header size
1467  * @dd: the infinipath device
1468  * @rhdrsize: the receive header size
1469  *
1470  * called from user init code, and also layered driver init
1471  */
1472 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1473 {
1474         int ret = 0;
1475
1476         if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1477                 if (dd->ipath_rcvhdrsize != rhdrsize) {
1478                         dev_info(&dd->pcidev->dev,
1479                                  "Error: can't set protocol header "
1480                                  "size %u, already %u\n",
1481                                  rhdrsize, dd->ipath_rcvhdrsize);
1482                         ret = -EAGAIN;
1483                 } else
1484                         ipath_cdbg(VERBOSE, "Reuse same protocol header "
1485                                    "size %u\n", dd->ipath_rcvhdrsize);
1486         } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1487                                (sizeof(u64) / sizeof(u32)))) {
1488                 ipath_dbg("Error: can't set protocol header size %u "
1489                           "(> max %u)\n", rhdrsize,
1490                           dd->ipath_rcvhdrentsize -
1491                           (u32) (sizeof(u64) / sizeof(u32)));
1492                 ret = -EOVERFLOW;
1493         } else {
1494                 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1495                 dd->ipath_rcvhdrsize = rhdrsize;
1496                 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1497                                  dd->ipath_rcvhdrsize);
1498                 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1499                            dd->ipath_rcvhdrsize);
1500         }
1501         return ret;
1502 }
1503
1504 /*
1505  * debugging code and stats updates if no pio buffers available.
1506  */
1507 static noinline void no_pio_bufs(struct ipath_devdata *dd)
1508 {
1509         unsigned long *shadow = dd->ipath_pioavailshadow;
1510         __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1511
1512         dd->ipath_upd_pio_shadow = 1;
1513
1514         /*
1515          * not atomic, but if we lose a stat count in a while, that's OK
1516          */
1517         ipath_stats.sps_nopiobufs++;
1518         if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1519                 ipath_force_pio_avail_update(dd); /* at start */
1520                 ipath_dbg("%u tries no piobufavail ts%lx; dmacopy: "
1521                         "%llx %llx %llx %llx\n"
1522                         "ipath  shadow:  %lx %lx %lx %lx\n",
1523                         dd->ipath_consec_nopiobuf,
1524                         (unsigned long)get_cycles(),
1525                         (unsigned long long) le64_to_cpu(dma[0]),
1526                         (unsigned long long) le64_to_cpu(dma[1]),
1527                         (unsigned long long) le64_to_cpu(dma[2]),
1528                         (unsigned long long) le64_to_cpu(dma[3]),
1529                         shadow[0], shadow[1], shadow[2], shadow[3]);
1530                 /*
1531                  * 4 buffers per byte, 4 registers above, cover rest
1532                  * below
1533                  */
1534                 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1535                     (sizeof(shadow[0]) * 4 * 4))
1536                         ipath_dbg("2nd group: dmacopy: "
1537                                   "%llx %llx %llx %llx\n"
1538                                   "ipath  shadow:  %lx %lx %lx %lx\n",
1539                                   (unsigned long long)le64_to_cpu(dma[4]),
1540                                   (unsigned long long)le64_to_cpu(dma[5]),
1541                                   (unsigned long long)le64_to_cpu(dma[6]),
1542                                   (unsigned long long)le64_to_cpu(dma[7]),
1543                                   shadow[4], shadow[5], shadow[6], shadow[7]);
1544
1545                 /* at end, so update likely happened */
1546                 ipath_reset_availshadow(dd);
1547         }
1548 }
1549
1550 /*
1551  * common code for normal driver pio buffer allocation, and reserved
1552  * allocation.
1553  *
1554  * do appropriate marking as busy, etc.
1555  * returns buffer number if one found (>=0), negative number is error.
1556  */
1557 static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1558         u32 *pbufnum, u32 first, u32 last, u32 firsti)
1559 {
1560         int i, j, updated = 0;
1561         unsigned piobcnt;
1562         unsigned long flags;
1563         unsigned long *shadow = dd->ipath_pioavailshadow;
1564         u32 __iomem *buf;
1565
1566         piobcnt = last - first;
1567         if (dd->ipath_upd_pio_shadow) {
1568                 /*
1569                  * Minor optimization.  If we had no buffers on last call,
1570                  * start out by doing the update; continue and do scan even
1571                  * if no buffers were updated, to be paranoid
1572                  */
1573                 ipath_update_pio_bufs(dd);
1574                 updated++;
1575                 i = first;
1576         } else
1577                 i = firsti;
1578 rescan:
1579         /*
1580          * while test_and_set_bit() is atomic, we do that and then the
1581          * change_bit(), and the pair is not.  See if this is the cause
1582          * of the remaining armlaunch errors.
1583          */
1584         spin_lock_irqsave(&ipath_pioavail_lock, flags);
1585         for (j = 0; j < piobcnt; j++, i++) {
1586                 if (i >= last)
1587                         i = first;
1588                 if (__test_and_set_bit((2 * i) + 1, shadow))
1589                         continue;
1590                 /* flip generation bit */
1591                 __change_bit(2 * i, shadow);
1592                 break;
1593         }
1594         spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1595
1596         if (j == piobcnt) {
1597                 if (!updated) {
1598                         /*
1599                          * first time through; shadow exhausted, but may be
1600                          * buffers available, try an update and then rescan.
1601                          */
1602                         ipath_update_pio_bufs(dd);
1603                         updated++;
1604                         i = first;
1605                         goto rescan;
1606                 } else if (updated == 1 && piobcnt <=
1607                         ((dd->ipath_sendctrl
1608                         >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1609                         INFINIPATH_S_UPDTHRESH_MASK)) {
1610                         /*
1611                          * for chips supporting and using the update
1612                          * threshold we need to force an update of the
1613                          * in-memory copy if the count is less than the
1614                          * thershold, then check one more time.
1615                          */
1616                         ipath_force_pio_avail_update(dd);
1617                         ipath_update_pio_bufs(dd);
1618                         updated++;
1619                         i = first;
1620                         goto rescan;
1621                 }
1622
1623                 no_pio_bufs(dd);
1624                 buf = NULL;
1625         } else {
1626                 if (i < dd->ipath_piobcnt2k)
1627                         buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1628                                                i * dd->ipath_palign);
1629                 else
1630                         buf = (u32 __iomem *)
1631                                 (dd->ipath_pio4kbase +
1632                                  (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1633                 if (pbufnum)
1634                         *pbufnum = i;
1635         }
1636
1637         return buf;
1638 }
1639
1640 /**
1641  * ipath_getpiobuf - find an available pio buffer
1642  * @dd: the infinipath device
1643  * @plen: the size of the PIO buffer needed in 32-bit words
1644  * @pbufnum: the buffer number is placed here
1645  */
1646 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1647 {
1648         u32 __iomem *buf;
1649         u32 pnum, nbufs;
1650         u32 first, lasti;
1651
1652         if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1653                 first = dd->ipath_piobcnt2k;
1654                 lasti = dd->ipath_lastpioindexl;
1655         } else {
1656                 first = 0;
1657                 lasti = dd->ipath_lastpioindex;
1658         }
1659         nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1660         buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1661
1662         if (buf) {
1663                 /*
1664                  * Set next starting place.  It's just an optimization,
1665                  * it doesn't matter who wins on this, so no locking
1666                  */
1667                 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1668                         dd->ipath_lastpioindexl = pnum + 1;
1669                 else
1670                         dd->ipath_lastpioindex = pnum + 1;
1671                 if (dd->ipath_upd_pio_shadow)
1672                         dd->ipath_upd_pio_shadow = 0;
1673                 if (dd->ipath_consec_nopiobuf)
1674                         dd->ipath_consec_nopiobuf = 0;
1675                 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1676                            pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1677                 if (pbufnum)
1678                         *pbufnum = pnum;
1679
1680         }
1681         return buf;
1682 }
1683
1684 /**
1685  * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1686  * @dd: the infinipath device
1687  * @start: the starting send buffer number
1688  * @len: the number of send buffers
1689  * @avail: true if the buffers are available for kernel use, false otherwise
1690  */
1691 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1692                               unsigned len, int avail)
1693 {
1694         unsigned long flags;
1695         unsigned end, cnt = 0, next;
1696
1697         /* There are two bits per send buffer (busy and generation) */
1698         start *= 2;
1699         end = start + len * 2;
1700
1701         spin_lock_irqsave(&ipath_pioavail_lock, flags);
1702         /* Set or clear the busy bit in the shadow. */
1703         while (start < end) {
1704                 if (avail) {
1705                         unsigned long dma;
1706                         int i, im;
1707                         /*
1708                          * the BUSY bit will never be set, because we disarm
1709                          * the user buffers before we hand them back to the
1710                          * kernel.  We do have to make sure the generation
1711                          * bit is set correctly in shadow, since it could
1712                          * have changed many times while allocated to user.
1713                          * We can't use the bitmap functions on the full
1714                          * dma array because it is always little-endian, so
1715                          * we have to flip to host-order first.
1716                          * BITS_PER_LONG is slightly wrong, since it's
1717                          * always 64 bits per register in chip...
1718                          * We only work on 64 bit kernels, so that's OK.
1719                          */
1720                         /* deal with 6110 chip bug on high register #s */
1721                         i = start / BITS_PER_LONG;
1722                         im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1723                                 i ^ 1 : i;
1724                         __clear_bit(INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
1725                                 + start, dd->ipath_pioavailshadow);
1726                         dma = (unsigned long) le64_to_cpu(
1727                                 dd->ipath_pioavailregs_dma[im]);
1728                         if (test_bit((INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1729                                 + start) % BITS_PER_LONG, &dma))
1730                                 __set_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1731                                         + start, dd->ipath_pioavailshadow);
1732                         else
1733                                 __clear_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1734                                         + start, dd->ipath_pioavailshadow);
1735                         __set_bit(start, dd->ipath_pioavailkernel);
1736                 } else {
1737                         __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1738                                 dd->ipath_pioavailshadow);
1739                         __clear_bit(start, dd->ipath_pioavailkernel);
1740                 }
1741                 start += 2;
1742         }
1743
1744         if (dd->ipath_pioupd_thresh) {
1745                 end = 2 * (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1746                 next = find_first_bit(dd->ipath_pioavailkernel, end);
1747                 while (next < end) {
1748                         cnt++;
1749                         next = find_next_bit(dd->ipath_pioavailkernel, end,
1750                                         next + 1);
1751                 }
1752         }
1753         spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1754
1755         /*
1756          * When moving buffers from kernel to user, if number assigned to
1757          * the user is less than the pio update threshold, and threshold
1758          * is supported (cnt was computed > 0), drop the update threshold
1759          * so we update at least once per allocated number of buffers.
1760          * In any case, if the kernel buffers are less than the threshold,
1761          * drop the threshold.  We don't bother increasing it, having once
1762          * decreased it, since it would typically just cycle back and forth.
1763          * If we don't decrease below buffers in use, we can wait a long
1764          * time for an update, until some other context uses PIO buffers.
1765          */
1766         if (!avail && len < cnt)
1767                 cnt = len;
1768         if (cnt < dd->ipath_pioupd_thresh) {
1769                 dd->ipath_pioupd_thresh = cnt;
1770                 ipath_dbg("Decreased pio update threshold to %u\n",
1771                         dd->ipath_pioupd_thresh);
1772                 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1773                 dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK
1774                         << INFINIPATH_S_UPDTHRESH_SHIFT);
1775                 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
1776                         << INFINIPATH_S_UPDTHRESH_SHIFT;
1777                 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1778                         dd->ipath_sendctrl);
1779                 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1780         }
1781 }
1782
1783 /**
1784  * ipath_create_rcvhdrq - create a receive header queue
1785  * @dd: the infinipath device
1786  * @pd: the port data
1787  *
1788  * this must be contiguous memory (from an i/o perspective), and must be
1789  * DMA'able (which means for some systems, it will go through an IOMMU,
1790  * or be forced into a low address range).
1791  */
1792 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1793                          struct ipath_portdata *pd)
1794 {
1795         int ret = 0;
1796
1797         if (!pd->port_rcvhdrq) {
1798                 dma_addr_t phys_hdrqtail;
1799                 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1800                 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1801                                 sizeof(u32), PAGE_SIZE);
1802
1803                 pd->port_rcvhdrq = dma_alloc_coherent(
1804                         &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1805                         gfp_flags);
1806
1807                 if (!pd->port_rcvhdrq) {
1808                         ipath_dev_err(dd, "attempt to allocate %d bytes "
1809                                       "for port %u rcvhdrq failed\n",
1810                                       amt, pd->port_port);
1811                         ret = -ENOMEM;
1812                         goto bail;
1813                 }
1814
1815                 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1816                         pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1817                                 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1818                                 GFP_KERNEL);
1819                         if (!pd->port_rcvhdrtail_kvaddr) {
1820                                 ipath_dev_err(dd, "attempt to allocate 1 page "
1821                                         "for port %u rcvhdrqtailaddr "
1822                                         "failed\n", pd->port_port);
1823                                 ret = -ENOMEM;
1824                                 dma_free_coherent(&dd->pcidev->dev, amt,
1825                                         pd->port_rcvhdrq,
1826                                         pd->port_rcvhdrq_phys);
1827                                 pd->port_rcvhdrq = NULL;
1828                                 goto bail;
1829                         }
1830                         pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1831                         ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1832                                    "physical\n", pd->port_port,
1833                                    (unsigned long long) phys_hdrqtail);
1834                 }
1835
1836                 pd->port_rcvhdrq_size = amt;
1837
1838                 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1839                            "for port %u rcvhdr Q\n",
1840                            amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1841                            (unsigned long) pd->port_rcvhdrq_phys,
1842                            (unsigned long) pd->port_rcvhdrq_size,
1843                            pd->port_port);
1844         }
1845         else
1846                 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1847                            "hdrtailaddr@%p %llx physical\n",
1848                            pd->port_port, pd->port_rcvhdrq,
1849                            (unsigned long long) pd->port_rcvhdrq_phys,
1850                            pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1851                            pd->port_rcvhdrqtailaddr_phys);
1852
1853         /* clear for security and sanity on each use */
1854         memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1855         if (pd->port_rcvhdrtail_kvaddr)
1856                 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1857
1858         /*
1859          * tell chip each time we init it, even if we are re-using previous
1860          * memory (we zero the register at process close)
1861          */
1862         ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1863                               pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1864         ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1865                               pd->port_port, pd->port_rcvhdrq_phys);
1866
1867 bail:
1868         return ret;
1869 }
1870
1871
1872 /*
1873  * Flush all sends that might be in the ready to send state, as well as any
1874  * that are in the process of being sent.   Used whenever we need to be
1875  * sure the send side is idle.  Cleans up all buffer state by canceling
1876  * all pio buffers, and issuing an abort, which cleans up anything in the
1877  * launch fifo.  The cancel is superfluous on some chip versions, but
1878  * it's safer to always do it.
1879  * PIOAvail bits are updated by the chip as if normal send had happened.
1880  */
1881 void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
1882 {
1883         unsigned long flags;
1884
1885         if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
1886                 ipath_cdbg(VERBOSE, "Ignore while in autonegotiation\n");
1887                 goto bail;
1888         }
1889         /*
1890          * If we have SDMA, and it's not disabled, we have to kick off the
1891          * abort state machine, provided we aren't already aborting.
1892          * If we are in the process of aborting SDMA (!DISABLED, but ABORTING),
1893          * we skip the rest of this routine. It is already "in progress"
1894          */
1895         if (dd->ipath_flags & IPATH_HAS_SEND_DMA) {
1896                 int skip_cancel;
1897                 unsigned long *statp = &dd->ipath_sdma_status;
1898
1899                 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1900                 skip_cancel =
1901                         test_and_set_bit(IPATH_SDMA_ABORTING, statp)
1902                         && !test_bit(IPATH_SDMA_DISABLED, statp);
1903                 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1904                 if (skip_cancel)
1905                         goto bail;
1906         }
1907
1908         ipath_dbg("Cancelling all in-progress send buffers\n");
1909
1910         /* skip armlaunch errs for a while */
1911         dd->ipath_lastcancel = jiffies + HZ / 2;
1912
1913         /*
1914          * The abort bit is auto-clearing.  We also don't want pioavail
1915          * update happening during this, and we don't want any other
1916          * sends going out, so turn those off for the duration.  We read
1917          * the scratch register to be sure that cancels and the abort
1918          * have taken effect in the chip.  Otherwise two parts are same
1919          * as ipath_force_pio_avail_update()
1920          */
1921         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1922         dd->ipath_sendctrl &= ~(INFINIPATH_S_PIOBUFAVAILUPD
1923                 | INFINIPATH_S_PIOENABLE);
1924         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1925                 dd->ipath_sendctrl | INFINIPATH_S_ABORT);
1926         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1927         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1928
1929         /* disarm all send buffers */
1930         ipath_disarm_piobufs(dd, 0,
1931                 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1932
1933         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1934                 set_bit(IPATH_SDMA_DISARMED, &dd->ipath_sdma_status);
1935
1936         if (restore_sendctrl) {
1937                 /* else done by caller later if needed */
1938                 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1939                 dd->ipath_sendctrl |= INFINIPATH_S_PIOBUFAVAILUPD |
1940                         INFINIPATH_S_PIOENABLE;
1941                 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1942                         dd->ipath_sendctrl);
1943                 /* and again, be sure all have hit the chip */
1944                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1945                 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1946         }
1947
1948         if ((dd->ipath_flags & IPATH_HAS_SEND_DMA) &&
1949             !test_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status) &&
1950             test_bit(IPATH_SDMA_RUNNING, &dd->ipath_sdma_status)) {
1951                 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1952                 /* only wait so long for intr */
1953                 dd->ipath_sdma_abort_intr_timeout = jiffies + HZ;
1954                 dd->ipath_sdma_reset_wait = 200;
1955                 if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status))
1956                         tasklet_hi_schedule(&dd->ipath_sdma_abort_task);
1957                 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1958         }
1959 bail:;
1960 }
1961
1962 /*
1963  * Force an update of in-memory copy of the pioavail registers, when
1964  * needed for any of a variety of reasons.  We read the scratch register
1965  * to make it highly likely that the update will have happened by the
1966  * time we return.  If already off (as in cancel_sends above), this
1967  * routine is a nop, on the assumption that the caller will "do the
1968  * right thing".
1969  */
1970 void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1971 {
1972         unsigned long flags;
1973
1974         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1975         if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1976                 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1977                         dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1978                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1979                 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1980                         dd->ipath_sendctrl);
1981                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1982         }
1983         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1984 }
1985
1986 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1987                                 int linitcmd)
1988 {
1989         u64 mod_wd;
1990         static const char *what[4] = {
1991                 [0] = "NOP",
1992                 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
1993                 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1994                 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1995         };
1996
1997         if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
1998                 /*
1999                  * If we are told to disable, note that so link-recovery
2000                  * code does not attempt to bring us back up.
2001                  */
2002                 preempt_disable();
2003                 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
2004                 preempt_enable();
2005         } else if (linitcmd) {
2006                 /*
2007                  * Any other linkinitcmd will lead to LINKDOWN and then
2008                  * to INIT (if all is well), so clear flag to let
2009                  * link-recovery code attempt to bring us back up.
2010                  */
2011                 preempt_disable();
2012                 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
2013                 preempt_enable();
2014         }
2015
2016         mod_wd = (linkcmd << dd->ibcc_lc_shift) |
2017                 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
2018         ipath_cdbg(VERBOSE,
2019                 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
2020                 dd->ipath_unit, what[linkcmd], linitcmd,
2021                 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
2022                         ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
2023
2024         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2025                          dd->ipath_ibcctrl | mod_wd);
2026         /* read from chip so write is flushed */
2027         (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2028 }
2029
2030 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
2031 {
2032         u32 lstate;
2033         int ret;
2034
2035         switch (newstate) {
2036         case IPATH_IB_LINKDOWN_ONLY:
2037                 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
2038                 /* don't wait */
2039                 ret = 0;
2040                 goto bail;
2041
2042         case IPATH_IB_LINKDOWN:
2043                 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2044                                         INFINIPATH_IBCC_LINKINITCMD_POLL);
2045                 /* don't wait */
2046                 ret = 0;
2047                 goto bail;
2048
2049         case IPATH_IB_LINKDOWN_SLEEP:
2050                 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2051                                         INFINIPATH_IBCC_LINKINITCMD_SLEEP);
2052                 /* don't wait */
2053                 ret = 0;
2054                 goto bail;
2055
2056         case IPATH_IB_LINKDOWN_DISABLE:
2057                 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2058                                         INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2059                 /* don't wait */
2060                 ret = 0;
2061                 goto bail;
2062
2063         case IPATH_IB_LINKARM:
2064                 if (dd->ipath_flags & IPATH_LINKARMED) {
2065                         ret = 0;
2066                         goto bail;
2067                 }
2068                 if (!(dd->ipath_flags &
2069                       (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
2070                         ret = -EINVAL;
2071                         goto bail;
2072                 }
2073                 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
2074
2075                 /*
2076                  * Since the port can transition to ACTIVE by receiving
2077                  * a non VL 15 packet, wait for either state.
2078                  */
2079                 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
2080                 break;
2081
2082         case IPATH_IB_LINKACTIVE:
2083                 if (dd->ipath_flags & IPATH_LINKACTIVE) {
2084                         ret = 0;
2085                         goto bail;
2086                 }
2087                 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
2088                         ret = -EINVAL;
2089                         goto bail;
2090                 }
2091                 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
2092                 lstate = IPATH_LINKACTIVE;
2093                 break;
2094
2095         case IPATH_IB_LINK_LOOPBACK:
2096                 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
2097                 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
2098                 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2099                                  dd->ipath_ibcctrl);
2100
2101                 /* turn heartbeat off, as it causes loopback to fail */
2102                 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2103                                        IPATH_IB_HRTBT_OFF);
2104                 /* don't wait */
2105                 ret = 0;
2106                 goto bail;
2107
2108         case IPATH_IB_LINK_EXTERNAL:
2109                 dev_info(&dd->pcidev->dev,
2110                         "Disabling IB local loopback (normal)\n");
2111                 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2112                                        IPATH_IB_HRTBT_ON);
2113                 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
2114                 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2115                                  dd->ipath_ibcctrl);
2116                 /* don't wait */
2117                 ret = 0;
2118                 goto bail;
2119
2120         /*
2121          * Heartbeat can be explicitly enabled by the user via
2122          * "hrtbt_enable" "file", and if disabled, trying to enable here
2123          * will have no effect.  Implicit changes (heartbeat off when
2124          * loopback on, and vice versa) are included to ease testing.
2125          */
2126         case IPATH_IB_LINK_HRTBT:
2127                 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2128                         IPATH_IB_HRTBT_ON);
2129                 goto bail;
2130
2131         case IPATH_IB_LINK_NO_HRTBT:
2132                 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2133                         IPATH_IB_HRTBT_OFF);
2134                 goto bail;
2135
2136         default:
2137                 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
2138                 ret = -EINVAL;
2139                 goto bail;
2140         }
2141         ret = ipath_wait_linkstate(dd, lstate, 2000);
2142
2143 bail:
2144         return ret;
2145 }
2146
2147 /**
2148  * ipath_set_mtu - set the MTU
2149  * @dd: the infinipath device
2150  * @arg: the new MTU
2151  *
2152  * we can handle "any" incoming size, the issue here is whether we
2153  * need to restrict our outgoing size.   For now, we don't do any
2154  * sanity checking on this, and we don't deal with what happens to
2155  * programs that are already running when the size changes.
2156  * NOTE: changing the MTU will usually cause the IBC to go back to
2157  * link INIT state...
2158  */
2159 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
2160 {
2161         u32 piosize;
2162         int changed = 0;
2163         int ret;
2164
2165         /*
2166          * mtu is IB data payload max.  It's the largest power of 2 less
2167          * than piosize (or even larger, since it only really controls the
2168          * largest we can receive; we can send the max of the mtu and
2169          * piosize).  We check that it's one of the valid IB sizes.
2170          */
2171         if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
2172             (arg != 4096 || !ipath_mtu4096)) {
2173                 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
2174                 ret = -EINVAL;
2175                 goto bail;
2176         }
2177         if (dd->ipath_ibmtu == arg) {
2178                 ret = 0;        /* same as current */
2179                 goto bail;
2180         }
2181
2182         piosize = dd->ipath_ibmaxlen;
2183         dd->ipath_ibmtu = arg;
2184
2185         if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
2186                 /* Only if it's not the initial value (or reset to it) */
2187                 if (piosize != dd->ipath_init_ibmaxlen) {
2188                         if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
2189                                 piosize = dd->ipath_init_ibmaxlen;
2190                         dd->ipath_ibmaxlen = piosize;
2191                         changed = 1;
2192                 }
2193         } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
2194                 piosize = arg + IPATH_PIO_MAXIBHDR;
2195                 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
2196                            "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
2197                            arg);
2198                 dd->ipath_ibmaxlen = piosize;
2199                 changed = 1;
2200         }
2201
2202         if (changed) {
2203                 u64 ibc = dd->ipath_ibcctrl, ibdw;
2204                 /*
2205                  * update our housekeeping variables, and set IBC max
2206                  * size, same as init code; max IBC is max we allow in
2207                  * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2208                  */
2209                 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
2210                 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
2211                 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
2212                          dd->ibcc_mpl_shift);
2213                 ibc |= ibdw << dd->ibcc_mpl_shift;
2214                 dd->ipath_ibcctrl = ibc;
2215                 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2216                                  dd->ipath_ibcctrl);
2217                 dd->ipath_f_tidtemplate(dd);
2218         }
2219
2220         ret = 0;
2221
2222 bail:
2223         return ret;
2224 }
2225
2226 int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc)
2227 {
2228         dd->ipath_lid = lid;
2229         dd->ipath_lmc = lmc;
2230
2231         dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid |
2232                 (~((1U << lmc) - 1)) << 16);
2233
2234         dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid);
2235
2236         return 0;
2237 }
2238
2239
2240 /**
2241  * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2242  * @dd: the infinipath device
2243  * @regno: the register number to write
2244  * @port: the port containing the register
2245  * @value: the value to write
2246  *
2247  * Registers that vary with the chip implementation constants (port)
2248  * use this routine.
2249  */
2250 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2251                           unsigned port, u64 value)
2252 {
2253         u16 where;
2254
2255         if (port < dd->ipath_portcnt &&
2256             (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2257              regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2258                 where = regno + port;
2259         else
2260                 where = -1;
2261
2262         ipath_write_kreg(dd, where, value);
2263 }
2264
2265 /*
2266  * Following deal with the "obviously simple" task of overriding the state
2267  * of the LEDS, which normally indicate link physical and logical status.
2268  * The complications arise in dealing with different hardware mappings
2269  * and the board-dependent routine being called from interrupts.
2270  * and then there's the requirement to _flash_ them.
2271  */
2272 #define LED_OVER_FREQ_SHIFT 8
2273 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2274 /* Below is "non-zero" to force override, but both actual LEDs are off */
2275 #define LED_OVER_BOTH_OFF (8)
2276
2277 static void ipath_run_led_override(unsigned long opaque)
2278 {
2279         struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2280         int timeoff;
2281         int pidx;
2282         u64 lstate, ltstate, val;
2283
2284         if (!(dd->ipath_flags & IPATH_INITTED))
2285                 return;
2286
2287         pidx = dd->ipath_led_override_phase++ & 1;
2288         dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2289         timeoff = dd->ipath_led_override_timeoff;
2290
2291         /*
2292          * below potentially restores the LED values per current status,
2293          * should also possibly setup the traffic-blink register,
2294          * but leave that to per-chip functions.
2295          */
2296         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2297         ltstate = ipath_ib_linktrstate(dd, val);
2298         lstate = ipath_ib_linkstate(dd, val);
2299
2300         dd->ipath_f_setextled(dd, lstate, ltstate);
2301         mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2302 }
2303
2304 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2305 {
2306         int timeoff, freq;
2307
2308         if (!(dd->ipath_flags & IPATH_INITTED))
2309                 return;
2310
2311         /* First check if we are blinking. If not, use 1HZ polling */
2312         timeoff = HZ;
2313         freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2314
2315         if (freq) {
2316                 /* For blink, set each phase from one nybble of val */
2317                 dd->ipath_led_override_vals[0] = val & 0xF;
2318                 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2319                 timeoff = (HZ << 4)/freq;
2320         } else {
2321                 /* Non-blink set both phases the same. */
2322                 dd->ipath_led_override_vals[0] = val & 0xF;
2323                 dd->ipath_led_override_vals[1] = val & 0xF;
2324         }
2325         dd->ipath_led_override_timeoff = timeoff;
2326
2327         /*
2328          * If the timer has not already been started, do so. Use a "quick"
2329          * timeout so the function will be called soon, to look at our request.
2330          */
2331         if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2332                 /* Need to start timer */
2333                 init_timer(&dd->ipath_led_override_timer);
2334                 dd->ipath_led_override_timer.function =
2335                                                  ipath_run_led_override;
2336                 dd->ipath_led_override_timer.data = (unsigned long) dd;
2337                 dd->ipath_led_override_timer.expires = jiffies + 1;
2338                 add_timer(&dd->ipath_led_override_timer);
2339         } else
2340                 atomic_dec(&dd->ipath_led_override_timer_active);
2341 }
2342
2343 /**
2344  * ipath_shutdown_device - shut down a device
2345  * @dd: the infinipath device
2346  *
2347  * This is called to make the device quiet when we are about to
2348  * unload the driver, and also when the device is administratively
2349  * disabled.   It does not free any data structures.
2350  * Everything it does has to be setup again by ipath_init_chip(dd,1)
2351  */
2352 void ipath_shutdown_device(struct ipath_devdata *dd)
2353 {
2354         unsigned long flags;
2355
2356         ipath_dbg("Shutting down the device\n");
2357
2358         ipath_hol_up(dd); /* make sure user processes aren't suspended */
2359
2360         dd->ipath_flags |= IPATH_LINKUNK;
2361         dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2362                              IPATH_LINKINIT | IPATH_LINKARMED |
2363                              IPATH_LINKACTIVE);
2364         *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2365                                 IPATH_STATUS_IB_READY);
2366
2367         /* mask interrupts, but not errors */
2368         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2369
2370         dd->ipath_rcvctrl = 0;
2371         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2372                          dd->ipath_rcvctrl);
2373
2374         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2375                 teardown_sdma(dd);
2376
2377         /*
2378          * gracefully stop all sends allowing any in progress to trickle out
2379          * first.
2380          */
2381         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2382         dd->ipath_sendctrl = 0;
2383         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
2384         /* flush it */
2385         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2386         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2387
2388         /*
2389          * enough for anything that's going to trickle out to have actually
2390          * done so.
2391          */
2392         udelay(5);
2393
2394         dd->ipath_f_setextled(dd, 0, 0); /* make sure LEDs are off */
2395
2396         ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2397         ipath_cancel_sends(dd, 0);
2398
2399         /*
2400          * we are shutting down, so tell components that care.  We don't do
2401          * this on just a link state change, much like ethernet, a cable
2402          * unplug, etc. doesn't change driver state
2403          */
2404         signal_ib_event(dd, IB_EVENT_PORT_ERR);
2405
2406         /* disable IBC */
2407         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2408         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2409                          dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2410
2411         /*
2412          * clear SerdesEnable and turn the leds off; do this here because
2413          * we are unloading, so don't count on interrupts to move along
2414          * Turn the LEDs off explictly for the same reason.
2415          */
2416         dd->ipath_f_quiet_serdes(dd);
2417
2418         /* stop all the timers that might still be running */
2419         del_timer_sync(&dd->ipath_hol_timer);
2420         if (dd->ipath_stats_timer_active) {
2421                 del_timer_sync(&dd->ipath_stats_timer);
2422                 dd->ipath_stats_timer_active = 0;
2423         }
2424         if (dd->ipath_intrchk_timer.data) {
2425                 del_timer_sync(&dd->ipath_intrchk_timer);
2426                 dd->ipath_intrchk_timer.data = 0;
2427         }
2428         if (atomic_read(&dd->ipath_led_override_timer_active)) {
2429                 del_timer_sync(&dd->ipath_led_override_timer);
2430                 atomic_set(&dd->ipath_led_override_timer_active, 0);
2431         }
2432
2433         /*
2434          * clear all interrupts and errors, so that the next time the driver
2435          * is loaded or device is enabled, we know that whatever is set
2436          * happened while we were unloaded
2437          */
2438         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2439                          ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2440         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2441         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2442
2443         ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2444         ipath_update_eeprom_log(dd);
2445 }
2446
2447 /**
2448  * ipath_free_pddata - free a port's allocated data
2449  * @dd: the infinipath device
2450  * @pd: the portdata structure
2451  *
2452  * free up any allocated data for a port
2453  * This should not touch anything that would affect a simultaneous
2454  * re-allocation of port data, because it is called after ipath_mutex
2455  * is released (and can be called from reinit as well).
2456  * It should never change any chip state, or global driver state.
2457  * (The only exception to global state is freeing the port0 port0_skbs.)
2458  */
2459 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2460 {
2461         if (!pd)
2462                 return;
2463
2464         if (pd->port_rcvhdrq) {
2465                 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2466                            "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2467                            (unsigned long) pd->port_rcvhdrq_size);
2468                 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2469                                   pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2470                 pd->port_rcvhdrq = NULL;
2471                 if (pd->port_rcvhdrtail_kvaddr) {
2472                         dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2473                                          pd->port_rcvhdrtail_kvaddr,
2474                                          pd->port_rcvhdrqtailaddr_phys);
2475                         pd->port_rcvhdrtail_kvaddr = NULL;
2476                 }
2477         }
2478         if (pd->port_port && pd->port_rcvegrbuf) {
2479                 unsigned e;
2480
2481                 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2482                         void *base = pd->port_rcvegrbuf[e];
2483                         size_t size = pd->port_rcvegrbuf_size;
2484
2485                         ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2486                                    "chunk %u/%u\n", base,
2487                                    (unsigned long) size,
2488                                    e, pd->port_rcvegrbuf_chunks);
2489                         dma_free_coherent(&dd->pcidev->dev, size,
2490                                 base, pd->port_rcvegrbuf_phys[e]);
2491                 }
2492                 kfree(pd->port_rcvegrbuf);
2493                 pd->port_rcvegrbuf = NULL;
2494                 kfree(pd->port_rcvegrbuf_phys);
2495                 pd->port_rcvegrbuf_phys = NULL;
2496                 pd->port_rcvegrbuf_chunks = 0;
2497         } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2498                 unsigned e;
2499                 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2500
2501                 dd->ipath_port0_skbinfo = NULL;
2502                 ipath_cdbg(VERBOSE, "free closed port %d "
2503                            "ipath_port0_skbinfo @ %p\n", pd->port_port,
2504                            skbinfo);
2505                 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2506                         if (skbinfo[e].skb) {
2507                                 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2508                                                  dd->ipath_ibmaxlen,
2509                                                  PCI_DMA_FROMDEVICE);
2510                                 dev_kfree_skb(skbinfo[e].skb);
2511                         }
2512                 vfree(skbinfo);
2513         }
2514         kfree(pd->port_tid_pg_list);
2515         vfree(pd->subport_uregbase);
2516         vfree(pd->subport_rcvegrbuf);
2517         vfree(pd->subport_rcvhdr_base);
2518         kfree(pd);
2519 }
2520
2521 static int __init infinipath_init(void)
2522 {
2523         int ret;
2524
2525         if (ipath_debug & __IPATH_DBG)
2526                 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2527
2528         /*
2529          * These must be called before the driver is registered with
2530          * the PCI subsystem.
2531          */
2532         idr_init(&unit_table);
2533         if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2534                 printk(KERN_ERR IPATH_DRV_NAME ": idr_pre_get() failed\n");
2535                 ret = -ENOMEM;
2536                 goto bail;
2537         }
2538
2539         ret = pci_register_driver(&ipath_driver);
2540         if (ret < 0) {
2541                 printk(KERN_ERR IPATH_DRV_NAME
2542                        ": Unable to register driver: error %d\n", -ret);
2543                 goto bail_unit;
2544         }
2545
2546         ret = ipath_init_ipathfs();
2547         if (ret < 0) {
2548                 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2549                        "ipathfs: error %d\n", -ret);
2550                 goto bail_pci;
2551         }
2552
2553         goto bail;
2554
2555 bail_pci:
2556         pci_unregister_driver(&ipath_driver);
2557
2558 bail_unit:
2559         idr_destroy(&unit_table);
2560
2561 bail:
2562         return ret;
2563 }
2564
2565 static void __exit infinipath_cleanup(void)
2566 {
2567         ipath_exit_ipathfs();
2568
2569         ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2570         pci_unregister_driver(&ipath_driver);
2571
2572         idr_destroy(&unit_table);
2573 }
2574
2575 /**
2576  * ipath_reset_device - reset the chip if possible
2577  * @unit: the device to reset
2578  *
2579  * Whether or not reset is successful, we attempt to re-initialize the chip
2580  * (that is, much like a driver unload/reload).  We clear the INITTED flag
2581  * so that the various entry points will fail until we reinitialize.  For
2582  * now, we only allow this if no user ports are open that use chip resources
2583  */
2584 int ipath_reset_device(int unit)
2585 {
2586         int ret, i;
2587         struct ipath_devdata *dd = ipath_lookup(unit);
2588
2589         if (!dd) {
2590                 ret = -ENODEV;
2591                 goto bail;
2592         }
2593
2594         if (atomic_read(&dd->ipath_led_override_timer_active)) {
2595                 /* Need to stop LED timer, _then_ shut off LEDs */
2596                 del_timer_sync(&dd->ipath_led_override_timer);
2597                 atomic_set(&dd->ipath_led_override_timer_active, 0);
2598         }
2599
2600         /* Shut off LEDs after we are sure timer is not running */
2601         dd->ipath_led_override = LED_OVER_BOTH_OFF;
2602         dd->ipath_f_setextled(dd, 0, 0);
2603
2604         dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2605
2606         if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2607                 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2608                          "not initialized or not present\n", unit);
2609                 ret = -ENXIO;
2610                 goto bail;
2611         }
2612
2613         if (dd->ipath_pd)
2614                 for (i = 1; i < dd->ipath_cfgports; i++) {
2615                         if (dd->ipath_pd[i] && dd->ipath_pd[i]->port_cnt) {
2616                                 ipath_dbg("unit %u port %d is in use "
2617                                           "(PID %u cmd %s), can't reset\n",
2618                                           unit, i,
2619                                           pid_nr(dd->ipath_pd[i]->port_pid),
2620                                           dd->ipath_pd[i]->port_comm);
2621                                 ret = -EBUSY;
2622                                 goto bail;
2623                         }
2624                 }
2625
2626         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2627                 teardown_sdma(dd);
2628
2629         dd->ipath_flags &= ~IPATH_INITTED;
2630         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2631         ret = dd->ipath_f_reset(dd);
2632         if (ret == 1) {
2633                 ipath_dbg("Reinitializing unit %u after reset attempt\n",
2634                           unit);
2635                 ret = ipath_init_chip(dd, 1);
2636         } else
2637                 ret = -EAGAIN;
2638         if (ret)
2639                 ipath_dev_err(dd, "Reinitialize unit %u after "
2640                               "reset failed with %d\n", unit, ret);
2641         else
2642                 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2643                          "resetting\n", unit);
2644
2645 bail:
2646         return ret;
2647 }
2648
2649 /*
2650  * send a signal to all the processes that have the driver open
2651  * through the normal interfaces (i.e., everything other than diags
2652  * interface).  Returns number of signalled processes.
2653  */
2654 static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2655 {
2656         int i, sub, any = 0;
2657         struct pid *pid;
2658
2659         if (!dd->ipath_pd)
2660                 return 0;
2661         for (i = 1; i < dd->ipath_cfgports; i++) {
2662                 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2663                         continue;
2664                 pid = dd->ipath_pd[i]->port_pid;
2665                 if (!pid)
2666                         continue;
2667
2668                 dev_info(&dd->pcidev->dev, "context %d in use "
2669                           "(PID %u), sending signal %d\n",
2670                           i, pid_nr(pid), sig);
2671                 kill_pid(pid, sig, 1);
2672                 any++;
2673                 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2674                         pid = dd->ipath_pd[i]->port_subpid[sub];
2675                         if (!pid)
2676                                 continue;
2677                         dev_info(&dd->pcidev->dev, "sub-context "
2678                                 "%d:%d in use (PID %u), sending "
2679                                 "signal %d\n", i, sub, pid_nr(pid), sig);
2680                         kill_pid(pid, sig, 1);
2681                         any++;
2682                 }
2683         }
2684         return any;
2685 }
2686
2687 static void ipath_hol_signal_down(struct ipath_devdata *dd)
2688 {
2689         if (ipath_signal_procs(dd, SIGSTOP))
2690                 ipath_dbg("Stopped some processes\n");
2691         ipath_cancel_sends(dd, 1);
2692 }
2693
2694
2695 static void ipath_hol_signal_up(struct ipath_devdata *dd)
2696 {
2697         if (ipath_signal_procs(dd, SIGCONT))
2698                 ipath_dbg("Continued some processes\n");
2699 }
2700
2701 /*
2702  * link is down, stop any users processes, and flush pending sends
2703  * to prevent HoL blocking, then start the HoL timer that
2704  * periodically continues, then stop procs, so they can detect
2705  * link down if they want, and do something about it.
2706  * Timer may already be running, so use __mod_timer, not add_timer.
2707  */
2708 void ipath_hol_down(struct ipath_devdata *dd)
2709 {
2710         dd->ipath_hol_state = IPATH_HOL_DOWN;
2711         ipath_hol_signal_down(dd);
2712         dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2713         dd->ipath_hol_timer.expires = jiffies +
2714                 msecs_to_jiffies(ipath_hol_timeout_ms);
2715         __mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
2716 }
2717
2718 /*
2719  * link is up, continue any user processes, and ensure timer
2720  * is a nop, if running.  Let timer keep running, if set; it
2721  * will nop when it sees the link is up
2722  */
2723 void ipath_hol_up(struct ipath_devdata *dd)
2724 {
2725         ipath_hol_signal_up(dd);
2726         dd->ipath_hol_state = IPATH_HOL_UP;
2727 }
2728
2729 /*
2730  * toggle the running/not running state of user proceses
2731  * to prevent HoL blocking on chip resources, but still allow
2732  * user processes to do link down special case handling.
2733  * Should only be called via the timer
2734  */
2735 void ipath_hol_event(unsigned long opaque)
2736 {
2737         struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2738
2739         if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2740                 && dd->ipath_hol_state != IPATH_HOL_UP) {
2741                 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2742                 ipath_dbg("Stopping processes\n");
2743                 ipath_hol_signal_down(dd);
2744         } else { /* may do "extra" if also in ipath_hol_up() */
2745                 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2746                 ipath_dbg("Continuing processes\n");
2747                 ipath_hol_signal_up(dd);
2748         }
2749         if (dd->ipath_hol_state == IPATH_HOL_UP)
2750                 ipath_dbg("link's up, don't resched timer\n");
2751         else {
2752                 dd->ipath_hol_timer.expires = jiffies +
2753                         msecs_to_jiffies(ipath_hol_timeout_ms);
2754                 __mod_timer(&dd->ipath_hol_timer,
2755                         dd->ipath_hol_timer.expires);
2756         }
2757 }
2758
2759 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2760 {
2761         u64 val;
2762
2763         if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
2764                 return -1;
2765         if (dd->ipath_rx_pol_inv != new_pol_inv) {
2766                 dd->ipath_rx_pol_inv = new_pol_inv;
2767                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2768                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2769                          INFINIPATH_XGXS_RX_POL_SHIFT);
2770                 val |= ((u64)dd->ipath_rx_pol_inv) <<
2771                         INFINIPATH_XGXS_RX_POL_SHIFT;
2772                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2773         }
2774         return 0;
2775 }
2776
2777 /*
2778  * Disable and enable the armlaunch error.  Used for PIO bandwidth testing on
2779  * the 7220, which is count-based, rather than trigger-based.  Safe for the
2780  * driver check, since it's at init.   Not completely safe when used for
2781  * user-mode checking, since some error checking can be lost, but not
2782  * particularly risky, and only has problematic side-effects in the face of
2783  * very buggy user code.  There is no reference counting, but that's also
2784  * fine, given the intended use.
2785  */
2786 void ipath_enable_armlaunch(struct ipath_devdata *dd)
2787 {
2788         dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2789         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2790                 INFINIPATH_E_SPIOARMLAUNCH);
2791         dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2792         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2793                 dd->ipath_errormask);
2794 }
2795
2796 void ipath_disable_armlaunch(struct ipath_devdata *dd)
2797 {
2798         /* so don't re-enable if already set */
2799         dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2800         dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2801         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2802                 dd->ipath_errormask);
2803 }
2804
2805 module_init(infinipath_init);
2806 module_exit(infinipath_cleanup);