git.oblomov.eu Git - linux-2.6/blob - drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61     NETIF_MSG_TX_QUEUED |
  62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  79         /* required last entry */
  80         {0,}
  81 };
  82
  83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  84
  85 /* This hardware semaphore causes exclusive access to
  86  * resources shared between the NIC driver, MPI firmware,
  87  * FCOE firmware and the FC driver.
  88  */
  89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  90 {
  91         u32 sem_bits = 0;
  92
  93         switch (sem_mask) {
  94         case SEM_XGMAC0_MASK:
  95                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  96                 break;
  97         case SEM_XGMAC1_MASK:
  98                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
  99                 break;
 100         case SEM_ICB_MASK:
 101                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 102                 break;
 103         case SEM_MAC_ADDR_MASK:
 104                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 105                 break;
 106         case SEM_FLASH_MASK:
 107                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 108                 break;
 109         case SEM_PROBE_MASK:
 110                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 111                 break;
 112         case SEM_RT_IDX_MASK:
 113                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 114                 break;
 115         case SEM_PROC_REG_MASK:
 116                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 117                 break;
 118         default:
 119                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 120                 return -EINVAL;
 121         }
 122
 123         ql_write32(qdev, SEM, sem_bits | sem_mask);
 124         return !(ql_read32(qdev, SEM) & sem_bits);
 125 }
 126
 127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 128 {
 129         unsigned int wait_count = 30;
 130         do {
 131                 if (!ql_sem_trylock(qdev, sem_mask))
 132                         return 0;
 133                 udelay(100);
 134         } while (--wait_count);
 135         return -ETIMEDOUT;
 136 }
 137
 138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 139 {
 140         ql_write32(qdev, SEM, sem_mask);
 141         ql_read32(qdev, SEM);   /* flush */
 142 }
 143
 144 /* This function waits for a specific bit to come ready
 145  * in a given register.  It is used mostly by the initialize
 146  * process, but is also used in kernel thread API such as
 147  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 148  */
 149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 150 {
 151         u32 temp;
 152         int count = UDELAY_COUNT;
 153
 154         while (count) {
 155                 temp = ql_read32(qdev, reg);
 156
 157                 /* check for errors */
 158                 if (temp & err_bit) {
 159                         QPRINTK(qdev, PROBE, ALERT,
 160                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 161                                 reg, temp);
 162                         return -EIO;
 163                 } else if (temp & bit)
 164                         return 0;
 165                 udelay(UDELAY_DELAY);
 166                 count--;
 167         }
 168         QPRINTK(qdev, PROBE, ALERT,
 169                 "Timed out waiting for reg %x to come ready.\n", reg);
 170         return -ETIMEDOUT;
 171 }
 172
 173 /* The CFG register is used to download TX and RX control blocks
 174  * to the chip. This function waits for an operation to complete.
 175  */
 176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 177 {
 178         int count = UDELAY_COUNT;
 179         u32 temp;
 180
 181         while (count) {
 182                 temp = ql_read32(qdev, CFG);
 183                 if (temp & CFG_LE)
 184                         return -EIO;
 185                 if (!(temp & bit))
 186                         return 0;
 187                 udelay(UDELAY_DELAY);
 188                 count--;
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193
 194 /* Used to issue init control blocks to hw. Maps control block,
 195  * sets address, triggers download, waits for completion.
 196  */
 197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 198                  u16 q_id)
 199 {
 200         u64 map;
 201         int status = 0;
 202         int direction;
 203         u32 mask;
 204         u32 value;
 205
 206         direction =
 207             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 208             PCI_DMA_FROMDEVICE;
 209
 210         map = pci_map_single(qdev->pdev, ptr, size, direction);
 211         if (pci_dma_mapping_error(qdev->pdev, map)) {
 212                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 213                 return -ENOMEM;
 214         }
 215
 216         status = ql_wait_cfg(qdev, bit);
 217         if (status) {
 218                 QPRINTK(qdev, IFUP, ERR,
 219                         "Timed out waiting for CFG to come ready.\n");
 220                 goto exit;
 221         }
 222
 223         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 224         if (status)
 225                 goto exit;
 226         ql_write32(qdev, ICB_L, (u32) map);
 227         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 228         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 229
 230         mask = CFG_Q_MASK | (bit << 16);
 231         value = bit | (q_id << CFG_Q_SHIFT);
 232         ql_write32(qdev, CFG, (mask | value));
 233
 234         /*
 235          * Wait for the bit to clear after signaling hw.
 236          */
 237         status = ql_wait_cfg(qdev, bit);
 238 exit:
 239         pci_unmap_single(qdev->pdev, map, size, direction);
 240         return status;
 241 }
 242
 243 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 245                         u32 *value)
 246 {
 247         u32 offset = 0;
 248         int status;
 249
 250         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 251         if (status)
 252                 return status;
 253         switch (type) {
 254         case MAC_ADDR_TYPE_MULTI_MAC:
 255         case MAC_ADDR_TYPE_CAM_MAC:
 256                 {
 257                         status =
 258                             ql_wait_reg_rdy(qdev,
 259                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 260                         if (status)
 261                                 goto exit;
 262                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 263                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 264                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 265                         status =
 266                             ql_wait_reg_rdy(qdev,
 267                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 268                         if (status)
 269                                 goto exit;
 270                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 271                         status =
 272                             ql_wait_reg_rdy(qdev,
 273                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 274                         if (status)
 275                                 goto exit;
 276                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 277                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 278                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 279                         status =
 280                             ql_wait_reg_rdy(qdev,
 281                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 282                         if (status)
 283                                 goto exit;
 284                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 285                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 286                                 status =
 287                                     ql_wait_reg_rdy(qdev,
 288                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 289                                 if (status)
 290                                         goto exit;
 291                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 292                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 293                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 294                                 status =
 295                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 296                                                     MAC_ADDR_MR, 0);
 297                                 if (status)
 298                                         goto exit;
 299                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 300                         }
 301                         break;
 302                 }
 303         case MAC_ADDR_TYPE_VLAN:
 304         case MAC_ADDR_TYPE_MULTI_FLTR:
 305         default:
 306                 QPRINTK(qdev, IFUP, CRIT,
 307                         "Address type %d not yet supported.\n", type);
 308                 status = -EPERM;
 309         }
 310 exit:
 311         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 312         return status;
 313 }
 314
 315 /* Set up a MAC, multicast or VLAN address for the
 316  * inbound frame matching.
 317  */
 318 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 319                                u16 index)
 320 {
 321         u32 offset = 0;
 322         int status = 0;
 323
 324         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 325         if (status)
 326                 return status;
 327         switch (type) {
 328         case MAC_ADDR_TYPE_MULTI_MAC:
 329         case MAC_ADDR_TYPE_CAM_MAC:
 330                 {
 331                         u32 cam_output;
 332                         u32 upper = (addr[0] << 8) | addr[1];
 333                         u32 lower =
 334                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 335                             (addr[5]);
 336
 337                         QPRINTK(qdev, IFUP, INFO,
 338                                 "Adding %s address %pM"
 339                                 " at index %d in the CAM.\n",
 340                                 ((type ==
 341                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 342                                  "UNICAST"), addr, index);
 343
 344                         status =
 345                             ql_wait_reg_rdy(qdev,
 346                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 347                         if (status)
 348                                 goto exit;
 349                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 350                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 351                                    type);       /* type */
 352                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 353                         status =
 354                             ql_wait_reg_rdy(qdev,
 355                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 356                         if (status)
 357                                 goto exit;
 358                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 359                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 360                                    type);       /* type */
 361                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 362                         status =
 363                             ql_wait_reg_rdy(qdev,
 364                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 365                         if (status)
 366                                 goto exit;
 367                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 368                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 369                                    type);       /* type */
 370                         /* This field should also include the queue id
 371                            and possibly the function id.  Right now we hardcode
 372                            the route field to NIC core.
 373                          */
 374                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 375                                 cam_output = (CAM_OUT_ROUTE_NIC |
 376                                               (qdev->
 377                                                func << CAM_OUT_FUNC_SHIFT) |
 378                                               (qdev->
 379                                                rss_ring_first_cq_id <<
 380                                                CAM_OUT_CQ_ID_SHIFT));
 381                                 if (qdev->vlgrp)
 382                                         cam_output |= CAM_OUT_RV;
 383                                 /* route to NIC core */
 384                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 385                         }
 386                         break;
 387                 }
 388         case MAC_ADDR_TYPE_VLAN:
 389                 {
 390                         u32 enable_bit = *((u32 *) &addr[0]);
 391                         /* For VLAN, the addr actually holds a bit that
 392                          * either enables or disables the vlan id we are
 393                          * addressing. It's either MAC_ADDR_E on or off.
 394                          * That's bit-27 we're talking about.
 395                          */
 396                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 397                                 (enable_bit ? "Adding" : "Removing"),
 398                                 index, (enable_bit ? "to" : "from"));
 399
 400                         status =
 401                             ql_wait_reg_rdy(qdev,
 402                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 403                         if (status)
 404                                 goto exit;
 405                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 406                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 407                                    type |       /* type */
 408                                    enable_bit); /* enable/disable */
 409                         break;
 410                 }
 411         case MAC_ADDR_TYPE_MULTI_FLTR:
 412         default:
 413                 QPRINTK(qdev, IFUP, CRIT,
 414                         "Address type %d not yet supported.\n", type);
 415                 status = -EPERM;
 416         }
 417 exit:
 418         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 419         return status;
 420 }
 421
 422 /* Get a specific frame routing value from the CAM.
 423  * Used for debug and reg dump.
 424  */
 425 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 426 {
 427         int status = 0;
 428
 429         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 430         if (status)
 431                 goto exit;
 432
 433         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 434         if (status)
 435                 goto exit;
 436
 437         ql_write32(qdev, RT_IDX,
 438                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 439         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 440         if (status)
 441                 goto exit;
 442         *value = ql_read32(qdev, RT_DATA);
 443 exit:
 444         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 445         return status;
 446 }
 447
 448 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 449  * to route different frame types to various inbound queues.  We send broadcast/
 450  * multicast/error frames to the default queue for slow handling,
 451  * and CAM hit/RSS frames to the fast handling queues.
 452  */
 453 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 454                               int enable)
 455 {
 456         int status;
 457         u32 value = 0;
 458
 459         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 460         if (status)
 461                 return status;
 462
 463         QPRINTK(qdev, IFUP, DEBUG,
 464                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 465                 (enable ? "Adding" : "Removing"),
 466                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 467                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 468                 ((index ==
 469                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 470                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 471                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 472                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 473                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 474                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 475                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 476                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 477                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 478                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 479                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 480                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 481                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 482                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 483                 (enable ? "to" : "from"));
 484
 485         switch (mask) {
 486         case RT_IDX_CAM_HIT:
 487                 {
 488                         value = RT_IDX_DST_CAM_Q |      /* dest */
 489                             RT_IDX_TYPE_NICQ |  /* type */
 490                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 491                         break;
 492                 }
 493         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 494                 {
 495                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 496                             RT_IDX_TYPE_NICQ |  /* type */
 497                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 498                         break;
 499                 }
 500         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 501                 {
 502                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 503                             RT_IDX_TYPE_NICQ |  /* type */
 504                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 505                         break;
 506                 }
 507         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 508                 {
 509                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 510                             RT_IDX_TYPE_NICQ |  /* type */
 511                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 512                         break;
 513                 }
 514         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 515                 {
 516                         value = RT_IDX_DST_CAM_Q |      /* dest */
 517                             RT_IDX_TYPE_NICQ |  /* type */
 518                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 519                         break;
 520                 }
 521         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 522                 {
 523                         value = RT_IDX_DST_CAM_Q |      /* dest */
 524                             RT_IDX_TYPE_NICQ |  /* type */
 525                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 526                         break;
 527                 }
 528         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 529                 {
 530                         value = RT_IDX_DST_RSS |        /* dest */
 531                             RT_IDX_TYPE_NICQ |  /* type */
 532                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 533                         break;
 534                 }
 535         case 0:         /* Clear the E-bit on an entry. */
 536                 {
 537                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 538                             RT_IDX_TYPE_NICQ |  /* type */
 539                             (index << RT_IDX_IDX_SHIFT);/* index */
 540                         break;
 541                 }
 542         default:
 543                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 544                         mask);
 545                 status = -EPERM;
 546                 goto exit;
 547         }
 548
 549         if (value) {
 550                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 551                 if (status)
 552                         goto exit;
 553                 value |= (enable ? RT_IDX_E : 0);
 554                 ql_write32(qdev, RT_IDX, value);
 555                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 556         }
 557 exit:
 558         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 559         return status;
 560 }
 561
 562 static void ql_enable_interrupts(struct ql_adapter *qdev)
 563 {
 564         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 565 }
 566
 567 static void ql_disable_interrupts(struct ql_adapter *qdev)
 568 {
 569         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 570 }
 571
 572 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 573  * Otherwise, we may have multiple outstanding workers and don't want to
 574  * enable until the last one finishes. In this case, the irq_cnt gets
 575  * incremented everytime we queue a worker and decremented everytime
 576  * a worker finishes.  Once it hits zero we enable the interrupt.
 577  */
 578 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 579 {
 580         u32 var = 0;
 581         unsigned long hw_flags = 0;
 582         struct intr_context *ctx = qdev->intr_context + intr;
 583
 584         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 585                 /* Always enable if we're MSIX multi interrupts and
 586                  * it's not the default (zeroeth) interrupt.
 587                  */
 588                 ql_write32(qdev, INTR_EN,
 589                            ctx->intr_en_mask);
 590                 var = ql_read32(qdev, STS);
 591                 return var;
 592         }
 593
 594         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 595         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 596                 ql_write32(qdev, INTR_EN,
 597                            ctx->intr_en_mask);
 598                 var = ql_read32(qdev, STS);
 599         }
 600         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 601         return var;
 602 }
 603
 604 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 605 {
 606         u32 var = 0;
 607         unsigned long hw_flags;
 608         struct intr_context *ctx;
 609
 610         /* HW disables for us if we're MSIX multi interrupts and
 611          * it's not the default (zeroeth) interrupt.
 612          */
 613         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 614                 return 0;
 615
 616         ctx = qdev->intr_context + intr;
 617         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 618         if (!atomic_read(&ctx->irq_cnt)) {
 619                 ql_write32(qdev, INTR_EN,
 620                 ctx->intr_dis_mask);
 621                 var = ql_read32(qdev, STS);
 622         }
 623         atomic_inc(&ctx->irq_cnt);
 624         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 625         return var;
 626 }
 627
 628 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 629 {
 630         int i;
 631         for (i = 0; i < qdev->intr_count; i++) {
 632                 /* The enable call does a atomic_dec_and_test
 633                  * and enables only if the result is zero.
 634                  * So we precharge it here.
 635                  */
 636                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 637                         i == 0))
 638                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 639                 ql_enable_completion_interrupt(qdev, i);
 640         }
 641
 642 }
 643
 644 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 645 {
 646         int status = 0;
 647         /* wait for reg to come ready */
 648         status = ql_wait_reg_rdy(qdev,
 649                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 650         if (status)
 651                 goto exit;
 652         /* set up for reg read */
 653         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 654         /* wait for reg to come ready */
 655         status = ql_wait_reg_rdy(qdev,
 656                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 657         if (status)
 658                 goto exit;
 659          /* This data is stored on flash as an array of
 660          * __le32.  Since ql_read32() returns cpu endian
 661          * we need to swap it back.
 662          */
 663         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 664 exit:
 665         return status;
 666 }
 667
 668 static int ql_get_flash_params(struct ql_adapter *qdev)
 669 {
 670         int i;
 671         int status;
 672         __le32 *p = (__le32 *)&qdev->flash;
 673         u32 offset = 0;
 674
 675         /* Second function's parameters follow the first
 676          * function's.
 677          */
 678         if (qdev->func)
 679                 offset = sizeof(qdev->flash) / sizeof(u32);
 680
 681         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 682                 return -ETIMEDOUT;
 683
 684         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 685                 status = ql_read_flash_word(qdev, i+offset, p);
 686                 if (status) {
 687                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 688                         goto exit;
 689                 }
 690
 691         }
 692 exit:
 693         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 694         return status;
 695 }
 696
 697 /* xgmac register are located behind the xgmac_addr and xgmac_data
 698  * register pair.  Each read/write requires us to wait for the ready
 699  * bit before reading/writing the data.
 700  */
 701 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 702 {
 703         int status;
 704         /* wait for reg to come ready */
 705         status = ql_wait_reg_rdy(qdev,
 706                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 707         if (status)
 708                 return status;
 709         /* write the data to the data reg */
 710         ql_write32(qdev, XGMAC_DATA, data);
 711         /* trigger the write */
 712         ql_write32(qdev, XGMAC_ADDR, reg);
 713         return status;
 714 }
 715
 716 /* xgmac register are located behind the xgmac_addr and xgmac_data
 717  * register pair.  Each read/write requires us to wait for the ready
 718  * bit before reading/writing the data.
 719  */
 720 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 721 {
 722         int status = 0;
 723         /* wait for reg to come ready */
 724         status = ql_wait_reg_rdy(qdev,
 725                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 726         if (status)
 727                 goto exit;
 728         /* set up for reg read */
 729         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 730         /* wait for reg to come ready */
 731         status = ql_wait_reg_rdy(qdev,
 732                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 733         if (status)
 734                 goto exit;
 735         /* get the data */
 736         *data = ql_read32(qdev, XGMAC_DATA);
 737 exit:
 738         return status;
 739 }
 740
 741 /* This is used for reading the 64-bit statistics regs. */
 742 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 743 {
 744         int status = 0;
 745         u32 hi = 0;
 746         u32 lo = 0;
 747
 748         status = ql_read_xgmac_reg(qdev, reg, &lo);
 749         if (status)
 750                 goto exit;
 751
 752         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 753         if (status)
 754                 goto exit;
 755
 756         *data = (u64) lo | ((u64) hi << 32);
 757
 758 exit:
 759         return status;
 760 }
 761
 762 /* Take the MAC Core out of reset.
 763  * Enable statistics counting.
 764  * Take the transmitter/receiver out of reset.
 765  * This functionality may be done in the MPI firmware at a
 766  * later date.
 767  */
 768 static int ql_port_initialize(struct ql_adapter *qdev)
 769 {
 770         int status = 0;
 771         u32 data;
 772
 773         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 774                 /* Another function has the semaphore, so
 775                  * wait for the port init bit to come ready.
 776                  */
 777                 QPRINTK(qdev, LINK, INFO,
 778                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 779                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 780                 if (status) {
 781                         QPRINTK(qdev, LINK, CRIT,
 782                                 "Port initialize timed out.\n");
 783                 }
 784                 return status;
 785         }
 786
 787         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 788         /* Set the core reset. */
 789         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 790         if (status)
 791                 goto end;
 792         data |= GLOBAL_CFG_RESET;
 793         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 794         if (status)
 795                 goto end;
 796
 797         /* Clear the core reset and turn on jumbo for receiver. */
 798         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 799         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 800         data |= GLOBAL_CFG_TX_STAT_EN;
 801         data |= GLOBAL_CFG_RX_STAT_EN;
 802         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 803         if (status)
 804                 goto end;
 805
 806         /* Enable transmitter, and clear it's reset. */
 807         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 808         if (status)
 809                 goto end;
 810         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 811         data |= TX_CFG_EN;      /* Enable the transmitter. */
 812         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 813         if (status)
 814                 goto end;
 815
 816         /* Enable receiver and clear it's reset. */
 817         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 818         if (status)
 819                 goto end;
 820         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 821         data |= RX_CFG_EN;      /* Enable the receiver. */
 822         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 823         if (status)
 824                 goto end;
 825
 826         /* Turn on jumbo. */
 827         status =
 828             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 829         if (status)
 830                 goto end;
 831         status =
 832             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 833         if (status)
 834                 goto end;
 835
 836         /* Signal to the world that the port is enabled.        */
 837         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 838 end:
 839         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 840         return status;
 841 }
 842
 843 /* Get the next large buffer. */
 844 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 845 {
 846         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 847         rx_ring->lbq_curr_idx++;
 848         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 849                 rx_ring->lbq_curr_idx = 0;
 850         rx_ring->lbq_free_cnt++;
 851         return lbq_desc;
 852 }
 853
 854 /* Get the next small buffer. */
 855 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 856 {
 857         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 858         rx_ring->sbq_curr_idx++;
 859         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 860                 rx_ring->sbq_curr_idx = 0;
 861         rx_ring->sbq_free_cnt++;
 862         return sbq_desc;
 863 }
 864
 865 /* Update an rx ring index. */
 866 static void ql_update_cq(struct rx_ring *rx_ring)
 867 {
 868         rx_ring->cnsmr_idx++;
 869         rx_ring->curr_entry++;
 870         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 871                 rx_ring->cnsmr_idx = 0;
 872                 rx_ring->curr_entry = rx_ring->cq_base;
 873         }
 874 }
 875
 876 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 877 {
 878         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 879 }
 880
 881 /* Process (refill) a large buffer queue. */
 882 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 883 {
 884         int clean_idx = rx_ring->lbq_clean_idx;
 885         struct bq_desc *lbq_desc;
 886         u64 map;
 887         int i;
 888
 889         while (rx_ring->lbq_free_cnt > 16) {
 890                 for (i = 0; i < 16; i++) {
 891                         QPRINTK(qdev, RX_STATUS, DEBUG,
 892                                 "lbq: try cleaning clean_idx = %d.\n",
 893                                 clean_idx);
 894                         lbq_desc = &rx_ring->lbq[clean_idx];
 895                         if (lbq_desc->p.lbq_page == NULL) {
 896                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 897                                         "lbq: getting new page for index %d.\n",
 898                                         lbq_desc->index);
 899                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 900                                 if (lbq_desc->p.lbq_page == NULL) {
 901                                         rx_ring->lbq_clean_idx = clean_idx;
 902                                         QPRINTK(qdev, RX_STATUS, ERR,
 903                                                 "Couldn't get a page.\n");
 904                                         return;
 905                                 }
 906                                 map = pci_map_page(qdev->pdev,
 907                                                    lbq_desc->p.lbq_page,
 908                                                    0, PAGE_SIZE,
 909                                                    PCI_DMA_FROMDEVICE);
 910                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 911                                         rx_ring->lbq_clean_idx = clean_idx;
 912                                         put_page(lbq_desc->p.lbq_page);
 913                                         lbq_desc->p.lbq_page = NULL;
 914                                         QPRINTK(qdev, RX_STATUS, ERR,
 915                                                 "PCI mapping failed.\n");
 916                                         return;
 917                                 }
 918                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 919                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 920                                 *lbq_desc->addr = cpu_to_le64(map);
 921                         }
 922                         clean_idx++;
 923                         if (clean_idx == rx_ring->lbq_len)
 924                                 clean_idx = 0;
 925                 }
 926
 927                 rx_ring->lbq_clean_idx = clean_idx;
 928                 rx_ring->lbq_prod_idx += 16;
 929                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 930                         rx_ring->lbq_prod_idx = 0;
 931                 QPRINTK(qdev, RX_STATUS, DEBUG,
 932                         "lbq: updating prod idx = %d.\n",
 933                         rx_ring->lbq_prod_idx);
 934                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 935                                 rx_ring->lbq_prod_idx_db_reg);
 936                 rx_ring->lbq_free_cnt -= 16;
 937         }
 938 }
 939
 940 /* Process (refill) a small buffer queue. */
 941 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 942 {
 943         int clean_idx = rx_ring->sbq_clean_idx;
 944         struct bq_desc *sbq_desc;
 945         u64 map;
 946         int i;
 947
 948         while (rx_ring->sbq_free_cnt > 16) {
 949                 for (i = 0; i < 16; i++) {
 950                         sbq_desc = &rx_ring->sbq[clean_idx];
 951                         QPRINTK(qdev, RX_STATUS, DEBUG,
 952                                 "sbq: try cleaning clean_idx = %d.\n",
 953                                 clean_idx);
 954                         if (sbq_desc->p.skb == NULL) {
 955                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 956                                         "sbq: getting new skb for index %d.\n",
 957                                         sbq_desc->index);
 958                                 sbq_desc->p.skb =
 959                                     netdev_alloc_skb(qdev->ndev,
 960                                                      rx_ring->sbq_buf_size);
 961                                 if (sbq_desc->p.skb == NULL) {
 962                                         QPRINTK(qdev, PROBE, ERR,
 963                                                 "Couldn't get an skb.\n");
 964                                         rx_ring->sbq_clean_idx = clean_idx;
 965                                         return;
 966                                 }
 967                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 968                                 map = pci_map_single(qdev->pdev,
 969                                                      sbq_desc->p.skb->data,
 970                                                      rx_ring->sbq_buf_size /
 971                                                      2, PCI_DMA_FROMDEVICE);
 972                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 973                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
 974                                         rx_ring->sbq_clean_idx = clean_idx;
 975                                         dev_kfree_skb_any(sbq_desc->p.skb);
 976                                         sbq_desc->p.skb = NULL;
 977                                         return;
 978                                 }
 979                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 980                                 pci_unmap_len_set(sbq_desc, maplen,
 981                                                   rx_ring->sbq_buf_size / 2);
 982                                 *sbq_desc->addr = cpu_to_le64(map);
 983                         }
 984
 985                         clean_idx++;
 986                         if (clean_idx == rx_ring->sbq_len)
 987                                 clean_idx = 0;
 988                 }
 989                 rx_ring->sbq_clean_idx = clean_idx;
 990                 rx_ring->sbq_prod_idx += 16;
 991                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 992                         rx_ring->sbq_prod_idx = 0;
 993                 QPRINTK(qdev, RX_STATUS, DEBUG,
 994                         "sbq: updating prod idx = %d.\n",
 995                         rx_ring->sbq_prod_idx);
 996                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 997                                 rx_ring->sbq_prod_idx_db_reg);
 998
 999                 rx_ring->sbq_free_cnt -= 16;
1000         }
1001 }
1002
1003 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1004                                     struct rx_ring *rx_ring)
1005 {
1006         ql_update_sbq(qdev, rx_ring);
1007         ql_update_lbq(qdev, rx_ring);
1008 }
1009
1010 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1011  * fails at some stage, or from the interrupt when a tx completes.
1012  */
1013 static void ql_unmap_send(struct ql_adapter *qdev,
1014                           struct tx_ring_desc *tx_ring_desc, int mapped)
1015 {
1016         int i;
1017         for (i = 0; i < mapped; i++) {
1018                 if (i == 0 || (i == 7 && mapped > 7)) {
1019                         /*
1020                          * Unmap the skb->data area, or the
1021                          * external sglist (AKA the Outbound
1022                          * Address List (OAL)).
1023                          * If its the zeroeth element, then it's
1024                          * the skb->data area.  If it's the 7th
1025                          * element and there is more than 6 frags,
1026                          * then its an OAL.
1027                          */
1028                         if (i == 7) {
1029                                 QPRINTK(qdev, TX_DONE, DEBUG,
1030                                         "unmapping OAL area.\n");
1031                         }
1032                         pci_unmap_single(qdev->pdev,
1033                                          pci_unmap_addr(&tx_ring_desc->map[i],
1034                                                         mapaddr),
1035                                          pci_unmap_len(&tx_ring_desc->map[i],
1036                                                        maplen),
1037                                          PCI_DMA_TODEVICE);
1038                 } else {
1039                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1040                                 i);
1041                         pci_unmap_page(qdev->pdev,
1042                                        pci_unmap_addr(&tx_ring_desc->map[i],
1043                                                       mapaddr),
1044                                        pci_unmap_len(&tx_ring_desc->map[i],
1045                                                      maplen), PCI_DMA_TODEVICE);
1046                 }
1047         }
1048
1049 }
1050
1051 /* Map the buffers for this transmit.  This will return
1052  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1053  */
1054 static int ql_map_send(struct ql_adapter *qdev,
1055                        struct ob_mac_iocb_req *mac_iocb_ptr,
1056                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1057 {
1058         int len = skb_headlen(skb);
1059         dma_addr_t map;
1060         int frag_idx, err, map_idx = 0;
1061         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1062         int frag_cnt = skb_shinfo(skb)->nr_frags;
1063
1064         if (frag_cnt) {
1065                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1066         }
1067         /*
1068          * Map the skb buffer first.
1069          */
1070         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1071
1072         err = pci_dma_mapping_error(qdev->pdev, map);
1073         if (err) {
1074                 QPRINTK(qdev, TX_QUEUED, ERR,
1075                         "PCI mapping failed with error: %d\n", err);
1076
1077                 return NETDEV_TX_BUSY;
1078         }
1079
1080         tbd->len = cpu_to_le32(len);
1081         tbd->addr = cpu_to_le64(map);
1082         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1083         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1084         map_idx++;
1085
1086         /*
1087          * This loop fills the remainder of the 8 address descriptors
1088          * in the IOCB.  If there are more than 7 fragments, then the
1089          * eighth address desc will point to an external list (OAL).
1090          * When this happens, the remainder of the frags will be stored
1091          * in this list.
1092          */
1093         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1094                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1095                 tbd++;
1096                 if (frag_idx == 6 && frag_cnt > 7) {
1097                         /* Let's tack on an sglist.
1098                          * Our control block will now
1099                          * look like this:
1100                          * iocb->seg[0] = skb->data
1101                          * iocb->seg[1] = frag[0]
1102                          * iocb->seg[2] = frag[1]
1103                          * iocb->seg[3] = frag[2]
1104                          * iocb->seg[4] = frag[3]
1105                          * iocb->seg[5] = frag[4]
1106                          * iocb->seg[6] = frag[5]
1107                          * iocb->seg[7] = ptr to OAL (external sglist)
1108                          * oal->seg[0] = frag[6]
1109                          * oal->seg[1] = frag[7]
1110                          * oal->seg[2] = frag[8]
1111                          * oal->seg[3] = frag[9]
1112                          * oal->seg[4] = frag[10]
1113                          *      etc...
1114                          */
1115                         /* Tack on the OAL in the eighth segment of IOCB. */
1116                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1117                                              sizeof(struct oal),
1118                                              PCI_DMA_TODEVICE);
1119                         err = pci_dma_mapping_error(qdev->pdev, map);
1120                         if (err) {
1121                                 QPRINTK(qdev, TX_QUEUED, ERR,
1122                                         "PCI mapping outbound address list with error: %d\n",
1123                                         err);
1124                                 goto map_error;
1125                         }
1126
1127                         tbd->addr = cpu_to_le64(map);
1128                         /*
1129                          * The length is the number of fragments
1130                          * that remain to be mapped times the length
1131                          * of our sglist (OAL).
1132                          */
1133                         tbd->len =
1134                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1135                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1136                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1137                                            map);
1138                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1139                                           sizeof(struct oal));
1140                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1141                         map_idx++;
1142                 }
1143
1144                 map =
1145                     pci_map_page(qdev->pdev, frag->page,
1146                                  frag->page_offset, frag->size,
1147                                  PCI_DMA_TODEVICE);
1148
1149                 err = pci_dma_mapping_error(qdev->pdev, map);
1150                 if (err) {
1151                         QPRINTK(qdev, TX_QUEUED, ERR,
1152                                 "PCI mapping frags failed with error: %d.\n",
1153                                 err);
1154                         goto map_error;
1155                 }
1156
1157                 tbd->addr = cpu_to_le64(map);
1158                 tbd->len = cpu_to_le32(frag->size);
1159                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1160                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1161                                   frag->size);
1162
1163         }
1164         /* Save the number of segments we've mapped. */
1165         tx_ring_desc->map_cnt = map_idx;
1166         /* Terminate the last segment. */
1167         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1168         return NETDEV_TX_OK;
1169
1170 map_error:
1171         /*
1172          * If the first frag mapping failed, then i will be zero.
1173          * This causes the unmap of the skb->data area.  Otherwise
1174          * we pass in the number of frags that mapped successfully
1175          * so they can be umapped.
1176          */
1177         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1178         return NETDEV_TX_BUSY;
1179 }
1180
1181 static void ql_realign_skb(struct sk_buff *skb, int len)
1182 {
1183         void *temp_addr = skb->data;
1184
1185         /* Undo the skb_reserve(skb,32) we did before
1186          * giving to hardware, and realign data on
1187          * a 2-byte boundary.
1188          */
1189         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1190         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1191         skb_copy_to_linear_data(skb, temp_addr,
1192                 (unsigned int)len);
1193 }
1194
1195 /*
1196  * This function builds an skb for the given inbound
1197  * completion.  It will be rewritten for readability in the near
1198  * future, but for not it works well.
1199  */
1200 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1201                                        struct rx_ring *rx_ring,
1202                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1203 {
1204         struct bq_desc *lbq_desc;
1205         struct bq_desc *sbq_desc;
1206         struct sk_buff *skb = NULL;
1207         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1208        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1209
1210         /*
1211          * Handle the header buffer if present.
1212          */
1213         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1214             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1215                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1216                 /*
1217                  * Headers fit nicely into a small buffer.
1218                  */
1219                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1220                 pci_unmap_single(qdev->pdev,
1221                                 pci_unmap_addr(sbq_desc, mapaddr),
1222                                 pci_unmap_len(sbq_desc, maplen),
1223                                 PCI_DMA_FROMDEVICE);
1224                 skb = sbq_desc->p.skb;
1225                 ql_realign_skb(skb, hdr_len);
1226                 skb_put(skb, hdr_len);
1227                 sbq_desc->p.skb = NULL;
1228         }
1229
1230         /*
1231          * Handle the data buffer(s).
1232          */
1233         if (unlikely(!length)) {        /* Is there data too? */
1234                 QPRINTK(qdev, RX_STATUS, DEBUG,
1235                         "No Data buffer in this packet.\n");
1236                 return skb;
1237         }
1238
1239         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1240                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1241                         QPRINTK(qdev, RX_STATUS, DEBUG,
1242                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1243                         /*
1244                          * Data is less than small buffer size so it's
1245                          * stuffed in a small buffer.
1246                          * For this case we append the data
1247                          * from the "data" small buffer to the "header" small
1248                          * buffer.
1249                          */
1250                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1251                         pci_dma_sync_single_for_cpu(qdev->pdev,
1252                                                     pci_unmap_addr
1253                                                     (sbq_desc, mapaddr),
1254                                                     pci_unmap_len
1255                                                     (sbq_desc, maplen),
1256                                                     PCI_DMA_FROMDEVICE);
1257                         memcpy(skb_put(skb, length),
1258                                sbq_desc->p.skb->data, length);
1259                         pci_dma_sync_single_for_device(qdev->pdev,
1260                                                        pci_unmap_addr
1261                                                        (sbq_desc,
1262                                                         mapaddr),
1263                                                        pci_unmap_len
1264                                                        (sbq_desc,
1265                                                         maplen),
1266                                                        PCI_DMA_FROMDEVICE);
1267                 } else {
1268                         QPRINTK(qdev, RX_STATUS, DEBUG,
1269                                 "%d bytes in a single small buffer.\n", length);
1270                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1271                         skb = sbq_desc->p.skb;
1272                         ql_realign_skb(skb, length);
1273                         skb_put(skb, length);
1274                         pci_unmap_single(qdev->pdev,
1275                                          pci_unmap_addr(sbq_desc,
1276                                                         mapaddr),
1277                                          pci_unmap_len(sbq_desc,
1278                                                        maplen),
1279                                          PCI_DMA_FROMDEVICE);
1280                         sbq_desc->p.skb = NULL;
1281                 }
1282         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1283                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1284                         QPRINTK(qdev, RX_STATUS, DEBUG,
1285                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1286                         /*
1287                          * The data is in a single large buffer.  We
1288                          * chain it to the header buffer's skb and let
1289                          * it rip.
1290                          */
1291                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1292                         pci_unmap_page(qdev->pdev,
1293                                        pci_unmap_addr(lbq_desc,
1294                                                       mapaddr),
1295                                        pci_unmap_len(lbq_desc, maplen),
1296                                        PCI_DMA_FROMDEVICE);
1297                         QPRINTK(qdev, RX_STATUS, DEBUG,
1298                                 "Chaining page to skb.\n");
1299                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1300                                            0, length);
1301                         skb->len += length;
1302                         skb->data_len += length;
1303                         skb->truesize += length;
1304                         lbq_desc->p.lbq_page = NULL;
1305                 } else {
1306                         /*
1307                          * The headers and data are in a single large buffer. We
1308                          * copy it to a new skb and let it go. This can happen with
1309                          * jumbo mtu on a non-TCP/UDP frame.
1310                          */
1311                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1312                         skb = netdev_alloc_skb(qdev->ndev, length);
1313                         if (skb == NULL) {
1314                                 QPRINTK(qdev, PROBE, DEBUG,
1315                                         "No skb available, drop the packet.\n");
1316                                 return NULL;
1317                         }
1318                         pci_unmap_page(qdev->pdev,
1319                                        pci_unmap_addr(lbq_desc,
1320                                                       mapaddr),
1321                                        pci_unmap_len(lbq_desc, maplen),
1322                                        PCI_DMA_FROMDEVICE);
1323                         skb_reserve(skb, NET_IP_ALIGN);
1324                         QPRINTK(qdev, RX_STATUS, DEBUG,
1325                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1326                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1327                                            0, length);
1328                         skb->len += length;
1329                         skb->data_len += length;
1330                         skb->truesize += length;
1331                         length -= length;
1332                         lbq_desc->p.lbq_page = NULL;
1333                         __pskb_pull_tail(skb,
1334                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1335                                 VLAN_ETH_HLEN : ETH_HLEN);
1336                 }
1337         } else {
1338                 /*
1339                  * The data is in a chain of large buffers
1340                  * pointed to by a small buffer.  We loop
1341                  * thru and chain them to the our small header
1342                  * buffer's skb.
1343                  * frags:  There are 18 max frags and our small
1344                  *         buffer will hold 32 of them. The thing is,
1345                  *         we'll use 3 max for our 9000 byte jumbo
1346                  *         frames.  If the MTU goes up we could
1347                  *          eventually be in trouble.
1348                  */
1349                 int size, offset, i = 0;
1350                 __le64 *bq, bq_array[8];
1351                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1352                 pci_unmap_single(qdev->pdev,
1353                                  pci_unmap_addr(sbq_desc, mapaddr),
1354                                  pci_unmap_len(sbq_desc, maplen),
1355                                  PCI_DMA_FROMDEVICE);
1356                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1357                         /*
1358                          * This is an non TCP/UDP IP frame, so
1359                          * the headers aren't split into a small
1360                          * buffer.  We have to use the small buffer
1361                          * that contains our sg list as our skb to
1362                          * send upstairs. Copy the sg list here to
1363                          * a local buffer and use it to find the
1364                          * pages to chain.
1365                          */
1366                         QPRINTK(qdev, RX_STATUS, DEBUG,
1367                                 "%d bytes of headers & data in chain of large.\n", length);
1368                         skb = sbq_desc->p.skb;
1369                         bq = &bq_array[0];
1370                         memcpy(bq, skb->data, sizeof(bq_array));
1371                         sbq_desc->p.skb = NULL;
1372                         skb_reserve(skb, NET_IP_ALIGN);
1373                 } else {
1374                         QPRINTK(qdev, RX_STATUS, DEBUG,
1375                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1376                         bq = (__le64 *)sbq_desc->p.skb->data;
1377                 }
1378                 while (length > 0) {
1379                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1380                         pci_unmap_page(qdev->pdev,
1381                                        pci_unmap_addr(lbq_desc,
1382                                                       mapaddr),
1383                                        pci_unmap_len(lbq_desc,
1384                                                      maplen),
1385                                        PCI_DMA_FROMDEVICE);
1386                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1387                         offset = 0;
1388
1389                         QPRINTK(qdev, RX_STATUS, DEBUG,
1390                                 "Adding page %d to skb for %d bytes.\n",
1391                                 i, size);
1392                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1393                                            offset, size);
1394                         skb->len += size;
1395                         skb->data_len += size;
1396                         skb->truesize += size;
1397                         length -= size;
1398                         lbq_desc->p.lbq_page = NULL;
1399                         bq++;
1400                         i++;
1401                 }
1402                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1403                                 VLAN_ETH_HLEN : ETH_HLEN);
1404         }
1405         return skb;
1406 }
1407
1408 /* Process an inbound completion from an rx ring. */
1409 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1410                                    struct rx_ring *rx_ring,
1411                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1412 {
1413         struct net_device *ndev = qdev->ndev;
1414         struct sk_buff *skb = NULL;
1415
1416         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1417
1418         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1419         if (unlikely(!skb)) {
1420                 QPRINTK(qdev, RX_STATUS, DEBUG,
1421                         "No skb available, drop packet.\n");
1422                 return;
1423         }
1424
1425         prefetch(skb->data);
1426         skb->dev = ndev;
1427         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1428                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1429                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1430                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1431                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1432                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1433                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1434                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1435         }
1436         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1437                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1438         }
1439
1440         skb->protocol = eth_type_trans(skb, ndev);
1441         skb->ip_summed = CHECKSUM_NONE;
1442
1443         /* If rx checksum is on, and there are no
1444          * csum or frame errors.
1445          */
1446         if (qdev->rx_csum &&
1447                 !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
1448                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1449                 /* TCP frame. */
1450                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1451                         QPRINTK(qdev, RX_STATUS, DEBUG,
1452                                         "TCP checksum done!\n");
1453                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1454                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1455                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1456                 /* Unfragmented ipv4 UDP frame. */
1457                         struct iphdr *iph = (struct iphdr *) skb->data;
1458                         if (!(iph->frag_off &
1459                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1460                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1461                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1462                                                 "TCP checksum done!\n");
1463                         }
1464                 }
1465         }
1466         qdev->stats.rx_packets++;
1467         qdev->stats.rx_bytes += skb->len;
1468         skb->protocol = eth_type_trans(skb, ndev);
1469         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1470                 QPRINTK(qdev, RX_STATUS, DEBUG,
1471                         "Passing a VLAN packet upstream.\n");
1472                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1473                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1474         } else {
1475                 QPRINTK(qdev, RX_STATUS, DEBUG,
1476                         "Passing a normal packet upstream.\n");
1477                 netif_receive_skb(skb);
1478         }
1479 }
1480
1481 /* Process an outbound completion from an rx ring. */
1482 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1483                                    struct ob_mac_iocb_rsp *mac_rsp)
1484 {
1485         struct tx_ring *tx_ring;
1486         struct tx_ring_desc *tx_ring_desc;
1487
1488         QL_DUMP_OB_MAC_RSP(mac_rsp);
1489         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1490         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1491         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1492         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1493         qdev->stats.tx_packets++;
1494         dev_kfree_skb(tx_ring_desc->skb);
1495         tx_ring_desc->skb = NULL;
1496
1497         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1498                                         OB_MAC_IOCB_RSP_S |
1499                                         OB_MAC_IOCB_RSP_L |
1500                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1501                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1502                         QPRINTK(qdev, TX_DONE, WARNING,
1503                                 "Total descriptor length did not match transfer length.\n");
1504                 }
1505                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1506                         QPRINTK(qdev, TX_DONE, WARNING,
1507                                 "Frame too short to be legal, not sent.\n");
1508                 }
1509                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1510                         QPRINTK(qdev, TX_DONE, WARNING,
1511                                 "Frame too long, but sent anyway.\n");
1512                 }
1513                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1514                         QPRINTK(qdev, TX_DONE, WARNING,
1515                                 "PCI backplane error. Frame not sent.\n");
1516                 }
1517         }
1518         atomic_inc(&tx_ring->tx_count);
1519 }
1520
1521 /* Fire up a handler to reset the MPI processor. */
1522 void ql_queue_fw_error(struct ql_adapter *qdev)
1523 {
1524         netif_stop_queue(qdev->ndev);
1525         netif_carrier_off(qdev->ndev);
1526         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1527 }
1528
1529 void ql_queue_asic_error(struct ql_adapter *qdev)
1530 {
1531         netif_stop_queue(qdev->ndev);
1532         netif_carrier_off(qdev->ndev);
1533         ql_disable_interrupts(qdev);
1534         /* Clear adapter up bit to signal the recovery
1535          * process that it shouldn't kill the reset worker
1536          * thread
1537          */
1538         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1539         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1540 }
1541
1542 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1543                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1544 {
1545         switch (ib_ae_rsp->event) {
1546         case MGMT_ERR_EVENT:
1547                 QPRINTK(qdev, RX_ERR, ERR,
1548                         "Management Processor Fatal Error.\n");
1549                 ql_queue_fw_error(qdev);
1550                 return;
1551
1552         case CAM_LOOKUP_ERR_EVENT:
1553                 QPRINTK(qdev, LINK, ERR,
1554                         "Multiple CAM hits lookup occurred.\n");
1555                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1556                 ql_queue_asic_error(qdev);
1557                 return;
1558
1559         case SOFT_ECC_ERROR_EVENT:
1560                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1561                 ql_queue_asic_error(qdev);
1562                 break;
1563
1564         case PCI_ERR_ANON_BUF_RD:
1565                 QPRINTK(qdev, RX_ERR, ERR,
1566                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1567                         ib_ae_rsp->q_id);
1568                 ql_queue_asic_error(qdev);
1569                 break;
1570
1571         default:
1572                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1573                         ib_ae_rsp->event);
1574                 ql_queue_asic_error(qdev);
1575                 break;
1576         }
1577 }
1578
1579 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1580 {
1581         struct ql_adapter *qdev = rx_ring->qdev;
1582         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1583         struct ob_mac_iocb_rsp *net_rsp = NULL;
1584         int count = 0;
1585
1586         /* While there are entries in the completion queue. */
1587         while (prod != rx_ring->cnsmr_idx) {
1588
1589                 QPRINTK(qdev, RX_STATUS, DEBUG,
1590                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1591                         prod, rx_ring->cnsmr_idx);
1592
1593                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1594                 rmb();
1595                 switch (net_rsp->opcode) {
1596
1597                 case OPCODE_OB_MAC_TSO_IOCB:
1598                 case OPCODE_OB_MAC_IOCB:
1599                         ql_process_mac_tx_intr(qdev, net_rsp);
1600                         break;
1601                 default:
1602                         QPRINTK(qdev, RX_STATUS, DEBUG,
1603                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1604                                 net_rsp->opcode);
1605                 }
1606                 count++;
1607                 ql_update_cq(rx_ring);
1608                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1609         }
1610         ql_write_cq_idx(rx_ring);
1611         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1612                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1613                 if (atomic_read(&tx_ring->queue_stopped) &&
1614                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1615                         /*
1616                          * The queue got stopped because the tx_ring was full.
1617                          * Wake it up, because it's now at least 25% empty.
1618                          */
1619                         netif_wake_queue(qdev->ndev);
1620         }
1621
1622         return count;
1623 }
1624
1625 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1626 {
1627         struct ql_adapter *qdev = rx_ring->qdev;
1628         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1629         struct ql_net_rsp_iocb *net_rsp;
1630         int count = 0;
1631
1632         /* While there are entries in the completion queue. */
1633         while (prod != rx_ring->cnsmr_idx) {
1634
1635                 QPRINTK(qdev, RX_STATUS, DEBUG,
1636                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1637                         prod, rx_ring->cnsmr_idx);
1638
1639                 net_rsp = rx_ring->curr_entry;
1640                 rmb();
1641                 switch (net_rsp->opcode) {
1642                 case OPCODE_IB_MAC_IOCB:
1643                         ql_process_mac_rx_intr(qdev, rx_ring,
1644                                                (struct ib_mac_iocb_rsp *)
1645                                                net_rsp);
1646                         break;
1647
1648                 case OPCODE_IB_AE_IOCB:
1649                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1650                                                 net_rsp);
1651                         break;
1652                 default:
1653                         {
1654                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1655                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1656                                         net_rsp->opcode);
1657                         }
1658                 }
1659                 count++;
1660                 ql_update_cq(rx_ring);
1661                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1662                 if (count == budget)
1663                         break;
1664         }
1665         ql_update_buffer_queues(qdev, rx_ring);
1666         ql_write_cq_idx(rx_ring);
1667         return count;
1668 }
1669
1670 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1671 {
1672         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1673         struct ql_adapter *qdev = rx_ring->qdev;
1674         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1675
1676         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1677                 rx_ring->cq_id);
1678
1679         if (work_done < budget) {
1680                 __netif_rx_complete(napi);
1681                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1682         }
1683         return work_done;
1684 }
1685
1686 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1687 {
1688         struct ql_adapter *qdev = netdev_priv(ndev);
1689
1690         qdev->vlgrp = grp;
1691         if (grp) {
1692                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1693                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1694                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1695         } else {
1696                 QPRINTK(qdev, IFUP, DEBUG,
1697                         "Turning off VLAN in NIC_RCV_CFG.\n");
1698                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1699         }
1700 }
1701
1702 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1703 {
1704         struct ql_adapter *qdev = netdev_priv(ndev);
1705         u32 enable_bit = MAC_ADDR_E;
1706
1707         spin_lock(&qdev->hw_lock);
1708         if (ql_set_mac_addr_reg
1709             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1710                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1711         }
1712         spin_unlock(&qdev->hw_lock);
1713 }
1714
1715 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1716 {
1717         struct ql_adapter *qdev = netdev_priv(ndev);
1718         u32 enable_bit = 0;
1719
1720         spin_lock(&qdev->hw_lock);
1721         if (ql_set_mac_addr_reg
1722             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1723                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1724         }
1725         spin_unlock(&qdev->hw_lock);
1726
1727 }
1728
1729 /* Worker thread to process a given rx_ring that is dedicated
1730  * to outbound completions.
1731  */
1732 static void ql_tx_clean(struct work_struct *work)
1733 {
1734         struct rx_ring *rx_ring =
1735             container_of(work, struct rx_ring, rx_work.work);
1736         ql_clean_outbound_rx_ring(rx_ring);
1737         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1738
1739 }
1740
1741 /* Worker thread to process a given rx_ring that is dedicated
1742  * to inbound completions.
1743  */
1744 static void ql_rx_clean(struct work_struct *work)
1745 {
1746         struct rx_ring *rx_ring =
1747             container_of(work, struct rx_ring, rx_work.work);
1748         ql_clean_inbound_rx_ring(rx_ring, 64);
1749         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1750 }
1751
1752 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1753 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1754 {
1755         struct rx_ring *rx_ring = dev_id;
1756         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1757                               &rx_ring->rx_work, 0);
1758         return IRQ_HANDLED;
1759 }
1760
1761 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1762 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1763 {
1764         struct rx_ring *rx_ring = dev_id;
1765         netif_rx_schedule(&rx_ring->napi);
1766         return IRQ_HANDLED;
1767 }
1768
1769 /* This handles a fatal error, MPI activity, and the default
1770  * rx_ring in an MSI-X multiple vector environment.
1771  * In MSI/Legacy environment it also process the rest of
1772  * the rx_rings.
1773  */
1774 static irqreturn_t qlge_isr(int irq, void *dev_id)
1775 {
1776         struct rx_ring *rx_ring = dev_id;
1777         struct ql_adapter *qdev = rx_ring->qdev;
1778         struct intr_context *intr_context = &qdev->intr_context[0];
1779         u32 var;
1780         int i;
1781         int work_done = 0;
1782
1783         spin_lock(&qdev->hw_lock);
1784         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1785                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1786                 spin_unlock(&qdev->hw_lock);
1787                 return IRQ_NONE;
1788         }
1789         spin_unlock(&qdev->hw_lock);
1790
1791         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1792
1793         /*
1794          * Check for fatal error.
1795          */
1796         if (var & STS_FE) {
1797                 ql_queue_asic_error(qdev);
1798                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1799                 var = ql_read32(qdev, ERR_STS);
1800                 QPRINTK(qdev, INTR, ERR,
1801                         "Resetting chip. Error Status Register = 0x%x\n", var);
1802                 return IRQ_HANDLED;
1803         }
1804
1805         /*
1806          * Check MPI processor activity.
1807          */
1808         if (var & STS_PI) {
1809                 /*
1810                  * We've got an async event or mailbox completion.
1811                  * Handle it and clear the source of the interrupt.
1812                  */
1813                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1814                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1815                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1816                                       &qdev->mpi_work, 0);
1817                 work_done++;
1818         }
1819
1820         /*
1821          * Check the default queue and wake handler if active.
1822          */
1823         rx_ring = &qdev->rx_ring[0];
1824         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1825                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1826                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1827                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1828                                       &rx_ring->rx_work, 0);
1829                 work_done++;
1830         }
1831
1832         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1833                 /*
1834                  * Start the DPC for each active queue.
1835                  */
1836                 for (i = 1; i < qdev->rx_ring_count; i++) {
1837                         rx_ring = &qdev->rx_ring[i];
1838                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1839                             rx_ring->cnsmr_idx) {
1840                                 QPRINTK(qdev, INTR, INFO,
1841                                         "Waking handler for rx_ring[%d].\n", i);
1842                                 ql_disable_completion_interrupt(qdev,
1843                                                                 intr_context->
1844                                                                 intr);
1845                                 if (i < qdev->rss_ring_first_cq_id)
1846                                         queue_delayed_work_on(rx_ring->cpu,
1847                                                               qdev->q_workqueue,
1848                                                               &rx_ring->rx_work,
1849                                                               0);
1850                                 else
1851                                         netif_rx_schedule(&rx_ring->napi);
1852                                 work_done++;
1853                         }
1854                 }
1855         }
1856         ql_enable_completion_interrupt(qdev, intr_context->intr);
1857         return work_done ? IRQ_HANDLED : IRQ_NONE;
1858 }
1859
1860 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1861 {
1862
1863         if (skb_is_gso(skb)) {
1864                 int err;
1865                 if (skb_header_cloned(skb)) {
1866                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1867                         if (err)
1868                                 return err;
1869                 }
1870
1871                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1872                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1873                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1874                 mac_iocb_ptr->total_hdrs_len =
1875                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1876                 mac_iocb_ptr->net_trans_offset =
1877                     cpu_to_le16(skb_network_offset(skb) |
1878                                 skb_transport_offset(skb)
1879                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1880                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1881                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1882                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1883                         struct iphdr *iph = ip_hdr(skb);
1884                         iph->check = 0;
1885                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1886                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1887                                                                  iph->daddr, 0,
1888                                                                  IPPROTO_TCP,
1889                                                                  0);
1890                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1891                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1892                         tcp_hdr(skb)->check =
1893                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1894                                              &ipv6_hdr(skb)->daddr,
1895                                              0, IPPROTO_TCP, 0);
1896                 }
1897                 return 1;
1898         }
1899         return 0;
1900 }
1901
1902 static void ql_hw_csum_setup(struct sk_buff *skb,
1903                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1904 {
1905         int len;
1906         struct iphdr *iph = ip_hdr(skb);
1907         __sum16 *check;
1908         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1909         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1910         mac_iocb_ptr->net_trans_offset =
1911                 cpu_to_le16(skb_network_offset(skb) |
1912                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1913
1914         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1915         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1916         if (likely(iph->protocol == IPPROTO_TCP)) {
1917                 check = &(tcp_hdr(skb)->check);
1918                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1919                 mac_iocb_ptr->total_hdrs_len =
1920                     cpu_to_le16(skb_transport_offset(skb) +
1921                                 (tcp_hdr(skb)->doff << 2));
1922         } else {
1923                 check = &(udp_hdr(skb)->check);
1924                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1925                 mac_iocb_ptr->total_hdrs_len =
1926                     cpu_to_le16(skb_transport_offset(skb) +
1927                                 sizeof(struct udphdr));
1928         }
1929         *check = ~csum_tcpudp_magic(iph->saddr,
1930                                     iph->daddr, len, iph->protocol, 0);
1931 }
1932
1933 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1934 {
1935         struct tx_ring_desc *tx_ring_desc;
1936         struct ob_mac_iocb_req *mac_iocb_ptr;
1937         struct ql_adapter *qdev = netdev_priv(ndev);
1938         int tso;
1939         struct tx_ring *tx_ring;
1940         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1941
1942         tx_ring = &qdev->tx_ring[tx_ring_idx];
1943
1944         if (skb_padto(skb, ETH_ZLEN))
1945                 return NETDEV_TX_OK;
1946
1947         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1948                 QPRINTK(qdev, TX_QUEUED, INFO,
1949                         "%s: shutting down tx queue %d du to lack of resources.\n",
1950                         __func__, tx_ring_idx);
1951                 netif_stop_queue(ndev);
1952                 atomic_inc(&tx_ring->queue_stopped);
1953                 return NETDEV_TX_BUSY;
1954         }
1955         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1956         mac_iocb_ptr = tx_ring_desc->queue_entry;
1957         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1958
1959         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1960         mac_iocb_ptr->tid = tx_ring_desc->index;
1961         /* We use the upper 32-bits to store the tx queue for this IO.
1962          * When we get the completion we can use it to establish the context.
1963          */
1964         mac_iocb_ptr->txq_idx = tx_ring_idx;
1965         tx_ring_desc->skb = skb;
1966
1967         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1968
1969         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1970                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1971                         vlan_tx_tag_get(skb));
1972                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1973                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1974         }
1975         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1976         if (tso < 0) {
1977                 dev_kfree_skb_any(skb);
1978                 return NETDEV_TX_OK;
1979         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1980                 ql_hw_csum_setup(skb,
1981                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1982         }
1983         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
1984                         NETDEV_TX_OK) {
1985                 QPRINTK(qdev, TX_QUEUED, ERR,
1986                                 "Could not map the segments.\n");
1987                 return NETDEV_TX_BUSY;
1988         }
1989         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1990         tx_ring->prod_idx++;
1991         if (tx_ring->prod_idx == tx_ring->wq_len)
1992                 tx_ring->prod_idx = 0;
1993         wmb();
1994
1995         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1996         ndev->trans_start = jiffies;
1997         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1998                 tx_ring->prod_idx, skb->len);
1999
2000         atomic_dec(&tx_ring->tx_count);
2001         return NETDEV_TX_OK;
2002 }
2003
2004 static void ql_free_shadow_space(struct ql_adapter *qdev)
2005 {
2006         if (qdev->rx_ring_shadow_reg_area) {
2007                 pci_free_consistent(qdev->pdev,
2008                                     PAGE_SIZE,
2009                                     qdev->rx_ring_shadow_reg_area,
2010                                     qdev->rx_ring_shadow_reg_dma);
2011                 qdev->rx_ring_shadow_reg_area = NULL;
2012         }
2013         if (qdev->tx_ring_shadow_reg_area) {
2014                 pci_free_consistent(qdev->pdev,
2015                                     PAGE_SIZE,
2016                                     qdev->tx_ring_shadow_reg_area,
2017                                     qdev->tx_ring_shadow_reg_dma);
2018                 qdev->tx_ring_shadow_reg_area = NULL;
2019         }
2020 }
2021
2022 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2023 {
2024         qdev->rx_ring_shadow_reg_area =
2025             pci_alloc_consistent(qdev->pdev,
2026                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2027         if (qdev->rx_ring_shadow_reg_area == NULL) {
2028                 QPRINTK(qdev, IFUP, ERR,
2029                         "Allocation of RX shadow space failed.\n");
2030                 return -ENOMEM;
2031         }
2032         qdev->tx_ring_shadow_reg_area =
2033             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2034                                  &qdev->tx_ring_shadow_reg_dma);
2035         if (qdev->tx_ring_shadow_reg_area == NULL) {
2036                 QPRINTK(qdev, IFUP, ERR,
2037                         "Allocation of TX shadow space failed.\n");
2038                 goto err_wqp_sh_area;
2039         }
2040         return 0;
2041
2042 err_wqp_sh_area:
2043         pci_free_consistent(qdev->pdev,
2044                             PAGE_SIZE,
2045                             qdev->rx_ring_shadow_reg_area,
2046                             qdev->rx_ring_shadow_reg_dma);
2047         return -ENOMEM;
2048 }
2049
2050 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2051 {
2052         struct tx_ring_desc *tx_ring_desc;
2053         int i;
2054         struct ob_mac_iocb_req *mac_iocb_ptr;
2055
2056         mac_iocb_ptr = tx_ring->wq_base;
2057         tx_ring_desc = tx_ring->q;
2058         for (i = 0; i < tx_ring->wq_len; i++) {
2059                 tx_ring_desc->index = i;
2060                 tx_ring_desc->skb = NULL;
2061                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2062                 mac_iocb_ptr++;
2063                 tx_ring_desc++;
2064         }
2065         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2066         atomic_set(&tx_ring->queue_stopped, 0);
2067 }
2068
2069 static void ql_free_tx_resources(struct ql_adapter *qdev,
2070                                  struct tx_ring *tx_ring)
2071 {
2072         if (tx_ring->wq_base) {
2073                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2074                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2075                 tx_ring->wq_base = NULL;
2076         }
2077         kfree(tx_ring->q);
2078         tx_ring->q = NULL;
2079 }
2080
2081 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2082                                  struct tx_ring *tx_ring)
2083 {
2084         tx_ring->wq_base =
2085             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2086                                  &tx_ring->wq_base_dma);
2087
2088         if ((tx_ring->wq_base == NULL)
2089             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2090                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2091                 return -ENOMEM;
2092         }
2093         tx_ring->q =
2094             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2095         if (tx_ring->q == NULL)
2096                 goto err;
2097
2098         return 0;
2099 err:
2100         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2101                             tx_ring->wq_base, tx_ring->wq_base_dma);
2102         return -ENOMEM;
2103 }
2104
2105 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2106 {
2107         int i;
2108         struct bq_desc *lbq_desc;
2109
2110         for (i = 0; i < rx_ring->lbq_len; i++) {
2111                 lbq_desc = &rx_ring->lbq[i];
2112                 if (lbq_desc->p.lbq_page) {
2113                         pci_unmap_page(qdev->pdev,
2114                                        pci_unmap_addr(lbq_desc, mapaddr),
2115                                        pci_unmap_len(lbq_desc, maplen),
2116                                        PCI_DMA_FROMDEVICE);
2117
2118                         put_page(lbq_desc->p.lbq_page);
2119                         lbq_desc->p.lbq_page = NULL;
2120                 }
2121         }
2122 }
2123
2124 /*
2125  * Allocate and map a page for each element of the lbq.
2126  */
2127 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2128                                 struct rx_ring *rx_ring)
2129 {
2130         int i;
2131         struct bq_desc *lbq_desc;
2132         u64 map;
2133         __le64 *bq = rx_ring->lbq_base;
2134
2135         for (i = 0; i < rx_ring->lbq_len; i++) {
2136                 lbq_desc = &rx_ring->lbq[i];
2137                 memset(lbq_desc, 0, sizeof(lbq_desc));
2138                 lbq_desc->addr = bq;
2139                 lbq_desc->index = i;
2140                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2141                 if (unlikely(!lbq_desc->p.lbq_page)) {
2142                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2143                         goto mem_error;
2144                 } else {
2145                         map = pci_map_page(qdev->pdev,
2146                                            lbq_desc->p.lbq_page,
2147                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2148                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2149                                 QPRINTK(qdev, IFUP, ERR,
2150                                         "PCI mapping failed.\n");
2151                                 goto mem_error;
2152                         }
2153                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2154                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2155                         *lbq_desc->addr = cpu_to_le64(map);
2156                 }
2157                 bq++;
2158         }
2159         return 0;
2160 mem_error:
2161         ql_free_lbq_buffers(qdev, rx_ring);
2162         return -ENOMEM;
2163 }
2164
2165 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2166 {
2167         int i;
2168         struct bq_desc *sbq_desc;
2169
2170         for (i = 0; i < rx_ring->sbq_len; i++) {
2171                 sbq_desc = &rx_ring->sbq[i];
2172                 if (sbq_desc == NULL) {
2173                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2174                         return;
2175                 }
2176                 if (sbq_desc->p.skb) {
2177                         pci_unmap_single(qdev->pdev,
2178                                          pci_unmap_addr(sbq_desc, mapaddr),
2179                                          pci_unmap_len(sbq_desc, maplen),
2180                                          PCI_DMA_FROMDEVICE);
2181                         dev_kfree_skb(sbq_desc->p.skb);
2182                         sbq_desc->p.skb = NULL;
2183                 }
2184         }
2185 }
2186
2187 /* Allocate and map an skb for each element of the sbq. */
2188 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2189                                 struct rx_ring *rx_ring)
2190 {
2191         int i;
2192         struct bq_desc *sbq_desc;
2193         struct sk_buff *skb;
2194         u64 map;
2195         __le64 *bq = rx_ring->sbq_base;
2196
2197         for (i = 0; i < rx_ring->sbq_len; i++) {
2198                 sbq_desc = &rx_ring->sbq[i];
2199                 memset(sbq_desc, 0, sizeof(sbq_desc));
2200                 sbq_desc->index = i;
2201                 sbq_desc->addr = bq;
2202                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2203                 if (unlikely(!skb)) {
2204                         /* Better luck next round */
2205                         QPRINTK(qdev, IFUP, ERR,
2206                                 "small buff alloc failed for %d bytes at index %d.\n",
2207                                 rx_ring->sbq_buf_size, i);
2208                         goto mem_err;
2209                 }
2210                 skb_reserve(skb, QLGE_SB_PAD);
2211                 sbq_desc->p.skb = skb;
2212                 /*
2213                  * Map only half the buffer. Because the
2214                  * other half may get some data copied to it
2215                  * when the completion arrives.
2216                  */
2217                 map = pci_map_single(qdev->pdev,
2218                                      skb->data,
2219                                      rx_ring->sbq_buf_size / 2,
2220                                      PCI_DMA_FROMDEVICE);
2221                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2222                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2223                         goto mem_err;
2224                 }
2225                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2226                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2227                 *sbq_desc->addr = cpu_to_le64(map);
2228                 bq++;
2229         }
2230         return 0;
2231 mem_err:
2232         ql_free_sbq_buffers(qdev, rx_ring);
2233         return -ENOMEM;
2234 }
2235
2236 static void ql_free_rx_resources(struct ql_adapter *qdev,
2237                                  struct rx_ring *rx_ring)
2238 {
2239         if (rx_ring->sbq_len)
2240                 ql_free_sbq_buffers(qdev, rx_ring);
2241         if (rx_ring->lbq_len)
2242                 ql_free_lbq_buffers(qdev, rx_ring);
2243
2244         /* Free the small buffer queue. */
2245         if (rx_ring->sbq_base) {
2246                 pci_free_consistent(qdev->pdev,
2247                                     rx_ring->sbq_size,
2248                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2249                 rx_ring->sbq_base = NULL;
2250         }
2251
2252         /* Free the small buffer queue control blocks. */
2253         kfree(rx_ring->sbq);
2254         rx_ring->sbq = NULL;
2255
2256         /* Free the large buffer queue. */
2257         if (rx_ring->lbq_base) {
2258                 pci_free_consistent(qdev->pdev,
2259                                     rx_ring->lbq_size,
2260                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2261                 rx_ring->lbq_base = NULL;
2262         }
2263
2264         /* Free the large buffer queue control blocks. */
2265         kfree(rx_ring->lbq);
2266         rx_ring->lbq = NULL;
2267
2268         /* Free the rx queue. */
2269         if (rx_ring->cq_base) {
2270                 pci_free_consistent(qdev->pdev,
2271                                     rx_ring->cq_size,
2272                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2273                 rx_ring->cq_base = NULL;
2274         }
2275 }
2276
2277 /* Allocate queues and buffers for this completions queue based
2278  * on the values in the parameter structure. */
2279 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2280                                  struct rx_ring *rx_ring)
2281 {
2282
2283         /*
2284          * Allocate the completion queue for this rx_ring.
2285          */
2286         rx_ring->cq_base =
2287             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2288                                  &rx_ring->cq_base_dma);
2289
2290         if (rx_ring->cq_base == NULL) {
2291                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2292                 return -ENOMEM;
2293         }
2294
2295         if (rx_ring->sbq_len) {
2296                 /*
2297                  * Allocate small buffer queue.
2298                  */
2299                 rx_ring->sbq_base =
2300                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2301                                          &rx_ring->sbq_base_dma);
2302
2303                 if (rx_ring->sbq_base == NULL) {
2304                         QPRINTK(qdev, IFUP, ERR,
2305                                 "Small buffer queue allocation failed.\n");
2306                         goto err_mem;
2307                 }
2308
2309                 /*
2310                  * Allocate small buffer queue control blocks.
2311                  */
2312                 rx_ring->sbq =
2313                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2314                             GFP_KERNEL);
2315                 if (rx_ring->sbq == NULL) {
2316                         QPRINTK(qdev, IFUP, ERR,
2317                                 "Small buffer queue control block allocation failed.\n");
2318                         goto err_mem;
2319                 }
2320
2321                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2322                         QPRINTK(qdev, IFUP, ERR,
2323                                 "Small buffer allocation failed.\n");
2324                         goto err_mem;
2325                 }
2326         }
2327
2328         if (rx_ring->lbq_len) {
2329                 /*
2330                  * Allocate large buffer queue.
2331                  */
2332                 rx_ring->lbq_base =
2333                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2334                                          &rx_ring->lbq_base_dma);
2335
2336                 if (rx_ring->lbq_base == NULL) {
2337                         QPRINTK(qdev, IFUP, ERR,
2338                                 "Large buffer queue allocation failed.\n");
2339                         goto err_mem;
2340                 }
2341                 /*
2342                  * Allocate large buffer queue control blocks.
2343                  */
2344                 rx_ring->lbq =
2345                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2346                             GFP_KERNEL);
2347                 if (rx_ring->lbq == NULL) {
2348                         QPRINTK(qdev, IFUP, ERR,
2349                                 "Large buffer queue control block allocation failed.\n");
2350                         goto err_mem;
2351                 }
2352
2353                 /*
2354                  * Allocate the buffers.
2355                  */
2356                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2357                         QPRINTK(qdev, IFUP, ERR,
2358                                 "Large buffer allocation failed.\n");
2359                         goto err_mem;
2360                 }
2361         }
2362
2363         return 0;
2364
2365 err_mem:
2366         ql_free_rx_resources(qdev, rx_ring);
2367         return -ENOMEM;
2368 }
2369
2370 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2371 {
2372         struct tx_ring *tx_ring;
2373         struct tx_ring_desc *tx_ring_desc;
2374         int i, j;
2375
2376         /*
2377          * Loop through all queues and free
2378          * any resources.
2379          */
2380         for (j = 0; j < qdev->tx_ring_count; j++) {
2381                 tx_ring = &qdev->tx_ring[j];
2382                 for (i = 0; i < tx_ring->wq_len; i++) {
2383                         tx_ring_desc = &tx_ring->q[i];
2384                         if (tx_ring_desc && tx_ring_desc->skb) {
2385                                 QPRINTK(qdev, IFDOWN, ERR,
2386                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2387                                         tx_ring_desc->skb, j,
2388                                         tx_ring_desc->index);
2389                                 ql_unmap_send(qdev, tx_ring_desc,
2390                                               tx_ring_desc->map_cnt);
2391                                 dev_kfree_skb(tx_ring_desc->skb);
2392                                 tx_ring_desc->skb = NULL;
2393                         }
2394                 }
2395         }
2396 }
2397
2398 static void ql_free_mem_resources(struct ql_adapter *qdev)
2399 {
2400         int i;
2401
2402         for (i = 0; i < qdev->tx_ring_count; i++)
2403                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2404         for (i = 0; i < qdev->rx_ring_count; i++)
2405                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2406         ql_free_shadow_space(qdev);
2407 }
2408
2409 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2410 {
2411         int i;
2412
2413         /* Allocate space for our shadow registers and such. */
2414         if (ql_alloc_shadow_space(qdev))
2415                 return -ENOMEM;
2416
2417         for (i = 0; i < qdev->rx_ring_count; i++) {
2418                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2419                         QPRINTK(qdev, IFUP, ERR,
2420                                 "RX resource allocation failed.\n");
2421                         goto err_mem;
2422                 }
2423         }
2424         /* Allocate tx queue resources */
2425         for (i = 0; i < qdev->tx_ring_count; i++) {
2426                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2427                         QPRINTK(qdev, IFUP, ERR,
2428                                 "TX resource allocation failed.\n");
2429                         goto err_mem;
2430                 }
2431         }
2432         return 0;
2433
2434 err_mem:
2435         ql_free_mem_resources(qdev);
2436         return -ENOMEM;
2437 }
2438
2439 /* Set up the rx ring control block and pass it to the chip.
2440  * The control block is defined as
2441  * "Completion Queue Initialization Control Block", or cqicb.
2442  */
2443 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2444 {
2445         struct cqicb *cqicb = &rx_ring->cqicb;
2446         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2447             (rx_ring->cq_id * sizeof(u64) * 4);
2448         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2449             (rx_ring->cq_id * sizeof(u64) * 4);
2450         void __iomem *doorbell_area =
2451             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2452         int err = 0;
2453         u16 bq_len;
2454
2455         /* Set up the shadow registers for this ring. */
2456         rx_ring->prod_idx_sh_reg = shadow_reg;
2457         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2458         shadow_reg += sizeof(u64);
2459         shadow_reg_dma += sizeof(u64);
2460         rx_ring->lbq_base_indirect = shadow_reg;
2461         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2462         shadow_reg += sizeof(u64);
2463         shadow_reg_dma += sizeof(u64);
2464         rx_ring->sbq_base_indirect = shadow_reg;
2465         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2466
2467         /* PCI doorbell mem area + 0x00 for consumer index register */
2468         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2469         rx_ring->cnsmr_idx = 0;
2470         rx_ring->curr_entry = rx_ring->cq_base;
2471
2472         /* PCI doorbell mem area + 0x04 for valid register */
2473         rx_ring->valid_db_reg = doorbell_area + 0x04;
2474
2475         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2476         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2477
2478         /* PCI doorbell mem area + 0x1c */
2479         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2480
2481         memset((void *)cqicb, 0, sizeof(struct cqicb));
2482         cqicb->msix_vect = rx_ring->irq;
2483
2484         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2485         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2486
2487         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2488
2489         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2490
2491         /*
2492          * Set up the control block load flags.
2493          */
2494         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2495             FLAGS_LV |          /* Load MSI-X vector */
2496             FLAGS_LI;           /* Load irq delay values */
2497         if (rx_ring->lbq_len) {
2498                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2499                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2500                 cqicb->lbq_addr =
2501                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2502                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2503                         (u16) rx_ring->lbq_buf_size;
2504                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2505                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2506                         (u16) rx_ring->lbq_len;
2507                 cqicb->lbq_len = cpu_to_le16(bq_len);
2508                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2509                 rx_ring->lbq_curr_idx = 0;
2510                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2511                 rx_ring->lbq_free_cnt = 16;
2512         }
2513         if (rx_ring->sbq_len) {
2514                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2515                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2516                 cqicb->sbq_addr =
2517                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2518                 cqicb->sbq_buf_size =
2519                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2520                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2521                         (u16) rx_ring->sbq_len;
2522                 cqicb->sbq_len = cpu_to_le16(bq_len);
2523                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2524                 rx_ring->sbq_curr_idx = 0;
2525                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2526                 rx_ring->sbq_free_cnt = 16;
2527         }
2528         switch (rx_ring->type) {
2529         case TX_Q:
2530                 /* If there's only one interrupt, then we use
2531                  * worker threads to process the outbound
2532                  * completion handling rx_rings. We do this so
2533                  * they can be run on multiple CPUs. There is
2534                  * room to play with this more where we would only
2535                  * run in a worker if there are more than x number
2536                  * of outbound completions on the queue and more
2537                  * than one queue active.  Some threshold that
2538                  * would indicate a benefit in spite of the cost
2539                  * of a context switch.
2540                  * If there's more than one interrupt, then the
2541                  * outbound completions are processed in the ISR.
2542                  */
2543                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2544                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2545                 else {
2546                         /* With all debug warnings on we see a WARN_ON message
2547                          * when we free the skb in the interrupt context.
2548                          */
2549                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2550                 }
2551                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2552                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2553                 break;
2554         case DEFAULT_Q:
2555                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2556                 cqicb->irq_delay = 0;
2557                 cqicb->pkt_delay = 0;
2558                 break;
2559         case RX_Q:
2560                 /* Inbound completion handling rx_rings run in
2561                  * separate NAPI contexts.
2562                  */
2563                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2564                                64);
2565                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2566                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2567                 break;
2568         default:
2569                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2570                         rx_ring->type);
2571         }
2572         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2573         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2574                            CFG_LCQ, rx_ring->cq_id);
2575         if (err) {
2576                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2577                 return err;
2578         }
2579         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2580         /*
2581          * Advance the producer index for the buffer queues.
2582          */
2583         wmb();
2584         if (rx_ring->lbq_len)
2585                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2586                                 rx_ring->lbq_prod_idx_db_reg);
2587         if (rx_ring->sbq_len)
2588                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2589                                 rx_ring->sbq_prod_idx_db_reg);
2590         return err;
2591 }
2592
2593 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2594 {
2595         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2596         void __iomem *doorbell_area =
2597             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2598         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2599             (tx_ring->wq_id * sizeof(u64));
2600         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2601             (tx_ring->wq_id * sizeof(u64));
2602         int err = 0;
2603
2604         /*
2605          * Assign doorbell registers for this tx_ring.
2606          */
2607         /* TX PCI doorbell mem area for tx producer index */
2608         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2609         tx_ring->prod_idx = 0;
2610         /* TX PCI doorbell mem area + 0x04 */
2611         tx_ring->valid_db_reg = doorbell_area + 0x04;
2612
2613         /*
2614          * Assign shadow registers for this tx_ring.
2615          */
2616         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2617         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2618
2619         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2620         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2621                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2622         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2623         wqicb->rid = 0;
2624         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2625
2626         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2627
2628         ql_init_tx_ring(qdev, tx_ring);
2629
2630         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2631                            (u16) tx_ring->wq_id);
2632         if (err) {
2633                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2634                 return err;
2635         }
2636         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2637         return err;
2638 }
2639
2640 static void ql_disable_msix(struct ql_adapter *qdev)
2641 {
2642         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2643                 pci_disable_msix(qdev->pdev);
2644                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2645                 kfree(qdev->msi_x_entry);
2646                 qdev->msi_x_entry = NULL;
2647         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2648                 pci_disable_msi(qdev->pdev);
2649                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2650         }
2651 }
2652
2653 static void ql_enable_msix(struct ql_adapter *qdev)
2654 {
2655         int i;
2656
2657         qdev->intr_count = 1;
2658         /* Get the MSIX vectors. */
2659         if (irq_type == MSIX_IRQ) {
2660                 /* Try to alloc space for the msix struct,
2661                  * if it fails then go to MSI/legacy.
2662                  */
2663                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2664                                             sizeof(struct msix_entry),
2665                                             GFP_KERNEL);
2666                 if (!qdev->msi_x_entry) {
2667                         irq_type = MSI_IRQ;
2668                         goto msi;
2669                 }
2670
2671                 for (i = 0; i < qdev->rx_ring_count; i++)
2672                         qdev->msi_x_entry[i].entry = i;
2673
2674                 if (!pci_enable_msix
2675                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2676                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2677                         qdev->intr_count = qdev->rx_ring_count;
2678                         QPRINTK(qdev, IFUP, INFO,
2679                                 "MSI-X Enabled, got %d vectors.\n",
2680                                 qdev->intr_count);
2681                         return;
2682                 } else {
2683                         kfree(qdev->msi_x_entry);
2684                         qdev->msi_x_entry = NULL;
2685                         QPRINTK(qdev, IFUP, WARNING,
2686                                 "MSI-X Enable failed, trying MSI.\n");
2687                         irq_type = MSI_IRQ;
2688                 }
2689         }
2690 msi:
2691         if (irq_type == MSI_IRQ) {
2692                 if (!pci_enable_msi(qdev->pdev)) {
2693                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2694                         QPRINTK(qdev, IFUP, INFO,
2695                                 "Running with MSI interrupts.\n");
2696                         return;
2697                 }
2698         }
2699         irq_type = LEG_IRQ;
2700         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2701 }
2702
2703 /*
2704  * Here we build the intr_context structures based on
2705  * our rx_ring count and intr vector count.
2706  * The intr_context structure is used to hook each vector
2707  * to possibly different handlers.
2708  */
2709 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2710 {
2711         int i = 0;
2712         struct intr_context *intr_context = &qdev->intr_context[0];
2713
2714         ql_enable_msix(qdev);
2715
2716         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2717                 /* Each rx_ring has it's
2718                  * own intr_context since we have separate
2719                  * vectors for each queue.
2720                  * This only true when MSI-X is enabled.
2721                  */
2722                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2723                         qdev->rx_ring[i].irq = i;
2724                         intr_context->intr = i;
2725                         intr_context->qdev = qdev;
2726                         /*
2727                          * We set up each vectors enable/disable/read bits so
2728                          * there's no bit/mask calculations in the critical path.
2729                          */
2730                         intr_context->intr_en_mask =
2731                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2732                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2733                             | i;
2734                         intr_context->intr_dis_mask =
2735                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2736                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2737                             INTR_EN_IHD | i;
2738                         intr_context->intr_read_mask =
2739                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2740                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2741                             i;
2742
2743                         if (i == 0) {
2744                                 /*
2745                                  * Default queue handles bcast/mcast plus
2746                                  * async events.  Needs buffers.
2747                                  */
2748                                 intr_context->handler = qlge_isr;
2749                                 sprintf(intr_context->name, "%s-default-queue",
2750                                         qdev->ndev->name);
2751                         } else if (i < qdev->rss_ring_first_cq_id) {
2752                                 /*
2753                                  * Outbound queue is for outbound completions only.
2754                                  */
2755                                 intr_context->handler = qlge_msix_tx_isr;
2756                                 sprintf(intr_context->name, "%s-tx-%d",
2757                                         qdev->ndev->name, i);
2758                         } else {
2759                                 /*
2760                                  * Inbound queues handle unicast frames only.
2761                                  */
2762                                 intr_context->handler = qlge_msix_rx_isr;
2763                                 sprintf(intr_context->name, "%s-rx-%d",
2764                                         qdev->ndev->name, i);
2765                         }
2766                 }
2767         } else {
2768                 /*
2769                  * All rx_rings use the same intr_context since
2770                  * there is only one vector.
2771                  */
2772                 intr_context->intr = 0;
2773                 intr_context->qdev = qdev;
2774                 /*
2775                  * We set up each vectors enable/disable/read bits so
2776                  * there's no bit/mask calculations in the critical path.
2777                  */
2778                 intr_context->intr_en_mask =
2779                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2780                 intr_context->intr_dis_mask =
2781                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2782                     INTR_EN_TYPE_DISABLE;
2783                 intr_context->intr_read_mask =
2784                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2785                 /*
2786                  * Single interrupt means one handler for all rings.
2787                  */
2788                 intr_context->handler = qlge_isr;
2789                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2790                 for (i = 0; i < qdev->rx_ring_count; i++)
2791                         qdev->rx_ring[i].irq = 0;
2792         }
2793 }
2794
2795 static void ql_free_irq(struct ql_adapter *qdev)
2796 {
2797         int i;
2798         struct intr_context *intr_context = &qdev->intr_context[0];
2799
2800         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2801                 if (intr_context->hooked) {
2802                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2803                                 free_irq(qdev->msi_x_entry[i].vector,
2804                                          &qdev->rx_ring[i]);
2805                                 QPRINTK(qdev, IFDOWN, ERR,
2806                                         "freeing msix interrupt %d.\n", i);
2807                         } else {
2808                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2809                                 QPRINTK(qdev, IFDOWN, ERR,
2810                                         "freeing msi interrupt %d.\n", i);
2811                         }
2812                 }
2813         }
2814         ql_disable_msix(qdev);
2815 }
2816
2817 static int ql_request_irq(struct ql_adapter *qdev)
2818 {
2819         int i;
2820         int status = 0;
2821         struct pci_dev *pdev = qdev->pdev;
2822         struct intr_context *intr_context = &qdev->intr_context[0];
2823
2824         ql_resolve_queues_to_irqs(qdev);
2825
2826         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2827                 atomic_set(&intr_context->irq_cnt, 0);
2828                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2829                         status = request_irq(qdev->msi_x_entry[i].vector,
2830                                              intr_context->handler,
2831                                              0,
2832                                              intr_context->name,
2833                                              &qdev->rx_ring[i]);
2834                         if (status) {
2835                                 QPRINTK(qdev, IFUP, ERR,
2836                                         "Failed request for MSIX interrupt %d.\n",
2837                                         i);
2838                                 goto err_irq;
2839                         } else {
2840                                 QPRINTK(qdev, IFUP, INFO,
2841                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2842                                         i,
2843                                         qdev->rx_ring[i].type ==
2844                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2845                                         qdev->rx_ring[i].type ==
2846                                         TX_Q ? "TX_Q" : "",
2847                                         qdev->rx_ring[i].type ==
2848                                         RX_Q ? "RX_Q" : "", intr_context->name);
2849                         }
2850                 } else {
2851                         QPRINTK(qdev, IFUP, DEBUG,
2852                                 "trying msi or legacy interrupts.\n");
2853                         QPRINTK(qdev, IFUP, DEBUG,
2854                                 "%s: irq = %d.\n", __func__, pdev->irq);
2855                         QPRINTK(qdev, IFUP, DEBUG,
2856                                 "%s: context->name = %s.\n", __func__,
2857                                intr_context->name);
2858                         QPRINTK(qdev, IFUP, DEBUG,
2859                                 "%s: dev_id = 0x%p.\n", __func__,
2860                                &qdev->rx_ring[0]);
2861                         status =
2862                             request_irq(pdev->irq, qlge_isr,
2863                                         test_bit(QL_MSI_ENABLED,
2864                                                  &qdev->
2865                                                  flags) ? 0 : IRQF_SHARED,
2866                                         intr_context->name, &qdev->rx_ring[0]);
2867                         if (status)
2868                                 goto err_irq;
2869
2870                         QPRINTK(qdev, IFUP, ERR,
2871                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2872                                 i,
2873                                 qdev->rx_ring[0].type ==
2874                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2875                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2876                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2877                                 intr_context->name);
2878                 }
2879                 intr_context->hooked = 1;
2880         }
2881         return status;
2882 err_irq:
2883         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2884         ql_free_irq(qdev);
2885         return status;
2886 }
2887
2888 static int ql_start_rss(struct ql_adapter *qdev)
2889 {
2890         struct ricb *ricb = &qdev->ricb;
2891         int status = 0;
2892         int i;
2893         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2894
2895         memset((void *)ricb, 0, sizeof(ricb));
2896
2897         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2898         ricb->flags =
2899             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2900              RSS_RT6);
2901         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2902
2903         /*
2904          * Fill out the Indirection Table.
2905          */
2906         for (i = 0; i < 256; i++)
2907                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2908
2909         /*
2910          * Random values for the IPv6 and IPv4 Hash Keys.
2911          */
2912         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2913         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2914
2915         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2916
2917         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2918         if (status) {
2919                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2920                 return status;
2921         }
2922         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2923         return status;
2924 }
2925
2926 /* Initialize the frame-to-queue routing. */
2927 static int ql_route_initialize(struct ql_adapter *qdev)
2928 {
2929         int status = 0;
2930         int i;
2931
2932         /* Clear all the entries in the routing table. */
2933         for (i = 0; i < 16; i++) {
2934                 status = ql_set_routing_reg(qdev, i, 0, 0);
2935                 if (status) {
2936                         QPRINTK(qdev, IFUP, ERR,
2937                                 "Failed to init routing register for CAM packets.\n");
2938                         return status;
2939                 }
2940         }
2941
2942         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2943         if (status) {
2944                 QPRINTK(qdev, IFUP, ERR,
2945                         "Failed to init routing register for error packets.\n");
2946                 return status;
2947         }
2948         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2949         if (status) {
2950                 QPRINTK(qdev, IFUP, ERR,
2951                         "Failed to init routing register for broadcast packets.\n");
2952                 return status;
2953         }
2954         /* If we have more than one inbound queue, then turn on RSS in the
2955          * routing block.
2956          */
2957         if (qdev->rss_ring_count > 1) {
2958                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2959                                         RT_IDX_RSS_MATCH, 1);
2960                 if (status) {
2961                         QPRINTK(qdev, IFUP, ERR,
2962                                 "Failed to init routing register for MATCH RSS packets.\n");
2963                         return status;
2964                 }
2965         }
2966
2967         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2968                                     RT_IDX_CAM_HIT, 1);
2969         if (status) {
2970                 QPRINTK(qdev, IFUP, ERR,
2971                         "Failed to init routing register for CAM packets.\n");
2972                 return status;
2973         }
2974         return status;
2975 }
2976
2977 static int ql_adapter_initialize(struct ql_adapter *qdev)
2978 {
2979         u32 value, mask;
2980         int i;
2981         int status = 0;
2982
2983         /*
2984          * Set up the System register to halt on errors.
2985          */
2986         value = SYS_EFE | SYS_FAE;
2987         mask = value << 16;
2988         ql_write32(qdev, SYS, mask | value);
2989
2990         /* Set the default queue, and VLAN behavior. */
2991         value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
2992         mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
2993         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2994
2995         /* Set the MPI interrupt to enabled. */
2996         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2997
2998         /* Enable the function, set pagesize, enable error checking. */
2999         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3000             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3001
3002         /* Set/clear header splitting. */
3003         mask = FSC_VM_PAGESIZE_MASK |
3004             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3005         ql_write32(qdev, FSC, mask | value);
3006
3007         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3008                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3009
3010         /* Start up the rx queues. */
3011         for (i = 0; i < qdev->rx_ring_count; i++) {
3012                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3013                 if (status) {
3014                         QPRINTK(qdev, IFUP, ERR,
3015                                 "Failed to start rx ring[%d].\n", i);
3016                         return status;
3017                 }
3018         }
3019
3020         /* If there is more than one inbound completion queue
3021          * then download a RICB to configure RSS.
3022          */
3023         if (qdev->rss_ring_count > 1) {
3024                 status = ql_start_rss(qdev);
3025                 if (status) {
3026                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3027                         return status;
3028                 }
3029         }
3030
3031         /* Start up the tx queues. */
3032         for (i = 0; i < qdev->tx_ring_count; i++) {
3033                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3034                 if (status) {
3035                         QPRINTK(qdev, IFUP, ERR,
3036                                 "Failed to start tx ring[%d].\n", i);
3037                         return status;
3038                 }
3039         }
3040
3041         status = ql_port_initialize(qdev);
3042         if (status) {
3043                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3044                 return status;
3045         }
3046
3047         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3048                                      MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3049         if (status) {
3050                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3051                 return status;
3052         }
3053
3054         status = ql_route_initialize(qdev);
3055         if (status) {
3056                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3057                 return status;
3058         }
3059
3060         /* Start NAPI for the RSS queues. */
3061         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3062                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3063                         i);
3064                 napi_enable(&qdev->rx_ring[i].napi);
3065         }
3066
3067         return status;
3068 }
3069
3070 /* Issue soft reset to chip. */
3071 static int ql_adapter_reset(struct ql_adapter *qdev)
3072 {
3073         u32 value;
3074         int max_wait_time;
3075         int status = 0;
3076         int resetCnt = 0;
3077
3078 #define MAX_RESET_CNT   1
3079 issueReset:
3080         resetCnt++;
3081         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3082         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3083         /* Wait for reset to complete. */
3084         max_wait_time = 3;
3085         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3086                 max_wait_time);
3087         do {
3088                 value = ql_read32(qdev, RST_FO);
3089                 if ((value & RST_FO_FR) == 0)
3090                         break;
3091
3092                 ssleep(1);
3093         } while ((--max_wait_time));
3094         if (value & RST_FO_FR) {
3095                 QPRINTK(qdev, IFDOWN, ERR,
3096                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3097                 if (resetCnt < MAX_RESET_CNT)
3098                         goto issueReset;
3099         }
3100         if (max_wait_time == 0) {
3101                 status = -ETIMEDOUT;
3102                 QPRINTK(qdev, IFDOWN, ERR,
3103                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3104         }
3105
3106         return status;
3107 }
3108
3109 static void ql_display_dev_info(struct net_device *ndev)
3110 {
3111         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3112
3113         QPRINTK(qdev, PROBE, INFO,
3114                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3115                 "XG Roll = %d, XG Rev = %d.\n",
3116                 qdev->func,
3117                 qdev->chip_rev_id & 0x0000000f,
3118                 qdev->chip_rev_id >> 4 & 0x0000000f,
3119                 qdev->chip_rev_id >> 8 & 0x0000000f,
3120                 qdev->chip_rev_id >> 12 & 0x0000000f);
3121         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3122 }
3123
3124 static int ql_adapter_down(struct ql_adapter *qdev)
3125 {
3126         struct net_device *ndev = qdev->ndev;
3127         int i, status = 0;
3128         struct rx_ring *rx_ring;
3129
3130         netif_stop_queue(ndev);
3131         netif_carrier_off(ndev);
3132
3133         /* Don't kill the reset worker thread if we
3134          * are in the process of recovery.
3135          */
3136         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3137                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3138         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3139         cancel_delayed_work_sync(&qdev->mpi_work);
3140
3141         /* The default queue at index 0 is always processed in
3142          * a workqueue.
3143          */
3144         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3145
3146         /* The rest of the rx_rings are processed in
3147          * a workqueue only if it's a single interrupt
3148          * environment (MSI/Legacy).
3149          */
3150         for (i = 1; i < qdev->rx_ring_count; i++) {
3151                 rx_ring = &qdev->rx_ring[i];
3152                 /* Only the RSS rings use NAPI on multi irq
3153                  * environment.  Outbound completion processing
3154                  * is done in interrupt context.
3155                  */
3156                 if (i >= qdev->rss_ring_first_cq_id) {
3157                         napi_disable(&rx_ring->napi);
3158                 } else {
3159                         cancel_delayed_work_sync(&rx_ring->rx_work);
3160                 }
3161         }
3162
3163         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3164
3165         ql_disable_interrupts(qdev);
3166
3167         ql_tx_ring_clean(qdev);
3168
3169         /* Call netif_napi_del() from common point.
3170          */
3171         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3172                 netif_napi_del(&qdev->rx_ring[i].napi);
3173
3174         spin_lock(&qdev->hw_lock);
3175         status = ql_adapter_reset(qdev);
3176         if (status)
3177                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3178                         qdev->func);
3179         spin_unlock(&qdev->hw_lock);
3180         return status;
3181 }
3182
3183 static int ql_adapter_up(struct ql_adapter *qdev)
3184 {
3185         int err = 0;
3186
3187         spin_lock(&qdev->hw_lock);
3188         err = ql_adapter_initialize(qdev);
3189         if (err) {
3190                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3191                 spin_unlock(&qdev->hw_lock);
3192                 goto err_init;
3193         }
3194         spin_unlock(&qdev->hw_lock);
3195         set_bit(QL_ADAPTER_UP, &qdev->flags);
3196         ql_enable_interrupts(qdev);
3197         ql_enable_all_completion_interrupts(qdev);
3198         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3199                 netif_carrier_on(qdev->ndev);
3200                 netif_start_queue(qdev->ndev);
3201         }
3202
3203         return 0;
3204 err_init:
3205         ql_adapter_reset(qdev);
3206         return err;
3207 }
3208
3209 static int ql_cycle_adapter(struct ql_adapter *qdev)
3210 {
3211         int status;
3212
3213         status = ql_adapter_down(qdev);
3214         if (status)
3215                 goto error;
3216
3217         status = ql_adapter_up(qdev);
3218         if (status)
3219                 goto error;
3220
3221         return status;
3222 error:
3223         QPRINTK(qdev, IFUP, ALERT,
3224                 "Driver up/down cycle failed, closing device\n");
3225         rtnl_lock();
3226         dev_close(qdev->ndev);
3227         rtnl_unlock();
3228         return status;
3229 }
3230
3231 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3232 {
3233         ql_free_mem_resources(qdev);
3234         ql_free_irq(qdev);
3235 }
3236
3237 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3238 {
3239         int status = 0;
3240
3241         if (ql_alloc_mem_resources(qdev)) {
3242                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3243                 return -ENOMEM;
3244         }
3245         status = ql_request_irq(qdev);
3246         if (status)
3247                 goto err_irq;
3248         return status;
3249 err_irq:
3250         ql_free_mem_resources(qdev);
3251         return status;
3252 }
3253
3254 static int qlge_close(struct net_device *ndev)
3255 {
3256         struct ql_adapter *qdev = netdev_priv(ndev);
3257
3258         /*
3259          * Wait for device to recover from a reset.
3260          * (Rarely happens, but possible.)
3261          */
3262         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3263                 msleep(1);
3264         ql_adapter_down(qdev);
3265         ql_release_adapter_resources(qdev);
3266         return 0;
3267 }
3268
3269 static int ql_configure_rings(struct ql_adapter *qdev)
3270 {
3271         int i;
3272         struct rx_ring *rx_ring;
3273         struct tx_ring *tx_ring;
3274         int cpu_cnt = num_online_cpus();
3275
3276         /*
3277          * For each processor present we allocate one
3278          * rx_ring for outbound completions, and one
3279          * rx_ring for inbound completions.  Plus there is
3280          * always the one default queue.  For the CPU
3281          * counts we end up with the following rx_rings:
3282          * rx_ring count =
3283          *  one default queue +
3284          *  (CPU count * outbound completion rx_ring) +
3285          *  (CPU count * inbound (RSS) completion rx_ring)
3286          * To keep it simple we limit the total number of
3287          * queues to < 32, so we truncate CPU to 8.
3288          * This limitation can be removed when requested.
3289          */
3290
3291         if (cpu_cnt > MAX_CPUS)
3292                 cpu_cnt = MAX_CPUS;
3293
3294         /*
3295          * rx_ring[0] is always the default queue.
3296          */
3297         /* Allocate outbound completion ring for each CPU. */
3298         qdev->tx_ring_count = cpu_cnt;
3299         /* Allocate inbound completion (RSS) ring for each CPU. */
3300         qdev->rss_ring_count = cpu_cnt;
3301         /* cq_id for the first inbound ring handler. */
3302         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3303         /*
3304          * qdev->rx_ring_count:
3305          * Total number of rx_rings.  This includes the one
3306          * default queue, a number of outbound completion
3307          * handler rx_rings, and the number of inbound
3308          * completion handler rx_rings.
3309          */
3310         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3311
3312         for (i = 0; i < qdev->tx_ring_count; i++) {
3313                 tx_ring = &qdev->tx_ring[i];
3314                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3315                 tx_ring->qdev = qdev;
3316                 tx_ring->wq_id = i;
3317                 tx_ring->wq_len = qdev->tx_ring_size;
3318                 tx_ring->wq_size =
3319                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3320
3321                 /*
3322                  * The completion queue ID for the tx rings start
3323                  * immediately after the default Q ID, which is zero.
3324                  */
3325                 tx_ring->cq_id = i + 1;
3326         }
3327
3328         for (i = 0; i < qdev->rx_ring_count; i++) {
3329                 rx_ring = &qdev->rx_ring[i];
3330                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3331                 rx_ring->qdev = qdev;
3332                 rx_ring->cq_id = i;
3333                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3334                 if (i == 0) {   /* Default queue at index 0. */
3335                         /*
3336                          * Default queue handles bcast/mcast plus
3337                          * async events.  Needs buffers.
3338                          */
3339                         rx_ring->cq_len = qdev->rx_ring_size;
3340                         rx_ring->cq_size =
3341                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3342                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3343                         rx_ring->lbq_size =
3344                             rx_ring->lbq_len * sizeof(__le64);
3345                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3346                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3347                         rx_ring->sbq_size =
3348                             rx_ring->sbq_len * sizeof(__le64);
3349                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3350                         rx_ring->type = DEFAULT_Q;
3351                 } else if (i < qdev->rss_ring_first_cq_id) {
3352                         /*
3353                          * Outbound queue handles outbound completions only.
3354                          */
3355                         /* outbound cq is same size as tx_ring it services. */
3356                         rx_ring->cq_len = qdev->tx_ring_size;
3357                         rx_ring->cq_size =
3358                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3359                         rx_ring->lbq_len = 0;
3360                         rx_ring->lbq_size = 0;
3361                         rx_ring->lbq_buf_size = 0;
3362                         rx_ring->sbq_len = 0;
3363                         rx_ring->sbq_size = 0;
3364                         rx_ring->sbq_buf_size = 0;
3365                         rx_ring->type = TX_Q;
3366                 } else {        /* Inbound completions (RSS) queues */
3367                         /*
3368                          * Inbound queues handle unicast frames only.
3369                          */
3370                         rx_ring->cq_len = qdev->rx_ring_size;
3371                         rx_ring->cq_size =
3372                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3373                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3374                         rx_ring->lbq_size =
3375                             rx_ring->lbq_len * sizeof(__le64);
3376                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3377                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3378                         rx_ring->sbq_size =
3379                             rx_ring->sbq_len * sizeof(__le64);
3380                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3381                         rx_ring->type = RX_Q;
3382                 }
3383         }
3384         return 0;
3385 }
3386
3387 static int qlge_open(struct net_device *ndev)
3388 {
3389         int err = 0;
3390         struct ql_adapter *qdev = netdev_priv(ndev);
3391
3392         err = ql_configure_rings(qdev);
3393         if (err)
3394                 return err;
3395
3396         err = ql_get_adapter_resources(qdev);
3397         if (err)
3398                 goto error_up;
3399
3400         err = ql_adapter_up(qdev);
3401         if (err)
3402                 goto error_up;
3403
3404         return err;
3405
3406 error_up:
3407         ql_release_adapter_resources(qdev);
3408         return err;
3409 }
3410
3411 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3412 {
3413         struct ql_adapter *qdev = netdev_priv(ndev);
3414
3415         if (ndev->mtu == 1500 && new_mtu == 9000) {
3416                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3417         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3418                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3419         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3420                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3421                 return 0;
3422         } else
3423                 return -EINVAL;
3424         ndev->mtu = new_mtu;
3425         return 0;
3426 }
3427
3428 static struct net_device_stats *qlge_get_stats(struct net_device
3429                                                *ndev)
3430 {
3431         struct ql_adapter *qdev = netdev_priv(ndev);
3432         return &qdev->stats;
3433 }
3434
3435 static void qlge_set_multicast_list(struct net_device *ndev)
3436 {
3437         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3438         struct dev_mc_list *mc_ptr;
3439         int i;
3440
3441         spin_lock(&qdev->hw_lock);
3442         /*
3443          * Set or clear promiscuous mode if a
3444          * transition is taking place.
3445          */
3446         if (ndev->flags & IFF_PROMISC) {
3447                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3448                         if (ql_set_routing_reg
3449                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3450                                 QPRINTK(qdev, HW, ERR,
3451                                         "Failed to set promiscous mode.\n");
3452                         } else {
3453                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3454                         }
3455                 }
3456         } else {
3457                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3458                         if (ql_set_routing_reg
3459                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3460                                 QPRINTK(qdev, HW, ERR,
3461                                         "Failed to clear promiscous mode.\n");
3462                         } else {
3463                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3464                         }
3465                 }
3466         }
3467
3468         /*
3469          * Set or clear all multicast mode if a
3470          * transition is taking place.
3471          */
3472         if ((ndev->flags & IFF_ALLMULTI) ||
3473             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3474                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3475                         if (ql_set_routing_reg
3476                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3477                                 QPRINTK(qdev, HW, ERR,
3478                                         "Failed to set all-multi mode.\n");
3479                         } else {
3480                                 set_bit(QL_ALLMULTI, &qdev->flags);
3481                         }
3482                 }
3483         } else {
3484                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3485                         if (ql_set_routing_reg
3486                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3487                                 QPRINTK(qdev, HW, ERR,
3488                                         "Failed to clear all-multi mode.\n");
3489                         } else {
3490                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3491                         }
3492                 }
3493         }
3494
3495         if (ndev->mc_count) {
3496                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3497                      i++, mc_ptr = mc_ptr->next)
3498                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3499                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3500                                 QPRINTK(qdev, HW, ERR,
3501                                         "Failed to loadmulticast address.\n");
3502                                 goto exit;
3503                         }
3504                 if (ql_set_routing_reg
3505                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3506                         QPRINTK(qdev, HW, ERR,
3507                                 "Failed to set multicast match mode.\n");
3508                 } else {
3509                         set_bit(QL_ALLMULTI, &qdev->flags);
3510                 }
3511         }
3512 exit:
3513         spin_unlock(&qdev->hw_lock);
3514 }
3515
3516 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3517 {
3518         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3519         struct sockaddr *addr = p;
3520         int ret = 0;
3521
3522         if (netif_running(ndev))
3523                 return -EBUSY;
3524
3525         if (!is_valid_ether_addr(addr->sa_data))
3526                 return -EADDRNOTAVAIL;
3527         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3528
3529         spin_lock(&qdev->hw_lock);
3530         if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3531                         MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3532                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3533                 ret = -1;
3534         }
3535         spin_unlock(&qdev->hw_lock);
3536
3537         return ret;
3538 }
3539
3540 static void qlge_tx_timeout(struct net_device *ndev)
3541 {
3542         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3543         ql_queue_asic_error(qdev);
3544 }
3545
3546 static void ql_asic_reset_work(struct work_struct *work)
3547 {
3548         struct ql_adapter *qdev =
3549             container_of(work, struct ql_adapter, asic_reset_work.work);
3550         ql_cycle_adapter(qdev);
3551 }
3552
3553 static void ql_get_board_info(struct ql_adapter *qdev)
3554 {
3555         qdev->func =
3556             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3557         if (qdev->func) {
3558                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3559                 qdev->port_link_up = STS_PL1;
3560                 qdev->port_init = STS_PI1;
3561                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3562                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3563         } else {
3564                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3565                 qdev->port_link_up = STS_PL0;
3566                 qdev->port_init = STS_PI0;
3567                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3568                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3569         }
3570         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3571 }
3572
3573 static void ql_release_all(struct pci_dev *pdev)
3574 {
3575         struct net_device *ndev = pci_get_drvdata(pdev);
3576         struct ql_adapter *qdev = netdev_priv(ndev);
3577
3578         if (qdev->workqueue) {
3579                 destroy_workqueue(qdev->workqueue);
3580                 qdev->workqueue = NULL;
3581         }
3582         if (qdev->q_workqueue) {
3583                 destroy_workqueue(qdev->q_workqueue);
3584                 qdev->q_workqueue = NULL;
3585         }
3586         if (qdev->reg_base)
3587                 iounmap(qdev->reg_base);
3588         if (qdev->doorbell_area)
3589                 iounmap(qdev->doorbell_area);
3590         pci_release_regions(pdev);
3591         pci_set_drvdata(pdev, NULL);
3592 }
3593
3594 static int __devinit ql_init_device(struct pci_dev *pdev,
3595                                     struct net_device *ndev, int cards_found)
3596 {
3597         struct ql_adapter *qdev = netdev_priv(ndev);
3598         int pos, err = 0;
3599         u16 val16;
3600
3601         memset((void *)qdev, 0, sizeof(qdev));
3602         err = pci_enable_device(pdev);
3603         if (err) {
3604                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3605                 return err;
3606         }
3607
3608         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3609         if (pos <= 0) {
3610                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3611                         "aborting.\n");
3612                 goto err_out;
3613         } else {
3614                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3615                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3616                 val16 |= (PCI_EXP_DEVCTL_CERE |
3617                           PCI_EXP_DEVCTL_NFERE |
3618                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3619                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3620         }
3621
3622         err = pci_request_regions(pdev, DRV_NAME);
3623         if (err) {
3624                 dev_err(&pdev->dev, "PCI region request failed.\n");
3625                 goto err_out;
3626         }
3627
3628         pci_set_master(pdev);
3629         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3630                 set_bit(QL_DMA64, &qdev->flags);
3631                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3632         } else {
3633                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3634                 if (!err)
3635                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3636         }
3637
3638         if (err) {
3639                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3640                 goto err_out;
3641         }
3642
3643         pci_set_drvdata(pdev, ndev);
3644         qdev->reg_base =
3645             ioremap_nocache(pci_resource_start(pdev, 1),
3646                             pci_resource_len(pdev, 1));
3647         if (!qdev->reg_base) {
3648                 dev_err(&pdev->dev, "Register mapping failed.\n");
3649                 err = -ENOMEM;
3650                 goto err_out;
3651         }
3652
3653         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3654         qdev->doorbell_area =
3655             ioremap_nocache(pci_resource_start(pdev, 3),
3656                             pci_resource_len(pdev, 3));
3657         if (!qdev->doorbell_area) {
3658                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3659                 err = -ENOMEM;
3660                 goto err_out;
3661         }
3662
3663         ql_get_board_info(qdev);
3664         qdev->ndev = ndev;
3665         qdev->pdev = pdev;
3666         qdev->msg_enable = netif_msg_init(debug, default_msg);
3667         spin_lock_init(&qdev->hw_lock);
3668         spin_lock_init(&qdev->stats_lock);
3669
3670         /* make sure the EEPROM is good */
3671         err = ql_get_flash_params(qdev);
3672         if (err) {
3673                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3674                 goto err_out;
3675         }
3676
3677         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3678                 goto err_out;
3679
3680         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3681         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3682
3683         /* Set up the default ring sizes. */
3684         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3685         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3686
3687         /* Set up the coalescing parameters. */
3688         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3689         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3690         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3691         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3692
3693         /*
3694          * Set up the operating parameters.
3695          */
3696         qdev->rx_csum = 1;
3697
3698         qdev->q_workqueue = create_workqueue(ndev->name);
3699         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3700         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3701         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3702         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3703
3704         if (!cards_found) {
3705                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3706                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3707                          DRV_NAME, DRV_VERSION);
3708         }
3709         return 0;
3710 err_out:
3711         ql_release_all(pdev);
3712         pci_disable_device(pdev);
3713         return err;
3714 }
3715
3716
3717 static const struct net_device_ops qlge_netdev_ops = {
3718         .ndo_open               = qlge_open,
3719         .ndo_stop               = qlge_close,
3720         .ndo_start_xmit         = qlge_send,
3721         .ndo_change_mtu         = qlge_change_mtu,
3722         .ndo_get_stats          = qlge_get_stats,
3723         .ndo_set_multicast_list = qlge_set_multicast_list,
3724         .ndo_set_mac_address    = qlge_set_mac_address,
3725         .ndo_validate_addr      = eth_validate_addr,
3726         .ndo_tx_timeout         = qlge_tx_timeout,
3727         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3728         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3729         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3730 };
3731
3732 static int __devinit qlge_probe(struct pci_dev *pdev,
3733                                 const struct pci_device_id *pci_entry)
3734 {
3735         struct net_device *ndev = NULL;
3736         struct ql_adapter *qdev = NULL;
3737         static int cards_found = 0;
3738         int err = 0;
3739
3740         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3741         if (!ndev)
3742                 return -ENOMEM;
3743
3744         err = ql_init_device(pdev, ndev, cards_found);
3745         if (err < 0) {
3746                 free_netdev(ndev);
3747                 return err;
3748         }
3749
3750         qdev = netdev_priv(ndev);
3751         SET_NETDEV_DEV(ndev, &pdev->dev);
3752         ndev->features = (0
3753                           | NETIF_F_IP_CSUM
3754                           | NETIF_F_SG
3755                           | NETIF_F_TSO
3756                           | NETIF_F_TSO6
3757                           | NETIF_F_TSO_ECN
3758                           | NETIF_F_HW_VLAN_TX
3759                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3760
3761         if (test_bit(QL_DMA64, &qdev->flags))
3762                 ndev->features |= NETIF_F_HIGHDMA;
3763
3764         /*
3765          * Set up net_device structure.
3766          */
3767         ndev->tx_queue_len = qdev->tx_ring_size;
3768         ndev->irq = pdev->irq;
3769
3770         ndev->netdev_ops = &qlge_netdev_ops;
3771         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3772         ndev->watchdog_timeo = 10 * HZ;
3773
3774         err = register_netdev(ndev);
3775         if (err) {
3776                 dev_err(&pdev->dev, "net device registration failed.\n");
3777                 ql_release_all(pdev);
3778                 pci_disable_device(pdev);
3779                 return err;
3780         }
3781         netif_carrier_off(ndev);
3782         netif_stop_queue(ndev);
3783         ql_display_dev_info(ndev);
3784         cards_found++;
3785         return 0;
3786 }
3787
3788 static void __devexit qlge_remove(struct pci_dev *pdev)
3789 {
3790         struct net_device *ndev = pci_get_drvdata(pdev);
3791         unregister_netdev(ndev);
3792         ql_release_all(pdev);
3793         pci_disable_device(pdev);
3794         free_netdev(ndev);
3795 }
3796
3797 /*
3798  * This callback is called by the PCI subsystem whenever
3799  * a PCI bus error is detected.
3800  */
3801 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3802                                                enum pci_channel_state state)
3803 {
3804         struct net_device *ndev = pci_get_drvdata(pdev);
3805         struct ql_adapter *qdev = netdev_priv(ndev);
3806
3807         if (netif_running(ndev))
3808                 ql_adapter_down(qdev);
3809
3810         pci_disable_device(pdev);
3811
3812         /* Request a slot reset. */
3813         return PCI_ERS_RESULT_NEED_RESET;
3814 }
3815
3816 /*
3817  * This callback is called after the PCI buss has been reset.
3818  * Basically, this tries to restart the card from scratch.
3819  * This is a shortened version of the device probe/discovery code,
3820  * it resembles the first-half of the () routine.
3821  */
3822 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3823 {
3824         struct net_device *ndev = pci_get_drvdata(pdev);
3825         struct ql_adapter *qdev = netdev_priv(ndev);
3826
3827         if (pci_enable_device(pdev)) {
3828                 QPRINTK(qdev, IFUP, ERR,
3829                         "Cannot re-enable PCI device after reset.\n");
3830                 return PCI_ERS_RESULT_DISCONNECT;
3831         }
3832
3833         pci_set_master(pdev);
3834
3835         netif_carrier_off(ndev);
3836         netif_stop_queue(ndev);
3837         ql_adapter_reset(qdev);
3838
3839         /* Make sure the EEPROM is good */
3840         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3841
3842         if (!is_valid_ether_addr(ndev->perm_addr)) {
3843                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3844                 return PCI_ERS_RESULT_DISCONNECT;
3845         }
3846
3847         return PCI_ERS_RESULT_RECOVERED;
3848 }
3849
3850 static void qlge_io_resume(struct pci_dev *pdev)
3851 {
3852         struct net_device *ndev = pci_get_drvdata(pdev);
3853         struct ql_adapter *qdev = netdev_priv(ndev);
3854
3855         pci_set_master(pdev);
3856
3857         if (netif_running(ndev)) {
3858                 if (ql_adapter_up(qdev)) {
3859                         QPRINTK(qdev, IFUP, ERR,
3860                                 "Device initialization failed after reset.\n");
3861                         return;
3862                 }
3863         }
3864
3865         netif_device_attach(ndev);
3866 }
3867
3868 static struct pci_error_handlers qlge_err_handler = {
3869         .error_detected = qlge_io_error_detected,
3870         .slot_reset = qlge_io_slot_reset,
3871         .resume = qlge_io_resume,
3872 };
3873
3874 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3875 {
3876         struct net_device *ndev = pci_get_drvdata(pdev);
3877         struct ql_adapter *qdev = netdev_priv(ndev);
3878         int err;
3879
3880         netif_device_detach(ndev);
3881
3882         if (netif_running(ndev)) {
3883                 err = ql_adapter_down(qdev);
3884                 if (!err)
3885                         return err;
3886         }
3887
3888         err = pci_save_state(pdev);
3889         if (err)
3890                 return err;
3891
3892         pci_disable_device(pdev);
3893
3894         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3895
3896         return 0;
3897 }
3898
3899 #ifdef CONFIG_PM
3900 static int qlge_resume(struct pci_dev *pdev)
3901 {
3902         struct net_device *ndev = pci_get_drvdata(pdev);
3903         struct ql_adapter *qdev = netdev_priv(ndev);
3904         int err;
3905
3906         pci_set_power_state(pdev, PCI_D0);
3907         pci_restore_state(pdev);
3908         err = pci_enable_device(pdev);
3909         if (err) {
3910                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3911                 return err;
3912         }
3913         pci_set_master(pdev);
3914
3915         pci_enable_wake(pdev, PCI_D3hot, 0);
3916         pci_enable_wake(pdev, PCI_D3cold, 0);
3917
3918         if (netif_running(ndev)) {
3919                 err = ql_adapter_up(qdev);
3920                 if (err)
3921                         return err;
3922         }
3923
3924         netif_device_attach(ndev);
3925
3926         return 0;
3927 }
3928 #endif /* CONFIG_PM */
3929
3930 static void qlge_shutdown(struct pci_dev *pdev)
3931 {
3932         qlge_suspend(pdev, PMSG_SUSPEND);
3933 }
3934
3935 static struct pci_driver qlge_driver = {
3936         .name = DRV_NAME,
3937         .id_table = qlge_pci_tbl,
3938         .probe = qlge_probe,
3939         .remove = __devexit_p(qlge_remove),
3940 #ifdef CONFIG_PM
3941         .suspend = qlge_suspend,
3942         .resume = qlge_resume,
3943 #endif
3944         .shutdown = qlge_shutdown,
3945         .err_handler = &qlge_err_handler
3946 };
3947
3948 static int __init qlge_init_module(void)
3949 {
3950         return pci_register_driver(&qlge_driver);
3951 }
3952
3953 static void __exit qlge_exit(void)
3954 {
3955         pci_unregister_driver(&qlge_driver);
3956 }
3957
3958 module_init(qlge_init_module);
3959 module_exit(qlge_exit);