Merge branch 'for-linus' of git://git.o-hand.com/linux-rpurdie-leds
[linux-2.6] / arch / arm / mach-pxa / corgi_lcd.c
1 /*
2  * linux/arch/arm/mach-pxa/corgi_lcd.c
3  *
4  * Corgi/Spitz LCD Specific Code
5  *
6  * Copyright (C) 2005 Richard Purdie
7  *
8  * Connectivity:
9  *   Corgi - LCD to ATI Imageon w100 (Wallaby)
10  *   Spitz - LCD to PXA Framebuffer
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  *
16  */
17
18 #include <linux/delay.h>
19 #include <linux/kernel.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/string.h>
23 #include <mach/corgi.h>
24 #include <mach/hardware.h>
25 #include <mach/pxa-regs.h>
26 #include <mach/sharpsl.h>
27 #include <mach/spitz.h>
28 #include <asm/hardware/scoop.h>
29 #include <asm/mach/sharpsl_param.h>
30 #include "generic.h"
31
32 /* Register Addresses */
33 #define RESCTL_ADRS     0x00
34 #define PHACTRL_ADRS    0x01
35 #define DUTYCTRL_ADRS   0x02
36 #define POWERREG0_ADRS  0x03
37 #define POWERREG1_ADRS  0x04
38 #define GPOR3_ADRS      0x05
39 #define PICTRL_ADRS     0x06
40 #define POLCTRL_ADRS    0x07
41
42 /* Register Bit Definitions */
43 #define RESCTL_QVGA     0x01
44 #define RESCTL_VGA      0x00
45
46 #define POWER1_VW_ON    0x01  /* VW Supply FET ON */
47 #define POWER1_GVSS_ON  0x02  /* GVSS(-8V) Power Supply ON */
48 #define POWER1_VDD_ON   0x04  /* VDD(8V),SVSS(-4V) Power Supply ON */
49
50 #define POWER1_VW_OFF   0x00  /* VW Supply FET OFF */
51 #define POWER1_GVSS_OFF 0x00  /* GVSS(-8V) Power Supply OFF */
52 #define POWER1_VDD_OFF  0x00  /* VDD(8V),SVSS(-4V) Power Supply OFF */
53
54 #define POWER0_COM_DCLK 0x01  /* COM Voltage DC Bias DAC Serial Data Clock */
55 #define POWER0_COM_DOUT 0x02  /* COM Voltage DC Bias DAC Serial Data Out */
56 #define POWER0_DAC_ON   0x04  /* DAC Power Supply ON */
57 #define POWER0_COM_ON   0x08  /* COM Power Supply ON */
58 #define POWER0_VCC5_ON  0x10  /* VCC5 Power Supply ON */
59
60 #define POWER0_DAC_OFF  0x00  /* DAC Power Supply OFF */
61 #define POWER0_COM_OFF  0x00  /* COM Power Supply OFF */
62 #define POWER0_VCC5_OFF 0x00  /* VCC5 Power Supply OFF */
63
64 #define PICTRL_INIT_STATE      0x01
65 #define PICTRL_INIOFF          0x02
66 #define PICTRL_POWER_DOWN      0x04
67 #define PICTRL_COM_SIGNAL_OFF  0x08
68 #define PICTRL_DAC_SIGNAL_OFF  0x10
69
70 #define POLCTRL_SYNC_POL_FALL  0x01
71 #define POLCTRL_EN_POL_FALL    0x02
72 #define POLCTRL_DATA_POL_FALL  0x04
73 #define POLCTRL_SYNC_ACT_H     0x08
74 #define POLCTRL_EN_ACT_L       0x10
75
76 #define POLCTRL_SYNC_POL_RISE  0x00
77 #define POLCTRL_EN_POL_RISE    0x00
78 #define POLCTRL_DATA_POL_RISE  0x00
79 #define POLCTRL_SYNC_ACT_L     0x00
80 #define POLCTRL_EN_ACT_H       0x00
81
82 #define PHACTRL_PHASE_MANUAL   0x01
83 #define DEFAULT_PHAD_QVGA     (9)
84 #define DEFAULT_COMADJ        (125)
85
86 /*
87  * This is only a psuedo I2C interface. We can't use the standard kernel
88  * routines as the interface is write only. We just assume the data is acked...
89  */
90 static void lcdtg_ssp_i2c_send(u8 data)
91 {
92         corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
93         udelay(10);
94 }
95
96 static void lcdtg_i2c_send_bit(u8 data)
97 {
98         lcdtg_ssp_i2c_send(data);
99         lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
100         lcdtg_ssp_i2c_send(data);
101 }
102
103 static void lcdtg_i2c_send_start(u8 base)
104 {
105         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
106         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
107         lcdtg_ssp_i2c_send(base);
108 }
109
110 static void lcdtg_i2c_send_stop(u8 base)
111 {
112         lcdtg_ssp_i2c_send(base);
113         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
114         lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
115 }
116
117 static void lcdtg_i2c_send_byte(u8 base, u8 data)
118 {
119         int i;
120         for (i = 0; i < 8; i++) {
121                 if (data & 0x80)
122                         lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
123                 else
124                         lcdtg_i2c_send_bit(base);
125                 data <<= 1;
126         }
127 }
128
129 static void lcdtg_i2c_wait_ack(u8 base)
130 {
131         lcdtg_i2c_send_bit(base);
132 }
133
134 static void lcdtg_set_common_voltage(u8 base_data, u8 data)
135 {
136         /* Set Common Voltage to M62332FP via I2C */
137         lcdtg_i2c_send_start(base_data);
138         lcdtg_i2c_send_byte(base_data, 0x9c);
139         lcdtg_i2c_wait_ack(base_data);
140         lcdtg_i2c_send_byte(base_data, 0x00);
141         lcdtg_i2c_wait_ack(base_data);
142         lcdtg_i2c_send_byte(base_data, data);
143         lcdtg_i2c_wait_ack(base_data);
144         lcdtg_i2c_send_stop(base_data);
145 }
146
147 /* Set Phase Adjust */
148 static void lcdtg_set_phadadj(int mode)
149 {
150         int adj;
151         switch(mode) {
152                 case 480:
153                 case 640:
154                         /* Setting for VGA */
155                         adj = sharpsl_param.phadadj;
156                         if (adj < 0) {
157                                 adj = PHACTRL_PHASE_MANUAL;
158                         } else {
159                                 adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
160                         }
161                         break;
162                 case 240:
163                 case 320:
164                 default:
165                         /* Setting for QVGA */
166                         adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
167                         break;
168         }
169
170         corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
171 }
172
173 static int lcd_inited;
174
175 void corgi_lcdtg_hw_init(int mode)
176 {
177         if (!lcd_inited) {
178                 int comadj;
179
180                 /* Initialize Internal Logic & Port */
181                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
182                                 | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
183
184                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
185                                 | POWER0_COM_OFF | POWER0_VCC5_OFF);
186
187                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
188
189                 /* VDD(+8V), SVSS(-4V) ON */
190                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
191                 mdelay(3);
192
193                 /* DAC ON */
194                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
195                                 | POWER0_COM_OFF | POWER0_VCC5_OFF);
196
197                 /* INIB = H, INI = L  */
198                 /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
199                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
200
201                 /* Set Common Voltage */
202                 comadj = sharpsl_param.comadj;
203                 if (comadj < 0)
204                         comadj = DEFAULT_COMADJ;
205                 lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
206
207                 /* VCC5 ON, DAC ON */
208                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
209                                 POWER0_COM_OFF | POWER0_VCC5_ON);
210
211                 /* GVSS(-8V) ON, VDD ON */
212                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
213                 mdelay(2);
214
215                 /* COM SIGNAL ON (PICTL[3] = L) */
216                 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
217
218                 /* COM ON, DAC ON, VCC5_ON */
219                 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
220                                 | POWER0_COM_ON | POWER0_VCC5_ON);
221
222                 /* VW ON, GVSS ON, VDD ON */
223                 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
224
225                 /* Signals output enable */
226                 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
227
228                 /* Set Phase Adjust */
229                 lcdtg_set_phadadj(mode);
230
231                 /* Initialize for Input Signals from ATI */
232                 corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
233                                 | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
234                 udelay(1000);
235
236                 lcd_inited=1;
237         } else {
238                 lcdtg_set_phadadj(mode);
239         }
240
241         switch(mode) {
242                 case 480:
243                 case 640:
244                         /* Set Lcd Resolution (VGA) */
245                         corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
246                         break;
247                 case 240:
248                 case 320:
249                 default:
250                         /* Set Lcd Resolution (QVGA) */
251                         corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
252                         break;
253         }
254 }
255
256 void corgi_lcdtg_suspend(void)
257 {
258         /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
259         mdelay(34);
260
261         /* (1)VW OFF */
262         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
263
264         /* (2)COM OFF */
265         corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
266         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
267
268         /* (3)Set Common Voltage Bias 0V */
269         lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
270
271         /* (4)GVSS OFF */
272         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
273
274         /* (5)VCC5 OFF */
275         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
276
277         /* (6)Set PDWN, INIOFF, DACOFF */
278         corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
279                         PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
280
281         /* (7)DAC OFF */
282         corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
283
284         /* (8)VDD OFF */
285         corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
286
287         lcd_inited = 0;
288 }
289