Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/jk/spufs into...
[linux-2.6] / arch / arm / mach-ixp2000 / core.c
1 /*
2  * arch/arm/mach-ixp2000/core.c
3  *
4  * Common routines used by all IXP2400/2800 based platforms.
5  *
6  * Author: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright 2004 (C) MontaVista Software, Inc. 
9  *
10  * Based on work Copyright (C) 2002-2003 Intel Corporation
11  * 
12  * This file is licensed under the terms of the GNU General Public
13  * License version 2. This program is licensed "as is" without any 
14  * warranty of any kind, whether express or implied.
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/bitops.h>
26 #include <linux/serial_8250.h>
27 #include <linux/mm.h>
28
29 #include <asm/types.h>
30 #include <asm/setup.h>
31 #include <asm/memory.h>
32 #include <mach/hardware.h>
33 #include <asm/irq.h>
34 #include <asm/system.h>
35 #include <asm/tlbflush.h>
36 #include <asm/pgtable.h>
37
38 #include <asm/mach/map.h>
39 #include <asm/mach/time.h>
40 #include <asm/mach/irq.h>
41
42 #include <mach/gpio.h>
43
44 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
45 static unsigned long ixp2000_slowport_irq_flags;
46
47 /*************************************************************************
48  * Slowport access routines
49  *************************************************************************/
50 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
51 {
52         spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
53
54         old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
55         old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
56         old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
57         old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
58         old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
59
60         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
61         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
62         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
63         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
64         ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
65 }
66
67 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
68 {
69         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
70         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
71         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
72         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
73         ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
74
75         spin_unlock_irqrestore(&ixp2000_slowport_lock, 
76                                         ixp2000_slowport_irq_flags);
77 }
78
79 /*************************************************************************
80  * Chip specific mappings shared by all IXP2000 systems
81  *************************************************************************/
82 static struct map_desc ixp2000_io_desc[] __initdata = {
83         {
84                 .virtual        = IXP2000_CAP_VIRT_BASE,
85                 .pfn            = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
86                 .length         = IXP2000_CAP_SIZE,
87                 .type           = MT_DEVICE_IXP2000,
88         }, {
89                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
90                 .pfn            = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
91                 .length         = IXP2000_INTCTL_SIZE,
92                 .type           = MT_DEVICE_IXP2000,
93         }, {
94                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
95                 .pfn            = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
96                 .length         = IXP2000_PCI_CREG_SIZE,
97                 .type           = MT_DEVICE_IXP2000,
98         }, {
99                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
100                 .pfn            = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
101                 .length         = IXP2000_PCI_CSR_SIZE,
102                 .type           = MT_DEVICE_IXP2000,
103         }, {
104                 .virtual        = IXP2000_MSF_VIRT_BASE,
105                 .pfn            = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
106                 .length         = IXP2000_MSF_SIZE,
107                 .type           = MT_DEVICE_IXP2000,
108         }, {
109                 .virtual        = IXP2000_SCRATCH_RING_VIRT_BASE,
110                 .pfn            = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
111                 .length         = IXP2000_SCRATCH_RING_SIZE,
112                 .type           = MT_DEVICE_IXP2000,
113         }, {
114                 .virtual        = IXP2000_SRAM0_VIRT_BASE,
115                 .pfn            = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
116                 .length         = IXP2000_SRAM0_SIZE,
117                 .type           = MT_DEVICE_IXP2000,
118         }, {
119                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
120                 .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
121                 .length         = IXP2000_PCI_IO_SIZE,
122                 .type           = MT_DEVICE_IXP2000,
123         }, {
124                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
125                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
126                 .length         = IXP2000_PCI_CFG0_SIZE,
127                 .type           = MT_DEVICE_IXP2000,
128         }, {
129                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
130                 .pfn            = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
131                 .length         = IXP2000_PCI_CFG1_SIZE,
132                 .type           = MT_DEVICE_IXP2000,
133         }
134 };
135
136 void __init ixp2000_map_io(void)
137 {
138         /*
139          * On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that
140          * XCB=101 (to avoid triggering erratum #66), and given that
141          * this mode speeds up I/O accesses and we have write buffer
142          * flushes in the right places anyway, it doesn't hurt to use
143          * XCB=101 for all IXP2000s.
144          */
145         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
146
147         /* Set slowport to 8-bit mode.  */
148         ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
149 }
150
151
152 /*************************************************************************
153  * Serial port support for IXP2000
154  *************************************************************************/
155 static struct plat_serial8250_port ixp2000_serial_port[] = {
156         {
157                 .mapbase        = IXP2000_UART_PHYS_BASE,
158                 .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
159                 .irq            = IRQ_IXP2000_UART,
160                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
161                 .iotype         = UPIO_MEM,
162                 .regshift       = 2,
163                 .uartclk        = 50000000,
164         },
165         { },
166 };
167
168 static struct resource ixp2000_uart_resource = {
169         .start          = IXP2000_UART_PHYS_BASE,
170         .end            = IXP2000_UART_PHYS_BASE + 0x1f,
171         .flags          = IORESOURCE_MEM,
172 };
173
174 static struct platform_device ixp2000_serial_device = {
175         .name           = "serial8250",
176         .id             = PLAT8250_DEV_PLATFORM,
177         .dev            = {
178                 .platform_data          = ixp2000_serial_port,
179         },
180         .num_resources  = 1,
181         .resource       = &ixp2000_uart_resource,
182 };
183
184 void __init ixp2000_uart_init(void)
185 {
186         platform_device_register(&ixp2000_serial_device);
187 }
188
189
190 /*************************************************************************
191  * Timer-tick functions for IXP2000
192  *************************************************************************/
193 static unsigned ticks_per_jiffy;
194 static unsigned ticks_per_usec;
195 static unsigned next_jiffy_time;
196 static volatile unsigned long *missing_jiffy_timer_csr;
197
198 unsigned long ixp2000_gettimeoffset (void)
199 {
200         unsigned long offset;
201
202         offset = next_jiffy_time - *missing_jiffy_timer_csr;
203
204         return offset / ticks_per_usec;
205 }
206
207 static int ixp2000_timer_interrupt(int irq, void *dev_id)
208 {
209         /* clear timer 1 */
210         ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
211
212         while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
213                                                         >= ticks_per_jiffy) {
214                 timer_tick();
215                 next_jiffy_time -= ticks_per_jiffy;
216         }
217
218         return IRQ_HANDLED;
219 }
220
221 static struct irqaction ixp2000_timer_irq = {
222         .name           = "IXP2000 Timer Tick",
223         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
224         .handler        = ixp2000_timer_interrupt,
225 };
226
227 void __init ixp2000_init_time(unsigned long tick_rate)
228 {
229         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
230         ticks_per_usec = tick_rate / 1000000;
231
232         /*
233          * We use timer 1 as our timer interrupt.
234          */
235         ixp2000_reg_write(IXP2000_T1_CLR, 0);
236         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
237         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
238
239         /*
240          * We use a second timer as a monotonic counter for tracking
241          * missed jiffies.  The IXP2000 has four timers, but if we're
242          * on an A-step IXP2800, timer 2 and 3 don't work, so on those
243          * chips we use timer 4.  Timer 4 is the only timer that can
244          * be used for the watchdog, so we use timer 2 if we're on a
245          * non-buggy chip.
246          */
247         if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
248                 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
249
250                 ixp2000_reg_write(IXP2000_T4_CLR, 0);
251                 ixp2000_reg_write(IXP2000_T4_CLD, -1);
252                 ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
253                 missing_jiffy_timer_csr = IXP2000_T4_CSR;
254         } else {
255                 ixp2000_reg_write(IXP2000_T2_CLR, 0);
256                 ixp2000_reg_write(IXP2000_T2_CLD, -1);
257                 ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
258                 missing_jiffy_timer_csr = IXP2000_T2_CSR;
259         }
260         next_jiffy_time = 0xffffffff;
261
262         /* register for interrupt */
263         setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
264 }
265
266 /*************************************************************************
267  * GPIO helpers
268  *************************************************************************/
269 static unsigned long GPIO_IRQ_falling_edge;
270 static unsigned long GPIO_IRQ_rising_edge;
271 static unsigned long GPIO_IRQ_level_low;
272 static unsigned long GPIO_IRQ_level_high;
273
274 static void update_gpio_int_csrs(void)
275 {
276         ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
277         ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
278         ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
279         ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
280 }
281
282 void gpio_line_config(int line, int direction)
283 {
284         unsigned long flags;
285
286         local_irq_save(flags);
287         if (direction == GPIO_OUT) {
288                 /* if it's an output, it ain't an interrupt anymore */
289                 GPIO_IRQ_falling_edge &= ~(1 << line);
290                 GPIO_IRQ_rising_edge &= ~(1 << line);
291                 GPIO_IRQ_level_low &= ~(1 << line);
292                 GPIO_IRQ_level_high &= ~(1 << line);
293                 update_gpio_int_csrs();
294
295                 ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
296         } else if (direction == GPIO_IN) {
297                 ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
298         }
299         local_irq_restore(flags);
300 }
301 EXPORT_SYMBOL(gpio_line_config);
302
303
304 /*************************************************************************
305  * IRQ handling IXP2000
306  *************************************************************************/
307 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
308 {                               
309         int i;
310         unsigned long status = *IXP2000_GPIO_INST;
311                    
312         for (i = 0; i <= 7; i++) {
313                 if (status & (1<<i)) {
314                         desc = irq_desc + i + IRQ_IXP2000_GPIO0;
315                         desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc);
316                 }
317         }
318 }
319
320 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
321 {
322         int line = irq - IRQ_IXP2000_GPIO0;
323
324         /*
325          * First, configure this GPIO line as an input.
326          */
327         ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
328
329         /*
330          * Then, set the proper trigger type.
331          */
332         if (type & IRQ_TYPE_EDGE_FALLING)
333                 GPIO_IRQ_falling_edge |= 1 << line;
334         else
335                 GPIO_IRQ_falling_edge &= ~(1 << line);
336         if (type & IRQ_TYPE_EDGE_RISING)
337                 GPIO_IRQ_rising_edge |= 1 << line;
338         else
339                 GPIO_IRQ_rising_edge &= ~(1 << line);
340         if (type & IRQ_TYPE_LEVEL_LOW)
341                 GPIO_IRQ_level_low |= 1 << line;
342         else
343                 GPIO_IRQ_level_low &= ~(1 << line);
344         if (type & IRQ_TYPE_LEVEL_HIGH)
345                 GPIO_IRQ_level_high |= 1 << line;
346         else
347                 GPIO_IRQ_level_high &= ~(1 << line);
348         update_gpio_int_csrs();
349
350         return 0;
351 }
352
353 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
354 {
355         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
356
357         ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
358         ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
359         ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
360 }
361
362 static void ixp2000_GPIO_irq_mask(unsigned int irq)
363 {
364         ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
365 }
366
367 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
368 {
369         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
370 }
371
372 static struct irq_chip ixp2000_GPIO_irq_chip = {
373         .ack            = ixp2000_GPIO_irq_mask_ack,
374         .mask           = ixp2000_GPIO_irq_mask,
375         .unmask         = ixp2000_GPIO_irq_unmask,
376         .set_type       = ixp2000_GPIO_irq_type,
377 };
378
379 static void ixp2000_pci_irq_mask(unsigned int irq)
380 {
381         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
382         if (irq == IRQ_IXP2000_PCIA)
383                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
384         else if (irq == IRQ_IXP2000_PCIB)
385                 ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
386 }
387
388 static void ixp2000_pci_irq_unmask(unsigned int irq)
389 {
390         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
391         if (irq == IRQ_IXP2000_PCIA)
392                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
393         else if (irq == IRQ_IXP2000_PCIB)
394                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
395 }
396
397 /*
398  * Error interrupts. These are used extensively by the microengine drivers
399  */
400 static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
401 {
402         int i;
403         unsigned long status = *IXP2000_IRQ_ERR_STATUS;
404
405         for(i = 31; i >= 0; i--) {
406                 if(status & (1 << i)) {
407                         desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
408                         desc_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc);
409                 }
410         }
411 }
412
413 static void ixp2000_err_irq_mask(unsigned int irq)
414 {
415         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
416                         (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
417 }
418
419 static void ixp2000_err_irq_unmask(unsigned int irq)
420 {
421         ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
422                         (1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
423 }
424
425 static struct irq_chip ixp2000_err_irq_chip = {
426         .ack    = ixp2000_err_irq_mask,
427         .mask   = ixp2000_err_irq_mask,
428         .unmask = ixp2000_err_irq_unmask
429 };
430
431 static struct irq_chip ixp2000_pci_irq_chip = {
432         .ack    = ixp2000_pci_irq_mask,
433         .mask   = ixp2000_pci_irq_mask,
434         .unmask = ixp2000_pci_irq_unmask
435 };
436
437 static void ixp2000_irq_mask(unsigned int irq)
438 {
439         ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
440 }
441
442 static void ixp2000_irq_unmask(unsigned int irq)
443 {
444         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
445 }
446
447 static struct irq_chip ixp2000_irq_chip = {
448         .ack    = ixp2000_irq_mask,
449         .mask   = ixp2000_irq_mask,
450         .unmask = ixp2000_irq_unmask
451 };
452
453 void __init ixp2000_init_irq(void)
454 {
455         int irq;
456
457         /*
458          * Mask all sources
459          */
460         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
461         ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
462
463         /* clear all GPIO edge/level detects */
464         ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
465         ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
466         ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
467         ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
468         ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
469
470         /* clear PCI interrupt sources */
471         ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
472
473         /*
474          * Certain bits in the IRQ status register of the 
475          * IXP2000 are reserved. Instead of trying to map
476          * things non 1:1 from bit position to IRQ number,
477          * we mark the reserved IRQs as invalid. This makes
478          * our mask/unmask code much simpler.
479          */
480         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
481                 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
482                         set_irq_chip(irq, &ixp2000_irq_chip);
483                         set_irq_handler(irq, handle_level_irq);
484                         set_irq_flags(irq, IRQF_VALID);
485                 } else set_irq_flags(irq, 0);
486         }
487
488         for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
489                 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
490                                 IXP2000_VALID_ERR_IRQ_MASK) {
491                         set_irq_chip(irq, &ixp2000_err_irq_chip);
492                         set_irq_handler(irq, handle_level_irq);
493                         set_irq_flags(irq, IRQF_VALID);
494                 }
495                 else
496                         set_irq_flags(irq, 0);
497         }
498         set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
499
500         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
501                 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
502                 set_irq_handler(irq, handle_level_irq);
503                 set_irq_flags(irq, IRQF_VALID);
504         }
505         set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
506
507         /*
508          * Enable PCI irqs.  The actual PCI[AB] decoding is done in
509          * entry-macro.S, so we don't need a chained handler for the
510          * PCI interrupt source.
511          */
512         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
513         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
514                 set_irq_chip(irq, &ixp2000_pci_irq_chip);
515                 set_irq_handler(irq, handle_level_irq);
516                 set_irq_flags(irq, IRQF_VALID);
517         }
518 }
519