1 #include <linux/serial_core.h>
5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6 #include <asm/regs306x.h>
8 #if defined(CONFIG_H8S2678)
9 #include <asm/regs267x.h>
12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
19 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20 # define SCIF0 0xA4400000
21 # define SCIF2 0xA4410000
22 # define SCSMR_Ir 0xA44A0000
23 # define IRDA_SCIF SCIF0
24 # define SCPCR 0xA4000116
25 # define SCPDR 0xA4000136
27 /* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
31 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
32 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
34 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
35 #define SCIF_ORER 0x0200 /* overrun error bit */
36 #elif defined(CONFIG_SH_RTS7751R2D)
37 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
38 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
39 # define SCIF_ORER 0x0001 /* overrun error bit */
40 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
41 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
42 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
43 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7751R)
47 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
48 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
49 # define SCIF_ORER 0x0001 /* overrun error bit */
50 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
51 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
52 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
53 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
54 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
55 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
56 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
57 # define SCIF_ORER 0x0001 /* overrun error bit */
58 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
59 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
60 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
61 # define SCIF_ORER 0x0001 /* overrun error bit */
62 # define PACR 0xa4050100
63 # define PBCR 0xa4050102
64 # define SCSCR_INIT(port) 0x3B
65 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
66 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
67 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
68 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
69 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
70 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
71 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
72 # define PADR 0xA4050120
73 # define PSDR 0xA405013e
74 # define PWDR 0xA4050166
75 # define PSCR 0xA405011E
76 # define SCIF_ORER 0x0001 /* overrun error bit */
77 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
78 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
79 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
80 # define SCSPTR0 SCPDR0
81 # define SCIF_ORER 0x0001 /* overrun error bit */
82 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
84 # define SCSPTR0 0xa4050160
85 # define SCSPTR1 0xa405013e
86 # define SCSPTR2 0xa4050160
87 # define SCSPTR3 0xa405013e
88 # define SCSPTR4 0xa4050128
89 # define SCSPTR5 0xa4050128
90 # define SCIF_ORER 0x0001 /* overrun error bit */
91 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
92 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
93 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
94 # define SCIF_ORER 0x0001 /* overrun error bit */
95 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
97 # define SCIF_BASE_ADDR 0x01030000
98 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
99 # define SCIF_PTR2_OFFS 0x0000020
100 # define SCIF_LSR2_OFFS 0x0000024
101 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
102 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
103 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
104 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
105 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
106 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
107 #elif defined(CONFIG_H8S2678)
108 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
109 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
110 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
111 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
112 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
113 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
114 # define SCIF_ORER 0x0001 /* overrun error bit */
115 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
116 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
117 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
118 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
119 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
120 # define SCIF_ORER 0x0001 /* overrun error bit */
121 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
122 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
123 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
124 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
125 # define SCIF_ORER 0x0001 /* Overrun error bit */
126 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
127 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
128 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
129 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
130 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
131 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
132 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
133 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
134 # define SCIF_OPER 0x0001 /* Overrun error bit */
135 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
136 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
137 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
138 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
139 defined(CONFIG_CPU_SUBTYPE_SH7263)
140 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
141 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
142 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
143 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
144 # if defined(CONFIG_CPU_SUBTYPE_SH7201)
145 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
146 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
147 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
148 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
150 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
151 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
152 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
153 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
154 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
155 # define SCIF_ORER 0x0001 /* overrun error bit */
156 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
157 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
158 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
159 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
160 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
161 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
162 # define SCIF_ORER 0x0001 /* Overrun error bit */
163 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
165 # error CPU subtype not defined
169 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
170 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
171 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
172 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
173 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
174 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
175 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
176 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
177 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
178 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
179 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
183 defined(CONFIG_CPU_SUBTYPE_SHX3)
184 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
186 #define SCI_CTRL_FLAGS_REIE 0
188 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
189 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
190 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
191 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
194 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
195 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
196 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
197 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
206 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
207 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
208 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
209 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
210 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
216 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
217 defined(CONFIG_CPU_SUBTYPE_SH7721)
218 # define SCIF_ORER 0x0200
219 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
220 # define SCIF_RFDC_MASK 0x007f
221 # define SCIF_TXROOM_MAX 64
222 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
223 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
224 # define SCIF_RFDC_MASK 0x007f
225 # define SCIF_TXROOM_MAX 64
226 /* SH7763 SCIF2 support */
227 # define SCIF2_RFDC_MASK 0x001f
228 # define SCIF2_TXROOM_MAX 16
230 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
231 # define SCIF_RFDC_MASK 0x001f
232 # define SCIF_TXROOM_MAX 16
236 #define SCIF_ORER 0x0000
239 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
240 #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
241 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
242 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
243 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
244 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
245 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
246 #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
248 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
249 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
250 defined(CONFIG_CPU_SUBTYPE_SH7721)
251 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
252 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
253 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
254 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
256 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
257 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
258 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
259 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
263 #define SCFCR_RFRST 0x0002
264 #define SCFCR_TFRST 0x0004
265 #define SCFCR_TCRST 0x4000
266 #define SCFCR_MCE 0x0008
268 #define SCI_MAJOR 204
269 #define SCI_MINOR_START 8
271 /* Generic serial flags */
272 #define SCI_RX_THROTTLE 0x0000001
274 #define SCI_MAGIC 0xbabeface
277 * Events are used to schedule things to happen at timer-interrupt
278 * time, instead of at rs interrupt time.
280 #define SCI_EVENT_WRITE_WAKEUP 0
282 #define SCI_IN(size, offset) \
284 return ioread8(port->membase + (offset)); \
286 return ioread16(port->membase + (offset)); \
288 #define SCI_OUT(size, offset, value) \
290 iowrite8(value, port->membase + (offset)); \
291 } else if ((size) == 16) { \
292 iowrite16(value, port->membase + (offset)); \
295 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
296 static inline unsigned int sci_##name##_in(struct uart_port *port) \
298 if (port->type == PORT_SCIF) { \
299 SCI_IN(scif_size, scif_offset) \
300 } else { /* PORT_SCI or PORT_SCIFA */ \
301 SCI_IN(sci_size, sci_offset); \
304 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
306 if (port->type == PORT_SCIF) { \
307 SCI_OUT(scif_size, scif_offset, value) \
308 } else { /* PORT_SCI or PORT_SCIFA */ \
309 SCI_OUT(sci_size, sci_offset, value); \
313 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
314 static inline unsigned int sci_##name##_in(struct uart_port *port) \
316 SCI_IN(scif_size, scif_offset); \
318 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
320 SCI_OUT(scif_size, scif_offset, value); \
323 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
324 static inline unsigned int sci_##name##_in(struct uart_port* port) \
326 SCI_IN(sci_size, sci_offset); \
328 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
330 SCI_OUT(sci_size, sci_offset, value); \
333 #ifdef CONFIG_CPU_SH3
334 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
335 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
336 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
337 h8_sci_offset, h8_sci_size) \
338 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
339 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
340 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
341 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
342 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
343 defined(CONFIG_CPU_SUBTYPE_SH7721)
344 #define SCIF_FNS(name, scif_offset, scif_size) \
345 CPU_SCIF_FNS(name, scif_offset, scif_size)
347 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
348 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
349 h8_sci_offset, h8_sci_size) \
350 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
351 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
352 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
354 #elif defined(__H8300H__) || defined(__H8300S__)
355 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
356 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
357 h8_sci_offset, h8_sci_size) \
358 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
359 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
360 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
361 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
362 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
363 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
366 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
367 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
368 h8_sci_offset, h8_sci_size) \
369 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
370 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
371 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
374 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
375 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
376 defined(CONFIG_CPU_SUBTYPE_SH7721)
378 SCIF_FNS(SCSMR, 0x00, 16)
379 SCIF_FNS(SCBRR, 0x04, 8)
380 SCIF_FNS(SCSCR, 0x08, 16)
381 SCIF_FNS(SCTDSR, 0x0c, 8)
382 SCIF_FNS(SCFER, 0x10, 16)
383 SCIF_FNS(SCxSR, 0x14, 16)
384 SCIF_FNS(SCFCR, 0x18, 16)
385 SCIF_FNS(SCFDR, 0x1c, 16)
386 SCIF_FNS(SCxTDR, 0x20, 8)
387 SCIF_FNS(SCxRDR, 0x24, 8)
388 SCIF_FNS(SCLSR, 0x24, 16)
389 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
390 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
391 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
392 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
393 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
394 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
395 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
396 SCIF_FNS(SCTDSR, 0x0c, 8)
397 SCIF_FNS(SCFER, 0x10, 16)
398 SCIF_FNS(SCFCR, 0x18, 16)
399 SCIF_FNS(SCFDR, 0x1c, 16)
400 SCIF_FNS(SCLSR, 0x24, 16)
402 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
403 /* name off sz off sz off sz off sz off sz*/
404 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
405 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
406 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
407 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
408 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
409 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
410 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
411 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
412 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
413 defined(CONFIG_CPU_SUBTYPE_SH7785)
414 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
415 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
416 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
417 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
418 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
419 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
420 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
421 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
422 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
423 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
424 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
425 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
426 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
428 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
429 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
430 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
432 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
434 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
437 #define sci_in(port, reg) sci_##reg##_in(port)
438 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
440 /* H8/300 series SCI pins assignment */
441 #if defined(__H8300H__) || defined(__H8300S__)
442 static const struct __attribute__((packed)) {
443 int port; /* GPIO port no */
444 unsigned short rx,tx; /* GPIO bit no */
445 } h8300_sci_pins[] = {
446 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
448 .port = H8300_GPIO_P9,
453 .port = H8300_GPIO_P9,
458 .port = H8300_GPIO_PB,
462 #elif defined(CONFIG_H8S2678)
464 .port = H8300_GPIO_P3,
469 .port = H8300_GPIO_P3,
474 .port = H8300_GPIO_P5,
482 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
483 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
484 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
485 defined(CONFIG_CPU_SUBTYPE_SH7709)
486 static inline int sci_rxd_in(struct uart_port *port)
488 if (port->mapbase == 0xfffffe80)
489 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
490 if (port->mapbase == 0xa4000150)
491 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
492 if (port->mapbase == 0xa4000140)
493 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
496 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
497 static inline int sci_rxd_in(struct uart_port *port)
499 if (port->mapbase == SCIF0)
500 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
501 if (port->mapbase == SCIF2)
502 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
505 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
506 static inline int sci_rxd_in(struct uart_port *port)
508 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
510 static inline void set_sh771x_scif_pfc(struct uart_port *port)
512 if (port->mapbase == 0xA4400000){
513 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
514 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
517 if (port->mapbase == 0xA4410000){
518 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
522 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
523 defined(CONFIG_CPU_SUBTYPE_SH7721)
524 static inline int sci_rxd_in(struct uart_port *port)
526 if (port->mapbase == 0xa4430000)
527 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
528 else if (port->mapbase == 0xa4438000)
529 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
532 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
533 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
534 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
535 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
536 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
537 defined(CONFIG_CPU_SUBTYPE_SH7091)
538 static inline int sci_rxd_in(struct uart_port *port)
540 if (port->mapbase == 0xffe00000)
541 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
542 if (port->mapbase == 0xffe80000)
543 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
546 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
547 static inline int sci_rxd_in(struct uart_port *port)
549 if (port->mapbase == 0xffe80000)
550 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
553 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
554 static inline int sci_rxd_in(struct uart_port *port)
556 if (port->mapbase == 0xfe600000)
557 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
558 if (port->mapbase == 0xfe610000)
559 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
560 if (port->mapbase == 0xfe620000)
561 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
564 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
565 static inline int sci_rxd_in(struct uart_port *port)
567 if (port->mapbase == 0xffe00000)
568 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
569 if (port->mapbase == 0xffe10000)
570 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
571 if (port->mapbase == 0xffe20000)
572 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
573 if (port->mapbase == 0xffe30000)
574 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
577 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
578 static inline int sci_rxd_in(struct uart_port *port)
580 if (port->mapbase == 0xffe00000)
581 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
584 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
585 static inline int sci_rxd_in(struct uart_port *port)
587 if (port->mapbase == 0xffe00000)
588 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
589 if (port->mapbase == 0xffe10000)
590 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
591 if (port->mapbase == 0xffe20000)
592 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
596 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
597 static inline int sci_rxd_in(struct uart_port *port)
599 if (port->mapbase == 0xffe00000)
600 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
601 if (port->mapbase == 0xffe10000)
602 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
603 if (port->mapbase == 0xffe20000)
604 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
605 if (port->mapbase == 0xa4e30000)
606 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
607 if (port->mapbase == 0xa4e40000)
608 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
609 if (port->mapbase == 0xa4e50000)
610 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
613 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
614 static inline int sci_rxd_in(struct uart_port *port)
616 return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
618 #elif defined(__H8300H__) || defined(__H8300S__)
619 static inline int sci_rxd_in(struct uart_port *port)
621 int ch = (port->mapbase - SMR0) >> 3;
622 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
624 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
625 static inline int sci_rxd_in(struct uart_port *port)
627 if (port->mapbase == 0xffe00000)
628 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
629 if (port->mapbase == 0xffe08000)
630 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
631 if (port->mapbase == 0xffe10000)
632 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
636 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
637 static inline int sci_rxd_in(struct uart_port *port)
639 if (port->mapbase == 0xff923000)
640 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
641 if (port->mapbase == 0xff924000)
642 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
643 if (port->mapbase == 0xff925000)
644 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
647 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
648 static inline int sci_rxd_in(struct uart_port *port)
650 if (port->mapbase == 0xffe00000)
651 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xffe10000)
653 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
656 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
657 static inline int sci_rxd_in(struct uart_port *port)
659 if (port->mapbase == 0xffea0000)
660 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
661 if (port->mapbase == 0xffeb0000)
662 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
663 if (port->mapbase == 0xffec0000)
664 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
665 if (port->mapbase == 0xffed0000)
666 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
667 if (port->mapbase == 0xffee0000)
668 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
669 if (port->mapbase == 0xffef0000)
670 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
673 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
674 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
675 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
676 defined(CONFIG_CPU_SUBTYPE_SH7263)
677 static inline int sci_rxd_in(struct uart_port *port)
679 if (port->mapbase == 0xfffe8000)
680 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
681 if (port->mapbase == 0xfffe8800)
682 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
683 if (port->mapbase == 0xfffe9000)
684 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
685 if (port->mapbase == 0xfffe9800)
686 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
687 #if defined(CONFIG_CPU_SUBTYPE_SH7201)
688 if (port->mapbase == 0xfffeA000)
689 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
690 if (port->mapbase == 0xfffeA800)
691 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
692 if (port->mapbase == 0xfffeB000)
693 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
694 if (port->mapbase == 0xfffeB800)
695 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
699 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
700 static inline int sci_rxd_in(struct uart_port *port)
702 if (port->mapbase == 0xf8400000)
703 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
704 if (port->mapbase == 0xf8410000)
705 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
706 if (port->mapbase == 0xf8420000)
707 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
710 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
711 static inline int sci_rxd_in(struct uart_port *port)
713 if (port->mapbase == 0xffc30000)
714 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
715 if (port->mapbase == 0xffc40000)
716 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
717 if (port->mapbase == 0xffc50000)
718 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
719 if (port->mapbase == 0xffc60000)
720 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
726 * Values for the BitRate Register (SCBRR)
728 * The values are actually divisors for a frequency which can
729 * be internal to the SH3 (14.7456MHz) or derived from an external
730 * clock source. This driver assumes the internal clock is used;
731 * to support using an external clock source, config options or
732 * possibly command-line options would need to be added.
734 * Also, to support speeds below 2400 (why?) the lower 2 bits of
735 * the SCSMR register would also need to be set to non-zero values.
737 * -- Greg Banks 27Feb2000
739 * Answer: The SCBRR register is only eight bits, and the value in
740 * it gets larger with lower baud rates. At around 2400 (depending on
741 * the peripherial module clock) you run out of bits. However the
742 * lower two bits of SCSMR allow the module clock to be divided down,
743 * scaling the value which is needed in SCBRR.
745 * -- Stuart Menefy - 23 May 2000
747 * I meant, why would anyone bother with bitrates below 2400.
749 * -- Greg Banks - 7Jul2000
751 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
752 * tape reader as a console!
754 * -- Mitch Davis - 15 Jul 2000
757 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
758 defined(CONFIG_CPU_SUBTYPE_SH7785)
759 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
760 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
761 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
762 defined(CONFIG_CPU_SUBTYPE_SH7721)
763 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
764 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
765 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
767 if (port->type == PORT_SCIF)
768 return (clk+16*bps)/(32*bps)-1;
770 return ((clk*2)+16*bps)/(16*bps)-1;
772 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
773 #elif defined(__H8300H__) || defined(__H8300S__)
774 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
775 #else /* Generic SH */
776 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)