git.oblomov.eu Git - linux-2.6/blob - drivers/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "kvm.h"
  19 #include "x86.h"
  20 #include "x86_emulate.h"
  21 #include "irq.h"
  22 #include "vmx.h"
  23 #include "segment_descriptor.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 struct vmcs {
  42         u32 revision_id;
  43         u32 abort;
  44         char data[0];
  45 };
  46
  47 struct vcpu_vmx {
  48         struct kvm_vcpu       vcpu;
  49         int                   launched;
  50         u8                    fail;
  51         u32                   idt_vectoring_info;
  52         struct kvm_msr_entry *guest_msrs;
  53         struct kvm_msr_entry *host_msrs;
  54         int                   nmsrs;
  55         int                   save_nmsrs;
  56         int                   msr_offset_efer;
  57 #ifdef CONFIG_X86_64
  58         int                   msr_offset_kernel_gs_base;
  59 #endif
  60         struct vmcs          *vmcs;
  61         struct {
  62                 int           loaded;
  63                 u16           fs_sel, gs_sel, ldt_sel;
  64                 int           gs_ldt_reload_needed;
  65                 int           fs_reload_needed;
  66                 int           guest_efer_loaded;
  67         } host_state;
  68         struct {
  69                 struct {
  70                         bool pending;
  71                         u8 vector;
  72                         unsigned rip;
  73                 } irq;
  74         } rmode;
  75 };
  76
  77 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  78 {
  79         return container_of(vcpu, struct vcpu_vmx, vcpu);
  80 }
  81
  82 static int init_rmode_tss(struct kvm *kvm);
  83
  84 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  85 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  86
  87 static struct page *vmx_io_bitmap_a;
  88 static struct page *vmx_io_bitmap_b;
  89
  90 static struct vmcs_config {
  91         int size;
  92         int order;
  93         u32 revision_id;
  94         u32 pin_based_exec_ctrl;
  95         u32 cpu_based_exec_ctrl;
  96         u32 cpu_based_2nd_exec_ctrl;
  97         u32 vmexit_ctrl;
  98         u32 vmentry_ctrl;
  99 } vmcs_config;
 100
 101 #define VMX_SEGMENT_FIELD(seg)                                  \
 102         [VCPU_SREG_##seg] = {                                   \
 103                 .selector = GUEST_##seg##_SELECTOR,             \
 104                 .base = GUEST_##seg##_BASE,                     \
 105                 .limit = GUEST_##seg##_LIMIT,                   \
 106                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 107         }
 108
 109 static struct kvm_vmx_segment_field {
 110         unsigned selector;
 111         unsigned base;
 112         unsigned limit;
 113         unsigned ar_bytes;
 114 } kvm_vmx_segment_fields[] = {
 115         VMX_SEGMENT_FIELD(CS),
 116         VMX_SEGMENT_FIELD(DS),
 117         VMX_SEGMENT_FIELD(ES),
 118         VMX_SEGMENT_FIELD(FS),
 119         VMX_SEGMENT_FIELD(GS),
 120         VMX_SEGMENT_FIELD(SS),
 121         VMX_SEGMENT_FIELD(TR),
 122         VMX_SEGMENT_FIELD(LDTR),
 123 };
 124
 125 /*
 126  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 127  * away by decrementing the array size.
 128  */
 129 static const u32 vmx_msr_index[] = {
 130 #ifdef CONFIG_X86_64
 131         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 132 #endif
 133         MSR_EFER, MSR_K6_STAR,
 134 };
 135 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 136
 137 static void load_msrs(struct kvm_msr_entry *e, int n)
 138 {
 139         int i;
 140
 141         for (i = 0; i < n; ++i)
 142                 wrmsrl(e[i].index, e[i].data);
 143 }
 144
 145 static void save_msrs(struct kvm_msr_entry *e, int n)
 146 {
 147         int i;
 148
 149         for (i = 0; i < n; ++i)
 150                 rdmsrl(e[i].index, e[i].data);
 151 }
 152
 153 static inline int is_page_fault(u32 intr_info)
 154 {
 155         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 156                              INTR_INFO_VALID_MASK)) ==
 157                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 158 }
 159
 160 static inline int is_no_device(u32 intr_info)
 161 {
 162         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 163                              INTR_INFO_VALID_MASK)) ==
 164                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 165 }
 166
 167 static inline int is_invalid_opcode(u32 intr_info)
 168 {
 169         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 170                              INTR_INFO_VALID_MASK)) ==
 171                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 172 }
 173
 174 static inline int is_external_interrupt(u32 intr_info)
 175 {
 176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 177                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 178 }
 179
 180 static inline int cpu_has_vmx_tpr_shadow(void)
 181 {
 182         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 183 }
 184
 185 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 186 {
 187         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 188 }
 189
 190 static inline int cpu_has_secondary_exec_ctrls(void)
 191 {
 192         return (vmcs_config.cpu_based_exec_ctrl &
 193                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 194 }
 195
 196 static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
 197 {
 198         return ((cpu_has_secondary_exec_ctrls()) && (irqchip_in_kernel(kvm)));
 199 }
 200
 201 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
 202 {
 203         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 204                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 205 }
 206
 207 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 208 {
 209         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 210                 (irqchip_in_kernel(kvm)));
 211 }
 212
 213 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 214 {
 215         int i;
 216
 217         for (i = 0; i < vmx->nmsrs; ++i)
 218                 if (vmx->guest_msrs[i].index == msr)
 219                         return i;
 220         return -1;
 221 }
 222
 223 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 224 {
 225         int i;
 226
 227         i = __find_msr_index(vmx, msr);
 228         if (i >= 0)
 229                 return &vmx->guest_msrs[i];
 230         return NULL;
 231 }
 232
 233 static void vmcs_clear(struct vmcs *vmcs)
 234 {
 235         u64 phys_addr = __pa(vmcs);
 236         u8 error;
 237
 238         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
 239                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 240                       : "cc", "memory");
 241         if (error)
 242                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 243                        vmcs, phys_addr);
 244 }
 245
 246 static void __vcpu_clear(void *arg)
 247 {
 248         struct vcpu_vmx *vmx = arg;
 249         int cpu = raw_smp_processor_id();
 250
 251         if (vmx->vcpu.cpu == cpu)
 252                 vmcs_clear(vmx->vmcs);
 253         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 254                 per_cpu(current_vmcs, cpu) = NULL;
 255         rdtscll(vmx->vcpu.host_tsc);
 256 }
 257
 258 static void vcpu_clear(struct vcpu_vmx *vmx)
 259 {
 260         if (vmx->vcpu.cpu == -1)
 261                 return;
 262         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
 263         vmx->launched = 0;
 264 }
 265
 266 static unsigned long vmcs_readl(unsigned long field)
 267 {
 268         unsigned long value;
 269
 270         asm volatile (ASM_VMX_VMREAD_RDX_RAX
 271                       : "=a"(value) : "d"(field) : "cc");
 272         return value;
 273 }
 274
 275 static u16 vmcs_read16(unsigned long field)
 276 {
 277         return vmcs_readl(field);
 278 }
 279
 280 static u32 vmcs_read32(unsigned long field)
 281 {
 282         return vmcs_readl(field);
 283 }
 284
 285 static u64 vmcs_read64(unsigned long field)
 286 {
 287 #ifdef CONFIG_X86_64
 288         return vmcs_readl(field);
 289 #else
 290         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 291 #endif
 292 }
 293
 294 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 295 {
 296         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 297                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 298         dump_stack();
 299 }
 300
 301 static void vmcs_writel(unsigned long field, unsigned long value)
 302 {
 303         u8 error;
 304
 305         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
 306                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 307         if (unlikely(error))
 308                 vmwrite_error(field, value);
 309 }
 310
 311 static void vmcs_write16(unsigned long field, u16 value)
 312 {
 313         vmcs_writel(field, value);
 314 }
 315
 316 static void vmcs_write32(unsigned long field, u32 value)
 317 {
 318         vmcs_writel(field, value);
 319 }
 320
 321 static void vmcs_write64(unsigned long field, u64 value)
 322 {
 323 #ifdef CONFIG_X86_64
 324         vmcs_writel(field, value);
 325 #else
 326         vmcs_writel(field, value);
 327         asm volatile ("");
 328         vmcs_writel(field+1, value >> 32);
 329 #endif
 330 }
 331
 332 static void vmcs_clear_bits(unsigned long field, u32 mask)
 333 {
 334         vmcs_writel(field, vmcs_readl(field) & ~mask);
 335 }
 336
 337 static void vmcs_set_bits(unsigned long field, u32 mask)
 338 {
 339         vmcs_writel(field, vmcs_readl(field) | mask);
 340 }
 341
 342 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 343 {
 344         u32 eb;
 345
 346         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 347         if (!vcpu->fpu_active)
 348                 eb |= 1u << NM_VECTOR;
 349         if (vcpu->guest_debug.enabled)
 350                 eb |= 1u << 1;
 351         if (vcpu->rmode.active)
 352                 eb = ~0;
 353         vmcs_write32(EXCEPTION_BITMAP, eb);
 354 }
 355
 356 static void reload_tss(void)
 357 {
 358 #ifndef CONFIG_X86_64
 359
 360         /*
 361          * VT restores TR but not its size.  Useless.
 362          */
 363         struct descriptor_table gdt;
 364         struct segment_descriptor *descs;
 365
 366         get_gdt(&gdt);
 367         descs = (void *)gdt.base;
 368         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 369         load_TR_desc();
 370 #endif
 371 }
 372
 373 static void load_transition_efer(struct vcpu_vmx *vmx)
 374 {
 375         int efer_offset = vmx->msr_offset_efer;
 376         u64 host_efer = vmx->host_msrs[efer_offset].data;
 377         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 378         u64 ignore_bits;
 379
 380         if (efer_offset < 0)
 381                 return;
 382         /*
 383          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 384          * outside long mode
 385          */
 386         ignore_bits = EFER_NX | EFER_SCE;
 387 #ifdef CONFIG_X86_64
 388         ignore_bits |= EFER_LMA | EFER_LME;
 389         /* SCE is meaningful only in long mode on Intel */
 390         if (guest_efer & EFER_LMA)
 391                 ignore_bits &= ~(u64)EFER_SCE;
 392 #endif
 393         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 394                 return;
 395
 396         vmx->host_state.guest_efer_loaded = 1;
 397         guest_efer &= ~ignore_bits;
 398         guest_efer |= host_efer & ignore_bits;
 399         wrmsrl(MSR_EFER, guest_efer);
 400         vmx->vcpu.stat.efer_reload++;
 401 }
 402
 403 static void reload_host_efer(struct vcpu_vmx *vmx)
 404 {
 405         if (vmx->host_state.guest_efer_loaded) {
 406                 vmx->host_state.guest_efer_loaded = 0;
 407                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 408         }
 409 }
 410
 411 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 412 {
 413         struct vcpu_vmx *vmx = to_vmx(vcpu);
 414
 415         if (vmx->host_state.loaded)
 416                 return;
 417
 418         vmx->host_state.loaded = 1;
 419         /*
 420          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 421          * allow segment selectors with cpl > 0 or ti == 1.
 422          */
 423         vmx->host_state.ldt_sel = read_ldt();
 424         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 425         vmx->host_state.fs_sel = read_fs();
 426         if (!(vmx->host_state.fs_sel & 7)) {
 427                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 428                 vmx->host_state.fs_reload_needed = 0;
 429         } else {
 430                 vmcs_write16(HOST_FS_SELECTOR, 0);
 431                 vmx->host_state.fs_reload_needed = 1;
 432         }
 433         vmx->host_state.gs_sel = read_gs();
 434         if (!(vmx->host_state.gs_sel & 7))
 435                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 436         else {
 437                 vmcs_write16(HOST_GS_SELECTOR, 0);
 438                 vmx->host_state.gs_ldt_reload_needed = 1;
 439         }
 440
 441 #ifdef CONFIG_X86_64
 442         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 443         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 444 #else
 445         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 446         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 447 #endif
 448
 449 #ifdef CONFIG_X86_64
 450         if (is_long_mode(&vmx->vcpu))
 451                 save_msrs(vmx->host_msrs +
 452                           vmx->msr_offset_kernel_gs_base, 1);
 453
 454 #endif
 455         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 456         load_transition_efer(vmx);
 457 }
 458
 459 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 460 {
 461         unsigned long flags;
 462
 463         if (!vmx->host_state.loaded)
 464                 return;
 465
 466         ++vmx->vcpu.stat.host_state_reload;
 467         vmx->host_state.loaded = 0;
 468         if (vmx->host_state.fs_reload_needed)
 469                 load_fs(vmx->host_state.fs_sel);
 470         if (vmx->host_state.gs_ldt_reload_needed) {
 471                 load_ldt(vmx->host_state.ldt_sel);
 472                 /*
 473                  * If we have to reload gs, we must take care to
 474                  * preserve our gs base.
 475                  */
 476                 local_irq_save(flags);
 477                 load_gs(vmx->host_state.gs_sel);
 478 #ifdef CONFIG_X86_64
 479                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 480 #endif
 481                 local_irq_restore(flags);
 482         }
 483         reload_tss();
 484         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 485         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 486         reload_host_efer(vmx);
 487 }
 488
 489 /*
 490  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 491  * vcpu mutex is already taken.
 492  */
 493 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 494 {
 495         struct vcpu_vmx *vmx = to_vmx(vcpu);
 496         u64 phys_addr = __pa(vmx->vmcs);
 497         u64 tsc_this, delta;
 498
 499         if (vcpu->cpu != cpu) {
 500                 vcpu_clear(vmx);
 501                 kvm_migrate_apic_timer(vcpu);
 502         }
 503
 504         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 505                 u8 error;
 506
 507                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 508                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
 509                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 510                               : "cc");
 511                 if (error)
 512                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 513                                vmx->vmcs, phys_addr);
 514         }
 515
 516         if (vcpu->cpu != cpu) {
 517                 struct descriptor_table dt;
 518                 unsigned long sysenter_esp;
 519
 520                 vcpu->cpu = cpu;
 521                 /*
 522                  * Linux uses per-cpu TSS and GDT, so set these when switching
 523                  * processors.
 524                  */
 525                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 526                 get_gdt(&dt);
 527                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 528
 529                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 530                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 531
 532                 /*
 533                  * Make sure the time stamp counter is monotonous.
 534                  */
 535                 rdtscll(tsc_this);
 536                 delta = vcpu->host_tsc - tsc_this;
 537                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
 538         }
 539 }
 540
 541 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 542 {
 543         vmx_load_host_state(to_vmx(vcpu));
 544 }
 545
 546 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 547 {
 548         if (vcpu->fpu_active)
 549                 return;
 550         vcpu->fpu_active = 1;
 551         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 552         if (vcpu->cr0 & X86_CR0_TS)
 553                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 554         update_exception_bitmap(vcpu);
 555 }
 556
 557 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 558 {
 559         if (!vcpu->fpu_active)
 560                 return;
 561         vcpu->fpu_active = 0;
 562         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 563         update_exception_bitmap(vcpu);
 564 }
 565
 566 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 567 {
 568         vcpu_clear(to_vmx(vcpu));
 569 }
 570
 571 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 572 {
 573         return vmcs_readl(GUEST_RFLAGS);
 574 }
 575
 576 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 577 {
 578         if (vcpu->rmode.active)
 579                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 580         vmcs_writel(GUEST_RFLAGS, rflags);
 581 }
 582
 583 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 584 {
 585         unsigned long rip;
 586         u32 interruptibility;
 587
 588         rip = vmcs_readl(GUEST_RIP);
 589         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 590         vmcs_writel(GUEST_RIP, rip);
 591
 592         /*
 593          * We emulated an instruction, so temporary interrupt blocking
 594          * should be removed, if set.
 595          */
 596         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 597         if (interruptibility & 3)
 598                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 599                              interruptibility & ~3);
 600         vcpu->interrupt_window_open = 1;
 601 }
 602
 603 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
 604 {
 605         printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
 606                vmcs_readl(GUEST_RIP));
 607         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 608         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 609                      GP_VECTOR |
 610                      INTR_TYPE_EXCEPTION |
 611                      INTR_INFO_DELIEVER_CODE_MASK |
 612                      INTR_INFO_VALID_MASK);
 613 }
 614
 615 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
 616 {
 617         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 618                      UD_VECTOR |
 619                      INTR_TYPE_EXCEPTION |
 620                      INTR_INFO_VALID_MASK);
 621 }
 622
 623 /*
 624  * Swap MSR entry in host/guest MSR entry array.
 625  */
 626 #ifdef CONFIG_X86_64
 627 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 628 {
 629         struct kvm_msr_entry tmp;
 630
 631         tmp = vmx->guest_msrs[to];
 632         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 633         vmx->guest_msrs[from] = tmp;
 634         tmp = vmx->host_msrs[to];
 635         vmx->host_msrs[to] = vmx->host_msrs[from];
 636         vmx->host_msrs[from] = tmp;
 637 }
 638 #endif
 639
 640 /*
 641  * Set up the vmcs to automatically save and restore system
 642  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 643  * mode, as fiddling with msrs is very expensive.
 644  */
 645 static void setup_msrs(struct vcpu_vmx *vmx)
 646 {
 647         int save_nmsrs;
 648
 649         save_nmsrs = 0;
 650 #ifdef CONFIG_X86_64
 651         if (is_long_mode(&vmx->vcpu)) {
 652                 int index;
 653
 654                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 655                 if (index >= 0)
 656                         move_msr_up(vmx, index, save_nmsrs++);
 657                 index = __find_msr_index(vmx, MSR_LSTAR);
 658                 if (index >= 0)
 659                         move_msr_up(vmx, index, save_nmsrs++);
 660                 index = __find_msr_index(vmx, MSR_CSTAR);
 661                 if (index >= 0)
 662                         move_msr_up(vmx, index, save_nmsrs++);
 663                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 664                 if (index >= 0)
 665                         move_msr_up(vmx, index, save_nmsrs++);
 666                 /*
 667                  * MSR_K6_STAR is only needed on long mode guests, and only
 668                  * if efer.sce is enabled.
 669                  */
 670                 index = __find_msr_index(vmx, MSR_K6_STAR);
 671                 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
 672                         move_msr_up(vmx, index, save_nmsrs++);
 673         }
 674 #endif
 675         vmx->save_nmsrs = save_nmsrs;
 676
 677 #ifdef CONFIG_X86_64
 678         vmx->msr_offset_kernel_gs_base =
 679                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 680 #endif
 681         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 682 }
 683
 684 /*
 685  * reads and returns guest's timestamp counter "register"
 686  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 687  */
 688 static u64 guest_read_tsc(void)
 689 {
 690         u64 host_tsc, tsc_offset;
 691
 692         rdtscll(host_tsc);
 693         tsc_offset = vmcs_read64(TSC_OFFSET);
 694         return host_tsc + tsc_offset;
 695 }
 696
 697 /*
 698  * writes 'guest_tsc' into guest's timestamp counter "register"
 699  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 700  */
 701 static void guest_write_tsc(u64 guest_tsc)
 702 {
 703         u64 host_tsc;
 704
 705         rdtscll(host_tsc);
 706         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 707 }
 708
 709 /*
 710  * Reads an msr value (of 'msr_index') into 'pdata'.
 711  * Returns 0 on success, non-0 otherwise.
 712  * Assumes vcpu_load() was already called.
 713  */
 714 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 715 {
 716         u64 data;
 717         struct kvm_msr_entry *msr;
 718
 719         if (!pdata) {
 720                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 721                 return -EINVAL;
 722         }
 723
 724         switch (msr_index) {
 725 #ifdef CONFIG_X86_64
 726         case MSR_FS_BASE:
 727                 data = vmcs_readl(GUEST_FS_BASE);
 728                 break;
 729         case MSR_GS_BASE:
 730                 data = vmcs_readl(GUEST_GS_BASE);
 731                 break;
 732         case MSR_EFER:
 733                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 734 #endif
 735         case MSR_IA32_TIME_STAMP_COUNTER:
 736                 data = guest_read_tsc();
 737                 break;
 738         case MSR_IA32_SYSENTER_CS:
 739                 data = vmcs_read32(GUEST_SYSENTER_CS);
 740                 break;
 741         case MSR_IA32_SYSENTER_EIP:
 742                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 743                 break;
 744         case MSR_IA32_SYSENTER_ESP:
 745                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 746                 break;
 747         default:
 748                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 749                 if (msr) {
 750                         data = msr->data;
 751                         break;
 752                 }
 753                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 754         }
 755
 756         *pdata = data;
 757         return 0;
 758 }
 759
 760 /*
 761  * Writes msr value into into the appropriate "register".
 762  * Returns 0 on success, non-0 otherwise.
 763  * Assumes vcpu_load() was already called.
 764  */
 765 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 766 {
 767         struct vcpu_vmx *vmx = to_vmx(vcpu);
 768         struct kvm_msr_entry *msr;
 769         int ret = 0;
 770
 771         switch (msr_index) {
 772 #ifdef CONFIG_X86_64
 773         case MSR_EFER:
 774                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 775                 if (vmx->host_state.loaded) {
 776                         reload_host_efer(vmx);
 777                         load_transition_efer(vmx);
 778                 }
 779                 break;
 780         case MSR_FS_BASE:
 781                 vmcs_writel(GUEST_FS_BASE, data);
 782                 break;
 783         case MSR_GS_BASE:
 784                 vmcs_writel(GUEST_GS_BASE, data);
 785                 break;
 786 #endif
 787         case MSR_IA32_SYSENTER_CS:
 788                 vmcs_write32(GUEST_SYSENTER_CS, data);
 789                 break;
 790         case MSR_IA32_SYSENTER_EIP:
 791                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 792                 break;
 793         case MSR_IA32_SYSENTER_ESP:
 794                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 795                 break;
 796         case MSR_IA32_TIME_STAMP_COUNTER:
 797                 guest_write_tsc(data);
 798                 break;
 799         default:
 800                 msr = find_msr_entry(vmx, msr_index);
 801                 if (msr) {
 802                         msr->data = data;
 803                         if (vmx->host_state.loaded)
 804                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 805                         break;
 806                 }
 807                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 808         }
 809
 810         return ret;
 811 }
 812
 813 /*
 814  * Sync the rsp and rip registers into the vcpu structure.  This allows
 815  * registers to be accessed by indexing vcpu->regs.
 816  */
 817 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 818 {
 819         vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 820         vcpu->rip = vmcs_readl(GUEST_RIP);
 821 }
 822
 823 /*
 824  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 825  * modification.
 826  */
 827 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 828 {
 829         vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
 830         vmcs_writel(GUEST_RIP, vcpu->rip);
 831 }
 832
 833 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 834 {
 835         unsigned long dr7 = 0x400;
 836         int old_singlestep;
 837
 838         old_singlestep = vcpu->guest_debug.singlestep;
 839
 840         vcpu->guest_debug.enabled = dbg->enabled;
 841         if (vcpu->guest_debug.enabled) {
 842                 int i;
 843
 844                 dr7 |= 0x200;  /* exact */
 845                 for (i = 0; i < 4; ++i) {
 846                         if (!dbg->breakpoints[i].enabled)
 847                                 continue;
 848                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 849                         dr7 |= 2 << (i*2);    /* global enable */
 850                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 851                 }
 852
 853                 vcpu->guest_debug.singlestep = dbg->singlestep;
 854         } else
 855                 vcpu->guest_debug.singlestep = 0;
 856
 857         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 858                 unsigned long flags;
 859
 860                 flags = vmcs_readl(GUEST_RFLAGS);
 861                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 862                 vmcs_writel(GUEST_RFLAGS, flags);
 863         }
 864
 865         update_exception_bitmap(vcpu);
 866         vmcs_writel(GUEST_DR7, dr7);
 867
 868         return 0;
 869 }
 870
 871 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 872 {
 873         struct vcpu_vmx *vmx = to_vmx(vcpu);
 874         u32 idtv_info_field;
 875
 876         idtv_info_field = vmx->idt_vectoring_info;
 877         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 878                 if (is_external_interrupt(idtv_info_field))
 879                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 880                 else
 881                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 882         }
 883         return -1;
 884 }
 885
 886 static __init int cpu_has_kvm_support(void)
 887 {
 888         unsigned long ecx = cpuid_ecx(1);
 889         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
 890 }
 891
 892 static __init int vmx_disabled_by_bios(void)
 893 {
 894         u64 msr;
 895
 896         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 897         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 898                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 899             == MSR_IA32_FEATURE_CONTROL_LOCKED;
 900         /* locked but not enabled */
 901 }
 902
 903 static void hardware_enable(void *garbage)
 904 {
 905         int cpu = raw_smp_processor_id();
 906         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 907         u64 old;
 908
 909         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
 910         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 911                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 912             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
 913                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 914                 /* enable and lock */
 915                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
 916                        MSR_IA32_FEATURE_CONTROL_LOCKED |
 917                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
 918         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
 919         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
 920                       : "memory", "cc");
 921 }
 922
 923 static void hardware_disable(void *garbage)
 924 {
 925         asm volatile (ASM_VMX_VMXOFF : : : "cc");
 926 }
 927
 928 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 929                                       u32 msr, u32 *result)
 930 {
 931         u32 vmx_msr_low, vmx_msr_high;
 932         u32 ctl = ctl_min | ctl_opt;
 933
 934         rdmsr(msr, vmx_msr_low, vmx_msr_high);
 935
 936         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
 937         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
 938
 939         /* Ensure minimum (required) set of control bits are supported. */
 940         if (ctl_min & ~ctl)
 941                 return -EIO;
 942
 943         *result = ctl;
 944         return 0;
 945 }
 946
 947 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 948 {
 949         u32 vmx_msr_low, vmx_msr_high;
 950         u32 min, opt;
 951         u32 _pin_based_exec_control = 0;
 952         u32 _cpu_based_exec_control = 0;
 953         u32 _cpu_based_2nd_exec_control = 0;
 954         u32 _vmexit_control = 0;
 955         u32 _vmentry_control = 0;
 956
 957         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
 958         opt = 0;
 959         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
 960                                 &_pin_based_exec_control) < 0)
 961                 return -EIO;
 962
 963         min = CPU_BASED_HLT_EXITING |
 964 #ifdef CONFIG_X86_64
 965               CPU_BASED_CR8_LOAD_EXITING |
 966               CPU_BASED_CR8_STORE_EXITING |
 967 #endif
 968               CPU_BASED_USE_IO_BITMAPS |
 969               CPU_BASED_MOV_DR_EXITING |
 970               CPU_BASED_USE_TSC_OFFSETING;
 971         opt = CPU_BASED_TPR_SHADOW |
 972               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 973         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 974                                 &_cpu_based_exec_control) < 0)
 975                 return -EIO;
 976 #ifdef CONFIG_X86_64
 977         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
 978                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 979                                            ~CPU_BASED_CR8_STORE_EXITING;
 980 #endif
 981         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
 982                 min = 0;
 983                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
 984                         SECONDARY_EXEC_WBINVD_EXITING;
 985                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
 986                                         &_cpu_based_2nd_exec_control) < 0)
 987                         return -EIO;
 988         }
 989 #ifndef CONFIG_X86_64
 990         if (!(_cpu_based_2nd_exec_control &
 991                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
 992                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
 993 #endif
 994
 995         min = 0;
 996 #ifdef CONFIG_X86_64
 997         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 998 #endif
 999         opt = 0;
1000         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1001                                 &_vmexit_control) < 0)
1002                 return -EIO;
1003
1004         min = opt = 0;
1005         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1006                                 &_vmentry_control) < 0)
1007                 return -EIO;
1008
1009         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1010
1011         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1012         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1013                 return -EIO;
1014
1015 #ifdef CONFIG_X86_64
1016         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1017         if (vmx_msr_high & (1u<<16))
1018                 return -EIO;
1019 #endif
1020
1021         /* Require Write-Back (WB) memory type for VMCS accesses. */
1022         if (((vmx_msr_high >> 18) & 15) != 6)
1023                 return -EIO;
1024
1025         vmcs_conf->size = vmx_msr_high & 0x1fff;
1026         vmcs_conf->order = get_order(vmcs_config.size);
1027         vmcs_conf->revision_id = vmx_msr_low;
1028
1029         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1030         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1031         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1032         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1033         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1034
1035         return 0;
1036 }
1037
1038 static struct vmcs *alloc_vmcs_cpu(int cpu)
1039 {
1040         int node = cpu_to_node(cpu);
1041         struct page *pages;
1042         struct vmcs *vmcs;
1043
1044         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1045         if (!pages)
1046                 return NULL;
1047         vmcs = page_address(pages);
1048         memset(vmcs, 0, vmcs_config.size);
1049         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1050         return vmcs;
1051 }
1052
1053 static struct vmcs *alloc_vmcs(void)
1054 {
1055         return alloc_vmcs_cpu(raw_smp_processor_id());
1056 }
1057
1058 static void free_vmcs(struct vmcs *vmcs)
1059 {
1060         free_pages((unsigned long)vmcs, vmcs_config.order);
1061 }
1062
1063 static void free_kvm_area(void)
1064 {
1065         int cpu;
1066
1067         for_each_online_cpu(cpu)
1068                 free_vmcs(per_cpu(vmxarea, cpu));
1069 }
1070
1071 static __init int alloc_kvm_area(void)
1072 {
1073         int cpu;
1074
1075         for_each_online_cpu(cpu) {
1076                 struct vmcs *vmcs;
1077
1078                 vmcs = alloc_vmcs_cpu(cpu);
1079                 if (!vmcs) {
1080                         free_kvm_area();
1081                         return -ENOMEM;
1082                 }
1083
1084                 per_cpu(vmxarea, cpu) = vmcs;
1085         }
1086         return 0;
1087 }
1088
1089 static __init int hardware_setup(void)
1090 {
1091         if (setup_vmcs_config(&vmcs_config) < 0)
1092                 return -EIO;
1093         return alloc_kvm_area();
1094 }
1095
1096 static __exit void hardware_unsetup(void)
1097 {
1098         free_kvm_area();
1099 }
1100
1101 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1102 {
1103         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1104
1105         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1106                 vmcs_write16(sf->selector, save->selector);
1107                 vmcs_writel(sf->base, save->base);
1108                 vmcs_write32(sf->limit, save->limit);
1109                 vmcs_write32(sf->ar_bytes, save->ar);
1110         } else {
1111                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1112                         << AR_DPL_SHIFT;
1113                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1114         }
1115 }
1116
1117 static void enter_pmode(struct kvm_vcpu *vcpu)
1118 {
1119         unsigned long flags;
1120
1121         vcpu->rmode.active = 0;
1122
1123         vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1124         vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1125         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1126
1127         flags = vmcs_readl(GUEST_RFLAGS);
1128         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1129         flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1130         vmcs_writel(GUEST_RFLAGS, flags);
1131
1132         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1133                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1134
1135         update_exception_bitmap(vcpu);
1136
1137         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1138         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1139         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1140         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1141
1142         vmcs_write16(GUEST_SS_SELECTOR, 0);
1143         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1144
1145         vmcs_write16(GUEST_CS_SELECTOR,
1146                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1147         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1148 }
1149
1150 static gva_t rmode_tss_base(struct kvm *kvm)
1151 {
1152         if (!kvm->tss_addr) {
1153                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1154                                  kvm->memslots[0].npages - 3;
1155                 return base_gfn << PAGE_SHIFT;
1156         }
1157         return kvm->tss_addr;
1158 }
1159
1160 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1161 {
1162         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1163
1164         save->selector = vmcs_read16(sf->selector);
1165         save->base = vmcs_readl(sf->base);
1166         save->limit = vmcs_read32(sf->limit);
1167         save->ar = vmcs_read32(sf->ar_bytes);
1168         vmcs_write16(sf->selector, save->base >> 4);
1169         vmcs_write32(sf->base, save->base & 0xfffff);
1170         vmcs_write32(sf->limit, 0xffff);
1171         vmcs_write32(sf->ar_bytes, 0xf3);
1172 }
1173
1174 static void enter_rmode(struct kvm_vcpu *vcpu)
1175 {
1176         unsigned long flags;
1177
1178         vcpu->rmode.active = 1;
1179
1180         vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1181         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1182
1183         vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1184         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1185
1186         vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1187         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1188
1189         flags = vmcs_readl(GUEST_RFLAGS);
1190         vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1191
1192         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1193
1194         vmcs_writel(GUEST_RFLAGS, flags);
1195         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1196         update_exception_bitmap(vcpu);
1197
1198         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1199         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1200         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1201
1202         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1203         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1204         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1205                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1206         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1207
1208         fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1209         fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1210         fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1211         fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1212
1213         kvm_mmu_reset_context(vcpu);
1214         init_rmode_tss(vcpu->kvm);
1215 }
1216
1217 #ifdef CONFIG_X86_64
1218
1219 static void enter_lmode(struct kvm_vcpu *vcpu)
1220 {
1221         u32 guest_tr_ar;
1222
1223         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1224         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1225                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1226                        __FUNCTION__);
1227                 vmcs_write32(GUEST_TR_AR_BYTES,
1228                              (guest_tr_ar & ~AR_TYPE_MASK)
1229                              | AR_TYPE_BUSY_64_TSS);
1230         }
1231
1232         vcpu->shadow_efer |= EFER_LMA;
1233
1234         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1235         vmcs_write32(VM_ENTRY_CONTROLS,
1236                      vmcs_read32(VM_ENTRY_CONTROLS)
1237                      | VM_ENTRY_IA32E_MODE);
1238 }
1239
1240 static void exit_lmode(struct kvm_vcpu *vcpu)
1241 {
1242         vcpu->shadow_efer &= ~EFER_LMA;
1243
1244         vmcs_write32(VM_ENTRY_CONTROLS,
1245                      vmcs_read32(VM_ENTRY_CONTROLS)
1246                      & ~VM_ENTRY_IA32E_MODE);
1247 }
1248
1249 #endif
1250
1251 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1252 {
1253         vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1254         vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1255 }
1256
1257 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1258 {
1259         vmx_fpu_deactivate(vcpu);
1260
1261         if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1262                 enter_pmode(vcpu);
1263
1264         if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1265                 enter_rmode(vcpu);
1266
1267 #ifdef CONFIG_X86_64
1268         if (vcpu->shadow_efer & EFER_LME) {
1269                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1270                         enter_lmode(vcpu);
1271                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1272                         exit_lmode(vcpu);
1273         }
1274 #endif
1275
1276         vmcs_writel(CR0_READ_SHADOW, cr0);
1277         vmcs_writel(GUEST_CR0,
1278                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1279         vcpu->cr0 = cr0;
1280
1281         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1282                 vmx_fpu_activate(vcpu);
1283 }
1284
1285 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1286 {
1287         vmcs_writel(GUEST_CR3, cr3);
1288         if (vcpu->cr0 & X86_CR0_PE)
1289                 vmx_fpu_deactivate(vcpu);
1290 }
1291
1292 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1293 {
1294         vmcs_writel(CR4_READ_SHADOW, cr4);
1295         vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1296                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1297         vcpu->cr4 = cr4;
1298 }
1299
1300 #ifdef CONFIG_X86_64
1301
1302 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1303 {
1304         struct vcpu_vmx *vmx = to_vmx(vcpu);
1305         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1306
1307         vcpu->shadow_efer = efer;
1308         if (efer & EFER_LMA) {
1309                 vmcs_write32(VM_ENTRY_CONTROLS,
1310                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1311                                      VM_ENTRY_IA32E_MODE);
1312                 msr->data = efer;
1313
1314         } else {
1315                 vmcs_write32(VM_ENTRY_CONTROLS,
1316                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1317                                      ~VM_ENTRY_IA32E_MODE);
1318
1319                 msr->data = efer & ~EFER_LME;
1320         }
1321         setup_msrs(vmx);
1322 }
1323
1324 #endif
1325
1326 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1327 {
1328         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1329
1330         return vmcs_readl(sf->base);
1331 }
1332
1333 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1334                             struct kvm_segment *var, int seg)
1335 {
1336         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1337         u32 ar;
1338
1339         var->base = vmcs_readl(sf->base);
1340         var->limit = vmcs_read32(sf->limit);
1341         var->selector = vmcs_read16(sf->selector);
1342         ar = vmcs_read32(sf->ar_bytes);
1343         if (ar & AR_UNUSABLE_MASK)
1344                 ar = 0;
1345         var->type = ar & 15;
1346         var->s = (ar >> 4) & 1;
1347         var->dpl = (ar >> 5) & 3;
1348         var->present = (ar >> 7) & 1;
1349         var->avl = (ar >> 12) & 1;
1350         var->l = (ar >> 13) & 1;
1351         var->db = (ar >> 14) & 1;
1352         var->g = (ar >> 15) & 1;
1353         var->unusable = (ar >> 16) & 1;
1354 }
1355
1356 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1357 {
1358         u32 ar;
1359
1360         if (var->unusable)
1361                 ar = 1 << 16;
1362         else {
1363                 ar = var->type & 15;
1364                 ar |= (var->s & 1) << 4;
1365                 ar |= (var->dpl & 3) << 5;
1366                 ar |= (var->present & 1) << 7;
1367                 ar |= (var->avl & 1) << 12;
1368                 ar |= (var->l & 1) << 13;
1369                 ar |= (var->db & 1) << 14;
1370                 ar |= (var->g & 1) << 15;
1371         }
1372         if (ar == 0) /* a 0 value means unusable */
1373                 ar = AR_UNUSABLE_MASK;
1374
1375         return ar;
1376 }
1377
1378 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1379                             struct kvm_segment *var, int seg)
1380 {
1381         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1382         u32 ar;
1383
1384         if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1385                 vcpu->rmode.tr.selector = var->selector;
1386                 vcpu->rmode.tr.base = var->base;
1387                 vcpu->rmode.tr.limit = var->limit;
1388                 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1389                 return;
1390         }
1391         vmcs_writel(sf->base, var->base);
1392         vmcs_write32(sf->limit, var->limit);
1393         vmcs_write16(sf->selector, var->selector);
1394         if (vcpu->rmode.active && var->s) {
1395                 /*
1396                  * Hack real-mode segments into vm86 compatibility.
1397                  */
1398                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1399                         vmcs_writel(sf->base, 0xf0000);
1400                 ar = 0xf3;
1401         } else
1402                 ar = vmx_segment_access_rights(var);
1403         vmcs_write32(sf->ar_bytes, ar);
1404 }
1405
1406 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1407 {
1408         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1409
1410         *db = (ar >> 14) & 1;
1411         *l = (ar >> 13) & 1;
1412 }
1413
1414 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1415 {
1416         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1417         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1418 }
1419
1420 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1421 {
1422         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1423         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1424 }
1425
1426 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1427 {
1428         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1429         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1430 }
1431
1432 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1433 {
1434         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1435         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1436 }
1437
1438 static int init_rmode_tss(struct kvm *kvm)
1439 {
1440         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1441         u16 data = 0;
1442         int r;
1443
1444         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1445         if (r < 0)
1446                 return 0;
1447         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1448         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1449         if (r < 0)
1450                 return 0;
1451         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1452         if (r < 0)
1453                 return 0;
1454         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1455         if (r < 0)
1456                 return 0;
1457         data = ~0;
1458         r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1459                         sizeof(u8));
1460         if (r < 0)
1461                 return 0;
1462         return 1;
1463 }
1464
1465 static void seg_setup(int seg)
1466 {
1467         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1468
1469         vmcs_write16(sf->selector, 0);
1470         vmcs_writel(sf->base, 0);
1471         vmcs_write32(sf->limit, 0xffff);
1472         vmcs_write32(sf->ar_bytes, 0x93);
1473 }
1474
1475 static int alloc_apic_access_page(struct kvm *kvm)
1476 {
1477         struct kvm_userspace_memory_region kvm_userspace_mem;
1478         int r = 0;
1479
1480         mutex_lock(&kvm->lock);
1481         if (kvm->apic_access_page)
1482                 goto out;
1483         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1484         kvm_userspace_mem.flags = 0;
1485         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1486         kvm_userspace_mem.memory_size = PAGE_SIZE;
1487         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1488         if (r)
1489                 goto out;
1490         kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1491 out:
1492         mutex_unlock(&kvm->lock);
1493         return r;
1494 }
1495
1496 /*
1497  * Sets up the vmcs for emulated real mode.
1498  */
1499 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1500 {
1501         u32 host_sysenter_cs;
1502         u32 junk;
1503         unsigned long a;
1504         struct descriptor_table dt;
1505         int i;
1506         unsigned long kvm_vmx_return;
1507         u32 exec_control;
1508
1509         /* I/O */
1510         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1511         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1512
1513         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1514
1515         /* Control */
1516         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1517                 vmcs_config.pin_based_exec_ctrl);
1518
1519         exec_control = vmcs_config.cpu_based_exec_ctrl;
1520         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1521                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1522 #ifdef CONFIG_X86_64
1523                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1524                                 CPU_BASED_CR8_LOAD_EXITING;
1525 #endif
1526         }
1527         if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1528                 exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1529         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1530
1531         if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1532                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
1533                              vmcs_config.cpu_based_2nd_exec_ctrl);
1534
1535         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1536         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1537         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1538
1539         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1540         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1541         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1542
1543         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1544         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1545         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1546         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1547         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1548         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1549 #ifdef CONFIG_X86_64
1550         rdmsrl(MSR_FS_BASE, a);
1551         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1552         rdmsrl(MSR_GS_BASE, a);
1553         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1554 #else
1555         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1556         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1557 #endif
1558
1559         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1560
1561         get_idt(&dt);
1562         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1563
1564         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1565         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1566         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1567         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1568         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1569
1570         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1571         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1572         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1573         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1574         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1575         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1576
1577         for (i = 0; i < NR_VMX_MSR; ++i) {
1578                 u32 index = vmx_msr_index[i];
1579                 u32 data_low, data_high;
1580                 u64 data;
1581                 int j = vmx->nmsrs;
1582
1583                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1584                         continue;
1585                 if (wrmsr_safe(index, data_low, data_high) < 0)
1586                         continue;
1587                 data = data_low | ((u64)data_high << 32);
1588                 vmx->host_msrs[j].index = index;
1589                 vmx->host_msrs[j].reserved = 0;
1590                 vmx->host_msrs[j].data = data;
1591                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1592                 ++vmx->nmsrs;
1593         }
1594
1595         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1596
1597         /* 22.2.1, 20.8.1 */
1598         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1599
1600         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1601         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1602
1603         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1604                 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1605                         return -ENOMEM;
1606
1607         return 0;
1608 }
1609
1610 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1611 {
1612         struct vcpu_vmx *vmx = to_vmx(vcpu);
1613         u64 msr;
1614         int ret;
1615
1616         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1617                 ret = -ENOMEM;
1618                 goto out;
1619         }
1620
1621         vmx->vcpu.rmode.active = 0;
1622
1623         vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1624         set_cr8(&vmx->vcpu, 0);
1625         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1626         if (vmx->vcpu.vcpu_id == 0)
1627                 msr |= MSR_IA32_APICBASE_BSP;
1628         kvm_set_apic_base(&vmx->vcpu, msr);
1629
1630         fx_init(&vmx->vcpu);
1631
1632         /*
1633          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1634          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1635          */
1636         if (vmx->vcpu.vcpu_id == 0) {
1637                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1638                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1639         } else {
1640                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1641                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1642         }
1643         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1644         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1645
1646         seg_setup(VCPU_SREG_DS);
1647         seg_setup(VCPU_SREG_ES);
1648         seg_setup(VCPU_SREG_FS);
1649         seg_setup(VCPU_SREG_GS);
1650         seg_setup(VCPU_SREG_SS);
1651
1652         vmcs_write16(GUEST_TR_SELECTOR, 0);
1653         vmcs_writel(GUEST_TR_BASE, 0);
1654         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1655         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1656
1657         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1658         vmcs_writel(GUEST_LDTR_BASE, 0);
1659         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1660         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1661
1662         vmcs_write32(GUEST_SYSENTER_CS, 0);
1663         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1664         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1665
1666         vmcs_writel(GUEST_RFLAGS, 0x02);
1667         if (vmx->vcpu.vcpu_id == 0)
1668                 vmcs_writel(GUEST_RIP, 0xfff0);
1669         else
1670                 vmcs_writel(GUEST_RIP, 0);
1671         vmcs_writel(GUEST_RSP, 0);
1672
1673         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1674         vmcs_writel(GUEST_DR7, 0x400);
1675
1676         vmcs_writel(GUEST_GDTR_BASE, 0);
1677         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1678
1679         vmcs_writel(GUEST_IDTR_BASE, 0);
1680         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1681
1682         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1683         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1684         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1685
1686         guest_write_tsc(0);
1687
1688         /* Special registers */
1689         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1690
1691         setup_msrs(vmx);
1692
1693         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1694
1695         if (cpu_has_vmx_tpr_shadow()) {
1696                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1697                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1698                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1699                                      page_to_phys(vmx->vcpu.apic->regs_page));
1700                 vmcs_write32(TPR_THRESHOLD, 0);
1701         }
1702
1703         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1704                 vmcs_write64(APIC_ACCESS_ADDR,
1705                              page_to_phys(vmx->vcpu.kvm->apic_access_page));
1706
1707         vmx->vcpu.cr0 = 0x60000010;
1708         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1709         vmx_set_cr4(&vmx->vcpu, 0);
1710 #ifdef CONFIG_X86_64
1711         vmx_set_efer(&vmx->vcpu, 0);
1712 #endif
1713         vmx_fpu_activate(&vmx->vcpu);
1714         update_exception_bitmap(&vmx->vcpu);
1715
1716         return 0;
1717
1718 out:
1719         return ret;
1720 }
1721
1722 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1723 {
1724         struct vcpu_vmx *vmx = to_vmx(vcpu);
1725
1726         if (vcpu->rmode.active) {
1727                 vmx->rmode.irq.pending = true;
1728                 vmx->rmode.irq.vector = irq;
1729                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1730                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1731                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1732                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1733                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1734                 return;
1735         }
1736         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1737                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1738 }
1739
1740 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1741 {
1742         int word_index = __ffs(vcpu->irq_summary);
1743         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1744         int irq = word_index * BITS_PER_LONG + bit_index;
1745
1746         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1747         if (!vcpu->irq_pending[word_index])
1748                 clear_bit(word_index, &vcpu->irq_summary);
1749         vmx_inject_irq(vcpu, irq);
1750 }
1751
1752
1753 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1754                                        struct kvm_run *kvm_run)
1755 {
1756         u32 cpu_based_vm_exec_control;
1757
1758         vcpu->interrupt_window_open =
1759                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1760                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1761
1762         if (vcpu->interrupt_window_open &&
1763             vcpu->irq_summary &&
1764             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1765                 /*
1766                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1767                  */
1768                 kvm_do_inject_irq(vcpu);
1769
1770         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1771         if (!vcpu->interrupt_window_open &&
1772             (vcpu->irq_summary || kvm_run->request_interrupt_window))
1773                 /*
1774                  * Interrupts blocked.  Wait for unblock.
1775                  */
1776                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1777         else
1778                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1779         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1780 }
1781
1782 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1783 {
1784         int ret;
1785         struct kvm_userspace_memory_region tss_mem = {
1786                 .slot = 8,
1787                 .guest_phys_addr = addr,
1788                 .memory_size = PAGE_SIZE * 3,
1789                 .flags = 0,
1790         };
1791
1792         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1793         if (ret)
1794                 return ret;
1795         kvm->tss_addr = addr;
1796         return 0;
1797 }
1798
1799 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1800 {
1801         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1802
1803         set_debugreg(dbg->bp[0], 0);
1804         set_debugreg(dbg->bp[1], 1);
1805         set_debugreg(dbg->bp[2], 2);
1806         set_debugreg(dbg->bp[3], 3);
1807
1808         if (dbg->singlestep) {
1809                 unsigned long flags;
1810
1811                 flags = vmcs_readl(GUEST_RFLAGS);
1812                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1813                 vmcs_writel(GUEST_RFLAGS, flags);
1814         }
1815 }
1816
1817 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1818                                   int vec, u32 err_code)
1819 {
1820         if (!vcpu->rmode.active)
1821                 return 0;
1822
1823         /*
1824          * Instruction with address size override prefix opcode 0x67
1825          * Cause the #SS fault with 0 error code in VM86 mode.
1826          */
1827         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1828                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1829                         return 1;
1830         return 0;
1831 }
1832
1833 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1834 {
1835         struct vcpu_vmx *vmx = to_vmx(vcpu);
1836         u32 intr_info, error_code;
1837         unsigned long cr2, rip;
1838         u32 vect_info;
1839         enum emulation_result er;
1840
1841         vect_info = vmx->idt_vectoring_info;
1842         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1843
1844         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1845                                                 !is_page_fault(intr_info))
1846                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1847                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1848
1849         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1850                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1851                 set_bit(irq, vcpu->irq_pending);
1852                 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1853         }
1854
1855         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1856                 return 1;  /* already handled by vmx_vcpu_run() */
1857
1858         if (is_no_device(intr_info)) {
1859                 vmx_fpu_activate(vcpu);
1860                 return 1;
1861         }
1862
1863         if (is_invalid_opcode(intr_info)) {
1864                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1865                 if (er != EMULATE_DONE)
1866                         vmx_inject_ud(vcpu);
1867
1868                 return 1;
1869         }
1870
1871         error_code = 0;
1872         rip = vmcs_readl(GUEST_RIP);
1873         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1874                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1875         if (is_page_fault(intr_info)) {
1876                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1877                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1878         }
1879
1880         if (vcpu->rmode.active &&
1881             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1882                                                                 error_code)) {
1883                 if (vcpu->halt_request) {
1884                         vcpu->halt_request = 0;
1885                         return kvm_emulate_halt(vcpu);
1886                 }
1887                 return 1;
1888         }
1889
1890         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1891             (INTR_TYPE_EXCEPTION | 1)) {
1892                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1893                 return 0;
1894         }
1895         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1896         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1897         kvm_run->ex.error_code = error_code;
1898         return 0;
1899 }
1900
1901 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1902                                      struct kvm_run *kvm_run)
1903 {
1904         ++vcpu->stat.irq_exits;
1905         return 1;
1906 }
1907
1908 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1909 {
1910         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1911         return 0;
1912 }
1913
1914 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1915 {
1916         unsigned long exit_qualification;
1917         int size, down, in, string, rep;
1918         unsigned port;
1919
1920         ++vcpu->stat.io_exits;
1921         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1922         string = (exit_qualification & 16) != 0;
1923
1924         if (string) {
1925                 if (emulate_instruction(vcpu,
1926                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1927                         return 0;
1928                 return 1;
1929         }
1930
1931         size = (exit_qualification & 7) + 1;
1932         in = (exit_qualification & 8) != 0;
1933         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1934         rep = (exit_qualification & 32) != 0;
1935         port = exit_qualification >> 16;
1936
1937         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1938 }
1939
1940 static void
1941 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1942 {
1943         /*
1944          * Patch in the VMCALL instruction:
1945          */
1946         hypercall[0] = 0x0f;
1947         hypercall[1] = 0x01;
1948         hypercall[2] = 0xc1;
1949 }
1950
1951 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1952 {
1953         unsigned long exit_qualification;
1954         int cr;
1955         int reg;
1956
1957         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1958         cr = exit_qualification & 15;
1959         reg = (exit_qualification >> 8) & 15;
1960         switch ((exit_qualification >> 4) & 3) {
1961         case 0: /* mov to cr */
1962                 switch (cr) {
1963                 case 0:
1964                         vcpu_load_rsp_rip(vcpu);
1965                         set_cr0(vcpu, vcpu->regs[reg]);
1966                         skip_emulated_instruction(vcpu);
1967                         return 1;
1968                 case 3:
1969                         vcpu_load_rsp_rip(vcpu);
1970                         set_cr3(vcpu, vcpu->regs[reg]);
1971                         skip_emulated_instruction(vcpu);
1972                         return 1;
1973                 case 4:
1974                         vcpu_load_rsp_rip(vcpu);
1975                         set_cr4(vcpu, vcpu->regs[reg]);
1976                         skip_emulated_instruction(vcpu);
1977                         return 1;
1978                 case 8:
1979                         vcpu_load_rsp_rip(vcpu);
1980                         set_cr8(vcpu, vcpu->regs[reg]);
1981                         skip_emulated_instruction(vcpu);
1982                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1983                         return 0;
1984                 };
1985                 break;
1986         case 2: /* clts */
1987                 vcpu_load_rsp_rip(vcpu);
1988                 vmx_fpu_deactivate(vcpu);
1989                 vcpu->cr0 &= ~X86_CR0_TS;
1990                 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1991                 vmx_fpu_activate(vcpu);
1992                 skip_emulated_instruction(vcpu);
1993                 return 1;
1994         case 1: /*mov from cr*/
1995                 switch (cr) {
1996                 case 3:
1997                         vcpu_load_rsp_rip(vcpu);
1998                         vcpu->regs[reg] = vcpu->cr3;
1999                         vcpu_put_rsp_rip(vcpu);
2000                         skip_emulated_instruction(vcpu);
2001                         return 1;
2002                 case 8:
2003                         vcpu_load_rsp_rip(vcpu);
2004                         vcpu->regs[reg] = get_cr8(vcpu);
2005                         vcpu_put_rsp_rip(vcpu);
2006                         skip_emulated_instruction(vcpu);
2007                         return 1;
2008                 }
2009                 break;
2010         case 3: /* lmsw */
2011                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2012
2013                 skip_emulated_instruction(vcpu);
2014                 return 1;
2015         default:
2016                 break;
2017         }
2018         kvm_run->exit_reason = 0;
2019         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2020                (int)(exit_qualification >> 4) & 3, cr);
2021         return 0;
2022 }
2023
2024 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2025 {
2026         unsigned long exit_qualification;
2027         unsigned long val;
2028         int dr, reg;
2029
2030         /*
2031          * FIXME: this code assumes the host is debugging the guest.
2032          *        need to deal with guest debugging itself too.
2033          */
2034         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2035         dr = exit_qualification & 7;
2036         reg = (exit_qualification >> 8) & 15;
2037         vcpu_load_rsp_rip(vcpu);
2038         if (exit_qualification & 16) {
2039                 /* mov from dr */
2040                 switch (dr) {
2041                 case 6:
2042                         val = 0xffff0ff0;
2043                         break;
2044                 case 7:
2045                         val = 0x400;
2046                         break;
2047                 default:
2048                         val = 0;
2049                 }
2050                 vcpu->regs[reg] = val;
2051         } else {
2052                 /* mov to dr */
2053         }
2054         vcpu_put_rsp_rip(vcpu);
2055         skip_emulated_instruction(vcpu);
2056         return 1;
2057 }
2058
2059 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2060 {
2061         kvm_emulate_cpuid(vcpu);
2062         return 1;
2063 }
2064
2065 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2066 {
2067         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2068         u64 data;
2069
2070         if (vmx_get_msr(vcpu, ecx, &data)) {
2071                 vmx_inject_gp(vcpu, 0);
2072                 return 1;
2073         }
2074
2075         /* FIXME: handling of bits 32:63 of rax, rdx */
2076         vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2077         vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2078         skip_emulated_instruction(vcpu);
2079         return 1;
2080 }
2081
2082 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2083 {
2084         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2085         u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2086                 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2087
2088         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2089                 vmx_inject_gp(vcpu, 0);
2090                 return 1;
2091         }
2092
2093         skip_emulated_instruction(vcpu);
2094         return 1;
2095 }
2096
2097 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2098                                       struct kvm_run *kvm_run)
2099 {
2100         return 1;
2101 }
2102
2103 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2104                                    struct kvm_run *kvm_run)
2105 {
2106         u32 cpu_based_vm_exec_control;
2107
2108         /* clear pending irq */
2109         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2110         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2111         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2112         /*
2113          * If the user space waits to inject interrupts, exit as soon as
2114          * possible
2115          */
2116         if (kvm_run->request_interrupt_window &&
2117             !vcpu->irq_summary) {
2118                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2119                 ++vcpu->stat.irq_window_exits;
2120                 return 0;
2121         }
2122         return 1;
2123 }
2124
2125 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2126 {
2127         skip_emulated_instruction(vcpu);
2128         return kvm_emulate_halt(vcpu);
2129 }
2130
2131 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2132 {
2133         skip_emulated_instruction(vcpu);
2134         kvm_emulate_hypercall(vcpu);
2135         return 1;
2136 }
2137
2138 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2139 {
2140         skip_emulated_instruction(vcpu);
2141         /* TODO: Add support for VT-d/pass-through device */
2142         return 1;
2143 }
2144
2145 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2146 {
2147         u64 exit_qualification;
2148         enum emulation_result er;
2149         unsigned long offset;
2150
2151         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2152         offset = exit_qualification & 0xffful;
2153
2154         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2155
2156         if (er !=  EMULATE_DONE) {
2157                 printk(KERN_ERR
2158                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2159                        offset);
2160                 return -ENOTSUPP;
2161         }
2162         return 1;
2163 }
2164
2165 /*
2166  * The exit handlers return 1 if the exit was handled fully and guest execution
2167  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2168  * to be done to userspace and return 0.
2169  */
2170 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2171                                       struct kvm_run *kvm_run) = {
2172         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2173         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2174         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2175         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2176         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2177         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2178         [EXIT_REASON_CPUID]                   = handle_cpuid,
2179         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2180         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2181         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2182         [EXIT_REASON_HLT]                     = handle_halt,
2183         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2184         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2185         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2186         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2187 };
2188
2189 static const int kvm_vmx_max_exit_handlers =
2190         ARRAY_SIZE(kvm_vmx_exit_handlers);
2191
2192 /*
2193  * The guest has exited.  See if we can fix it or if we need userspace
2194  * assistance.
2195  */
2196 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2197 {
2198         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2199         struct vcpu_vmx *vmx = to_vmx(vcpu);
2200         u32 vectoring_info = vmx->idt_vectoring_info;
2201
2202         if (unlikely(vmx->fail)) {
2203                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2204                 kvm_run->fail_entry.hardware_entry_failure_reason
2205                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2206                 return 0;
2207         }
2208
2209         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2210                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2211                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2212                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2213         if (exit_reason < kvm_vmx_max_exit_handlers
2214             && kvm_vmx_exit_handlers[exit_reason])
2215                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2216         else {
2217                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2218                 kvm_run->hw.hardware_exit_reason = exit_reason;
2219         }
2220         return 0;
2221 }
2222
2223 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2224 {
2225 }
2226
2227 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2228 {
2229         int max_irr, tpr;
2230
2231         if (!vm_need_tpr_shadow(vcpu->kvm))
2232                 return;
2233
2234         if (!kvm_lapic_enabled(vcpu) ||
2235             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2236                 vmcs_write32(TPR_THRESHOLD, 0);
2237                 return;
2238         }
2239
2240         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2241         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2242 }
2243
2244 static void enable_irq_window(struct kvm_vcpu *vcpu)
2245 {
2246         u32 cpu_based_vm_exec_control;
2247
2248         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2249         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2250         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2251 }
2252
2253 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2254 {
2255         struct vcpu_vmx *vmx = to_vmx(vcpu);
2256         u32 idtv_info_field, intr_info_field;
2257         int has_ext_irq, interrupt_window_open;
2258         int vector;
2259
2260         update_tpr_threshold(vcpu);
2261
2262         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2263         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2264         idtv_info_field = vmx->idt_vectoring_info;
2265         if (intr_info_field & INTR_INFO_VALID_MASK) {
2266                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2267                         /* TODO: fault when IDT_Vectoring */
2268                         printk(KERN_ERR "Fault when IDT_Vectoring\n");
2269                 }
2270                 if (has_ext_irq)
2271                         enable_irq_window(vcpu);
2272                 return;
2273         }
2274         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2275                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2276                     == INTR_TYPE_EXT_INTR
2277                     && vcpu->rmode.active) {
2278                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2279
2280                         vmx_inject_irq(vcpu, vect);
2281                         if (unlikely(has_ext_irq))
2282                                 enable_irq_window(vcpu);
2283                         return;
2284                 }
2285
2286                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2287                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2288                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2289
2290                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2291                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2292                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2293                 if (unlikely(has_ext_irq))
2294                         enable_irq_window(vcpu);
2295                 return;
2296         }
2297         if (!has_ext_irq)
2298                 return;
2299         interrupt_window_open =
2300                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2301                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2302         if (interrupt_window_open) {
2303                 vector = kvm_cpu_get_interrupt(vcpu);
2304                 vmx_inject_irq(vcpu, vector);
2305                 kvm_timer_intr_post(vcpu, vector);
2306         } else
2307                 enable_irq_window(vcpu);
2308 }
2309
2310 /*
2311  * Failure to inject an interrupt should give us the information
2312  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2313  * when fetching the interrupt redirection bitmap in the real-mode
2314  * tss, this doesn't happen.  So we do it ourselves.
2315  */
2316 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2317 {
2318         vmx->rmode.irq.pending = 0;
2319         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2320                 return;
2321         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2322         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2323                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2324                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2325                 return;
2326         }
2327         vmx->idt_vectoring_info =
2328                 VECTORING_INFO_VALID_MASK
2329                 | INTR_TYPE_EXT_INTR
2330                 | vmx->rmode.irq.vector;
2331 }
2332
2333 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2334 {
2335         struct vcpu_vmx *vmx = to_vmx(vcpu);
2336         u32 intr_info;
2337
2338         /*
2339          * Loading guest fpu may have cleared host cr0.ts
2340          */
2341         vmcs_writel(HOST_CR0, read_cr0());
2342
2343         asm(
2344                 /* Store host registers */
2345 #ifdef CONFIG_X86_64
2346                 "push %%rdx; push %%rbp;"
2347                 "push %%rcx \n\t"
2348 #else
2349                 "push %%edx; push %%ebp;"
2350                 "push %%ecx \n\t"
2351 #endif
2352                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2353                 /* Check if vmlaunch of vmresume is needed */
2354                 "cmpl $0, %c[launched](%0) \n\t"
2355                 /* Load guest registers.  Don't clobber flags. */
2356 #ifdef CONFIG_X86_64
2357                 "mov %c[cr2](%0), %%rax \n\t"
2358                 "mov %%rax, %%cr2 \n\t"
2359                 "mov %c[rax](%0), %%rax \n\t"
2360                 "mov %c[rbx](%0), %%rbx \n\t"
2361                 "mov %c[rdx](%0), %%rdx \n\t"
2362                 "mov %c[rsi](%0), %%rsi \n\t"
2363                 "mov %c[rdi](%0), %%rdi \n\t"
2364                 "mov %c[rbp](%0), %%rbp \n\t"
2365                 "mov %c[r8](%0),  %%r8  \n\t"
2366                 "mov %c[r9](%0),  %%r9  \n\t"
2367                 "mov %c[r10](%0), %%r10 \n\t"
2368                 "mov %c[r11](%0), %%r11 \n\t"
2369                 "mov %c[r12](%0), %%r12 \n\t"
2370                 "mov %c[r13](%0), %%r13 \n\t"
2371                 "mov %c[r14](%0), %%r14 \n\t"
2372                 "mov %c[r15](%0), %%r15 \n\t"
2373                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2374 #else
2375                 "mov %c[cr2](%0), %%eax \n\t"
2376                 "mov %%eax,   %%cr2 \n\t"
2377                 "mov %c[rax](%0), %%eax \n\t"
2378                 "mov %c[rbx](%0), %%ebx \n\t"
2379                 "mov %c[rdx](%0), %%edx \n\t"
2380                 "mov %c[rsi](%0), %%esi \n\t"
2381                 "mov %c[rdi](%0), %%edi \n\t"
2382                 "mov %c[rbp](%0), %%ebp \n\t"
2383                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2384 #endif
2385                 /* Enter guest mode */
2386                 "jne .Llaunched \n\t"
2387                 ASM_VMX_VMLAUNCH "\n\t"
2388                 "jmp .Lkvm_vmx_return \n\t"
2389                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2390                 ".Lkvm_vmx_return: "
2391                 /* Save guest registers, load host registers, keep flags */
2392 #ifdef CONFIG_X86_64
2393                 "xchg %0,     (%%rsp) \n\t"
2394                 "mov %%rax, %c[rax](%0) \n\t"
2395                 "mov %%rbx, %c[rbx](%0) \n\t"
2396                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2397                 "mov %%rdx, %c[rdx](%0) \n\t"
2398                 "mov %%rsi, %c[rsi](%0) \n\t"
2399                 "mov %%rdi, %c[rdi](%0) \n\t"
2400                 "mov %%rbp, %c[rbp](%0) \n\t"
2401                 "mov %%r8,  %c[r8](%0) \n\t"
2402                 "mov %%r9,  %c[r9](%0) \n\t"
2403                 "mov %%r10, %c[r10](%0) \n\t"
2404                 "mov %%r11, %c[r11](%0) \n\t"
2405                 "mov %%r12, %c[r12](%0) \n\t"
2406                 "mov %%r13, %c[r13](%0) \n\t"
2407                 "mov %%r14, %c[r14](%0) \n\t"
2408                 "mov %%r15, %c[r15](%0) \n\t"
2409                 "mov %%cr2, %%rax   \n\t"
2410                 "mov %%rax, %c[cr2](%0) \n\t"
2411
2412                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2413 #else
2414                 "xchg %0, (%%esp) \n\t"
2415                 "mov %%eax, %c[rax](%0) \n\t"
2416                 "mov %%ebx, %c[rbx](%0) \n\t"
2417                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2418                 "mov %%edx, %c[rdx](%0) \n\t"
2419                 "mov %%esi, %c[rsi](%0) \n\t"
2420                 "mov %%edi, %c[rdi](%0) \n\t"
2421                 "mov %%ebp, %c[rbp](%0) \n\t"
2422                 "mov %%cr2, %%eax  \n\t"
2423                 "mov %%eax, %c[cr2](%0) \n\t"
2424
2425                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2426 #endif
2427                 "setbe %c[fail](%0) \n\t"
2428               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2429                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2430                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2431                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RAX])),
2432                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBX])),
2433                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RCX])),
2434                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDX])),
2435                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RSI])),
2436                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDI])),
2437                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBP])),
2438 #ifdef CONFIG_X86_64
2439                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R8])),
2440                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R9])),
2441                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R10])),
2442                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R11])),
2443                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R12])),
2444                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R13])),
2445                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R14])),
2446                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R15])),
2447 #endif
2448                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.cr2))
2449               : "cc", "memory"
2450 #ifdef CONFIG_X86_64
2451                 , "rbx", "rdi", "rsi"
2452                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2453 #else
2454                 , "ebx", "edi", "rsi"
2455 #endif
2456               );
2457
2458         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2459         if (vmx->rmode.irq.pending)
2460                 fixup_rmode_irq(vmx);
2461
2462         vcpu->interrupt_window_open =
2463                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2464
2465         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2466         vmx->launched = 1;
2467
2468         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2469
2470         /* We need to handle NMIs before interrupts are enabled */
2471         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2472                 asm("int $2");
2473 }
2474
2475 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2476                                   unsigned long addr,
2477                                   u32 err_code)
2478 {
2479         struct vcpu_vmx *vmx = to_vmx(vcpu);
2480         u32 vect_info = vmx->idt_vectoring_info;
2481
2482         ++vcpu->stat.pf_guest;
2483
2484         if (is_page_fault(vect_info)) {
2485                 printk(KERN_DEBUG "inject_page_fault: "
2486                        "double fault 0x%lx @ 0x%lx\n",
2487                        addr, vmcs_readl(GUEST_RIP));
2488                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2489                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2490                              DF_VECTOR |
2491                              INTR_TYPE_EXCEPTION |
2492                              INTR_INFO_DELIEVER_CODE_MASK |
2493                              INTR_INFO_VALID_MASK);
2494                 return;
2495         }
2496         vcpu->cr2 = addr;
2497         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2498         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2499                      PF_VECTOR |
2500                      INTR_TYPE_EXCEPTION |
2501                      INTR_INFO_DELIEVER_CODE_MASK |
2502                      INTR_INFO_VALID_MASK);
2503
2504 }
2505
2506 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2507 {
2508         struct vcpu_vmx *vmx = to_vmx(vcpu);
2509
2510         if (vmx->vmcs) {
2511                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2512                 free_vmcs(vmx->vmcs);
2513                 vmx->vmcs = NULL;
2514         }
2515 }
2516
2517 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2518 {
2519         struct vcpu_vmx *vmx = to_vmx(vcpu);
2520
2521         vmx_free_vmcs(vcpu);
2522         kfree(vmx->host_msrs);
2523         kfree(vmx->guest_msrs);
2524         kvm_vcpu_uninit(vcpu);
2525         kmem_cache_free(kvm_vcpu_cache, vmx);
2526 }
2527
2528 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2529 {
2530         int err;
2531         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2532         int cpu;
2533
2534         if (!vmx)
2535                 return ERR_PTR(-ENOMEM);
2536
2537         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2538         if (err)
2539                 goto free_vcpu;
2540
2541         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2542         if (!vmx->guest_msrs) {
2543                 err = -ENOMEM;
2544                 goto uninit_vcpu;
2545         }
2546
2547         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2548         if (!vmx->host_msrs)
2549                 goto free_guest_msrs;
2550
2551         vmx->vmcs = alloc_vmcs();
2552         if (!vmx->vmcs)
2553                 goto free_msrs;
2554
2555         vmcs_clear(vmx->vmcs);
2556
2557         cpu = get_cpu();
2558         vmx_vcpu_load(&vmx->vcpu, cpu);
2559         err = vmx_vcpu_setup(vmx);
2560         vmx_vcpu_put(&vmx->vcpu);
2561         put_cpu();
2562         if (err)
2563                 goto free_vmcs;
2564
2565         return &vmx->vcpu;
2566
2567 free_vmcs:
2568         free_vmcs(vmx->vmcs);
2569 free_msrs:
2570         kfree(vmx->host_msrs);
2571 free_guest_msrs:
2572         kfree(vmx->guest_msrs);
2573 uninit_vcpu:
2574         kvm_vcpu_uninit(&vmx->vcpu);
2575 free_vcpu:
2576         kmem_cache_free(kvm_vcpu_cache, vmx);
2577         return ERR_PTR(err);
2578 }
2579
2580 static void __init vmx_check_processor_compat(void *rtn)
2581 {
2582         struct vmcs_config vmcs_conf;
2583
2584         *(int *)rtn = 0;
2585         if (setup_vmcs_config(&vmcs_conf) < 0)
2586                 *(int *)rtn = -EIO;
2587         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2588                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2589                                 smp_processor_id());
2590                 *(int *)rtn = -EIO;
2591         }
2592 }
2593
2594 static struct kvm_x86_ops vmx_x86_ops = {
2595         .cpu_has_kvm_support = cpu_has_kvm_support,
2596         .disabled_by_bios = vmx_disabled_by_bios,
2597         .hardware_setup = hardware_setup,
2598         .hardware_unsetup = hardware_unsetup,
2599         .check_processor_compatibility = vmx_check_processor_compat,
2600         .hardware_enable = hardware_enable,
2601         .hardware_disable = hardware_disable,
2602
2603         .vcpu_create = vmx_create_vcpu,
2604         .vcpu_free = vmx_free_vcpu,
2605         .vcpu_reset = vmx_vcpu_reset,
2606
2607         .prepare_guest_switch = vmx_save_host_state,
2608         .vcpu_load = vmx_vcpu_load,
2609         .vcpu_put = vmx_vcpu_put,
2610         .vcpu_decache = vmx_vcpu_decache,
2611
2612         .set_guest_debug = set_guest_debug,
2613         .guest_debug_pre = kvm_guest_debug_pre,
2614         .get_msr = vmx_get_msr,
2615         .set_msr = vmx_set_msr,
2616         .get_segment_base = vmx_get_segment_base,
2617         .get_segment = vmx_get_segment,
2618         .set_segment = vmx_set_segment,
2619         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2620         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2621         .set_cr0 = vmx_set_cr0,
2622         .set_cr3 = vmx_set_cr3,
2623         .set_cr4 = vmx_set_cr4,
2624 #ifdef CONFIG_X86_64
2625         .set_efer = vmx_set_efer,
2626 #endif
2627         .get_idt = vmx_get_idt,
2628         .set_idt = vmx_set_idt,
2629         .get_gdt = vmx_get_gdt,
2630         .set_gdt = vmx_set_gdt,
2631         .cache_regs = vcpu_load_rsp_rip,
2632         .decache_regs = vcpu_put_rsp_rip,
2633         .get_rflags = vmx_get_rflags,
2634         .set_rflags = vmx_set_rflags,
2635
2636         .tlb_flush = vmx_flush_tlb,
2637         .inject_page_fault = vmx_inject_page_fault,
2638
2639         .inject_gp = vmx_inject_gp,
2640
2641         .run = vmx_vcpu_run,
2642         .handle_exit = kvm_handle_exit,
2643         .skip_emulated_instruction = skip_emulated_instruction,
2644         .patch_hypercall = vmx_patch_hypercall,
2645         .get_irq = vmx_get_irq,
2646         .set_irq = vmx_inject_irq,
2647         .inject_pending_irq = vmx_intr_assist,
2648         .inject_pending_vectors = do_interrupt_requests,
2649
2650         .set_tss_addr = vmx_set_tss_addr,
2651 };
2652
2653 static int __init vmx_init(void)
2654 {
2655         void *iova;
2656         int r;
2657
2658         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2659         if (!vmx_io_bitmap_a)
2660                 return -ENOMEM;
2661
2662         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2663         if (!vmx_io_bitmap_b) {
2664                 r = -ENOMEM;
2665                 goto out;
2666         }
2667
2668         /*
2669          * Allow direct access to the PC debug port (it is often used for I/O
2670          * delays, but the vmexits simply slow things down).
2671          */
2672         iova = kmap(vmx_io_bitmap_a);
2673         memset(iova, 0xff, PAGE_SIZE);
2674         clear_bit(0x80, iova);
2675         kunmap(vmx_io_bitmap_a);
2676
2677         iova = kmap(vmx_io_bitmap_b);
2678         memset(iova, 0xff, PAGE_SIZE);
2679         kunmap(vmx_io_bitmap_b);
2680
2681         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2682         if (r)
2683                 goto out1;
2684
2685         if (bypass_guest_pf)
2686                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2687
2688         return 0;
2689
2690 out1:
2691         __free_page(vmx_io_bitmap_b);
2692 out:
2693         __free_page(vmx_io_bitmap_a);
2694         return r;
2695 }
2696
2697 static void __exit vmx_exit(void)
2698 {
2699         __free_page(vmx_io_bitmap_b);
2700         __free_page(vmx_io_bitmap_a);
2701
2702         kvm_exit();
2703 }
2704
2705 module_init(vmx_init)
2706 module_exit(vmx_exit)