2 * Static Memory Controller for AT32 chips
4 * Copyright (C) 2006 Atmel Corporation
6 * Inspired by the OMAP2 General-Purpose Memory Controller interface
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #ifndef __ARCH_AT32AP_SMC_H
13 #define __ARCH_AT32AP_SMC_H
16 * All timing parameters are in nanoseconds.
19 /* Delay from address valid to assertion of given strobe */
25 /* Pulse length of given strobe */
31 /* Total cycle length of given operation */
35 /* Bus width in bytes */
39 * 0: Data is sampled on rising edge of NCS
40 * 1: Data is sampled on rising edge of NRD
42 unsigned int nrd_controlled:1;
45 * 0: Data is driven on falling edge of NCS
46 * 1: Data is driven on falling edge of NWR
48 unsigned int nwe_controlled:1;
51 * 0: NWAIT is disabled
53 * 2: NWAIT is frozen mode
54 * 3: NWAIT in ready mode
56 unsigned int nwait_mode:2;
59 * 0: Byte select access type
60 * 1: Byte write access type
62 unsigned int byte_write:1;
65 * Number of clock cycles before data is released after
66 * the rising edge of the read controlling signal
68 * Total cycles from SMC is tdf_cycles + 1
70 unsigned int tdf_cycles:4;
73 * 0: TDF optimization disabled
74 * 1: TDF optimization enabled
76 unsigned int tdf_mode:1;
79 extern int smc_set_configuration(int cs, const struct smc_config *config);
80 extern struct smc_config *smc_get_configuration(int cs);
82 #endif /* __ARCH_AT32AP_SMC_H */