git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Copyright (C) 2000-2003 Broadcom Corporation.
  11  */
  12
  13 #include <linux/config.h>
  14
  15 #include <linux/module.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/compiler.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/ioport.h>
  24 #include <linux/pci.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/ethtool.h>
  29 #include <linux/mii.h>
  30 #include <linux/if_vlan.h>
  31 #include <linux/ip.h>
  32 #include <linux/tcp.h>
  33 #include <linux/workqueue.h>
  34
  35 #include <net/checksum.h>
  36
  37 #include <asm/system.h>
  38 #include <asm/io.h>
  39 #include <asm/byteorder.h>
  40 #include <asm/uaccess.h>
  41
  42 #ifdef CONFIG_SPARC64
  43 #include <asm/idprom.h>
  44 #include <asm/oplib.h>
  45 #include <asm/pbm.h>
  46 #endif
  47
  48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  49 #define TG3_VLAN_TAG_USED 1
  50 #else
  51 #define TG3_VLAN_TAG_USED 0
  52 #endif
  53
  54 #ifdef NETIF_F_TSO
  55 #define TG3_TSO_SUPPORT 1
  56 #else
  57 #define TG3_TSO_SUPPORT 0
  58 #endif
  59
  60 #include "tg3.h"
  61
  62 #define DRV_MODULE_NAME         "tg3"
  63 #define PFX DRV_MODULE_NAME     ": "
  64 #define DRV_MODULE_VERSION      "3.29"
  65 #define DRV_MODULE_RELDATE      "May 23, 2005"
  66
  67 #define TG3_DEF_MAC_MODE        0
  68 #define TG3_DEF_RX_MODE         0
  69 #define TG3_DEF_TX_MODE         0
  70 #define TG3_DEF_MSG_ENABLE        \
  71         (NETIF_MSG_DRV          | \
  72          NETIF_MSG_PROBE        | \
  73          NETIF_MSG_LINK         | \
  74          NETIF_MSG_TIMER        | \
  75          NETIF_MSG_IFDOWN       | \
  76          NETIF_MSG_IFUP         | \
  77          NETIF_MSG_RX_ERR       | \
  78          NETIF_MSG_TX_ERR)
  79
  80 /* length of time before we decide the hardware is borked,
  81  * and dev->tx_timeout() should be called to fix the problem
  82  */
  83 #define TG3_TX_TIMEOUT                  (5 * HZ)
  84
  85 /* hardware minimum and maximum for a single frame's data payload */
  86 #define TG3_MIN_MTU                     60
  87 #define TG3_MAX_MTU(tp) \
  88         (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
  89
  90 /* These numbers seem to be hard coded in the NIC firmware somehow.
  91  * You can't change the ring sizes, but you can change where you place
  92  * them in the NIC onboard memory.
  93  */
  94 #define TG3_RX_RING_SIZE                512
  95 #define TG3_DEF_RX_RING_PENDING         200
  96 #define TG3_RX_JUMBO_RING_SIZE          256
  97 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
  98
  99 /* Do not place this n-ring entries value into the tp struct itself,
 100  * we really want to expose these constants to GCC so that modulo et
 101  * al.  operations are done with shifts and masks instead of with
 102  * hw multiply/modulo instructions.  Another solution would be to
 103  * replace things like '% foo' with '& (foo - 1)'.
 104  */
 105 #define TG3_RX_RCB_RING_SIZE(tp)        \
 106         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 107
 108 #define TG3_TX_RING_SIZE                512
 109 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 110
 111 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 112                                  TG3_RX_RING_SIZE)
 113 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 114                                  TG3_RX_JUMBO_RING_SIZE)
 115 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 116                                    TG3_RX_RCB_RING_SIZE(tp))
 117 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 118                                  TG3_TX_RING_SIZE)
 119 #define TX_RING_GAP(TP) \
 120         (TG3_TX_RING_SIZE - (TP)->tx_pending)
 121 #define TX_BUFFS_AVAIL(TP)                                              \
 122         (((TP)->tx_cons <= (TP)->tx_prod) ?                             \
 123           (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod :            \
 124           (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
 125 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 126
 127 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 128 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 129
 130 /* minimum number of free TX descriptors required to wake up TX process */
 131 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 132
 133 /* number of ETHTOOL_GSTATS u64's */
 134 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 135
 136 #define TG3_NUM_TEST            6
 137
 138 static char version[] __devinitdata =
 139         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 140
 141 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 142 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 143 MODULE_LICENSE("GPL");
 144 MODULE_VERSION(DRV_MODULE_VERSION);
 145
 146 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 147 module_param(tg3_debug, int, 0);
 148 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 149
 150 static struct pci_device_id tg3_pci_tbl[] = {
 151         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 152           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 153         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 154           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 155         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 156           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 157         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 158           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 159         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 160           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 161         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 162           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 163         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 164           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 165         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 166           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 167         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 168           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 169         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 170           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 171         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 172           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 173         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 174           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 175         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 176           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 177         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 178           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 179         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 180           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 181         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 182           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 183         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 184           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 185         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 186           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 187         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 188           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 189         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 190           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 191         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 192           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 193         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 194           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 195         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 196           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 197         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 198           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 199         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 200           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 201         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 202           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 203         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 204           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 205         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 206           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 207         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 208           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 209         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 210           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 211         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 212           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 213         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 214           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 215         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 216           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 217         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 219         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 221         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 223         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 224           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 225         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 226           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 227         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 228           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 229         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 230           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 231         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 232           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 233         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 234           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 235         { 0, }
 236 };
 237
 238 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 239
 240 static struct {
 241         const char string[ETH_GSTRING_LEN];
 242 } ethtool_stats_keys[TG3_NUM_STATS] = {
 243         { "rx_octets" },
 244         { "rx_fragments" },
 245         { "rx_ucast_packets" },
 246         { "rx_mcast_packets" },
 247         { "rx_bcast_packets" },
 248         { "rx_fcs_errors" },
 249         { "rx_align_errors" },
 250         { "rx_xon_pause_rcvd" },
 251         { "rx_xoff_pause_rcvd" },
 252         { "rx_mac_ctrl_rcvd" },
 253         { "rx_xoff_entered" },
 254         { "rx_frame_too_long_errors" },
 255         { "rx_jabbers" },
 256         { "rx_undersize_packets" },
 257         { "rx_in_length_errors" },
 258         { "rx_out_length_errors" },
 259         { "rx_64_or_less_octet_packets" },
 260         { "rx_65_to_127_octet_packets" },
 261         { "rx_128_to_255_octet_packets" },
 262         { "rx_256_to_511_octet_packets" },
 263         { "rx_512_to_1023_octet_packets" },
 264         { "rx_1024_to_1522_octet_packets" },
 265         { "rx_1523_to_2047_octet_packets" },
 266         { "rx_2048_to_4095_octet_packets" },
 267         { "rx_4096_to_8191_octet_packets" },
 268         { "rx_8192_to_9022_octet_packets" },
 269
 270         { "tx_octets" },
 271         { "tx_collisions" },
 272
 273         { "tx_xon_sent" },
 274         { "tx_xoff_sent" },
 275         { "tx_flow_control" },
 276         { "tx_mac_errors" },
 277         { "tx_single_collisions" },
 278         { "tx_mult_collisions" },
 279         { "tx_deferred" },
 280         { "tx_excessive_collisions" },
 281         { "tx_late_collisions" },
 282         { "tx_collide_2times" },
 283         { "tx_collide_3times" },
 284         { "tx_collide_4times" },
 285         { "tx_collide_5times" },
 286         { "tx_collide_6times" },
 287         { "tx_collide_7times" },
 288         { "tx_collide_8times" },
 289         { "tx_collide_9times" },
 290         { "tx_collide_10times" },
 291         { "tx_collide_11times" },
 292         { "tx_collide_12times" },
 293         { "tx_collide_13times" },
 294         { "tx_collide_14times" },
 295         { "tx_collide_15times" },
 296         { "tx_ucast_packets" },
 297         { "tx_mcast_packets" },
 298         { "tx_bcast_packets" },
 299         { "tx_carrier_sense_errors" },
 300         { "tx_discards" },
 301         { "tx_errors" },
 302
 303         { "dma_writeq_full" },
 304         { "dma_write_prioq_full" },
 305         { "rxbds_empty" },
 306         { "rx_discards" },
 307         { "rx_errors" },
 308         { "rx_threshold_hit" },
 309
 310         { "dma_readq_full" },
 311         { "dma_read_prioq_full" },
 312         { "tx_comp_queue_full" },
 313
 314         { "ring_set_send_prod_index" },
 315         { "ring_status_update" },
 316         { "nic_irqs" },
 317         { "nic_avoided_irqs" },
 318         { "nic_tx_threshold_hit" }
 319 };
 320
 321 static struct {
 322         const char string[ETH_GSTRING_LEN];
 323 } ethtool_test_keys[TG3_NUM_TEST] = {
 324         { "nvram test     (online) " },
 325         { "link test      (online) " },
 326         { "register test  (offline)" },
 327         { "memory test    (offline)" },
 328         { "loopback test  (offline)" },
 329         { "interrupt test (offline)" },
 330 };
 331
 332 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 333 {
 334         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 335                 unsigned long flags;
 336
 337                 spin_lock_irqsave(&tp->indirect_lock, flags);
 338                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 339                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 340                 spin_unlock_irqrestore(&tp->indirect_lock, flags);
 341         } else {
 342                 writel(val, tp->regs + off);
 343                 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
 344                         readl(tp->regs + off);
 345         }
 346 }
 347
 348 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 349 {
 350         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
 351                 unsigned long flags;
 352
 353                 spin_lock_irqsave(&tp->indirect_lock, flags);
 354                 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 355                 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 356                 spin_unlock_irqrestore(&tp->indirect_lock, flags);
 357         } else {
 358                 void __iomem *dest = tp->regs + off;
 359                 writel(val, dest);
 360                 readl(dest);    /* always flush PCI write */
 361         }
 362 }
 363
 364 static inline void _tw32_rx_mbox(struct tg3 *tp, u32 off, u32 val)
 365 {
 366         void __iomem *mbox = tp->regs + off;
 367         writel(val, mbox);
 368         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 369                 readl(mbox);
 370 }
 371
 372 static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         void __iomem *mbox = tp->regs + off;
 375         writel(val, mbox);
 376         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 377                 writel(val, mbox);
 378         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 379                 readl(mbox);
 380 }
 381
 382 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tp->regs + (reg))
 383 #define tw32_rx_mbox(reg, val)  _tw32_rx_mbox(tp, reg, val)
 384 #define tw32_tx_mbox(reg, val)  _tw32_tx_mbox(tp, reg, val)
 385
 386 #define tw32(reg,val)           tg3_write_indirect_reg32(tp,(reg),(val))
 387 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 388 #define tw16(reg,val)           writew(((val) & 0xffff), tp->regs + (reg))
 389 #define tw8(reg,val)            writeb(((val) & 0xff), tp->regs + (reg))
 390 #define tr32(reg)               readl(tp->regs + (reg))
 391 #define tr16(reg)               readw(tp->regs + (reg))
 392 #define tr8(reg)                readb(tp->regs + (reg))
 393
 394 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 395 {
 396         unsigned long flags;
 397
 398         spin_lock_irqsave(&tp->indirect_lock, flags);
 399         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 400         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 401
 402         /* Always leave this as zero. */
 403         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 404         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 405 }
 406
 407 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 408 {
 409         unsigned long flags;
 410
 411         spin_lock_irqsave(&tp->indirect_lock, flags);
 412         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 413         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 414
 415         /* Always leave this as zero. */
 416         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 417         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 418 }
 419
 420 static void tg3_disable_ints(struct tg3 *tp)
 421 {
 422         tw32(TG3PCI_MISC_HOST_CTRL,
 423              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 424         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 425         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 426 }
 427
 428 static inline void tg3_cond_int(struct tg3 *tp)
 429 {
 430         if (tp->hw_status->status & SD_STATUS_UPDATED)
 431                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 432 }
 433
 434 static void tg3_enable_ints(struct tg3 *tp)
 435 {
 436         tw32(TG3PCI_MISC_HOST_CTRL,
 437              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 438         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 439                      (tp->last_tag << 24));
 440         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
 441
 442         tg3_cond_int(tp);
 443 }
 444
 445 static inline unsigned int tg3_has_work(struct tg3 *tp)
 446 {
 447         struct tg3_hw_status *sblk = tp->hw_status;
 448         unsigned int work_exists = 0;
 449
 450         /* check for phy events */
 451         if (!(tp->tg3_flags &
 452               (TG3_FLAG_USE_LINKCHG_REG |
 453                TG3_FLAG_POLL_SERDES))) {
 454                 if (sblk->status & SD_STATUS_LINK_CHG)
 455                         work_exists = 1;
 456         }
 457         /* check for RX/TX work to do */
 458         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 459             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 460                 work_exists = 1;
 461
 462         return work_exists;
 463 }
 464
 465 /* tg3_restart_ints
 466  *  similar to tg3_enable_ints, but it accurately determines whether there
 467  *  is new work pending and can return without flushing the PIO write
 468  *  which reenables interrupts
 469  */
 470 static void tg3_restart_ints(struct tg3 *tp)
 471 {
 472         tw32(TG3PCI_MISC_HOST_CTRL,
 473                 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 474         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 475                      tp->last_tag << 24);
 476         mmiowb();
 477
 478         /* When doing tagged status, this work check is unnecessary.
 479          * The last_tag we write above tells the chip which piece of
 480          * work we've completed.
 481          */
 482         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 483             tg3_has_work(tp))
 484                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 485                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 486 }
 487
 488 static inline void tg3_netif_stop(struct tg3 *tp)
 489 {
 490         netif_poll_disable(tp->dev);
 491         netif_tx_disable(tp->dev);
 492 }
 493
 494 static inline void tg3_netif_start(struct tg3 *tp)
 495 {
 496         netif_wake_queue(tp->dev);
 497         /* NOTE: unconditional netif_wake_queue is only appropriate
 498          * so long as all callers are assured to have free tx slots
 499          * (such as after tg3_init_hw)
 500          */
 501         netif_poll_enable(tp->dev);
 502         tg3_cond_int(tp);
 503 }
 504
 505 static void tg3_switch_clocks(struct tg3 *tp)
 506 {
 507         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 508         u32 orig_clock_ctrl;
 509
 510         orig_clock_ctrl = clock_ctrl;
 511         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 512                        CLOCK_CTRL_CLKRUN_OENABLE |
 513                        0x1f);
 514         tp->pci_clock_ctrl = clock_ctrl;
 515
 516         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 517                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 518                         tw32_f(TG3PCI_CLOCK_CTRL,
 519                                clock_ctrl | CLOCK_CTRL_625_CORE);
 520                         udelay(40);
 521                 }
 522         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 523                 tw32_f(TG3PCI_CLOCK_CTRL,
 524                      clock_ctrl |
 525                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 526                 udelay(40);
 527                 tw32_f(TG3PCI_CLOCK_CTRL,
 528                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 529                 udelay(40);
 530         }
 531         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 532         udelay(40);
 533 }
 534
 535 #define PHY_BUSY_LOOPS  5000
 536
 537 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 538 {
 539         u32 frame_val;
 540         unsigned int loops;
 541         int ret;
 542
 543         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 544                 tw32_f(MAC_MI_MODE,
 545                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 546                 udelay(80);
 547         }
 548
 549         *val = 0x0;
 550
 551         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 552                       MI_COM_PHY_ADDR_MASK);
 553         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 554                       MI_COM_REG_ADDR_MASK);
 555         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 556
 557         tw32_f(MAC_MI_COM, frame_val);
 558
 559         loops = PHY_BUSY_LOOPS;
 560         while (loops != 0) {
 561                 udelay(10);
 562                 frame_val = tr32(MAC_MI_COM);
 563
 564                 if ((frame_val & MI_COM_BUSY) == 0) {
 565                         udelay(5);
 566                         frame_val = tr32(MAC_MI_COM);
 567                         break;
 568                 }
 569                 loops -= 1;
 570         }
 571
 572         ret = -EBUSY;
 573         if (loops != 0) {
 574                 *val = frame_val & MI_COM_DATA_MASK;
 575                 ret = 0;
 576         }
 577
 578         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 579                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 580                 udelay(80);
 581         }
 582
 583         return ret;
 584 }
 585
 586 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 587 {
 588         u32 frame_val;
 589         unsigned int loops;
 590         int ret;
 591
 592         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 593                 tw32_f(MAC_MI_MODE,
 594                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 595                 udelay(80);
 596         }
 597
 598         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 599                       MI_COM_PHY_ADDR_MASK);
 600         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 601                       MI_COM_REG_ADDR_MASK);
 602         frame_val |= (val & MI_COM_DATA_MASK);
 603         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 604
 605         tw32_f(MAC_MI_COM, frame_val);
 606
 607         loops = PHY_BUSY_LOOPS;
 608         while (loops != 0) {
 609                 udelay(10);
 610                 frame_val = tr32(MAC_MI_COM);
 611                 if ((frame_val & MI_COM_BUSY) == 0) {
 612                         udelay(5);
 613                         frame_val = tr32(MAC_MI_COM);
 614                         break;
 615                 }
 616                 loops -= 1;
 617         }
 618
 619         ret = -EBUSY;
 620         if (loops != 0)
 621                 ret = 0;
 622
 623         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 624                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 625                 udelay(80);
 626         }
 627
 628         return ret;
 629 }
 630
 631 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 632 {
 633         u32 val;
 634
 635         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 636                 return;
 637
 638         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 639             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 640                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 641                              (val | (1 << 15) | (1 << 4)));
 642 }
 643
 644 static int tg3_bmcr_reset(struct tg3 *tp)
 645 {
 646         u32 phy_control;
 647         int limit, err;
 648
 649         /* OK, reset it, and poll the BMCR_RESET bit until it
 650          * clears or we time out.
 651          */
 652         phy_control = BMCR_RESET;
 653         err = tg3_writephy(tp, MII_BMCR, phy_control);
 654         if (err != 0)
 655                 return -EBUSY;
 656
 657         limit = 5000;
 658         while (limit--) {
 659                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 660                 if (err != 0)
 661                         return -EBUSY;
 662
 663                 if ((phy_control & BMCR_RESET) == 0) {
 664                         udelay(40);
 665                         break;
 666                 }
 667                 udelay(10);
 668         }
 669         if (limit <= 0)
 670                 return -EBUSY;
 671
 672         return 0;
 673 }
 674
 675 static int tg3_wait_macro_done(struct tg3 *tp)
 676 {
 677         int limit = 100;
 678
 679         while (limit--) {
 680                 u32 tmp32;
 681
 682                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 683                         if ((tmp32 & 0x1000) == 0)
 684                                 break;
 685                 }
 686         }
 687         if (limit <= 0)
 688                 return -EBUSY;
 689
 690         return 0;
 691 }
 692
 693 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 694 {
 695         static const u32 test_pat[4][6] = {
 696         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 697         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 698         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 699         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 700         };
 701         int chan;
 702
 703         for (chan = 0; chan < 4; chan++) {
 704                 int i;
 705
 706                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 707                              (chan * 0x2000) | 0x0200);
 708                 tg3_writephy(tp, 0x16, 0x0002);
 709
 710                 for (i = 0; i < 6; i++)
 711                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 712                                      test_pat[chan][i]);
 713
 714                 tg3_writephy(tp, 0x16, 0x0202);
 715                 if (tg3_wait_macro_done(tp)) {
 716                         *resetp = 1;
 717                         return -EBUSY;
 718                 }
 719
 720                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 721                              (chan * 0x2000) | 0x0200);
 722                 tg3_writephy(tp, 0x16, 0x0082);
 723                 if (tg3_wait_macro_done(tp)) {
 724                         *resetp = 1;
 725                         return -EBUSY;
 726                 }
 727
 728                 tg3_writephy(tp, 0x16, 0x0802);
 729                 if (tg3_wait_macro_done(tp)) {
 730                         *resetp = 1;
 731                         return -EBUSY;
 732                 }
 733
 734                 for (i = 0; i < 6; i += 2) {
 735                         u32 low, high;
 736
 737                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 738                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 739                             tg3_wait_macro_done(tp)) {
 740                                 *resetp = 1;
 741                                 return -EBUSY;
 742                         }
 743                         low &= 0x7fff;
 744                         high &= 0x000f;
 745                         if (low != test_pat[chan][i] ||
 746                             high != test_pat[chan][i+1]) {
 747                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 748                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 749                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 750
 751                                 return -EBUSY;
 752                         }
 753                 }
 754         }
 755
 756         return 0;
 757 }
 758
 759 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 760 {
 761         int chan;
 762
 763         for (chan = 0; chan < 4; chan++) {
 764                 int i;
 765
 766                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 767                              (chan * 0x2000) | 0x0200);
 768                 tg3_writephy(tp, 0x16, 0x0002);
 769                 for (i = 0; i < 6; i++)
 770                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 771                 tg3_writephy(tp, 0x16, 0x0202);
 772                 if (tg3_wait_macro_done(tp))
 773                         return -EBUSY;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 780 {
 781         u32 reg32, phy9_orig;
 782         int retries, do_phy_reset, err;
 783
 784         retries = 10;
 785         do_phy_reset = 1;
 786         do {
 787                 if (do_phy_reset) {
 788                         err = tg3_bmcr_reset(tp);
 789                         if (err)
 790                                 return err;
 791                         do_phy_reset = 0;
 792                 }
 793
 794                 /* Disable transmitter and interrupt.  */
 795                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 796                         continue;
 797
 798                 reg32 |= 0x3000;
 799                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 800
 801                 /* Set full-duplex, 1000 mbps.  */
 802                 tg3_writephy(tp, MII_BMCR,
 803                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 804
 805                 /* Set to master mode.  */
 806                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 807                         continue;
 808
 809                 tg3_writephy(tp, MII_TG3_CTRL,
 810                              (MII_TG3_CTRL_AS_MASTER |
 811                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 812
 813                 /* Enable SM_DSP_CLOCK and 6dB.  */
 814                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 815
 816                 /* Block the PHY control access.  */
 817                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 818                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 819
 820                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 821                 if (!err)
 822                         break;
 823         } while (--retries);
 824
 825         err = tg3_phy_reset_chanpat(tp);
 826         if (err)
 827                 return err;
 828
 829         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 830         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 831
 832         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 833         tg3_writephy(tp, 0x16, 0x0000);
 834
 835         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 836             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 837                 /* Set Extended packet length bit for jumbo frames */
 838                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 839         }
 840         else {
 841                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 842         }
 843
 844         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 845
 846         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 847                 reg32 &= ~0x3000;
 848                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 849         } else if (!err)
 850                 err = -EBUSY;
 851
 852         return err;
 853 }
 854
 855 /* This will reset the tigon3 PHY if there is no valid
 856  * link unless the FORCE argument is non-zero.
 857  */
 858 static int tg3_phy_reset(struct tg3 *tp)
 859 {
 860         u32 phy_status;
 861         int err;
 862
 863         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 864         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 865         if (err != 0)
 866                 return -EBUSY;
 867
 868         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 869             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 870             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 871                 err = tg3_phy_reset_5703_4_5(tp);
 872                 if (err)
 873                         return err;
 874                 goto out;
 875         }
 876
 877         err = tg3_bmcr_reset(tp);
 878         if (err)
 879                 return err;
 880
 881 out:
 882         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 883                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 884                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 885                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 886                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 887                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 888                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 889         }
 890         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 891                 tg3_writephy(tp, 0x1c, 0x8d68);
 892                 tg3_writephy(tp, 0x1c, 0x8d68);
 893         }
 894         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 895                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 896                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 897                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 898                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 899                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 900                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 901                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 902                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 903         }
 904         /* Set Extended packet length bit (bit 14) on all chips that */
 905         /* support jumbo frames */
 906         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 907                 /* Cannot do read-modify-write on 5401 */
 908                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 909         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 910                 u32 phy_reg;
 911
 912                 /* Set bit 14 with read-modify-write to preserve other bits */
 913                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
 914                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
 915                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 916         }
 917
 918         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
 919          * jumbo frames transmission.
 920          */
 921         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 922                 u32 phy_reg;
 923
 924                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
 925                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
 926                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
 927         }
 928
 929         tg3_phy_set_wirespeed(tp);
 930         return 0;
 931 }
 932
 933 static void tg3_frob_aux_power(struct tg3 *tp)
 934 {
 935         struct tg3 *tp_peer = tp;
 936
 937         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
 938                 return;
 939
 940         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 941                 tp_peer = pci_get_drvdata(tp->pdev_peer);
 942                 if (!tp_peer)
 943                         BUG();
 944         }
 945
 946
 947         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
 948             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0) {
 949                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
 950                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
 951                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 952                              (GRC_LCLCTRL_GPIO_OE0 |
 953                               GRC_LCLCTRL_GPIO_OE1 |
 954                               GRC_LCLCTRL_GPIO_OE2 |
 955                               GRC_LCLCTRL_GPIO_OUTPUT0 |
 956                               GRC_LCLCTRL_GPIO_OUTPUT1));
 957                         udelay(100);
 958                 } else {
 959                         u32 no_gpio2;
 960                         u32 grc_local_ctrl;
 961
 962                         if (tp_peer != tp &&
 963                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
 964                                 return;
 965
 966                         /* On 5753 and variants, GPIO2 cannot be used. */
 967                         no_gpio2 = tp->nic_sram_data_cfg &
 968                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
 969
 970                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 971                                          GRC_LCLCTRL_GPIO_OE1 |
 972                                          GRC_LCLCTRL_GPIO_OE2 |
 973                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
 974                                          GRC_LCLCTRL_GPIO_OUTPUT2;
 975                         if (no_gpio2) {
 976                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
 977                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
 978                         }
 979                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 980                                                 grc_local_ctrl);
 981                         udelay(100);
 982
 983                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
 984
 985                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 986                                                 grc_local_ctrl);
 987                         udelay(100);
 988
 989                         if (!no_gpio2) {
 990                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
 991                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 992                                        grc_local_ctrl);
 993                                 udelay(100);
 994                         }
 995                 }
 996         } else {
 997                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
 998                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
 999                         if (tp_peer != tp &&
1000                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1001                                 return;
1002
1003                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1004                              (GRC_LCLCTRL_GPIO_OE1 |
1005                               GRC_LCLCTRL_GPIO_OUTPUT1));
1006                         udelay(100);
1007
1008                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1009                              (GRC_LCLCTRL_GPIO_OE1));
1010                         udelay(100);
1011
1012                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1013                              (GRC_LCLCTRL_GPIO_OE1 |
1014                               GRC_LCLCTRL_GPIO_OUTPUT1));
1015                         udelay(100);
1016                 }
1017         }
1018 }
1019
1020 static int tg3_setup_phy(struct tg3 *, int);
1021
1022 #define RESET_KIND_SHUTDOWN     0
1023 #define RESET_KIND_INIT         1
1024 #define RESET_KIND_SUSPEND      2
1025
1026 static void tg3_write_sig_post_reset(struct tg3 *, int);
1027 static int tg3_halt_cpu(struct tg3 *, u32);
1028
1029 static int tg3_set_power_state(struct tg3 *tp, int state)
1030 {
1031         u32 misc_host_ctrl;
1032         u16 power_control, power_caps;
1033         int pm = tp->pm_cap;
1034
1035         /* Make sure register accesses (indirect or otherwise)
1036          * will function correctly.
1037          */
1038         pci_write_config_dword(tp->pdev,
1039                                TG3PCI_MISC_HOST_CTRL,
1040                                tp->misc_host_ctrl);
1041
1042         pci_read_config_word(tp->pdev,
1043                              pm + PCI_PM_CTRL,
1044                              &power_control);
1045         power_control |= PCI_PM_CTRL_PME_STATUS;
1046         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1047         switch (state) {
1048         case 0:
1049                 power_control |= 0;
1050                 pci_write_config_word(tp->pdev,
1051                                       pm + PCI_PM_CTRL,
1052                                       power_control);
1053                 udelay(100);    /* Delay after power state change */
1054
1055                 /* Switch out of Vaux if it is not a LOM */
1056                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1057                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1058                         udelay(100);
1059                 }
1060
1061                 return 0;
1062
1063         case 1:
1064                 power_control |= 1;
1065                 break;
1066
1067         case 2:
1068                 power_control |= 2;
1069                 break;
1070
1071         case 3:
1072                 power_control |= 3;
1073                 break;
1074
1075         default:
1076                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1077                        "requested.\n",
1078                        tp->dev->name, state);
1079                 return -EINVAL;
1080         };
1081
1082         power_control |= PCI_PM_CTRL_PME_ENABLE;
1083
1084         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1085         tw32(TG3PCI_MISC_HOST_CTRL,
1086              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1087
1088         if (tp->link_config.phy_is_low_power == 0) {
1089                 tp->link_config.phy_is_low_power = 1;
1090                 tp->link_config.orig_speed = tp->link_config.speed;
1091                 tp->link_config.orig_duplex = tp->link_config.duplex;
1092                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1093         }
1094
1095         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1096                 tp->link_config.speed = SPEED_10;
1097                 tp->link_config.duplex = DUPLEX_HALF;
1098                 tp->link_config.autoneg = AUTONEG_ENABLE;
1099                 tg3_setup_phy(tp, 0);
1100         }
1101
1102         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1103
1104         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1105                 u32 mac_mode;
1106
1107                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1108                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1109                         udelay(40);
1110
1111                         mac_mode = MAC_MODE_PORT_MODE_MII;
1112
1113                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1114                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1115                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1116                 } else {
1117                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1118                 }
1119
1120                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1121                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1122
1123                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1124                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1125                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1126
1127                 tw32_f(MAC_MODE, mac_mode);
1128                 udelay(100);
1129
1130                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1131                 udelay(10);
1132         }
1133
1134         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1135             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1136              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1137                 u32 base_val;
1138
1139                 base_val = tp->pci_clock_ctrl;
1140                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1141                              CLOCK_CTRL_TXCLK_DISABLE);
1142
1143                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1144                      CLOCK_CTRL_ALTCLK |
1145                      CLOCK_CTRL_PWRDOWN_PLL133);
1146                 udelay(40);
1147         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1148                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1149                 u32 newbits1, newbits2;
1150
1151                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1152                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1153                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1154                                     CLOCK_CTRL_TXCLK_DISABLE |
1155                                     CLOCK_CTRL_ALTCLK);
1156                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1157                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1158                         newbits1 = CLOCK_CTRL_625_CORE;
1159                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1160                 } else {
1161                         newbits1 = CLOCK_CTRL_ALTCLK;
1162                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1163                 }
1164
1165                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1166                 udelay(40);
1167
1168                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1169                 udelay(40);
1170
1171                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1172                         u32 newbits3;
1173
1174                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1175                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1176                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1177                                             CLOCK_CTRL_TXCLK_DISABLE |
1178                                             CLOCK_CTRL_44MHZ_CORE);
1179                         } else {
1180                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1181                         }
1182
1183                         tw32_f(TG3PCI_CLOCK_CTRL,
1184                                          tp->pci_clock_ctrl | newbits3);
1185                         udelay(40);
1186                 }
1187         }
1188
1189         tg3_frob_aux_power(tp);
1190
1191         /* Workaround for unstable PLL clock */
1192         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1193             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1194                 u32 val = tr32(0x7d00);
1195
1196                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1197                 tw32(0x7d00, val);
1198                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1199                         tg3_halt_cpu(tp, RX_CPU_BASE);
1200         }
1201
1202         /* Finally, set the new power state. */
1203         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1204         udelay(100);    /* Delay after power state change */
1205
1206         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1207
1208         return 0;
1209 }
1210
1211 static void tg3_link_report(struct tg3 *tp)
1212 {
1213         if (!netif_carrier_ok(tp->dev)) {
1214                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1215         } else {
1216                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1217                        tp->dev->name,
1218                        (tp->link_config.active_speed == SPEED_1000 ?
1219                         1000 :
1220                         (tp->link_config.active_speed == SPEED_100 ?
1221                          100 : 10)),
1222                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1223                         "full" : "half"));
1224
1225                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1226                        "%s for RX.\n",
1227                        tp->dev->name,
1228                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1229                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1230         }
1231 }
1232
1233 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1234 {
1235         u32 new_tg3_flags = 0;
1236         u32 old_rx_mode = tp->rx_mode;
1237         u32 old_tx_mode = tp->tx_mode;
1238
1239         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1240                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1241                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1242                                 if (remote_adv & LPA_PAUSE_CAP)
1243                                         new_tg3_flags |=
1244                                                 (TG3_FLAG_RX_PAUSE |
1245                                                 TG3_FLAG_TX_PAUSE);
1246                                 else if (remote_adv & LPA_PAUSE_ASYM)
1247                                         new_tg3_flags |=
1248                                                 (TG3_FLAG_RX_PAUSE);
1249                         } else {
1250                                 if (remote_adv & LPA_PAUSE_CAP)
1251                                         new_tg3_flags |=
1252                                                 (TG3_FLAG_RX_PAUSE |
1253                                                 TG3_FLAG_TX_PAUSE);
1254                         }
1255                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1256                         if ((remote_adv & LPA_PAUSE_CAP) &&
1257                         (remote_adv & LPA_PAUSE_ASYM))
1258                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1259                 }
1260
1261                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1262                 tp->tg3_flags |= new_tg3_flags;
1263         } else {
1264                 new_tg3_flags = tp->tg3_flags;
1265         }
1266
1267         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1268                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1269         else
1270                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1271
1272         if (old_rx_mode != tp->rx_mode) {
1273                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1274         }
1275
1276         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1277                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1278         else
1279                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1280
1281         if (old_tx_mode != tp->tx_mode) {
1282                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1283         }
1284 }
1285
1286 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1287 {
1288         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1289         case MII_TG3_AUX_STAT_10HALF:
1290                 *speed = SPEED_10;
1291                 *duplex = DUPLEX_HALF;
1292                 break;
1293
1294         case MII_TG3_AUX_STAT_10FULL:
1295                 *speed = SPEED_10;
1296                 *duplex = DUPLEX_FULL;
1297                 break;
1298
1299         case MII_TG3_AUX_STAT_100HALF:
1300                 *speed = SPEED_100;
1301                 *duplex = DUPLEX_HALF;
1302                 break;
1303
1304         case MII_TG3_AUX_STAT_100FULL:
1305                 *speed = SPEED_100;
1306                 *duplex = DUPLEX_FULL;
1307                 break;
1308
1309         case MII_TG3_AUX_STAT_1000HALF:
1310                 *speed = SPEED_1000;
1311                 *duplex = DUPLEX_HALF;
1312                 break;
1313
1314         case MII_TG3_AUX_STAT_1000FULL:
1315                 *speed = SPEED_1000;
1316                 *duplex = DUPLEX_FULL;
1317                 break;
1318
1319         default:
1320                 *speed = SPEED_INVALID;
1321                 *duplex = DUPLEX_INVALID;
1322                 break;
1323         };
1324 }
1325
1326 static void tg3_phy_copper_begin(struct tg3 *tp)
1327 {
1328         u32 new_adv;
1329         int i;
1330
1331         if (tp->link_config.phy_is_low_power) {
1332                 /* Entering low power mode.  Disable gigabit and
1333                  * 100baseT advertisements.
1334                  */
1335                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1336
1337                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1338                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1339                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1340                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1341
1342                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1343         } else if (tp->link_config.speed == SPEED_INVALID) {
1344                 tp->link_config.advertising =
1345                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1346                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1347                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1348                          ADVERTISED_Autoneg | ADVERTISED_MII);
1349
1350                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1351                         tp->link_config.advertising &=
1352                                 ~(ADVERTISED_1000baseT_Half |
1353                                   ADVERTISED_1000baseT_Full);
1354
1355                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1356                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1357                         new_adv |= ADVERTISE_10HALF;
1358                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1359                         new_adv |= ADVERTISE_10FULL;
1360                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1361                         new_adv |= ADVERTISE_100HALF;
1362                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1363                         new_adv |= ADVERTISE_100FULL;
1364                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1365
1366                 if (tp->link_config.advertising &
1367                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1368                         new_adv = 0;
1369                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1370                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1371                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1372                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1373                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1374                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1375                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1376                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1377                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1378                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1379                 } else {
1380                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1381                 }
1382         } else {
1383                 /* Asking for a specific link mode. */
1384                 if (tp->link_config.speed == SPEED_1000) {
1385                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1386                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1387
1388                         if (tp->link_config.duplex == DUPLEX_FULL)
1389                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1390                         else
1391                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1392                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1393                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1394                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1395                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1396                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1397                 } else {
1398                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1399
1400                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1401                         if (tp->link_config.speed == SPEED_100) {
1402                                 if (tp->link_config.duplex == DUPLEX_FULL)
1403                                         new_adv |= ADVERTISE_100FULL;
1404                                 else
1405                                         new_adv |= ADVERTISE_100HALF;
1406                         } else {
1407                                 if (tp->link_config.duplex == DUPLEX_FULL)
1408                                         new_adv |= ADVERTISE_10FULL;
1409                                 else
1410                                         new_adv |= ADVERTISE_10HALF;
1411                         }
1412                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1413                 }
1414         }
1415
1416         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1417             tp->link_config.speed != SPEED_INVALID) {
1418                 u32 bmcr, orig_bmcr;
1419
1420                 tp->link_config.active_speed = tp->link_config.speed;
1421                 tp->link_config.active_duplex = tp->link_config.duplex;
1422
1423                 bmcr = 0;
1424                 switch (tp->link_config.speed) {
1425                 default:
1426                 case SPEED_10:
1427                         break;
1428
1429                 case SPEED_100:
1430                         bmcr |= BMCR_SPEED100;
1431                         break;
1432
1433                 case SPEED_1000:
1434                         bmcr |= TG3_BMCR_SPEED1000;
1435                         break;
1436                 };
1437
1438                 if (tp->link_config.duplex == DUPLEX_FULL)
1439                         bmcr |= BMCR_FULLDPLX;
1440
1441                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1442                     (bmcr != orig_bmcr)) {
1443                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1444                         for (i = 0; i < 1500; i++) {
1445                                 u32 tmp;
1446
1447                                 udelay(10);
1448                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1449                                     tg3_readphy(tp, MII_BMSR, &tmp))
1450                                         continue;
1451                                 if (!(tmp & BMSR_LSTATUS)) {
1452                                         udelay(40);
1453                                         break;
1454                                 }
1455                         }
1456                         tg3_writephy(tp, MII_BMCR, bmcr);
1457                         udelay(40);
1458                 }
1459         } else {
1460                 tg3_writephy(tp, MII_BMCR,
1461                              BMCR_ANENABLE | BMCR_ANRESTART);
1462         }
1463 }
1464
1465 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1466 {
1467         int err;
1468
1469         /* Turn off tap power management. */
1470         /* Set Extended packet length bit */
1471         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1472
1473         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1474         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1475
1476         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1477         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1478
1479         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1480         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1481
1482         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1483         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1484
1485         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1486         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1487
1488         udelay(40);
1489
1490         return err;
1491 }
1492
1493 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1494 {
1495         u32 adv_reg, all_mask;
1496
1497         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1498                 return 0;
1499
1500         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1501                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1502         if ((adv_reg & all_mask) != all_mask)
1503                 return 0;
1504         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1505                 u32 tg3_ctrl;
1506
1507                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1508                         return 0;
1509
1510                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1511                             MII_TG3_CTRL_ADV_1000_FULL);
1512                 if ((tg3_ctrl & all_mask) != all_mask)
1513                         return 0;
1514         }
1515         return 1;
1516 }
1517
1518 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1519 {
1520         int current_link_up;
1521         u32 bmsr, dummy;
1522         u16 current_speed;
1523         u8 current_duplex;
1524         int i, err;
1525
1526         tw32(MAC_EVENT, 0);
1527
1528         tw32_f(MAC_STATUS,
1529              (MAC_STATUS_SYNC_CHANGED |
1530               MAC_STATUS_CFG_CHANGED |
1531               MAC_STATUS_MI_COMPLETION |
1532               MAC_STATUS_LNKSTATE_CHANGED));
1533         udelay(40);
1534
1535         tp->mi_mode = MAC_MI_MODE_BASE;
1536         tw32_f(MAC_MI_MODE, tp->mi_mode);
1537         udelay(80);
1538
1539         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1540
1541         /* Some third-party PHYs need to be reset on link going
1542          * down.
1543          */
1544         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1545              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1546              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1547             netif_carrier_ok(tp->dev)) {
1548                 tg3_readphy(tp, MII_BMSR, &bmsr);
1549                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1550                     !(bmsr & BMSR_LSTATUS))
1551                         force_reset = 1;
1552         }
1553         if (force_reset)
1554                 tg3_phy_reset(tp);
1555
1556         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1557                 tg3_readphy(tp, MII_BMSR, &bmsr);
1558                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1559                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1560                         bmsr = 0;
1561
1562                 if (!(bmsr & BMSR_LSTATUS)) {
1563                         err = tg3_init_5401phy_dsp(tp);
1564                         if (err)
1565                                 return err;
1566
1567                         tg3_readphy(tp, MII_BMSR, &bmsr);
1568                         for (i = 0; i < 1000; i++) {
1569                                 udelay(10);
1570                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1571                                     (bmsr & BMSR_LSTATUS)) {
1572                                         udelay(40);
1573                                         break;
1574                                 }
1575                         }
1576
1577                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1578                             !(bmsr & BMSR_LSTATUS) &&
1579                             tp->link_config.active_speed == SPEED_1000) {
1580                                 err = tg3_phy_reset(tp);
1581                                 if (!err)
1582                                         err = tg3_init_5401phy_dsp(tp);
1583                                 if (err)
1584                                         return err;
1585                         }
1586                 }
1587         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1588                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1589                 /* 5701 {A0,B0} CRC bug workaround */
1590                 tg3_writephy(tp, 0x15, 0x0a75);
1591                 tg3_writephy(tp, 0x1c, 0x8c68);
1592                 tg3_writephy(tp, 0x1c, 0x8d68);
1593                 tg3_writephy(tp, 0x1c, 0x8c68);
1594         }
1595
1596         /* Clear pending interrupts... */
1597         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1598         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1599
1600         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1601                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1602         else
1603                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1604
1605         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1606             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1607                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1608                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1609                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1610                 else
1611                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1612         }
1613
1614         current_link_up = 0;
1615         current_speed = SPEED_INVALID;
1616         current_duplex = DUPLEX_INVALID;
1617
1618         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1619                 u32 val;
1620
1621                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1622                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1623                 if (!(val & (1 << 10))) {
1624                         val |= (1 << 10);
1625                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1626                         goto relink;
1627                 }
1628         }
1629
1630         bmsr = 0;
1631         for (i = 0; i < 100; i++) {
1632                 tg3_readphy(tp, MII_BMSR, &bmsr);
1633                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1634                     (bmsr & BMSR_LSTATUS))
1635                         break;
1636                 udelay(40);
1637         }
1638
1639         if (bmsr & BMSR_LSTATUS) {
1640                 u32 aux_stat, bmcr;
1641
1642                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1643                 for (i = 0; i < 2000; i++) {
1644                         udelay(10);
1645                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1646                             aux_stat)
1647                                 break;
1648                 }
1649
1650                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1651                                              &current_speed,
1652                                              &current_duplex);
1653
1654                 bmcr = 0;
1655                 for (i = 0; i < 200; i++) {
1656                         tg3_readphy(tp, MII_BMCR, &bmcr);
1657                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1658                                 continue;
1659                         if (bmcr && bmcr != 0x7fff)
1660                                 break;
1661                         udelay(10);
1662                 }
1663
1664                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1665                         if (bmcr & BMCR_ANENABLE) {
1666                                 current_link_up = 1;
1667
1668                                 /* Force autoneg restart if we are exiting
1669                                  * low power mode.
1670                                  */
1671                                 if (!tg3_copper_is_advertising_all(tp))
1672                                         current_link_up = 0;
1673                         } else {
1674                                 current_link_up = 0;
1675                         }
1676                 } else {
1677                         if (!(bmcr & BMCR_ANENABLE) &&
1678                             tp->link_config.speed == current_speed &&
1679                             tp->link_config.duplex == current_duplex) {
1680                                 current_link_up = 1;
1681                         } else {
1682                                 current_link_up = 0;
1683                         }
1684                 }
1685
1686                 tp->link_config.active_speed = current_speed;
1687                 tp->link_config.active_duplex = current_duplex;
1688         }
1689
1690         if (current_link_up == 1 &&
1691             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1692             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1693                 u32 local_adv, remote_adv;
1694
1695                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1696                         local_adv = 0;
1697                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1698
1699                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1700                         remote_adv = 0;
1701
1702                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1703
1704                 /* If we are not advertising full pause capability,
1705                  * something is wrong.  Bring the link down and reconfigure.
1706                  */
1707                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1708                         current_link_up = 0;
1709                 } else {
1710                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1711                 }
1712         }
1713 relink:
1714         if (current_link_up == 0) {
1715                 u32 tmp;
1716
1717                 tg3_phy_copper_begin(tp);
1718
1719                 tg3_readphy(tp, MII_BMSR, &tmp);
1720                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1721                     (tmp & BMSR_LSTATUS))
1722                         current_link_up = 1;
1723         }
1724
1725         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1726         if (current_link_up == 1) {
1727                 if (tp->link_config.active_speed == SPEED_100 ||
1728                     tp->link_config.active_speed == SPEED_10)
1729                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1730                 else
1731                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1732         } else
1733                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1734
1735         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1736         if (tp->link_config.active_duplex == DUPLEX_HALF)
1737                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1738
1739         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1741                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1742                     (current_link_up == 1 &&
1743                      tp->link_config.active_speed == SPEED_10))
1744                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1745         } else {
1746                 if (current_link_up == 1)
1747                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1748         }
1749
1750         /* ??? Without this setting Netgear GA302T PHY does not
1751          * ??? send/receive packets...
1752          */
1753         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1754             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1755                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1756                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1757                 udelay(80);
1758         }
1759
1760         tw32_f(MAC_MODE, tp->mac_mode);
1761         udelay(40);
1762
1763         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1764                 /* Polled via timer. */
1765                 tw32_f(MAC_EVENT, 0);
1766         } else {
1767                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1768         }
1769         udelay(40);
1770
1771         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1772             current_link_up == 1 &&
1773             tp->link_config.active_speed == SPEED_1000 &&
1774             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1775              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1776                 udelay(120);
1777                 tw32_f(MAC_STATUS,
1778                      (MAC_STATUS_SYNC_CHANGED |
1779                       MAC_STATUS_CFG_CHANGED));
1780                 udelay(40);
1781                 tg3_write_mem(tp,
1782                               NIC_SRAM_FIRMWARE_MBOX,
1783                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1784         }
1785
1786         if (current_link_up != netif_carrier_ok(tp->dev)) {
1787                 if (current_link_up)
1788                         netif_carrier_on(tp->dev);
1789                 else
1790                         netif_carrier_off(tp->dev);
1791                 tg3_link_report(tp);
1792         }
1793
1794         return 0;
1795 }
1796
1797 struct tg3_fiber_aneginfo {
1798         int state;
1799 #define ANEG_STATE_UNKNOWN              0
1800 #define ANEG_STATE_AN_ENABLE            1
1801 #define ANEG_STATE_RESTART_INIT         2
1802 #define ANEG_STATE_RESTART              3
1803 #define ANEG_STATE_DISABLE_LINK_OK      4
1804 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1805 #define ANEG_STATE_ABILITY_DETECT       6
1806 #define ANEG_STATE_ACK_DETECT_INIT      7
1807 #define ANEG_STATE_ACK_DETECT           8
1808 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1809 #define ANEG_STATE_COMPLETE_ACK         10
1810 #define ANEG_STATE_IDLE_DETECT_INIT     11
1811 #define ANEG_STATE_IDLE_DETECT          12
1812 #define ANEG_STATE_LINK_OK              13
1813 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1814 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1815
1816         u32 flags;
1817 #define MR_AN_ENABLE            0x00000001
1818 #define MR_RESTART_AN           0x00000002
1819 #define MR_AN_COMPLETE          0x00000004
1820 #define MR_PAGE_RX              0x00000008
1821 #define MR_NP_LOADED            0x00000010
1822 #define MR_TOGGLE_TX            0x00000020
1823 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1824 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1825 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1826 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1827 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1828 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1829 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1830 #define MR_TOGGLE_RX            0x00002000
1831 #define MR_NP_RX                0x00004000
1832
1833 #define MR_LINK_OK              0x80000000
1834
1835         unsigned long link_time, cur_time;
1836
1837         u32 ability_match_cfg;
1838         int ability_match_count;
1839
1840         char ability_match, idle_match, ack_match;
1841
1842         u32 txconfig, rxconfig;
1843 #define ANEG_CFG_NP             0x00000080
1844 #define ANEG_CFG_ACK            0x00000040
1845 #define ANEG_CFG_RF2            0x00000020
1846 #define ANEG_CFG_RF1            0x00000010
1847 #define ANEG_CFG_PS2            0x00000001
1848 #define ANEG_CFG_PS1            0x00008000
1849 #define ANEG_CFG_HD             0x00004000
1850 #define ANEG_CFG_FD             0x00002000
1851 #define ANEG_CFG_INVAL          0x00001f06
1852
1853 };
1854 #define ANEG_OK         0
1855 #define ANEG_DONE       1
1856 #define ANEG_TIMER_ENAB 2
1857 #define ANEG_FAILED     -1
1858
1859 #define ANEG_STATE_SETTLE_TIME  10000
1860
1861 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1862                                    struct tg3_fiber_aneginfo *ap)
1863 {
1864         unsigned long delta;
1865         u32 rx_cfg_reg;
1866         int ret;
1867
1868         if (ap->state == ANEG_STATE_UNKNOWN) {
1869                 ap->rxconfig = 0;
1870                 ap->link_time = 0;
1871                 ap->cur_time = 0;
1872                 ap->ability_match_cfg = 0;
1873                 ap->ability_match_count = 0;
1874                 ap->ability_match = 0;
1875                 ap->idle_match = 0;
1876                 ap->ack_match = 0;
1877         }
1878         ap->cur_time++;
1879
1880         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1881                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1882
1883                 if (rx_cfg_reg != ap->ability_match_cfg) {
1884                         ap->ability_match_cfg = rx_cfg_reg;
1885                         ap->ability_match = 0;
1886                         ap->ability_match_count = 0;
1887                 } else {
1888                         if (++ap->ability_match_count > 1) {
1889                                 ap->ability_match = 1;
1890                                 ap->ability_match_cfg = rx_cfg_reg;
1891                         }
1892                 }
1893                 if (rx_cfg_reg & ANEG_CFG_ACK)
1894                         ap->ack_match = 1;
1895                 else
1896                         ap->ack_match = 0;
1897
1898                 ap->idle_match = 0;
1899         } else {
1900                 ap->idle_match = 1;
1901                 ap->ability_match_cfg = 0;
1902                 ap->ability_match_count = 0;
1903                 ap->ability_match = 0;
1904                 ap->ack_match = 0;
1905
1906                 rx_cfg_reg = 0;
1907         }
1908
1909         ap->rxconfig = rx_cfg_reg;
1910         ret = ANEG_OK;
1911
1912         switch(ap->state) {
1913         case ANEG_STATE_UNKNOWN:
1914                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1915                         ap->state = ANEG_STATE_AN_ENABLE;
1916
1917                 /* fallthru */
1918         case ANEG_STATE_AN_ENABLE:
1919                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1920                 if (ap->flags & MR_AN_ENABLE) {
1921                         ap->link_time = 0;
1922                         ap->cur_time = 0;
1923                         ap->ability_match_cfg = 0;
1924                         ap->ability_match_count = 0;
1925                         ap->ability_match = 0;
1926                         ap->idle_match = 0;
1927                         ap->ack_match = 0;
1928
1929                         ap->state = ANEG_STATE_RESTART_INIT;
1930                 } else {
1931                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1932                 }
1933                 break;
1934
1935         case ANEG_STATE_RESTART_INIT:
1936                 ap->link_time = ap->cur_time;
1937                 ap->flags &= ~(MR_NP_LOADED);
1938                 ap->txconfig = 0;
1939                 tw32(MAC_TX_AUTO_NEG, 0);
1940                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1941                 tw32_f(MAC_MODE, tp->mac_mode);
1942                 udelay(40);
1943
1944                 ret = ANEG_TIMER_ENAB;
1945                 ap->state = ANEG_STATE_RESTART;
1946
1947                 /* fallthru */
1948         case ANEG_STATE_RESTART:
1949                 delta = ap->cur_time - ap->link_time;
1950                 if (delta > ANEG_STATE_SETTLE_TIME) {
1951                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1952                 } else {
1953                         ret = ANEG_TIMER_ENAB;
1954                 }
1955                 break;
1956
1957         case ANEG_STATE_DISABLE_LINK_OK:
1958                 ret = ANEG_DONE;
1959                 break;
1960
1961         case ANEG_STATE_ABILITY_DETECT_INIT:
1962                 ap->flags &= ~(MR_TOGGLE_TX);
1963                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1964                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1965                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1966                 tw32_f(MAC_MODE, tp->mac_mode);
1967                 udelay(40);
1968
1969                 ap->state = ANEG_STATE_ABILITY_DETECT;
1970                 break;
1971
1972         case ANEG_STATE_ABILITY_DETECT:
1973                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1974                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1975                 }
1976                 break;
1977
1978         case ANEG_STATE_ACK_DETECT_INIT:
1979                 ap->txconfig |= ANEG_CFG_ACK;
1980                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1981                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1982                 tw32_f(MAC_MODE, tp->mac_mode);
1983                 udelay(40);
1984
1985                 ap->state = ANEG_STATE_ACK_DETECT;
1986
1987                 /* fallthru */
1988         case ANEG_STATE_ACK_DETECT:
1989                 if (ap->ack_match != 0) {
1990                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1991                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1992                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1993                         } else {
1994                                 ap->state = ANEG_STATE_AN_ENABLE;
1995                         }
1996                 } else if (ap->ability_match != 0 &&
1997                            ap->rxconfig == 0) {
1998                         ap->state = ANEG_STATE_AN_ENABLE;
1999                 }
2000                 break;
2001
2002         case ANEG_STATE_COMPLETE_ACK_INIT:
2003                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2004                         ret = ANEG_FAILED;
2005                         break;
2006                 }
2007                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2008                                MR_LP_ADV_HALF_DUPLEX |
2009                                MR_LP_ADV_SYM_PAUSE |
2010                                MR_LP_ADV_ASYM_PAUSE |
2011                                MR_LP_ADV_REMOTE_FAULT1 |
2012                                MR_LP_ADV_REMOTE_FAULT2 |
2013                                MR_LP_ADV_NEXT_PAGE |
2014                                MR_TOGGLE_RX |
2015                                MR_NP_RX);
2016                 if (ap->rxconfig & ANEG_CFG_FD)
2017                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2018                 if (ap->rxconfig & ANEG_CFG_HD)
2019                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2020                 if (ap->rxconfig & ANEG_CFG_PS1)
2021                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2022                 if (ap->rxconfig & ANEG_CFG_PS2)
2023                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2024                 if (ap->rxconfig & ANEG_CFG_RF1)
2025                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2026                 if (ap->rxconfig & ANEG_CFG_RF2)
2027                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2028                 if (ap->rxconfig & ANEG_CFG_NP)
2029                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2030
2031                 ap->link_time = ap->cur_time;
2032
2033                 ap->flags ^= (MR_TOGGLE_TX);
2034                 if (ap->rxconfig & 0x0008)
2035                         ap->flags |= MR_TOGGLE_RX;
2036                 if (ap->rxconfig & ANEG_CFG_NP)
2037                         ap->flags |= MR_NP_RX;
2038                 ap->flags |= MR_PAGE_RX;
2039
2040                 ap->state = ANEG_STATE_COMPLETE_ACK;
2041                 ret = ANEG_TIMER_ENAB;
2042                 break;
2043
2044         case ANEG_STATE_COMPLETE_ACK:
2045                 if (ap->ability_match != 0 &&
2046                     ap->rxconfig == 0) {
2047                         ap->state = ANEG_STATE_AN_ENABLE;
2048                         break;
2049                 }
2050                 delta = ap->cur_time - ap->link_time;
2051                 if (delta > ANEG_STATE_SETTLE_TIME) {
2052                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2053                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2054                         } else {
2055                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2056                                     !(ap->flags & MR_NP_RX)) {
2057                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2058                                 } else {
2059                                         ret = ANEG_FAILED;
2060                                 }
2061                         }
2062                 }
2063                 break;
2064
2065         case ANEG_STATE_IDLE_DETECT_INIT:
2066                 ap->link_time = ap->cur_time;
2067                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2068                 tw32_f(MAC_MODE, tp->mac_mode);
2069                 udelay(40);
2070
2071                 ap->state = ANEG_STATE_IDLE_DETECT;
2072                 ret = ANEG_TIMER_ENAB;
2073                 break;
2074
2075         case ANEG_STATE_IDLE_DETECT:
2076                 if (ap->ability_match != 0 &&
2077                     ap->rxconfig == 0) {
2078                         ap->state = ANEG_STATE_AN_ENABLE;
2079                         break;
2080                 }
2081                 delta = ap->cur_time - ap->link_time;
2082                 if (delta > ANEG_STATE_SETTLE_TIME) {
2083                         /* XXX another gem from the Broadcom driver :( */
2084                         ap->state = ANEG_STATE_LINK_OK;
2085                 }
2086                 break;
2087
2088         case ANEG_STATE_LINK_OK:
2089                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2090                 ret = ANEG_DONE;
2091                 break;
2092
2093         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2094                 /* ??? unimplemented */
2095                 break;
2096
2097         case ANEG_STATE_NEXT_PAGE_WAIT:
2098                 /* ??? unimplemented */
2099                 break;
2100
2101         default:
2102                 ret = ANEG_FAILED;
2103                 break;
2104         };
2105
2106         return ret;
2107 }
2108
2109 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2110 {
2111         int res = 0;
2112         struct tg3_fiber_aneginfo aninfo;
2113         int status = ANEG_FAILED;
2114         unsigned int tick;
2115         u32 tmp;
2116
2117         tw32_f(MAC_TX_AUTO_NEG, 0);
2118
2119         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2120         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2121         udelay(40);
2122
2123         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2124         udelay(40);
2125
2126         memset(&aninfo, 0, sizeof(aninfo));
2127         aninfo.flags |= MR_AN_ENABLE;
2128         aninfo.state = ANEG_STATE_UNKNOWN;
2129         aninfo.cur_time = 0;
2130         tick = 0;
2131         while (++tick < 195000) {
2132                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2133                 if (status == ANEG_DONE || status == ANEG_FAILED)
2134                         break;
2135
2136                 udelay(1);
2137         }
2138
2139         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2140         tw32_f(MAC_MODE, tp->mac_mode);
2141         udelay(40);
2142
2143         *flags = aninfo.flags;
2144
2145         if (status == ANEG_DONE &&
2146             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2147                              MR_LP_ADV_FULL_DUPLEX)))
2148                 res = 1;
2149
2150         return res;
2151 }
2152
2153 static void tg3_init_bcm8002(struct tg3 *tp)
2154 {
2155         u32 mac_status = tr32(MAC_STATUS);
2156         int i;
2157
2158         /* Reset when initting first time or we have a link. */
2159         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2160             !(mac_status & MAC_STATUS_PCS_SYNCED))
2161                 return;
2162
2163         /* Set PLL lock range. */
2164         tg3_writephy(tp, 0x16, 0x8007);
2165
2166         /* SW reset */
2167         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2168
2169         /* Wait for reset to complete. */
2170         /* XXX schedule_timeout() ... */
2171         for (i = 0; i < 500; i++)
2172                 udelay(10);
2173
2174         /* Config mode; select PMA/Ch 1 regs. */
2175         tg3_writephy(tp, 0x10, 0x8411);
2176
2177         /* Enable auto-lock and comdet, select txclk for tx. */
2178         tg3_writephy(tp, 0x11, 0x0a10);
2179
2180         tg3_writephy(tp, 0x18, 0x00a0);
2181         tg3_writephy(tp, 0x16, 0x41ff);
2182
2183         /* Assert and deassert POR. */
2184         tg3_writephy(tp, 0x13, 0x0400);
2185         udelay(40);
2186         tg3_writephy(tp, 0x13, 0x0000);
2187
2188         tg3_writephy(tp, 0x11, 0x0a50);
2189         udelay(40);
2190         tg3_writephy(tp, 0x11, 0x0a10);
2191
2192         /* Wait for signal to stabilize */
2193         /* XXX schedule_timeout() ... */
2194         for (i = 0; i < 15000; i++)
2195                 udelay(10);
2196
2197         /* Deselect the channel register so we can read the PHYID
2198          * later.
2199          */
2200         tg3_writephy(tp, 0x10, 0x8011);
2201 }
2202
2203 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2204 {
2205         u32 sg_dig_ctrl, sg_dig_status;
2206         u32 serdes_cfg, expected_sg_dig_ctrl;
2207         int workaround, port_a;
2208         int current_link_up;
2209
2210         serdes_cfg = 0;
2211         expected_sg_dig_ctrl = 0;
2212         workaround = 0;
2213         port_a = 1;
2214         current_link_up = 0;
2215
2216         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2217             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2218                 workaround = 1;
2219                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2220                         port_a = 0;
2221
2222                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2223                 /* preserve bits 20-23 for voltage regulator */
2224                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2225         }
2226
2227         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2228
2229         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2230                 if (sg_dig_ctrl & (1 << 31)) {
2231                         if (workaround) {
2232                                 u32 val = serdes_cfg;
2233
2234                                 if (port_a)
2235                                         val |= 0xc010000;
2236                                 else
2237                                         val |= 0x4010000;
2238                                 tw32_f(MAC_SERDES_CFG, val);
2239                         }
2240                         tw32_f(SG_DIG_CTRL, 0x01388400);
2241                 }
2242                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2243                         tg3_setup_flow_control(tp, 0, 0);
2244                         current_link_up = 1;
2245                 }
2246                 goto out;
2247         }
2248
2249         /* Want auto-negotiation.  */
2250         expected_sg_dig_ctrl = 0x81388400;
2251
2252         /* Pause capability */
2253         expected_sg_dig_ctrl |= (1 << 11);
2254
2255         /* Asymettric pause */
2256         expected_sg_dig_ctrl |= (1 << 12);
2257
2258         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2259                 if (workaround)
2260                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2261                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2262                 udelay(5);
2263                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2264
2265                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2266         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2267                                  MAC_STATUS_SIGNAL_DET)) {
2268                 int i;
2269
2270                 /* Giver time to negotiate (~200ms) */
2271                 for (i = 0; i < 40000; i++) {
2272                         sg_dig_status = tr32(SG_DIG_STATUS);
2273                         if (sg_dig_status & (0x3))
2274                                 break;
2275                         udelay(5);
2276                 }
2277                 mac_status = tr32(MAC_STATUS);
2278
2279                 if ((sg_dig_status & (1 << 1)) &&
2280                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2281                         u32 local_adv, remote_adv;
2282
2283                         local_adv = ADVERTISE_PAUSE_CAP;
2284                         remote_adv = 0;
2285                         if (sg_dig_status & (1 << 19))
2286                                 remote_adv |= LPA_PAUSE_CAP;
2287                         if (sg_dig_status & (1 << 20))
2288                                 remote_adv |= LPA_PAUSE_ASYM;
2289
2290                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2291                         current_link_up = 1;
2292                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2293                 } else if (!(sg_dig_status & (1 << 1))) {
2294                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2295                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2296                         else {
2297                                 if (workaround) {
2298                                         u32 val = serdes_cfg;
2299
2300                                         if (port_a)
2301                                                 val |= 0xc010000;
2302                                         else
2303                                                 val |= 0x4010000;
2304
2305                                         tw32_f(MAC_SERDES_CFG, val);
2306                                 }
2307
2308                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2309                                 udelay(40);
2310
2311                                 /* Link parallel detection - link is up */
2312                                 /* only if we have PCS_SYNC and not */
2313                                 /* receiving config code words */
2314                                 mac_status = tr32(MAC_STATUS);
2315                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2316                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2317                                         tg3_setup_flow_control(tp, 0, 0);
2318                                         current_link_up = 1;
2319                                 }
2320                         }
2321                 }
2322         }
2323
2324 out:
2325         return current_link_up;
2326 }
2327
2328 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2329 {
2330         int current_link_up = 0;
2331
2332         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2333                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2334                 goto out;
2335         }
2336
2337         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2338                 u32 flags;
2339                 int i;
2340
2341                 if (fiber_autoneg(tp, &flags)) {
2342                         u32 local_adv, remote_adv;
2343
2344                         local_adv = ADVERTISE_PAUSE_CAP;
2345                         remote_adv = 0;
2346                         if (flags & MR_LP_ADV_SYM_PAUSE)
2347                                 remote_adv |= LPA_PAUSE_CAP;
2348                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2349                                 remote_adv |= LPA_PAUSE_ASYM;
2350
2351                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2352
2353                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2354                         current_link_up = 1;
2355                 }
2356                 for (i = 0; i < 30; i++) {
2357                         udelay(20);
2358                         tw32_f(MAC_STATUS,
2359                                (MAC_STATUS_SYNC_CHANGED |
2360                                 MAC_STATUS_CFG_CHANGED));
2361                         udelay(40);
2362                         if ((tr32(MAC_STATUS) &
2363                              (MAC_STATUS_SYNC_CHANGED |
2364                               MAC_STATUS_CFG_CHANGED)) == 0)
2365                                 break;
2366                 }
2367
2368                 mac_status = tr32(MAC_STATUS);
2369                 if (current_link_up == 0 &&
2370                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2371                     !(mac_status & MAC_STATUS_RCVD_CFG))
2372                         current_link_up = 1;
2373         } else {
2374                 /* Forcing 1000FD link up. */
2375                 current_link_up = 1;
2376                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2377
2378                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2379                 udelay(40);
2380         }
2381
2382 out:
2383         return current_link_up;
2384 }
2385
2386 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2387 {
2388         u32 orig_pause_cfg;
2389         u16 orig_active_speed;
2390         u8 orig_active_duplex;
2391         u32 mac_status;
2392         int current_link_up;
2393         int i;
2394
2395         orig_pause_cfg =
2396                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2397                                   TG3_FLAG_TX_PAUSE));
2398         orig_active_speed = tp->link_config.active_speed;
2399         orig_active_duplex = tp->link_config.active_duplex;
2400
2401         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2402             netif_carrier_ok(tp->dev) &&
2403             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2404                 mac_status = tr32(MAC_STATUS);
2405                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2406                                MAC_STATUS_SIGNAL_DET |
2407                                MAC_STATUS_CFG_CHANGED |
2408                                MAC_STATUS_RCVD_CFG);
2409                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2410                                    MAC_STATUS_SIGNAL_DET)) {
2411                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2412                                             MAC_STATUS_CFG_CHANGED));
2413                         return 0;
2414                 }
2415         }
2416
2417         tw32_f(MAC_TX_AUTO_NEG, 0);
2418
2419         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2420         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2421         tw32_f(MAC_MODE, tp->mac_mode);
2422         udelay(40);
2423
2424         if (tp->phy_id == PHY_ID_BCM8002)
2425                 tg3_init_bcm8002(tp);
2426
2427         /* Enable link change event even when serdes polling.  */
2428         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2429         udelay(40);
2430
2431         current_link_up = 0;
2432         mac_status = tr32(MAC_STATUS);
2433
2434         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2435                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2436         else
2437                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2438
2439         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2440         tw32_f(MAC_MODE, tp->mac_mode);
2441         udelay(40);
2442
2443         tp->hw_status->status =
2444                 (SD_STATUS_UPDATED |
2445                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2446
2447         for (i = 0; i < 100; i++) {
2448                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2449                                     MAC_STATUS_CFG_CHANGED));
2450                 udelay(5);
2451                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2452                                          MAC_STATUS_CFG_CHANGED)) == 0)
2453                         break;
2454         }
2455
2456         mac_status = tr32(MAC_STATUS);
2457         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2458                 current_link_up = 0;
2459                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2460                         tw32_f(MAC_MODE, (tp->mac_mode |
2461                                           MAC_MODE_SEND_CONFIGS));
2462                         udelay(1);
2463                         tw32_f(MAC_MODE, tp->mac_mode);
2464                 }
2465         }
2466
2467         if (current_link_up == 1) {
2468                 tp->link_config.active_speed = SPEED_1000;
2469                 tp->link_config.active_duplex = DUPLEX_FULL;
2470                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2471                                     LED_CTRL_LNKLED_OVERRIDE |
2472                                     LED_CTRL_1000MBPS_ON));
2473         } else {
2474                 tp->link_config.active_speed = SPEED_INVALID;
2475                 tp->link_config.active_duplex = DUPLEX_INVALID;
2476                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2477                                     LED_CTRL_LNKLED_OVERRIDE |
2478                                     LED_CTRL_TRAFFIC_OVERRIDE));
2479         }
2480
2481         if (current_link_up != netif_carrier_ok(tp->dev)) {
2482                 if (current_link_up)
2483                         netif_carrier_on(tp->dev);
2484                 else
2485                         netif_carrier_off(tp->dev);
2486                 tg3_link_report(tp);
2487         } else {
2488                 u32 now_pause_cfg =
2489                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2490                                          TG3_FLAG_TX_PAUSE);
2491                 if (orig_pause_cfg != now_pause_cfg ||
2492                     orig_active_speed != tp->link_config.active_speed ||
2493                     orig_active_duplex != tp->link_config.active_duplex)
2494                         tg3_link_report(tp);
2495         }
2496
2497         return 0;
2498 }
2499
2500 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2501 {
2502         int err;
2503
2504         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2505                 err = tg3_setup_fiber_phy(tp, force_reset);
2506         } else {
2507                 err = tg3_setup_copper_phy(tp, force_reset);
2508         }
2509
2510         if (tp->link_config.active_speed == SPEED_1000 &&
2511             tp->link_config.active_duplex == DUPLEX_HALF)
2512                 tw32(MAC_TX_LENGTHS,
2513                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2514                       (6 << TX_LENGTHS_IPG_SHIFT) |
2515                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2516         else
2517                 tw32(MAC_TX_LENGTHS,
2518                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2519                       (6 << TX_LENGTHS_IPG_SHIFT) |
2520                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2521
2522         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2523                 if (netif_carrier_ok(tp->dev)) {
2524                         tw32(HOSTCC_STAT_COAL_TICKS,
2525                              tp->coal.stats_block_coalesce_usecs);
2526                 } else {
2527                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2528                 }
2529         }
2530
2531         return err;
2532 }
2533
2534 /* Tigon3 never reports partial packet sends.  So we do not
2535  * need special logic to handle SKBs that have not had all
2536  * of their frags sent yet, like SunGEM does.
2537  */
2538 static void tg3_tx(struct tg3 *tp)
2539 {
2540         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2541         u32 sw_idx = tp->tx_cons;
2542
2543         while (sw_idx != hw_idx) {
2544                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2545                 struct sk_buff *skb = ri->skb;
2546                 int i;
2547
2548                 if (unlikely(skb == NULL))
2549                         BUG();
2550
2551                 pci_unmap_single(tp->pdev,
2552                                  pci_unmap_addr(ri, mapping),
2553                                  skb_headlen(skb),
2554                                  PCI_DMA_TODEVICE);
2555
2556                 ri->skb = NULL;
2557
2558                 sw_idx = NEXT_TX(sw_idx);
2559
2560                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2561                         if (unlikely(sw_idx == hw_idx))
2562                                 BUG();
2563
2564                         ri = &tp->tx_buffers[sw_idx];
2565                         if (unlikely(ri->skb != NULL))
2566                                 BUG();
2567
2568                         pci_unmap_page(tp->pdev,
2569                                        pci_unmap_addr(ri, mapping),
2570                                        skb_shinfo(skb)->frags[i].size,
2571                                        PCI_DMA_TODEVICE);
2572
2573                         sw_idx = NEXT_TX(sw_idx);
2574                 }
2575
2576                 dev_kfree_skb_irq(skb);
2577         }
2578
2579         tp->tx_cons = sw_idx;
2580
2581         if (netif_queue_stopped(tp->dev) &&
2582             (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2583                 netif_wake_queue(tp->dev);
2584 }
2585
2586 /* Returns size of skb allocated or < 0 on error.
2587  *
2588  * We only need to fill in the address because the other members
2589  * of the RX descriptor are invariant, see tg3_init_rings.
2590  *
2591  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2592  * posting buffers we only dirty the first cache line of the RX
2593  * descriptor (containing the address).  Whereas for the RX status
2594  * buffers the cpu only reads the last cacheline of the RX descriptor
2595  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2596  */
2597 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2598                             int src_idx, u32 dest_idx_unmasked)
2599 {
2600         struct tg3_rx_buffer_desc *desc;
2601         struct ring_info *map, *src_map;
2602         struct sk_buff *skb;
2603         dma_addr_t mapping;
2604         int skb_size, dest_idx;
2605
2606         src_map = NULL;
2607         switch (opaque_key) {
2608         case RXD_OPAQUE_RING_STD:
2609                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2610                 desc = &tp->rx_std[dest_idx];
2611                 map = &tp->rx_std_buffers[dest_idx];
2612                 if (src_idx >= 0)
2613                         src_map = &tp->rx_std_buffers[src_idx];
2614                 skb_size = RX_PKT_BUF_SZ;
2615                 break;
2616
2617         case RXD_OPAQUE_RING_JUMBO:
2618                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2619                 desc = &tp->rx_jumbo[dest_idx];
2620                 map = &tp->rx_jumbo_buffers[dest_idx];
2621                 if (src_idx >= 0)
2622                         src_map = &tp->rx_jumbo_buffers[src_idx];
2623                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2624                 break;
2625
2626         default:
2627                 return -EINVAL;
2628         };
2629
2630         /* Do not overwrite any of the map or rp information
2631          * until we are sure we can commit to a new buffer.
2632          *
2633          * Callers depend upon this behavior and assume that
2634          * we leave everything unchanged if we fail.
2635          */
2636         skb = dev_alloc_skb(skb_size);
2637         if (skb == NULL)
2638                 return -ENOMEM;
2639
2640         skb->dev = tp->dev;
2641         skb_reserve(skb, tp->rx_offset);
2642
2643         mapping = pci_map_single(tp->pdev, skb->data,
2644                                  skb_size - tp->rx_offset,
2645                                  PCI_DMA_FROMDEVICE);
2646
2647         map->skb = skb;
2648         pci_unmap_addr_set(map, mapping, mapping);
2649
2650         if (src_map != NULL)
2651                 src_map->skb = NULL;
2652
2653         desc->addr_hi = ((u64)mapping >> 32);
2654         desc->addr_lo = ((u64)mapping & 0xffffffff);
2655
2656         return skb_size;
2657 }
2658
2659 /* We only need to move over in the address because the other
2660  * members of the RX descriptor are invariant.  See notes above
2661  * tg3_alloc_rx_skb for full details.
2662  */
2663 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
2664                            int src_idx, u32 dest_idx_unmasked)
2665 {
2666         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
2667         struct ring_info *src_map, *dest_map;
2668         int dest_idx;
2669
2670         switch (opaque_key) {
2671         case RXD_OPAQUE_RING_STD:
2672                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2673                 dest_desc = &tp->rx_std[dest_idx];
2674                 dest_map = &tp->rx_std_buffers[dest_idx];
2675                 src_desc = &tp->rx_std[src_idx];
2676                 src_map = &tp->rx_std_buffers[src_idx];
2677                 break;
2678
2679         case RXD_OPAQUE_RING_JUMBO:
2680                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2681                 dest_desc = &tp->rx_jumbo[dest_idx];
2682                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
2683                 src_desc = &tp->rx_jumbo[src_idx];
2684                 src_map = &tp->rx_jumbo_buffers[src_idx];
2685                 break;
2686
2687         default:
2688                 return;
2689         };
2690
2691         dest_map->skb = src_map->skb;
2692         pci_unmap_addr_set(dest_map, mapping,
2693                            pci_unmap_addr(src_map, mapping));
2694         dest_desc->addr_hi = src_desc->addr_hi;
2695         dest_desc->addr_lo = src_desc->addr_lo;
2696
2697         src_map->skb = NULL;
2698 }
2699
2700 #if TG3_VLAN_TAG_USED
2701 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2702 {
2703         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
2704 }
2705 #endif
2706
2707 /* The RX ring scheme is composed of multiple rings which post fresh
2708  * buffers to the chip, and one special ring the chip uses to report
2709  * status back to the host.
2710  *
2711  * The special ring reports the status of received packets to the
2712  * host.  The chip does not write into the original descriptor the
2713  * RX buffer was obtained from.  The chip simply takes the original
2714  * descriptor as provided by the host, updates the status and length
2715  * field, then writes this into the next status ring entry.
2716  *
2717  * Each ring the host uses to post buffers to the chip is described
2718  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
2719  * it is first placed into the on-chip ram.  When the packet's length
2720  * is known, it walks down the TG3_BDINFO entries to select the ring.
2721  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
2722  * which is within the range of the new packet's length is chosen.
2723  *
2724  * The "separate ring for rx status" scheme may sound queer, but it makes
2725  * sense from a cache coherency perspective.  If only the host writes
2726  * to the buffer post rings, and only the chip writes to the rx status
2727  * rings, then cache lines never move beyond shared-modified state.
2728  * If both the host and chip were to write into the same ring, cache line
2729  * eviction could occur since both entities want it in an exclusive state.
2730  */
2731 static int tg3_rx(struct tg3 *tp, int budget)
2732 {
2733         u32 work_mask;
2734         u32 sw_idx = tp->rx_rcb_ptr;
2735         u16 hw_idx;
2736         int received;
2737
2738         hw_idx = tp->hw_status->idx[0].rx_producer;
2739         /*
2740          * We need to order the read of hw_idx and the read of
2741          * the opaque cookie.
2742          */
2743         rmb();
2744         work_mask = 0;
2745         received = 0;
2746         while (sw_idx != hw_idx && budget > 0) {
2747                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
2748                 unsigned int len;
2749                 struct sk_buff *skb;
2750                 dma_addr_t dma_addr;
2751                 u32 opaque_key, desc_idx, *post_ptr;
2752
2753                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
2754                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
2755                 if (opaque_key == RXD_OPAQUE_RING_STD) {
2756                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
2757                                                   mapping);
2758                         skb = tp->rx_std_buffers[desc_idx].skb;
2759                         post_ptr = &tp->rx_std_ptr;
2760                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
2761                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
2762                                                   mapping);
2763                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
2764                         post_ptr = &tp->rx_jumbo_ptr;
2765                 }
2766                 else {
2767                         goto next_pkt_nopost;
2768                 }
2769
2770                 work_mask |= opaque_key;
2771
2772                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
2773                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
2774                 drop_it:
2775                         tg3_recycle_rx(tp, opaque_key,
2776                                        desc_idx, *post_ptr);
2777                 drop_it_no_recycle:
2778                         /* Other statistics kept track of by card. */
2779                         tp->net_stats.rx_dropped++;
2780                         goto next_pkt;
2781                 }
2782
2783                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
2784
2785                 if (len > RX_COPY_THRESHOLD
2786                         && tp->rx_offset == 2
2787                         /* rx_offset != 2 iff this is a 5701 card running
2788                          * in PCI-X mode [see tg3_get_invariants()] */
2789                 ) {
2790                         int skb_size;
2791
2792                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
2793                                                     desc_idx, *post_ptr);
2794                         if (skb_size < 0)
2795                                 goto drop_it;
2796
2797                         pci_unmap_single(tp->pdev, dma_addr,
2798                                          skb_size - tp->rx_offset,
2799                                          PCI_DMA_FROMDEVICE);
2800
2801                         skb_put(skb, len);
2802                 } else {
2803                         struct sk_buff *copy_skb;
2804
2805                         tg3_recycle_rx(tp, opaque_key,
2806                                        desc_idx, *post_ptr);
2807
2808                         copy_skb = dev_alloc_skb(len + 2);
2809                         if (copy_skb == NULL)
2810                                 goto drop_it_no_recycle;
2811
2812                         copy_skb->dev = tp->dev;
2813                         skb_reserve(copy_skb, 2);
2814                         skb_put(copy_skb, len);
2815                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2816                         memcpy(copy_skb->data, skb->data, len);
2817                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
2818
2819                         /* We'll reuse the original ring buffer. */
2820                         skb = copy_skb;
2821                 }
2822
2823                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
2824                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
2825                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
2826                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
2827                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2828                 else
2829                         skb->ip_summed = CHECKSUM_NONE;
2830
2831                 skb->protocol = eth_type_trans(skb, tp->dev);
2832 #if TG3_VLAN_TAG_USED
2833                 if (tp->vlgrp != NULL &&
2834                     desc->type_flags & RXD_FLAG_VLAN) {
2835                         tg3_vlan_rx(tp, skb,
2836                                     desc->err_vlan & RXD_VLAN_MASK);
2837                 } else
2838 #endif
2839                         netif_receive_skb(skb);
2840
2841                 tp->dev->last_rx = jiffies;
2842                 received++;
2843                 budget--;
2844
2845 next_pkt:
2846                 (*post_ptr)++;
2847 next_pkt_nopost:
2848                 sw_idx++;
2849                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
2850
2851                 /* Refresh hw_idx to see if there is new work */
2852                 if (sw_idx == hw_idx) {
2853                         hw_idx = tp->hw_status->idx[0].rx_producer;
2854                         rmb();
2855                 }
2856         }
2857
2858         /* ACK the status ring. */
2859         tp->rx_rcb_ptr = sw_idx;
2860         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
2861
2862         /* Refill RX ring(s). */
2863         if (work_mask & RXD_OPAQUE_RING_STD) {
2864                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
2865                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2866                              sw_idx);
2867         }
2868         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
2869                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
2870                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
2871                              sw_idx);
2872         }
2873         mmiowb();
2874
2875         return received;
2876 }
2877
2878 static int tg3_poll(struct net_device *netdev, int *budget)
2879 {
2880         struct tg3 *tp = netdev_priv(netdev);
2881         struct tg3_hw_status *sblk = tp->hw_status;
2882         unsigned long flags;
2883         int done;
2884
2885         spin_lock_irqsave(&tp->lock, flags);
2886
2887         /* handle link change and other phy events */
2888         if (!(tp->tg3_flags &
2889               (TG3_FLAG_USE_LINKCHG_REG |
2890                TG3_FLAG_POLL_SERDES))) {
2891                 if (sblk->status & SD_STATUS_LINK_CHG) {
2892                         sblk->status = SD_STATUS_UPDATED |
2893                                 (sblk->status & ~SD_STATUS_LINK_CHG);
2894                         tg3_setup_phy(tp, 0);
2895                 }
2896         }
2897
2898         /* run TX completion thread */
2899         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
2900                 spin_lock(&tp->tx_lock);
2901                 tg3_tx(tp);
2902                 spin_unlock(&tp->tx_lock);
2903         }
2904
2905         spin_unlock_irqrestore(&tp->lock, flags);
2906
2907         /* run RX thread, within the bounds set by NAPI.
2908          * All RX "locking" is done by ensuring outside
2909          * code synchronizes with dev->poll()
2910          */
2911         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2912                 int orig_budget = *budget;
2913                 int work_done;
2914
2915                 if (orig_budget > netdev->quota)
2916                         orig_budget = netdev->quota;
2917
2918                 work_done = tg3_rx(tp, orig_budget);
2919
2920                 *budget -= work_done;
2921                 netdev->quota -= work_done;
2922         }
2923
2924         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2925                 tp->last_tag = sblk->status_tag;
2926         rmb();
2927
2928         /* if no more work, tell net stack and NIC we're done */
2929         done = !tg3_has_work(tp);
2930         if (done) {
2931                 spin_lock_irqsave(&tp->lock, flags);
2932                 __netif_rx_complete(netdev);
2933                 tg3_restart_ints(tp);
2934                 spin_unlock_irqrestore(&tp->lock, flags);
2935         }
2936
2937         return (done ? 0 : 1);
2938 }
2939
2940 /* MSI ISR - No need to check for interrupt sharing and no need to
2941  * flush status block and interrupt mailbox. PCI ordering rules
2942  * guarantee that MSI will arrive after the status block.
2943  */
2944 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2945 {
2946         struct net_device *dev = dev_id;
2947         struct tg3 *tp = netdev_priv(dev);
2948         struct tg3_hw_status *sblk = tp->hw_status;
2949         unsigned long flags;
2950
2951         spin_lock_irqsave(&tp->lock, flags);
2952
2953         /*
2954          * Writing any value to intr-mbox-0 clears PCI INTA# and
2955          * chip-internal interrupt pending events.
2956          * Writing non-zero to intr-mbox-0 additional tells the
2957          * NIC to stop sending us irqs, engaging "in-intr-handler"
2958          * event coalescing.
2959          */
2960         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
2961         tp->last_tag = sblk->status_tag;
2962         sblk->status &= ~SD_STATUS_UPDATED;
2963         if (likely(tg3_has_work(tp)))
2964                 netif_rx_schedule(dev);         /* schedule NAPI poll */
2965         else {
2966                 /* No work, re-enable interrupts.  */
2967                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2968                              tp->last_tag << 24);
2969         }
2970
2971         spin_unlock_irqrestore(&tp->lock, flags);
2972
2973         return IRQ_RETVAL(1);
2974 }
2975
2976 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2977 {
2978         struct net_device *dev = dev_id;
2979         struct tg3 *tp = netdev_priv(dev);
2980         struct tg3_hw_status *sblk = tp->hw_status;
2981         unsigned long flags;
2982         unsigned int handled = 1;
2983
2984         spin_lock_irqsave(&tp->lock, flags);
2985
2986         /* In INTx mode, it is possible for the interrupt to arrive at
2987          * the CPU before the status block posted prior to the interrupt.
2988          * Reading the PCI State register will confirm whether the
2989          * interrupt is ours and will flush the status block.
2990          */
2991         if ((sblk->status & SD_STATUS_UPDATED) ||
2992             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
2993                 /*
2994                  * Writing any value to intr-mbox-0 clears PCI INTA# and
2995                  * chip-internal interrupt pending events.
2996                  * Writing non-zero to intr-mbox-0 additional tells the
2997                  * NIC to stop sending us irqs, engaging "in-intr-handler"
2998                  * event coalescing.
2999                  */
3000                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3001                              0x00000001);
3002                 sblk->status &= ~SD_STATUS_UPDATED;
3003                 if (likely(tg3_has_work(tp)))
3004                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3005                 else {
3006                         /* No work, shared interrupt perhaps?  re-enable
3007                          * interrupts, and flush that PCI write
3008                          */
3009                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3010                                 0x00000000);
3011                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3012                 }
3013         } else {        /* shared interrupt */
3014                 handled = 0;
3015         }
3016
3017         spin_unlock_irqrestore(&tp->lock, flags);
3018
3019         return IRQ_RETVAL(handled);
3020 }
3021
3022 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3023 {
3024         struct net_device *dev = dev_id;
3025         struct tg3 *tp = netdev_priv(dev);
3026         struct tg3_hw_status *sblk = tp->hw_status;
3027         unsigned long flags;
3028         unsigned int handled = 1;
3029
3030         spin_lock_irqsave(&tp->lock, flags);
3031
3032         /* In INTx mode, it is possible for the interrupt to arrive at
3033          * the CPU before the status block posted prior to the interrupt.
3034          * Reading the PCI State register will confirm whether the
3035          * interrupt is ours and will flush the status block.
3036          */
3037         if ((sblk->status & SD_STATUS_UPDATED) ||
3038             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3039                 /*
3040                  * writing any value to intr-mbox-0 clears PCI INTA# and
3041                  * chip-internal interrupt pending events.
3042                  * writing non-zero to intr-mbox-0 additional tells the
3043                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3044                  * event coalescing.
3045                  */
3046                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3047                              0x00000001);
3048                 tp->last_tag = sblk->status_tag;
3049                 sblk->status &= ~SD_STATUS_UPDATED;
3050                 if (likely(tg3_has_work(tp)))
3051                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3052                 else {
3053                         /* no work, shared interrupt perhaps?  re-enable
3054                          * interrupts, and flush that PCI write
3055                          */
3056                         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3057                                      tp->last_tag << 24);
3058                         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3059                 }
3060         } else {        /* shared interrupt */
3061                 handled = 0;
3062         }
3063
3064         spin_unlock_irqrestore(&tp->lock, flags);
3065
3066         return IRQ_RETVAL(handled);
3067 }
3068
3069 /* ISR for interrupt test */
3070 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3071                 struct pt_regs *regs)
3072 {
3073         struct net_device *dev = dev_id;
3074         struct tg3 *tp = netdev_priv(dev);
3075         struct tg3_hw_status *sblk = tp->hw_status;
3076
3077         if (sblk->status & SD_STATUS_UPDATED) {
3078                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3079                              0x00000001);
3080                 return IRQ_RETVAL(1);
3081         }
3082         return IRQ_RETVAL(0);
3083 }
3084
3085 static int tg3_init_hw(struct tg3 *);
3086 static int tg3_halt(struct tg3 *, int, int);
3087
3088 #ifdef CONFIG_NET_POLL_CONTROLLER
3089 static void tg3_poll_controller(struct net_device *dev)
3090 {
3091         struct tg3 *tp = netdev_priv(dev);
3092
3093         tg3_interrupt(tp->pdev->irq, dev, NULL);
3094 }
3095 #endif
3096
3097 static void tg3_reset_task(void *_data)
3098 {
3099         struct tg3 *tp = _data;
3100         unsigned int restart_timer;
3101
3102         tg3_netif_stop(tp);
3103
3104         spin_lock_irq(&tp->lock);
3105         spin_lock(&tp->tx_lock);
3106
3107         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3108         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3109
3110         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3111         tg3_init_hw(tp);
3112
3113         tg3_netif_start(tp);
3114
3115         spin_unlock(&tp->tx_lock);
3116         spin_unlock_irq(&tp->lock);
3117
3118         if (restart_timer)
3119                 mod_timer(&tp->timer, jiffies + 1);
3120 }
3121
3122 static void tg3_tx_timeout(struct net_device *dev)
3123 {
3124         struct tg3 *tp = netdev_priv(dev);
3125
3126         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3127                dev->name);
3128
3129         schedule_work(&tp->reset_task);
3130 }
3131
3132 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3133
3134 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3135                                        u32 guilty_entry, int guilty_len,
3136                                        u32 last_plus_one, u32 *start, u32 mss)
3137 {
3138         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3139         dma_addr_t new_addr;
3140         u32 entry = *start;
3141         int i;
3142
3143         if (!new_skb) {
3144                 dev_kfree_skb(skb);
3145                 return -1;
3146         }
3147
3148         /* New SKB is guaranteed to be linear. */
3149         entry = *start;
3150         new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3151                                   PCI_DMA_TODEVICE);
3152         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3153                     (skb->ip_summed == CHECKSUM_HW) ?
3154                     TXD_FLAG_TCPUDP_CSUM : 0, 1 | (mss << 1));
3155         *start = NEXT_TX(entry);
3156
3157         /* Now clean up the sw ring entries. */
3158         i = 0;
3159         while (entry != last_plus_one) {
3160                 int len;
3161
3162                 if (i == 0)
3163                         len = skb_headlen(skb);
3164                 else
3165                         len = skb_shinfo(skb)->frags[i-1].size;
3166                 pci_unmap_single(tp->pdev,
3167                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3168                                  len, PCI_DMA_TODEVICE);
3169                 if (i == 0) {
3170                         tp->tx_buffers[entry].skb = new_skb;
3171                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3172                 } else {
3173                         tp->tx_buffers[entry].skb = NULL;
3174                 }
3175                 entry = NEXT_TX(entry);
3176                 i++;
3177         }
3178
3179         dev_kfree_skb(skb);
3180
3181         return 0;
3182 }
3183
3184 static void tg3_set_txd(struct tg3 *tp, int entry,
3185                         dma_addr_t mapping, int len, u32 flags,
3186                         u32 mss_and_is_end)
3187 {
3188         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3189         int is_end = (mss_and_is_end & 0x1);
3190         u32 mss = (mss_and_is_end >> 1);
3191         u32 vlan_tag = 0;
3192
3193         if (is_end)
3194                 flags |= TXD_FLAG_END;
3195         if (flags & TXD_FLAG_VLAN) {
3196                 vlan_tag = flags >> 16;
3197                 flags &= 0xffff;
3198         }
3199         vlan_tag |= (mss << TXD_MSS_SHIFT);
3200
3201         txd->addr_hi = ((u64) mapping >> 32);
3202         txd->addr_lo = ((u64) mapping & 0xffffffff);
3203         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3204         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3205 }
3206
3207 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3208 {
3209         u32 base = (u32) mapping & 0xffffffff;
3210
3211         return ((base > 0xffffdcc0) &&
3212                 (base + len + 8 < base));
3213 }
3214
3215 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3216 {
3217         struct tg3 *tp = netdev_priv(dev);
3218         dma_addr_t mapping;
3219         unsigned int i;
3220         u32 len, entry, base_flags, mss;
3221         int would_hit_hwbug;
3222         unsigned long flags;
3223
3224         len = skb_headlen(skb);
3225
3226         /* No BH disabling for tx_lock here.  We are running in BH disabled
3227          * context and TX reclaim runs via tp->poll inside of a software
3228          * interrupt.  Rejoice!
3229          *
3230          * Actually, things are not so simple.  If we are to take a hw
3231          * IRQ here, we can deadlock, consider:
3232          *
3233          *       CPU1           CPU2
3234          *   tg3_start_xmit
3235          *   take tp->tx_lock
3236          *                      tg3_timer
3237          *                      take tp->lock
3238          *   tg3_interrupt
3239          *   spin on tp->lock
3240          *                      spin on tp->tx_lock
3241          *
3242          * So we really do need to disable interrupts when taking
3243          * tx_lock here.
3244          */
3245         local_irq_save(flags);
3246         if (!spin_trylock(&tp->tx_lock)) {
3247                 local_irq_restore(flags);
3248                 return NETDEV_TX_LOCKED;
3249         }
3250
3251         /* This is a hard error, log it. */
3252         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3253                 netif_stop_queue(dev);
3254                 spin_unlock_irqrestore(&tp->tx_lock, flags);
3255                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3256                        dev->name);
3257                 return NETDEV_TX_BUSY;
3258         }
3259
3260         entry = tp->tx_prod;
3261         base_flags = 0;
3262         if (skb->ip_summed == CHECKSUM_HW)
3263                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3264 #if TG3_TSO_SUPPORT != 0
3265         mss = 0;
3266         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3267             (mss = skb_shinfo(skb)->tso_size) != 0) {
3268                 int tcp_opt_len, ip_tcp_len;
3269
3270                 if (skb_header_cloned(skb) &&
3271                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3272                         dev_kfree_skb(skb);
3273                         goto out_unlock;
3274                 }
3275
3276                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3277                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3278
3279                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3280                                TXD_FLAG_CPU_POST_DMA);
3281
3282                 skb->nh.iph->check = 0;
3283                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3284                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3285                         skb->h.th->check = 0;
3286                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3287                 }
3288                 else {
3289                         skb->h.th->check =
3290                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3291                                                    skb->nh.iph->daddr,
3292                                                    0, IPPROTO_TCP, 0);
3293                 }
3294
3295                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3296                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3297                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3298                                 int tsflags;
3299
3300                                 tsflags = ((skb->nh.iph->ihl - 5) +
3301                                            (tcp_opt_len >> 2));
3302                                 mss |= (tsflags << 11);
3303                         }
3304                 } else {
3305                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3306                                 int tsflags;
3307
3308                                 tsflags = ((skb->nh.iph->ihl - 5) +
3309                                            (tcp_opt_len >> 2));
3310                                 base_flags |= tsflags << 12;
3311                         }
3312                 }
3313         }
3314 #else
3315         mss = 0;
3316 #endif
3317 #if TG3_VLAN_TAG_USED
3318         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3319                 base_flags |= (TXD_FLAG_VLAN |
3320                                (vlan_tx_tag_get(skb) << 16));
3321 #endif
3322
3323         /* Queue skb data, a.k.a. the main skb fragment. */
3324         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3325
3326         tp->tx_buffers[entry].skb = skb;
3327         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3328
3329         would_hit_hwbug = 0;
3330
3331         if (tg3_4g_overflow_test(mapping, len))
3332                 would_hit_hwbug = entry + 1;
3333
3334         tg3_set_txd(tp, entry, mapping, len, base_flags,
3335                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3336
3337         entry = NEXT_TX(entry);
3338
3339         /* Now loop through additional data fragments, and queue them. */
3340         if (skb_shinfo(skb)->nr_frags > 0) {
3341                 unsigned int i, last;
3342
3343                 last = skb_shinfo(skb)->nr_frags - 1;
3344                 for (i = 0; i <= last; i++) {
3345                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3346
3347                         len = frag->size;
3348                         mapping = pci_map_page(tp->pdev,
3349                                                frag->page,
3350                                                frag->page_offset,
3351                                                len, PCI_DMA_TODEVICE);
3352
3353                         tp->tx_buffers[entry].skb = NULL;
3354                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3355
3356                         if (tg3_4g_overflow_test(mapping, len)) {
3357                                 /* Only one should match. */
3358                                 if (would_hit_hwbug)
3359                                         BUG();
3360                                 would_hit_hwbug = entry + 1;
3361                         }
3362
3363                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3364                                 tg3_set_txd(tp, entry, mapping, len,
3365                                             base_flags, (i == last)|(mss << 1));
3366                         else
3367                                 tg3_set_txd(tp, entry, mapping, len,
3368                                             base_flags, (i == last));
3369
3370                         entry = NEXT_TX(entry);
3371                 }
3372         }
3373
3374         if (would_hit_hwbug) {
3375                 u32 last_plus_one = entry;
3376                 u32 start;
3377                 unsigned int len = 0;
3378
3379                 would_hit_hwbug -= 1;
3380                 entry = entry - 1 - skb_shinfo(skb)->nr_frags;
3381                 entry &= (TG3_TX_RING_SIZE - 1);
3382                 start = entry;
3383                 i = 0;
3384                 while (entry != last_plus_one) {
3385                         if (i == 0)
3386                                 len = skb_headlen(skb);
3387                         else
3388                                 len = skb_shinfo(skb)->frags[i-1].size;
3389
3390                         if (entry == would_hit_hwbug)
3391                                 break;
3392
3393                         i++;
3394                         entry = NEXT_TX(entry);
3395
3396                 }
3397
3398                 /* If the workaround fails due to memory/mapping
3399                  * failure, silently drop this packet.
3400                  */
3401                 if (tigon3_4gb_hwbug_workaround(tp, skb,
3402                                                 entry, len,
3403                                                 last_plus_one,
3404                                                 &start, mss))
3405                         goto out_unlock;
3406
3407                 entry = start;
3408         }
3409
3410         /* Packets are ready, update Tx producer idx local and on card. */
3411         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3412
3413         tp->tx_prod = entry;
3414         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1))
3415                 netif_stop_queue(dev);
3416
3417 out_unlock:
3418         mmiowb();
3419         spin_unlock_irqrestore(&tp->tx_lock, flags);
3420
3421         dev->trans_start = jiffies;
3422
3423         return NETDEV_TX_OK;
3424 }
3425
3426 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3427                                int new_mtu)
3428 {
3429         dev->mtu = new_mtu;
3430
3431         if (new_mtu > ETH_DATA_LEN)
3432                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
3433         else
3434                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_ENABLE;
3435 }
3436
3437 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3438 {
3439         struct tg3 *tp = netdev_priv(dev);
3440
3441         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3442                 return -EINVAL;
3443
3444         if (!netif_running(dev)) {
3445                 /* We'll just catch it later when the
3446                  * device is up'd.
3447                  */
3448                 tg3_set_mtu(dev, tp, new_mtu);
3449                 return 0;
3450         }
3451
3452         tg3_netif_stop(tp);
3453         spin_lock_irq(&tp->lock);
3454         spin_lock(&tp->tx_lock);
3455
3456         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3457
3458         tg3_set_mtu(dev, tp, new_mtu);
3459
3460         tg3_init_hw(tp);
3461
3462         tg3_netif_start(tp);
3463
3464         spin_unlock(&tp->tx_lock);
3465         spin_unlock_irq(&tp->lock);
3466
3467         return 0;
3468 }
3469
3470 /* Free up pending packets in all rx/tx rings.
3471  *
3472  * The chip has been shut down and the driver detached from
3473  * the networking, so no interrupts or new tx packets will
3474  * end up in the driver.  tp->{tx,}lock is not held and we are not
3475  * in an interrupt context and thus may sleep.
3476  */
3477 static void tg3_free_rings(struct tg3 *tp)
3478 {
3479         struct ring_info *rxp;
3480         int i;
3481
3482         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3483                 rxp = &tp->rx_std_buffers[i];
3484
3485                 if (rxp->skb == NULL)
3486                         continue;
3487                 pci_unmap_single(tp->pdev,
3488                                  pci_unmap_addr(rxp, mapping),
3489                                  RX_PKT_BUF_SZ - tp->rx_offset,
3490                                  PCI_DMA_FROMDEVICE);
3491                 dev_kfree_skb_any(rxp->skb);
3492                 rxp->skb = NULL;
3493         }
3494
3495         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3496                 rxp = &tp->rx_jumbo_buffers[i];
3497
3498                 if (rxp->skb == NULL)
3499                         continue;
3500                 pci_unmap_single(tp->pdev,
3501                                  pci_unmap_addr(rxp, mapping),
3502                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3503                                  PCI_DMA_FROMDEVICE);
3504                 dev_kfree_skb_any(rxp->skb);
3505                 rxp->skb = NULL;
3506         }
3507
3508         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3509                 struct tx_ring_info *txp;
3510                 struct sk_buff *skb;
3511                 int j;
3512
3513                 txp = &tp->tx_buffers[i];
3514                 skb = txp->skb;
3515
3516                 if (skb == NULL) {
3517                         i++;
3518                         continue;
3519                 }
3520
3521                 pci_unmap_single(tp->pdev,
3522                                  pci_unmap_addr(txp, mapping),
3523                                  skb_headlen(skb),
3524                                  PCI_DMA_TODEVICE);
3525                 txp->skb = NULL;
3526
3527                 i++;
3528
3529                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3530                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3531                         pci_unmap_page(tp->pdev,
3532                                        pci_unmap_addr(txp, mapping),
3533                                        skb_shinfo(skb)->frags[j].size,
3534                                        PCI_DMA_TODEVICE);
3535                         i++;
3536                 }
3537
3538                 dev_kfree_skb_any(skb);
3539         }
3540 }
3541
3542 /* Initialize tx/rx rings for packet processing.
3543  *
3544  * The chip has been shut down and the driver detached from
3545  * the networking, so no interrupts or new tx packets will
3546  * end up in the driver.  tp->{tx,}lock are held and thus
3547  * we may not sleep.
3548  */
3549 static void tg3_init_rings(struct tg3 *tp)
3550 {
3551         u32 i;
3552
3553         /* Free up all the SKBs. */
3554         tg3_free_rings(tp);
3555
3556         /* Zero out all descriptors. */
3557         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3558         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3559         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3560         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3561
3562         /* Initialize invariants of the rings, we only set this
3563          * stuff once.  This works because the card does not
3564          * write into the rx buffer posting rings.
3565          */
3566         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3567                 struct tg3_rx_buffer_desc *rxd;
3568
3569                 rxd = &tp->rx_std[i];
3570                 rxd->idx_len = (RX_PKT_BUF_SZ - tp->rx_offset - 64)
3571                         << RXD_LEN_SHIFT;
3572                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3573                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3574                                (i << RXD_OPAQUE_INDEX_SHIFT));
3575         }
3576
3577         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3578                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3579                         struct tg3_rx_buffer_desc *rxd;
3580
3581                         rxd = &tp->rx_jumbo[i];
3582                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3583                                 << RXD_LEN_SHIFT;
3584                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3585                                 RXD_FLAG_JUMBO;
3586                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3587                                (i << RXD_OPAQUE_INDEX_SHIFT));
3588                 }
3589         }
3590
3591         /* Now allocate fresh SKBs for each rx ring. */
3592         for (i = 0; i < tp->rx_pending; i++) {
3593                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3594                                      -1, i) < 0)
3595                         break;
3596         }
3597
3598         if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
3599                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3600                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3601                                              -1, i) < 0)
3602                                 break;
3603                 }
3604         }
3605 }
3606
3607 /*
3608  * Must not be invoked with interrupt sources disabled and
3609  * the hardware shutdown down.
3610  */
3611 static void tg3_free_consistent(struct tg3 *tp)
3612 {
3613         if (tp->rx_std_buffers) {
3614                 kfree(tp->rx_std_buffers);
3615                 tp->rx_std_buffers = NULL;
3616         }
3617         if (tp->rx_std) {
3618                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3619                                     tp->rx_std, tp->rx_std_mapping);
3620                 tp->rx_std = NULL;
3621         }
3622         if (tp->rx_jumbo) {
3623                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3624                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3625                 tp->rx_jumbo = NULL;
3626         }
3627         if (tp->rx_rcb) {
3628                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3629                                     tp->rx_rcb, tp->rx_rcb_mapping);
3630                 tp->rx_rcb = NULL;
3631         }
3632         if (tp->tx_ring) {
3633                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3634                         tp->tx_ring, tp->tx_desc_mapping);
3635                 tp->tx_ring = NULL;
3636         }
3637         if (tp->hw_status) {
3638                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3639                                     tp->hw_status, tp->status_mapping);
3640                 tp->hw_status = NULL;
3641         }
3642         if (tp->hw_stats) {
3643                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3644                                     tp->hw_stats, tp->stats_mapping);
3645                 tp->hw_stats = NULL;
3646         }
3647 }
3648
3649 /*
3650  * Must not be invoked with interrupt sources disabled and
3651  * the hardware shutdown down.  Can sleep.
3652  */
3653 static int tg3_alloc_consistent(struct tg3 *tp)
3654 {
3655         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
3656                                       (TG3_RX_RING_SIZE +
3657                                        TG3_RX_JUMBO_RING_SIZE)) +
3658                                      (sizeof(struct tx_ring_info) *
3659                                       TG3_TX_RING_SIZE),
3660                                      GFP_KERNEL);
3661         if (!tp->rx_std_buffers)
3662                 return -ENOMEM;
3663
3664         memset(tp->rx_std_buffers, 0,
3665                (sizeof(struct ring_info) *
3666                 (TG3_RX_RING_SIZE +
3667                  TG3_RX_JUMBO_RING_SIZE)) +
3668                (sizeof(struct tx_ring_info) *
3669                 TG3_TX_RING_SIZE));
3670
3671         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
3672         tp->tx_buffers = (struct tx_ring_info *)
3673                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
3674
3675         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
3676                                           &tp->rx_std_mapping);
3677         if (!tp->rx_std)
3678                 goto err_out;
3679
3680         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3681                                             &tp->rx_jumbo_mapping);
3682
3683         if (!tp->rx_jumbo)
3684                 goto err_out;
3685
3686         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3687                                           &tp->rx_rcb_mapping);
3688         if (!tp->rx_rcb)
3689                 goto err_out;
3690
3691         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
3692                                            &tp->tx_desc_mapping);
3693         if (!tp->tx_ring)
3694                 goto err_out;
3695
3696         tp->hw_status = pci_alloc_consistent(tp->pdev,
3697                                              TG3_HW_STATUS_SIZE,
3698                                              &tp->status_mapping);
3699         if (!tp->hw_status)
3700                 goto err_out;
3701
3702         tp->hw_stats = pci_alloc_consistent(tp->pdev,
3703                                             sizeof(struct tg3_hw_stats),
3704                                             &tp->stats_mapping);
3705         if (!tp->hw_stats)
3706                 goto err_out;
3707
3708         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3709         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3710
3711         return 0;
3712
3713 err_out:
3714         tg3_free_consistent(tp);
3715         return -ENOMEM;
3716 }
3717
3718 #define MAX_WAIT_CNT 1000
3719
3720 /* To stop a block, clear the enable bit and poll till it
3721  * clears.  tp->lock is held.
3722  */
3723 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
3724 {
3725         unsigned int i;
3726         u32 val;
3727
3728         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
3729                 switch (ofs) {
3730                 case RCVLSC_MODE:
3731                 case DMAC_MODE:
3732                 case MBFREE_MODE:
3733                 case BUFMGR_MODE:
3734                 case MEMARB_MODE:
3735                         /* We can't enable/disable these bits of the
3736                          * 5705/5750, just say success.
3737                          */
3738                         return 0;
3739
3740                 default:
3741                         break;
3742                 };
3743         }
3744
3745         val = tr32(ofs);
3746         val &= ~enable_bit;
3747         tw32_f(ofs, val);
3748
3749         for (i = 0; i < MAX_WAIT_CNT; i++) {
3750                 udelay(100);
3751                 val = tr32(ofs);
3752                 if ((val & enable_bit) == 0)
3753                         break;
3754         }
3755
3756         if (i == MAX_WAIT_CNT && !silent) {
3757                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
3758                        "ofs=%lx enable_bit=%x\n",
3759                        ofs, enable_bit);
3760                 return -ENODEV;
3761         }
3762
3763         return 0;
3764 }
3765
3766 /* tp->lock is held. */
3767 static int tg3_abort_hw(struct tg3 *tp, int silent)
3768 {
3769         int i, err;
3770
3771         tg3_disable_ints(tp);
3772
3773         tp->rx_mode &= ~RX_MODE_ENABLE;
3774         tw32_f(MAC_RX_MODE, tp->rx_mode);
3775         udelay(10);
3776
3777         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
3778         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
3779         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
3780         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
3781         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
3782         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
3783
3784         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
3785         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
3786         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
3787         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
3788         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
3789         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
3790         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
3791
3792         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
3793         tw32_f(MAC_MODE, tp->mac_mode);
3794         udelay(40);
3795
3796         tp->tx_mode &= ~TX_MODE_ENABLE;
3797         tw32_f(MAC_TX_MODE, tp->tx_mode);
3798
3799         for (i = 0; i < MAX_WAIT_CNT; i++) {
3800                 udelay(100);
3801                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
3802                         break;
3803         }
3804         if (i >= MAX_WAIT_CNT) {
3805                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
3806                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
3807                        tp->dev->name, tr32(MAC_TX_MODE));
3808                 err |= -ENODEV;
3809         }
3810
3811         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
3812         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
3813         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
3814
3815         tw32(FTQ_RESET, 0xffffffff);
3816         tw32(FTQ_RESET, 0x00000000);
3817
3818         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
3819         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
3820
3821         if (tp->hw_status)
3822                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
3823         if (tp->hw_stats)
3824                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
3825
3826         return err;
3827 }
3828
3829 /* tp->lock is held. */
3830 static int tg3_nvram_lock(struct tg3 *tp)
3831 {
3832         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
3833                 int i;
3834
3835                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3836                 for (i = 0; i < 8000; i++) {
3837                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3838                                 break;
3839                         udelay(20);
3840                 }
3841                 if (i == 8000)
3842                         return -ENODEV;
3843         }
3844         return 0;
3845 }
3846
3847 /* tp->lock is held. */
3848 static void tg3_nvram_unlock(struct tg3 *tp)
3849 {
3850         if (tp->tg3_flags & TG3_FLAG_NVRAM)
3851                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3852 }
3853
3854 /* tp->lock is held. */
3855 static void tg3_enable_nvram_access(struct tg3 *tp)
3856 {
3857         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3858             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3859                 u32 nvaccess = tr32(NVRAM_ACCESS);
3860
3861                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3862         }
3863 }
3864
3865 /* tp->lock is held. */
3866 static void tg3_disable_nvram_access(struct tg3 *tp)
3867 {
3868         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3869             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3870                 u32 nvaccess = tr32(NVRAM_ACCESS);
3871
3872                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3873         }
3874 }
3875
3876 /* tp->lock is held. */
3877 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3878 {
3879         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3880                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
3881                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
3882
3883         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3884                 switch (kind) {
3885                 case RESET_KIND_INIT:
3886                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3887                                       DRV_STATE_START);
3888                         break;
3889
3890                 case RESET_KIND_SHUTDOWN:
3891                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3892                                       DRV_STATE_UNLOAD);
3893                         break;
3894
3895                 case RESET_KIND_SUSPEND:
3896                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3897                                       DRV_STATE_SUSPEND);
3898                         break;
3899
3900                 default:
3901                         break;
3902                 };
3903         }
3904 }
3905
3906 /* tp->lock is held. */
3907 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
3908 {
3909         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
3910                 switch (kind) {
3911                 case RESET_KIND_INIT:
3912                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3913                                       DRV_STATE_START_DONE);
3914                         break;
3915
3916                 case RESET_KIND_SHUTDOWN:
3917                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3918                                       DRV_STATE_UNLOAD_DONE);
3919                         break;
3920
3921                 default:
3922                         break;
3923                 };
3924         }
3925 }
3926
3927 /* tp->lock is held. */
3928 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
3929 {
3930         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
3931                 switch (kind) {
3932                 case RESET_KIND_INIT:
3933                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3934                                       DRV_STATE_START);
3935                         break;
3936
3937                 case RESET_KIND_SHUTDOWN:
3938                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3939                                       DRV_STATE_UNLOAD);
3940                         break;
3941
3942                 case RESET_KIND_SUSPEND:
3943                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
3944                                       DRV_STATE_SUSPEND);
3945                         break;
3946
3947                 default:
3948                         break;
3949                 };
3950         }
3951 }
3952
3953 static void tg3_stop_fw(struct tg3 *);
3954
3955 /* tp->lock is held. */
3956 static int tg3_chip_reset(struct tg3 *tp)
3957 {
3958         u32 val;
3959         u32 flags_save;
3960         int i;
3961
3962         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
3963                 tg3_nvram_lock(tp);
3964
3965         /*
3966          * We must avoid the readl() that normally takes place.
3967          * It locks machines, causes machine checks, and other
3968          * fun things.  So, temporarily disable the 5701
3969          * hardware workaround, while we do the reset.
3970          */
3971         flags_save = tp->tg3_flags;
3972         tp->tg3_flags &= ~TG3_FLAG_5701_REG_WRITE_BUG;
3973
3974         /* do the reset */
3975         val = GRC_MISC_CFG_CORECLK_RESET;
3976
3977         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3978                 if (tr32(0x7e2c) == 0x60) {
3979                         tw32(0x7e2c, 0x20);
3980                 }
3981                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
3982                         tw32(GRC_MISC_CFG, (1 << 29));
3983                         val |= (1 << 29);
3984                 }
3985         }
3986
3987         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
3988                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
3989         tw32(GRC_MISC_CFG, val);
3990
3991         /* restore 5701 hardware bug workaround flag */
3992         tp->tg3_flags = flags_save;
3993
3994         /* Unfortunately, we have to delay before the PCI read back.
3995          * Some 575X chips even will not respond to a PCI cfg access
3996          * when the reset command is given to the chip.
3997          *
3998          * How do these hardware designers expect things to work
3999          * properly if the PCI write is posted for a long period
4000          * of time?  It is always necessary to have some method by
4001          * which a register read back can occur to push the write
4002          * out which does the reset.
4003          *
4004          * For most tg3 variants the trick below was working.
4005          * Ho hum...
4006          */
4007         udelay(120);
4008
4009         /* Flush PCI posted writes.  The normal MMIO registers
4010          * are inaccessible at this time so this is the only
4011          * way to make this reliably (actually, this is no longer
4012          * the case, see above).  I tried to use indirect
4013          * register read/write but this upset some 5701 variants.
4014          */
4015         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4016
4017         udelay(120);
4018
4019         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4020                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4021                         int i;
4022                         u32 cfg_val;
4023
4024                         /* Wait for link training to complete.  */
4025                         for (i = 0; i < 5000; i++)
4026                                 udelay(100);
4027
4028                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4029                         pci_write_config_dword(tp->pdev, 0xc4,
4030                                                cfg_val | (1 << 15));
4031                 }
4032                 /* Set PCIE max payload size and clear error status.  */
4033                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4034         }
4035
4036         /* Re-enable indirect register accesses. */
4037         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4038                                tp->misc_host_ctrl);
4039
4040         /* Set MAX PCI retry to zero. */
4041         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4042         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4043             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4044                 val |= PCISTATE_RETRY_SAME_DMA;
4045         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4046
4047         pci_restore_state(tp->pdev);
4048
4049         /* Make sure PCI-X relaxed ordering bit is clear. */
4050         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4051         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4052         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4053
4054         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4055
4056         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4057                 tg3_stop_fw(tp);
4058                 tw32(0x5000, 0x400);
4059         }
4060
4061         tw32(GRC_MODE, tp->grc_mode);
4062
4063         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4064                 u32 val = tr32(0xc4);
4065
4066                 tw32(0xc4, val | (1 << 15));
4067         }
4068
4069         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4070             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4071                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4072                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4073                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4074                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4075         }
4076
4077         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4078                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4079                 tw32_f(MAC_MODE, tp->mac_mode);
4080         } else
4081                 tw32_f(MAC_MODE, 0);
4082         udelay(40);
4083
4084         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4085                 /* Wait for firmware initialization to complete. */
4086                 for (i = 0; i < 100000; i++) {
4087                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4088                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4089                                 break;
4090                         udelay(10);
4091                 }
4092                 if (i >= 100000) {
4093                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4094                                "firmware will not restart magic=%08x\n",
4095                                tp->dev->name, val);
4096                         return -ENODEV;
4097                 }
4098         }
4099
4100         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4101             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4102                 u32 val = tr32(0x7c00);
4103
4104                 tw32(0x7c00, val | (1 << 25));
4105         }
4106
4107         /* Reprobe ASF enable state.  */
4108         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4109         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4110         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4111         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4112                 u32 nic_cfg;
4113
4114                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4115                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4116                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4117                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4118                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4119                 }
4120         }
4121
4122         return 0;
4123 }
4124
4125 /* tp->lock is held. */
4126 static void tg3_stop_fw(struct tg3 *tp)
4127 {
4128         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4129                 u32 val;
4130                 int i;
4131
4132                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4133                 val = tr32(GRC_RX_CPU_EVENT);
4134                 val |= (1 << 14);
4135                 tw32(GRC_RX_CPU_EVENT, val);
4136
4137                 /* Wait for RX cpu to ACK the event.  */
4138                 for (i = 0; i < 100; i++) {
4139                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4140                                 break;
4141                         udelay(1);
4142                 }
4143         }
4144 }
4145
4146 /* tp->lock is held. */
4147 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4148 {
4149         int err;
4150
4151         tg3_stop_fw(tp);
4152
4153         tg3_write_sig_pre_reset(tp, kind);
4154
4155         tg3_abort_hw(tp, silent);
4156         err = tg3_chip_reset(tp);
4157
4158         tg3_write_sig_legacy(tp, kind);
4159         tg3_write_sig_post_reset(tp, kind);
4160
4161         if (err)
4162                 return err;
4163
4164         return 0;
4165 }
4166
4167 #define TG3_FW_RELEASE_MAJOR    0x0
4168 #define TG3_FW_RELASE_MINOR     0x0
4169 #define TG3_FW_RELEASE_FIX      0x0
4170 #define TG3_FW_START_ADDR       0x08000000
4171 #define TG3_FW_TEXT_ADDR        0x08000000
4172 #define TG3_FW_TEXT_LEN         0x9c0
4173 #define TG3_FW_RODATA_ADDR      0x080009c0
4174 #define TG3_FW_RODATA_LEN       0x60
4175 #define TG3_FW_DATA_ADDR        0x08000a40
4176 #define TG3_FW_DATA_LEN         0x20
4177 #define TG3_FW_SBSS_ADDR        0x08000a60
4178 #define TG3_FW_SBSS_LEN         0xc
4179 #define TG3_FW_BSS_ADDR         0x08000a70
4180 #define TG3_FW_BSS_LEN          0x10
4181
4182 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4183         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4184         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4185         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4186         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4187         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4188         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4189         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4190         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4191         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4192         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4193         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4194         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4195         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4196         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4197         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4198         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4199         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4200         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4201         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4202         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4203         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4204         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4205         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4206         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4207         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4208         0, 0, 0, 0, 0, 0,
4209         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4210         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4211         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4212         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4213         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4214         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4215         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4216         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4217         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4218         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4219         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4220         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4221         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4222         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4223         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4224         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4225         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4226         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4227         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4228         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4229         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4230         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4231         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4232         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4233         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4234         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4235         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4236         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4237         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4238         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4239         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4240         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4241         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4242         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4243         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4244         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4245         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4246         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4247         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4248         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4249         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4250         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4251         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4252         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4253         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4254         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4255         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4256         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4257         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4258         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4259         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4260         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4261         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4262         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4263         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4264         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4265         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4266         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4267         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4268         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4269         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4270         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4271         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4272         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4273         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4274 };
4275
4276 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4277         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4278         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4279         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4280         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4281         0x00000000
4282 };
4283
4284 #if 0 /* All zeros, don't eat up space with it. */
4285 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4286         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4287         0x00000000, 0x00000000, 0x00000000, 0x00000000
4288 };
4289 #endif
4290
4291 #define RX_CPU_SCRATCH_BASE     0x30000
4292 #define RX_CPU_SCRATCH_SIZE     0x04000
4293 #define TX_CPU_SCRATCH_BASE     0x34000
4294 #define TX_CPU_SCRATCH_SIZE     0x04000
4295
4296 /* tp->lock is held. */
4297 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4298 {
4299         int i;
4300
4301         if (offset == TX_CPU_BASE &&
4302             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4303                 BUG();
4304
4305         if (offset == RX_CPU_BASE) {
4306                 for (i = 0; i < 10000; i++) {
4307                         tw32(offset + CPU_STATE, 0xffffffff);
4308                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4309                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4310                                 break;
4311                 }
4312
4313                 tw32(offset + CPU_STATE, 0xffffffff);
4314                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4315                 udelay(10);
4316         } else {
4317                 for (i = 0; i < 10000; i++) {
4318                         tw32(offset + CPU_STATE, 0xffffffff);
4319                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4320                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4321                                 break;
4322                 }
4323         }
4324
4325         if (i >= 10000) {
4326                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4327                        "and %s CPU\n",
4328                        tp->dev->name,
4329                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4330                 return -ENODEV;
4331         }
4332         return 0;
4333 }
4334
4335 struct fw_info {
4336         unsigned int text_base;
4337         unsigned int text_len;
4338         u32 *text_data;
4339         unsigned int rodata_base;
4340         unsigned int rodata_len;
4341         u32 *rodata_data;
4342         unsigned int data_base;
4343         unsigned int data_len;
4344         u32 *data_data;
4345 };
4346
4347 /* tp->lock is held. */
4348 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4349                                  int cpu_scratch_size, struct fw_info *info)
4350 {
4351         int err, i;
4352         u32 orig_tg3_flags = tp->tg3_flags;
4353         void (*write_op)(struct tg3 *, u32, u32);
4354
4355         if (cpu_base == TX_CPU_BASE &&
4356             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4357                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4358                        "TX cpu firmware on %s which is 5705.\n",
4359                        tp->dev->name);
4360                 return -EINVAL;
4361         }
4362
4363         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4364                 write_op = tg3_write_mem;
4365         else
4366                 write_op = tg3_write_indirect_reg32;
4367
4368         /* Force use of PCI config space for indirect register
4369          * write calls.
4370          */
4371         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4372
4373         /* It is possible that bootcode is still loading at this point.
4374          * Get the nvram lock first before halting the cpu.
4375          */
4376         tg3_nvram_lock(tp);
4377         err = tg3_halt_cpu(tp, cpu_base);
4378         tg3_nvram_unlock(tp);
4379         if (err)
4380                 goto out;
4381
4382         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4383                 write_op(tp, cpu_scratch_base + i, 0);
4384         tw32(cpu_base + CPU_STATE, 0xffffffff);
4385         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4386         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4387                 write_op(tp, (cpu_scratch_base +
4388                               (info->text_base & 0xffff) +
4389                               (i * sizeof(u32))),
4390                          (info->text_data ?
4391                           info->text_data[i] : 0));
4392         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4393                 write_op(tp, (cpu_scratch_base +
4394                               (info->rodata_base & 0xffff) +
4395                               (i * sizeof(u32))),
4396                          (info->rodata_data ?
4397                           info->rodata_data[i] : 0));
4398         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4399                 write_op(tp, (cpu_scratch_base +
4400                               (info->data_base & 0xffff) +
4401                               (i * sizeof(u32))),
4402                          (info->data_data ?
4403                           info->data_data[i] : 0));
4404
4405         err = 0;
4406
4407 out:
4408         tp->tg3_flags = orig_tg3_flags;
4409         return err;
4410 }
4411
4412 /* tp->lock is held. */
4413 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4414 {
4415         struct fw_info info;
4416         int err, i;
4417
4418         info.text_base = TG3_FW_TEXT_ADDR;
4419         info.text_len = TG3_FW_TEXT_LEN;
4420         info.text_data = &tg3FwText[0];
4421         info.rodata_base = TG3_FW_RODATA_ADDR;
4422         info.rodata_len = TG3_FW_RODATA_LEN;
4423         info.rodata_data = &tg3FwRodata[0];
4424         info.data_base = TG3_FW_DATA_ADDR;
4425         info.data_len = TG3_FW_DATA_LEN;
4426         info.data_data = NULL;
4427
4428         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4429                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4430                                     &info);
4431         if (err)
4432                 return err;
4433
4434         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4435                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4436                                     &info);
4437         if (err)
4438                 return err;
4439
4440         /* Now startup only the RX cpu. */
4441         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4442         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4443
4444         for (i = 0; i < 5; i++) {
4445                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4446                         break;
4447                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4448                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4449                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4450                 udelay(1000);
4451         }
4452         if (i >= 5) {
4453                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4454                        "to set RX CPU PC, is %08x should be %08x\n",
4455                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4456                        TG3_FW_TEXT_ADDR);
4457                 return -ENODEV;
4458         }
4459         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4460         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4461
4462         return 0;
4463 }
4464
4465 #if TG3_TSO_SUPPORT != 0
4466
4467 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4468 #define TG3_TSO_FW_RELASE_MINOR         0x6
4469 #define TG3_TSO_FW_RELEASE_FIX          0x0
4470 #define TG3_TSO_FW_START_ADDR           0x08000000
4471 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4472 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4473 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4474 #define TG3_TSO_FW_RODATA_LEN           0x60
4475 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4476 #define TG3_TSO_FW_DATA_LEN             0x30
4477 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4478 #define TG3_TSO_FW_SBSS_LEN             0x2c
4479 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4480 #define TG3_TSO_FW_BSS_LEN              0x894
4481
4482 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4483         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4484         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4485         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4486         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4487         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4488         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4489         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4490         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4491         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4492         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4493         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4494         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4495         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4496         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4497         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4498         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4499         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4500         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4501         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4502         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4503         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4504         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4505         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4506         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4507         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4508         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4509         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4510         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4511         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4512         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4513         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4514         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4515         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4516         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4517         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4518         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4519         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4520         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4521         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4522         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4523         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4524         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4525         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4526         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4527         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4528         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4529         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4530         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4531         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4532         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4533         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4534         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4535         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4536         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4537         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4538         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4539         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4540         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4541         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4542         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4543         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4544         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4545         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4546         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4547         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4548         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4549         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4550         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4551         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4552         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4553         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4554         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4555         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4556         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4557         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4558         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4559         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4560         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4561         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4562         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4563         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4564         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4565         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4566         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4567         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4568         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4569         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4570         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4571         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4572         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4573         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4574         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4575         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4576         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4577         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4578         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4579         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4580         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4581         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4582         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4583         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4584         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4585         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4586         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4587         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4588         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4589         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4590         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4591         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4592         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4593         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4594         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4595         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4596         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4597         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4598         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4599         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4600         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4601         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4602         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4603         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4604         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4605         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4606         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4607         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4608         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4609         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4610         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4611         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4612         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4613         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4614         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4615         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4616         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4617         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4618         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4619         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4620         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4621         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4622         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4623         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4624         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4625         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4626         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4627         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4628         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4629         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4630         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4631         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4632         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
4633         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
4634         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
4635         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
4636         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
4637         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
4638         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
4639         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
4640         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
4641         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
4642         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
4643         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
4644         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
4645         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
4646         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
4647         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
4648         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
4649         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
4650         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
4651         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
4652         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
4653         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
4654         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
4655         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
4656         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
4657         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
4658         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
4659         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
4660         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
4661         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
4662         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
4663         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
4664         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
4665         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
4666         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
4667         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
4668         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
4669         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
4670         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
4671         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
4672         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
4673         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
4674         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
4675         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
4676         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
4677         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
4678         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
4679         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
4680         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
4681         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
4682         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
4683         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
4684         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
4685         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
4686         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
4687         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
4688         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
4689         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
4690         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
4691         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
4692         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
4693         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
4694         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
4695         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
4696         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
4697         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
4698         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
4699         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
4700         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
4701         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
4702         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
4703         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4704         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
4705         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
4706         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
4707         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
4708         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
4709         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
4710         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
4711         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
4712         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
4713         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
4714         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
4715         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
4716         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
4717         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
4718         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
4719         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
4720         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
4721         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
4722         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
4723         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
4724         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
4725         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
4726         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
4727         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
4728         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
4729         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
4730         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
4731         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
4732         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
4733         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
4734         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
4735         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
4736         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
4737         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
4738         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
4739         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
4740         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
4741         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
4742         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
4743         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
4744         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
4745         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
4746         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
4747         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4748         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
4749         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
4750         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
4751         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
4752         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
4753         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
4754         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
4755         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
4756         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
4757         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
4758         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
4759         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
4760         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
4761         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
4762         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
4763         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
4764         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
4765         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
4766         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
4767 };
4768
4769 static u32 tg3TsoFwRodata[] = {
4770         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4771         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
4772         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
4773         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
4774         0x00000000,
4775 };
4776
4777 static u32 tg3TsoFwData[] = {
4778         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
4779         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4780         0x00000000,
4781 };
4782
4783 /* 5705 needs a special version of the TSO firmware.  */
4784 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
4785 #define TG3_TSO5_FW_RELASE_MINOR        0x2
4786 #define TG3_TSO5_FW_RELEASE_FIX         0x0
4787 #define TG3_TSO5_FW_START_ADDR          0x00010000
4788 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
4789 #define TG3_TSO5_FW_TEXT_LEN            0xe90
4790 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
4791 #define TG3_TSO5_FW_RODATA_LEN          0x50
4792 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
4793 #define TG3_TSO5_FW_DATA_LEN            0x20
4794 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
4795 #define TG3_TSO5_FW_SBSS_LEN            0x28
4796 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
4797 #define TG3_TSO5_FW_BSS_LEN             0x88
4798
4799 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
4800         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
4801         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
4802         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4803         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
4804         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
4805         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
4806         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4807         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
4808         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
4809         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
4810         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
4811         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
4812         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
4813         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
4814         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
4815         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
4816         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
4817         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
4818         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
4819         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
4820         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
4821         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
4822         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
4823         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
4824         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
4825         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
4826         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
4827         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
4828         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
4829         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
4830         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4831         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
4832         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
4833         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
4834         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
4835         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
4836         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
4837         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
4838         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
4839         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
4840         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
4841         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
4842         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
4843         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
4844         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
4845         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
4846         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
4847         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
4848         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
4849         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
4850         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
4851         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
4852         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
4853         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
4854         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
4855         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
4856         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
4857         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
4858         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
4859         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
4860         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
4861         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
4862         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
4863         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
4864         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
4865         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
4866         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
4867         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
4868         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
4869         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
4870         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
4871         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
4872         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
4873         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
4874         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
4875         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
4876         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
4877         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
4878         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
4879         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
4880         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
4881         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
4882         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
4883         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
4884         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
4885         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
4886         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
4887         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
4888         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
4889         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
4890         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
4891         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
4892         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
4893         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
4894         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
4895         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
4896         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
4897         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
4898         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
4899         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
4900         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
4901         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
4902         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
4903         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
4904         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
4905         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
4906         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4907         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4908         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
4909         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
4910         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
4911         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
4912         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
4913         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
4914         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
4915         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
4916         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
4917         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
4918         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
4919         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
4920         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
4921         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
4922         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
4923         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4924         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
4925         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
4926         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
4927         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
4928         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
4929         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
4930         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
4931         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
4932         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
4933         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
4934         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
4935         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
4936         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
4937         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
4938         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
4939         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
4940         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
4941         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
4942         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
4943         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
4944         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
4945         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
4946         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
4947         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4948         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
4949         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
4950         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
4951         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4952         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
4953         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
4954         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4955         0x00000000, 0x00000000, 0x00000000,
4956 };
4957
4958 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
4959         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
4960         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
4961         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4962         0x00000000, 0x00000000, 0x00000000,
4963 };
4964
4965 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
4966         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
4967         0x00000000, 0x00000000, 0x00000000,
4968 };
4969
4970 /* tp->lock is held. */
4971 static int tg3_load_tso_firmware(struct tg3 *tp)
4972 {
4973         struct fw_info info;
4974         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
4975         int err, i;
4976
4977         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4978                 return 0;
4979
4980         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4981                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
4982                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
4983                 info.text_data = &tg3Tso5FwText[0];
4984                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
4985                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
4986                 info.rodata_data = &tg3Tso5FwRodata[0];
4987                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
4988                 info.data_len = TG3_TSO5_FW_DATA_LEN;
4989                 info.data_data = &tg3Tso5FwData[0];
4990                 cpu_base = RX_CPU_BASE;
4991                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
4992                 cpu_scratch_size = (info.text_len +
4993                                     info.rodata_len +
4994                                     info.data_len +
4995                                     TG3_TSO5_FW_SBSS_LEN +
4996                                     TG3_TSO5_FW_BSS_LEN);
4997         } else {
4998                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
4999                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5000                 info.text_data = &tg3TsoFwText[0];
5001                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5002                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5003                 info.rodata_data = &tg3TsoFwRodata[0];
5004                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5005                 info.data_len = TG3_TSO_FW_DATA_LEN;
5006                 info.data_data = &tg3TsoFwData[0];
5007                 cpu_base = TX_CPU_BASE;
5008                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5009                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5010         }
5011
5012         err = tg3_load_firmware_cpu(tp, cpu_base,
5013                                     cpu_scratch_base, cpu_scratch_size,
5014                                     &info);
5015         if (err)
5016                 return err;
5017
5018         /* Now startup the cpu. */
5019         tw32(cpu_base + CPU_STATE, 0xffffffff);
5020         tw32_f(cpu_base + CPU_PC,    info.text_base);
5021
5022         for (i = 0; i < 5; i++) {
5023                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5024                         break;
5025                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5026                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5027                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5028                 udelay(1000);
5029         }
5030         if (i >= 5) {
5031                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5032                        "to set CPU PC, is %08x should be %08x\n",
5033                        tp->dev->name, tr32(cpu_base + CPU_PC),
5034                        info.text_base);
5035                 return -ENODEV;
5036         }
5037         tw32(cpu_base + CPU_STATE, 0xffffffff);
5038         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5039         return 0;
5040 }
5041
5042 #endif /* TG3_TSO_SUPPORT != 0 */
5043
5044 /* tp->lock is held. */
5045 static void __tg3_set_mac_addr(struct tg3 *tp)
5046 {
5047         u32 addr_high, addr_low;
5048         int i;
5049
5050         addr_high = ((tp->dev->dev_addr[0] << 8) |
5051                      tp->dev->dev_addr[1]);
5052         addr_low = ((tp->dev->dev_addr[2] << 24) |
5053                     (tp->dev->dev_addr[3] << 16) |
5054                     (tp->dev->dev_addr[4] <<  8) |
5055                     (tp->dev->dev_addr[5] <<  0));
5056         for (i = 0; i < 4; i++) {
5057                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5058                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5059         }
5060
5061         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5062             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5063                 for (i = 0; i < 12; i++) {
5064                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5065                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5066                 }
5067         }
5068
5069         addr_high = (tp->dev->dev_addr[0] +
5070                      tp->dev->dev_addr[1] +
5071                      tp->dev->dev_addr[2] +
5072                      tp->dev->dev_addr[3] +
5073                      tp->dev->dev_addr[4] +
5074                      tp->dev->dev_addr[5]) &
5075                 TX_BACKOFF_SEED_MASK;
5076         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5077 }
5078
5079 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5080 {
5081         struct tg3 *tp = netdev_priv(dev);
5082         struct sockaddr *addr = p;
5083
5084         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5085
5086         spin_lock_irq(&tp->lock);
5087         __tg3_set_mac_addr(tp);
5088         spin_unlock_irq(&tp->lock);
5089
5090         return 0;
5091 }
5092
5093 /* tp->lock is held. */
5094 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5095                            dma_addr_t mapping, u32 maxlen_flags,
5096                            u32 nic_addr)
5097 {
5098         tg3_write_mem(tp,
5099                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5100                       ((u64) mapping >> 32));
5101         tg3_write_mem(tp,
5102                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5103                       ((u64) mapping & 0xffffffff));
5104         tg3_write_mem(tp,
5105                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5106                        maxlen_flags);
5107
5108         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5109                 tg3_write_mem(tp,
5110                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5111                               nic_addr);
5112 }
5113
5114 static void __tg3_set_rx_mode(struct net_device *);
5115 static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5116 {
5117         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5118         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5119         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5120         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5121         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5122                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5123                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5124         }
5125         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5126         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5127         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5128                 u32 val = ec->stats_block_coalesce_usecs;
5129
5130                 if (!netif_carrier_ok(tp->dev))
5131                         val = 0;
5132
5133                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5134         }
5135 }
5136
5137 /* tp->lock is held. */
5138 static int tg3_reset_hw(struct tg3 *tp)
5139 {
5140         u32 val, rdmac_mode;
5141         int i, err, limit;
5142
5143         tg3_disable_ints(tp);
5144
5145         tg3_stop_fw(tp);
5146
5147         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5148
5149         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5150                 tg3_abort_hw(tp, 1);
5151         }
5152
5153         err = tg3_chip_reset(tp);
5154         if (err)
5155                 return err;
5156
5157         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5158
5159         /* This works around an issue with Athlon chipsets on
5160          * B3 tigon3 silicon.  This bit has no effect on any
5161          * other revision.  But do not set this on PCI Express
5162          * chips.
5163          */
5164         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5165                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5166         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5167
5168         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5169             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5170                 val = tr32(TG3PCI_PCISTATE);
5171                 val |= PCISTATE_RETRY_SAME_DMA;
5172                 tw32(TG3PCI_PCISTATE, val);
5173         }
5174
5175         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5176                 /* Enable some hw fixes.  */
5177                 val = tr32(TG3PCI_MSI_DATA);
5178                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5179                 tw32(TG3PCI_MSI_DATA, val);
5180         }
5181
5182         /* Descriptor ring init may make accesses to the
5183          * NIC SRAM area to setup the TX descriptors, so we
5184          * can only do this after the hardware has been
5185          * successfully reset.
5186          */
5187         tg3_init_rings(tp);
5188
5189         /* This value is determined during the probe time DMA
5190          * engine test, tg3_test_dma.
5191          */
5192         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5193
5194         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5195                           GRC_MODE_4X_NIC_SEND_RINGS |
5196                           GRC_MODE_NO_TX_PHDR_CSUM |
5197                           GRC_MODE_NO_RX_PHDR_CSUM);
5198         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5199         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5200                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5201         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5202                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5203
5204         tw32(GRC_MODE,
5205              tp->grc_mode |
5206              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5207
5208         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5209         val = tr32(GRC_MISC_CFG);
5210         val &= ~0xff;
5211         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5212         tw32(GRC_MISC_CFG, val);
5213
5214         /* Initialize MBUF/DESC pool. */
5215         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5216                 /* Do nothing.  */
5217         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5218                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5219                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5220                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5221                 else
5222                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5223                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5224                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5225         }
5226 #if TG3_TSO_SUPPORT != 0
5227         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5228                 int fw_len;
5229
5230                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5231                           TG3_TSO5_FW_RODATA_LEN +
5232                           TG3_TSO5_FW_DATA_LEN +
5233                           TG3_TSO5_FW_SBSS_LEN +
5234                           TG3_TSO5_FW_BSS_LEN);
5235                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5236                 tw32(BUFMGR_MB_POOL_ADDR,
5237                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5238                 tw32(BUFMGR_MB_POOL_SIZE,
5239                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5240         }
5241 #endif
5242
5243         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
5244                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5245                      tp->bufmgr_config.mbuf_read_dma_low_water);
5246                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5247                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5248                 tw32(BUFMGR_MB_HIGH_WATER,
5249                      tp->bufmgr_config.mbuf_high_water);
5250         } else {
5251                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5252                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5253                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5254                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5255                 tw32(BUFMGR_MB_HIGH_WATER,
5256                      tp->bufmgr_config.mbuf_high_water_jumbo);
5257         }
5258         tw32(BUFMGR_DMA_LOW_WATER,
5259              tp->bufmgr_config.dma_low_water);
5260         tw32(BUFMGR_DMA_HIGH_WATER,
5261              tp->bufmgr_config.dma_high_water);
5262
5263         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5264         for (i = 0; i < 2000; i++) {
5265                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5266                         break;
5267                 udelay(10);
5268         }
5269         if (i >= 2000) {
5270                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5271                        tp->dev->name);
5272                 return -ENODEV;
5273         }
5274
5275         /* Setup replenish threshold. */
5276         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5277
5278         /* Initialize TG3_BDINFO's at:
5279          *  RCVDBDI_STD_BD:     standard eth size rx ring
5280          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5281          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5282          *
5283          * like so:
5284          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5285          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5286          *                              ring attribute flags
5287          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5288          *
5289          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5290          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5291          *
5292          * The size of each ring is fixed in the firmware, but the location is
5293          * configurable.
5294          */
5295         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5296              ((u64) tp->rx_std_mapping >> 32));
5297         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5298              ((u64) tp->rx_std_mapping & 0xffffffff));
5299         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5300              NIC_SRAM_RX_BUFFER_DESC);
5301
5302         /* Don't even try to program the JUMBO/MINI buffer descriptor
5303          * configs on 5705.
5304          */
5305         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5306                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5307                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5308         } else {
5309                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5310                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5311
5312                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5313                      BDINFO_FLAGS_DISABLED);
5314
5315                 /* Setup replenish threshold. */
5316                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5317
5318                 if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
5319                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5320                              ((u64) tp->rx_jumbo_mapping >> 32));
5321                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5322                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5323                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5324                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5325                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5326                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5327                 } else {
5328                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5329                              BDINFO_FLAGS_DISABLED);
5330                 }
5331
5332         }
5333
5334         /* There is only one send ring on 5705/5750, no need to explicitly
5335          * disable the others.
5336          */
5337         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5338                 /* Clear out send RCB ring in SRAM. */
5339                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5340                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5341                                       BDINFO_FLAGS_DISABLED);
5342         }
5343
5344         tp->tx_prod = 0;
5345         tp->tx_cons = 0;
5346         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5347         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5348
5349         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5350                        tp->tx_desc_mapping,
5351                        (TG3_TX_RING_SIZE <<
5352                         BDINFO_FLAGS_MAXLEN_SHIFT),
5353                        NIC_SRAM_TX_BUFFER_DESC);
5354
5355         /* There is only one receive return ring on 5705/5750, no need
5356          * to explicitly disable the others.
5357          */
5358         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5359                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5360                      i += TG3_BDINFO_SIZE) {
5361                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5362                                       BDINFO_FLAGS_DISABLED);
5363                 }
5364         }
5365
5366         tp->rx_rcb_ptr = 0;
5367         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5368
5369         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5370                        tp->rx_rcb_mapping,
5371                        (TG3_RX_RCB_RING_SIZE(tp) <<
5372                         BDINFO_FLAGS_MAXLEN_SHIFT),
5373                        0);
5374
5375         tp->rx_std_ptr = tp->rx_pending;
5376         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5377                      tp->rx_std_ptr);
5378
5379         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) ?
5380                                                 tp->rx_jumbo_pending : 0;
5381         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5382                      tp->rx_jumbo_ptr);
5383
5384         /* Initialize MAC address and backoff seed. */
5385         __tg3_set_mac_addr(tp);
5386
5387         /* MTU + ethernet header + FCS + optional VLAN tag */
5388         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5389
5390         /* The slot time is changed by tg3_setup_phy if we
5391          * run at gigabit with half duplex.
5392          */
5393         tw32(MAC_TX_LENGTHS,
5394              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5395              (6 << TX_LENGTHS_IPG_SHIFT) |
5396              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5397
5398         /* Receive rules. */
5399         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5400         tw32(RCVLPC_CONFIG, 0x0181);
5401
5402         /* Calculate RDMAC_MODE setting early, we need it to determine
5403          * the RCVLPC_STATE_ENABLE mask.
5404          */
5405         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5406                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5407                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5408                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5409                       RDMAC_MODE_LNGREAD_ENAB);
5410         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5411                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5412
5413         /* If statement applies to 5705 and 5750 PCI devices only */
5414         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5415              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5416             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5417                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5418                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5419                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5420                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5421                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5422                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5423                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5424                 }
5425         }
5426
5427         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5428                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5429
5430 #if TG3_TSO_SUPPORT != 0
5431         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5432                 rdmac_mode |= (1 << 27);
5433 #endif
5434
5435         /* Receive/send statistics. */
5436         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5437             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5438                 val = tr32(RCVLPC_STATS_ENABLE);
5439                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5440                 tw32(RCVLPC_STATS_ENABLE, val);
5441         } else {
5442                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5443         }
5444         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5445         tw32(SNDDATAI_STATSENAB, 0xffffff);
5446         tw32(SNDDATAI_STATSCTRL,
5447              (SNDDATAI_SCTRL_ENABLE |
5448               SNDDATAI_SCTRL_FASTUPD));
5449
5450         /* Setup host coalescing engine. */
5451         tw32(HOSTCC_MODE, 0);
5452         for (i = 0; i < 2000; i++) {
5453                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5454                         break;
5455                 udelay(10);
5456         }
5457
5458         tg3_set_coalesce(tp, &tp->coal);
5459
5460         /* set status block DMA address */
5461         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5462              ((u64) tp->status_mapping >> 32));
5463         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5464              ((u64) tp->status_mapping & 0xffffffff));
5465
5466         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5467                 /* Status/statistics block address.  See tg3_timer,
5468                  * the tg3_periodic_fetch_stats call there, and
5469                  * tg3_get_stats to see how this works for 5705/5750 chips.
5470                  */
5471                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5472                      ((u64) tp->stats_mapping >> 32));
5473                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5474                      ((u64) tp->stats_mapping & 0xffffffff));
5475                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5476                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5477         }
5478
5479         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5480
5481         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5482         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5483         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5484                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5485
5486         /* Clear statistics/status block in chip, and status block in ram. */
5487         for (i = NIC_SRAM_STATS_BLK;
5488              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5489              i += sizeof(u32)) {
5490                 tg3_write_mem(tp, i, 0);
5491                 udelay(40);
5492         }
5493         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5494
5495         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5496                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5497         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5498         udelay(40);
5499
5500         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5501          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5502          * register to preserve the GPIO settings for LOMs. The GPIOs,
5503          * whether used as inputs or outputs, are set by boot code after
5504          * reset.
5505          */
5506         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5507                 u32 gpio_mask;
5508
5509                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5510                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5511
5512                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5513                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5514                                      GRC_LCLCTRL_GPIO_OUTPUT3;
5515
5516                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5517
5518                 /* GPIO1 must be driven high for eeprom write protect */
5519                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5520                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5521         }
5522         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5523         udelay(100);
5524
5525         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5526         tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5527         tp->last_tag = 0;
5528
5529         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5530                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5531                 udelay(40);
5532         }
5533
5534         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5535                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5536                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5537                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5538                WDMAC_MODE_LNGREAD_ENAB);
5539
5540         /* If statement applies to 5705 and 5750 PCI devices only */
5541         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5542              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5544                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5545                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5546                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5547                         /* nothing */
5548                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5549                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5550                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5551                         val |= WDMAC_MODE_RX_ACCEL;
5552                 }
5553         }
5554
5555         tw32_f(WDMAC_MODE, val);
5556         udelay(40);
5557
5558         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5559                 val = tr32(TG3PCI_X_CAPS);
5560                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5561                         val &= ~PCIX_CAPS_BURST_MASK;
5562                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5563                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5564                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5565                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5566                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5567                                 val |= (tp->split_mode_max_reqs <<
5568                                         PCIX_CAPS_SPLIT_SHIFT);
5569                 }
5570                 tw32(TG3PCI_X_CAPS, val);
5571         }
5572
5573         tw32_f(RDMAC_MODE, rdmac_mode);
5574         udelay(40);
5575
5576         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5577         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5578                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5579         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5580         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5581         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5582         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5583         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5584 #if TG3_TSO_SUPPORT != 0
5585         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5586                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5587 #endif
5588         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5589         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5590
5591         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5592                 err = tg3_load_5701_a0_firmware_fix(tp);
5593                 if (err)
5594                         return err;
5595         }
5596
5597 #if TG3_TSO_SUPPORT != 0
5598         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5599                 err = tg3_load_tso_firmware(tp);
5600                 if (err)
5601                         return err;
5602         }
5603 #endif
5604
5605         tp->tx_mode = TX_MODE_ENABLE;
5606         tw32_f(MAC_TX_MODE, tp->tx_mode);
5607         udelay(100);
5608
5609         tp->rx_mode = RX_MODE_ENABLE;
5610         tw32_f(MAC_RX_MODE, tp->rx_mode);
5611         udelay(10);
5612
5613         if (tp->link_config.phy_is_low_power) {
5614                 tp->link_config.phy_is_low_power = 0;
5615                 tp->link_config.speed = tp->link_config.orig_speed;
5616                 tp->link_config.duplex = tp->link_config.orig_duplex;
5617                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5618         }
5619
5620         tp->mi_mode = MAC_MI_MODE_BASE;
5621         tw32_f(MAC_MI_MODE, tp->mi_mode);
5622         udelay(80);
5623
5624         tw32(MAC_LED_CTRL, tp->led_ctrl);
5625
5626         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
5627         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5628                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5629                 udelay(10);
5630         }
5631         tw32_f(MAC_RX_MODE, tp->rx_mode);
5632         udelay(10);
5633
5634         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5635                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
5636                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
5637                         /* Set drive transmission level to 1.2V  */
5638                         /* only if the signal pre-emphasis bit is not set  */
5639                         val = tr32(MAC_SERDES_CFG);
5640                         val &= 0xfffff000;
5641                         val |= 0x880;
5642                         tw32(MAC_SERDES_CFG, val);
5643                 }
5644                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
5645                         tw32(MAC_SERDES_CFG, 0x616000);
5646         }
5647
5648         /* Prevent chip from dropping frames when flow control
5649          * is enabled.
5650          */
5651         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
5652
5653         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
5654             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5655                 /* Use hardware link auto-negotiation */
5656                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
5657         }
5658
5659         err = tg3_setup_phy(tp, 1);
5660         if (err)
5661                 return err;
5662
5663         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
5664                 u32 tmp;
5665
5666                 /* Clear CRC stats. */
5667                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
5668                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
5669                         tg3_readphy(tp, 0x14, &tmp);
5670                 }
5671         }
5672
5673         __tg3_set_rx_mode(tp->dev);
5674
5675         /* Initialize receive rules. */
5676         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
5677         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
5678         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
5679         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5680
5681         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5682                 limit = 8;
5683         else
5684                 limit = 16;
5685         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
5686                 limit -= 4;
5687         switch (limit) {
5688         case 16:
5689                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
5690         case 15:
5691                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
5692         case 14:
5693                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
5694         case 13:
5695                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
5696         case 12:
5697                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
5698         case 11:
5699                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
5700         case 10:
5701                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
5702         case 9:
5703                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
5704         case 8:
5705                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
5706         case 7:
5707                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
5708         case 6:
5709                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
5710         case 5:
5711                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
5712         case 4:
5713                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
5714         case 3:
5715                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
5716         case 2:
5717         case 1:
5718
5719         default:
5720                 break;
5721         };
5722
5723         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5724
5725         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5726                 tg3_enable_ints(tp);
5727
5728         return 0;
5729 }
5730
5731 /* Called at device open time to get the chip ready for
5732  * packet processing.  Invoked with tp->lock held.
5733  */
5734 static int tg3_init_hw(struct tg3 *tp)
5735 {
5736         int err;
5737
5738         /* Force the chip into D0. */
5739         err = tg3_set_power_state(tp, 0);
5740         if (err)
5741                 goto out;
5742
5743         tg3_switch_clocks(tp);
5744
5745         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
5746
5747         err = tg3_reset_hw(tp);
5748
5749 out:
5750         return err;
5751 }
5752
5753 #define TG3_STAT_ADD32(PSTAT, REG) \
5754 do {    u32 __val = tr32(REG); \
5755         (PSTAT)->low += __val; \
5756         if ((PSTAT)->low < __val) \
5757                 (PSTAT)->high += 1; \
5758 } while (0)
5759
5760 static void tg3_periodic_fetch_stats(struct tg3 *tp)
5761 {
5762         struct tg3_hw_stats *sp = tp->hw_stats;
5763
5764         if (!netif_carrier_ok(tp->dev))
5765                 return;
5766
5767         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
5768         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
5769         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
5770         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
5771         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
5772         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
5773         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
5774         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
5775         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
5776         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
5777         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
5778         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
5779         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
5780
5781         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
5782         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
5783         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
5784         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
5785         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
5786         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
5787         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
5788         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
5789         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
5790         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
5791         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
5792         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
5793         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
5794         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
5795 }
5796
5797 static void tg3_timer(unsigned long __opaque)
5798 {
5799         struct tg3 *tp = (struct tg3 *) __opaque;
5800         unsigned long flags;
5801
5802         spin_lock_irqsave(&tp->lock, flags);
5803         spin_lock(&tp->tx_lock);
5804
5805         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5806                 /* All of this garbage is because when using non-tagged
5807                  * IRQ status the mailbox/status_block protocol the chip
5808                  * uses with the cpu is race prone.
5809                  */
5810                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5811                         tw32(GRC_LOCAL_CTRL,
5812                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5813                 } else {
5814                         tw32(HOSTCC_MODE, tp->coalesce_mode |
5815                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5816                 }
5817
5818                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5819                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5820                         spin_unlock(&tp->tx_lock);
5821                         spin_unlock_irqrestore(&tp->lock, flags);
5822                         schedule_work(&tp->reset_task);
5823                         return;
5824                 }
5825         }
5826
5827         /* This part only runs once per second. */
5828         if (!--tp->timer_counter) {
5829                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5830                         tg3_periodic_fetch_stats(tp);
5831
5832                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5833                         u32 mac_stat;
5834                         int phy_event;
5835
5836                         mac_stat = tr32(MAC_STATUS);
5837
5838                         phy_event = 0;
5839                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
5840                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
5841                                         phy_event = 1;
5842                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
5843                                 phy_event = 1;
5844
5845                         if (phy_event)
5846                                 tg3_setup_phy(tp, 0);
5847                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
5848                         u32 mac_stat = tr32(MAC_STATUS);
5849                         int need_setup = 0;
5850
5851                         if (netif_carrier_ok(tp->dev) &&
5852                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
5853                                 need_setup = 1;
5854                         }
5855                         if (! netif_carrier_ok(tp->dev) &&
5856                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
5857                                          MAC_STATUS_SIGNAL_DET))) {
5858                                 need_setup = 1;
5859                         }
5860                         if (need_setup) {
5861                                 tw32_f(MAC_MODE,
5862                                      (tp->mac_mode &
5863                                       ~MAC_MODE_PORT_MODE_MASK));
5864                                 udelay(40);
5865                                 tw32_f(MAC_MODE, tp->mac_mode);
5866                                 udelay(40);
5867                                 tg3_setup_phy(tp, 0);
5868                         }
5869                 }
5870
5871                 tp->timer_counter = tp->timer_multiplier;
5872         }
5873
5874         /* Heartbeat is only sent once every 120 seconds.  */
5875         if (!--tp->asf_counter) {
5876                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5877                         u32 val;
5878
5879                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_ALIVE);
5880                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
5881                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 3);
5882                         val = tr32(GRC_RX_CPU_EVENT);
5883                         val |= (1 << 14);
5884                         tw32(GRC_RX_CPU_EVENT, val);
5885                 }
5886                 tp->asf_counter = tp->asf_multiplier;
5887         }
5888
5889         spin_unlock(&tp->tx_lock);
5890         spin_unlock_irqrestore(&tp->lock, flags);
5891
5892         tp->timer.expires = jiffies + tp->timer_offset;
5893         add_timer(&tp->timer);
5894 }
5895
5896 static int tg3_test_interrupt(struct tg3 *tp)
5897 {
5898         struct net_device *dev = tp->dev;
5899         int err, i;
5900         u32 int_mbox = 0;
5901
5902         if (!netif_running(dev))
5903                 return -ENODEV;
5904
5905         tg3_disable_ints(tp);
5906
5907         free_irq(tp->pdev->irq, dev);
5908
5909         err = request_irq(tp->pdev->irq, tg3_test_isr,
5910                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5911         if (err)
5912                 return err;
5913
5914         tg3_enable_ints(tp);
5915
5916         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
5917                HOSTCC_MODE_NOW);
5918
5919         for (i = 0; i < 5; i++) {
5920                 int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5921                 if (int_mbox != 0)
5922                         break;
5923                 msleep(10);
5924         }
5925
5926         tg3_disable_ints(tp);
5927
5928         free_irq(tp->pdev->irq, dev);
5929
5930         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5931                 err = request_irq(tp->pdev->irq, tg3_msi,
5932                                   SA_SAMPLE_RANDOM, dev->name, dev);
5933         else {
5934                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5935                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5936                         fn = tg3_interrupt_tagged;
5937                 err = request_irq(tp->pdev->irq, fn,
5938                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5939         }
5940
5941         if (err)
5942                 return err;
5943
5944         if (int_mbox != 0)
5945                 return 0;
5946
5947         return -EIO;
5948 }
5949
5950 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
5951  * successfully restored
5952  */
5953 static int tg3_test_msi(struct tg3 *tp)
5954 {
5955         struct net_device *dev = tp->dev;
5956         int err;
5957         u16 pci_cmd;
5958
5959         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
5960                 return 0;
5961
5962         /* Turn off SERR reporting in case MSI terminates with Master
5963          * Abort.
5964          */
5965         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
5966         pci_write_config_word(tp->pdev, PCI_COMMAND,
5967                               pci_cmd & ~PCI_COMMAND_SERR);
5968
5969         err = tg3_test_interrupt(tp);
5970
5971         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
5972
5973         if (!err)
5974                 return 0;
5975
5976         /* other failures */
5977         if (err != -EIO)
5978                 return err;
5979
5980         /* MSI test failed, go back to INTx mode */
5981         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
5982                "switching to INTx mode. Please report this failure to "
5983                "the PCI maintainer and include system chipset information.\n",
5984                        tp->dev->name);
5985
5986         free_irq(tp->pdev->irq, dev);
5987         pci_disable_msi(tp->pdev);
5988
5989         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5990
5991         {
5992                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5993                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5994                         fn = tg3_interrupt_tagged;
5995
5996                 err = request_irq(tp->pdev->irq, fn,
5997                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5998         }
5999         if (err)
6000                 return err;
6001
6002         /* Need to reset the chip because the MSI cycle may have terminated
6003          * with Master Abort.
6004          */
6005         spin_lock_irq(&tp->lock);
6006         spin_lock(&tp->tx_lock);
6007
6008         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6009         err = tg3_init_hw(tp);
6010
6011         spin_unlock(&tp->tx_lock);
6012         spin_unlock_irq(&tp->lock);
6013
6014         if (err)
6015                 free_irq(tp->pdev->irq, dev);
6016
6017         return err;
6018 }
6019
6020 static int tg3_open(struct net_device *dev)
6021 {
6022         struct tg3 *tp = netdev_priv(dev);
6023         int err;
6024
6025         spin_lock_irq(&tp->lock);
6026         spin_lock(&tp->tx_lock);
6027
6028         tg3_disable_ints(tp);
6029         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6030
6031         spin_unlock(&tp->tx_lock);
6032         spin_unlock_irq(&tp->lock);
6033
6034         /* The placement of this call is tied
6035          * to the setup and use of Host TX descriptors.
6036          */
6037         err = tg3_alloc_consistent(tp);
6038         if (err)
6039                 return err;
6040
6041         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6042             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6043             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6044                 /* All MSI supporting chips should support tagged
6045                  * status.  Assert that this is the case.
6046                  */
6047                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6048                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6049                                "Not using MSI.\n", tp->dev->name);
6050                 } else if (pci_enable_msi(tp->pdev) == 0) {
6051                         u32 msi_mode;
6052
6053                         msi_mode = tr32(MSGINT_MODE);
6054                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6055                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6056                 }
6057         }
6058         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6059                 err = request_irq(tp->pdev->irq, tg3_msi,
6060                                   SA_SAMPLE_RANDOM, dev->name, dev);
6061         else {
6062                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6063                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6064                         fn = tg3_interrupt_tagged;
6065
6066                 err = request_irq(tp->pdev->irq, fn,
6067                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6068         }
6069
6070         if (err) {
6071                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6072                         pci_disable_msi(tp->pdev);
6073                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6074                 }
6075                 tg3_free_consistent(tp);
6076                 return err;
6077         }
6078
6079         spin_lock_irq(&tp->lock);
6080         spin_lock(&tp->tx_lock);
6081
6082         err = tg3_init_hw(tp);
6083         if (err) {
6084                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6085                 tg3_free_rings(tp);
6086         } else {
6087                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6088                         tp->timer_offset = HZ;
6089                 else
6090                         tp->timer_offset = HZ / 10;
6091
6092                 BUG_ON(tp->timer_offset > HZ);
6093                 tp->timer_counter = tp->timer_multiplier =
6094                         (HZ / tp->timer_offset);
6095                 tp->asf_counter = tp->asf_multiplier =
6096                         ((HZ / tp->timer_offset) * 120);
6097
6098                 init_timer(&tp->timer);
6099                 tp->timer.expires = jiffies + tp->timer_offset;
6100                 tp->timer.data = (unsigned long) tp;
6101                 tp->timer.function = tg3_timer;
6102         }
6103
6104         spin_unlock(&tp->tx_lock);
6105         spin_unlock_irq(&tp->lock);
6106
6107         if (err) {
6108                 free_irq(tp->pdev->irq, dev);
6109                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6110                         pci_disable_msi(tp->pdev);
6111                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6112                 }
6113                 tg3_free_consistent(tp);
6114                 return err;
6115         }
6116
6117         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6118                 err = tg3_test_msi(tp);
6119
6120                 if (err) {
6121                         spin_lock_irq(&tp->lock);
6122                         spin_lock(&tp->tx_lock);
6123
6124                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6125                                 pci_disable_msi(tp->pdev);
6126                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6127                         }
6128                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6129                         tg3_free_rings(tp);
6130                         tg3_free_consistent(tp);
6131
6132                         spin_unlock(&tp->tx_lock);
6133                         spin_unlock_irq(&tp->lock);
6134
6135                         return err;
6136                 }
6137         }
6138
6139         spin_lock_irq(&tp->lock);
6140         spin_lock(&tp->tx_lock);
6141
6142         add_timer(&tp->timer);
6143         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6144         tg3_enable_ints(tp);
6145
6146         spin_unlock(&tp->tx_lock);
6147         spin_unlock_irq(&tp->lock);
6148
6149         netif_start_queue(dev);
6150
6151         return 0;
6152 }
6153
6154 #if 0
6155 /*static*/ void tg3_dump_state(struct tg3 *tp)
6156 {
6157         u32 val32, val32_2, val32_3, val32_4, val32_5;
6158         u16 val16;
6159         int i;
6160
6161         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6162         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6163         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6164                val16, val32);
6165
6166         /* MAC block */
6167         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6168                tr32(MAC_MODE), tr32(MAC_STATUS));
6169         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6170                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6171         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6172                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6173         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6174                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6175
6176         /* Send data initiator control block */
6177         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6178                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6179         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6180                tr32(SNDDATAI_STATSCTRL));
6181
6182         /* Send data completion control block */
6183         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6184
6185         /* Send BD ring selector block */
6186         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6187                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6188
6189         /* Send BD initiator control block */
6190         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6191                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6192
6193         /* Send BD completion control block */
6194         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6195
6196         /* Receive list placement control block */
6197         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6198                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6199         printk("       RCVLPC_STATSCTRL[%08x]\n",
6200                tr32(RCVLPC_STATSCTRL));
6201
6202         /* Receive data and receive BD initiator control block */
6203         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6204                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6205
6206         /* Receive data completion control block */
6207         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6208                tr32(RCVDCC_MODE));
6209
6210         /* Receive BD initiator control block */
6211         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6212                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6213
6214         /* Receive BD completion control block */
6215         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6216                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6217
6218         /* Receive list selector control block */
6219         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6220                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6221
6222         /* Mbuf cluster free block */
6223         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6224                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6225
6226         /* Host coalescing control block */
6227         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6228                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6229         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6230                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6231                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6232         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6233                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6234                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6235         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6236                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6237         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6238                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6239
6240         /* Memory arbiter control block */
6241         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6242                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6243
6244         /* Buffer manager control block */
6245         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6246                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6247         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6248                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6249         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6250                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6251                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6252                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6253
6254         /* Read DMA control block */
6255         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6256                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6257
6258         /* Write DMA control block */
6259         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6260                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6261
6262         /* DMA completion block */
6263         printk("DEBUG: DMAC_MODE[%08x]\n",
6264                tr32(DMAC_MODE));
6265
6266         /* GRC block */
6267         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6268                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6269         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6270                tr32(GRC_LOCAL_CTRL));
6271
6272         /* TG3_BDINFOs */
6273         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6274                tr32(RCVDBDI_JUMBO_BD + 0x0),
6275                tr32(RCVDBDI_JUMBO_BD + 0x4),
6276                tr32(RCVDBDI_JUMBO_BD + 0x8),
6277                tr32(RCVDBDI_JUMBO_BD + 0xc));
6278         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6279                tr32(RCVDBDI_STD_BD + 0x0),
6280                tr32(RCVDBDI_STD_BD + 0x4),
6281                tr32(RCVDBDI_STD_BD + 0x8),
6282                tr32(RCVDBDI_STD_BD + 0xc));
6283         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6284                tr32(RCVDBDI_MINI_BD + 0x0),
6285                tr32(RCVDBDI_MINI_BD + 0x4),
6286                tr32(RCVDBDI_MINI_BD + 0x8),
6287                tr32(RCVDBDI_MINI_BD + 0xc));
6288
6289         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6290         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6291         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6292         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6293         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6294                val32, val32_2, val32_3, val32_4);
6295
6296         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6297         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6298         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6299         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6300         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6301                val32, val32_2, val32_3, val32_4);
6302
6303         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6304         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6305         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6306         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6307         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6308         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6309                val32, val32_2, val32_3, val32_4, val32_5);
6310
6311         /* SW status block */
6312         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6313                tp->hw_status->status,
6314                tp->hw_status->status_tag,
6315                tp->hw_status->rx_jumbo_consumer,
6316                tp->hw_status->rx_consumer,
6317                tp->hw_status->rx_mini_consumer,
6318                tp->hw_status->idx[0].rx_producer,
6319                tp->hw_status->idx[0].tx_consumer);
6320
6321         /* SW statistics block */
6322         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6323                ((u32 *)tp->hw_stats)[0],
6324                ((u32 *)tp->hw_stats)[1],
6325                ((u32 *)tp->hw_stats)[2],
6326                ((u32 *)tp->hw_stats)[3]);
6327
6328         /* Mailboxes */
6329         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6330                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6331                tr32(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6332                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6333                tr32(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6334
6335         /* NIC side send descriptors. */
6336         for (i = 0; i < 6; i++) {
6337                 unsigned long txd;
6338
6339                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6340                         + (i * sizeof(struct tg3_tx_buffer_desc));
6341                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6342                        i,
6343                        readl(txd + 0x0), readl(txd + 0x4),
6344                        readl(txd + 0x8), readl(txd + 0xc));
6345         }
6346
6347         /* NIC side RX descriptors. */
6348         for (i = 0; i < 6; i++) {
6349                 unsigned long rxd;
6350
6351                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6352                         + (i * sizeof(struct tg3_rx_buffer_desc));
6353                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6354                        i,
6355                        readl(rxd + 0x0), readl(rxd + 0x4),
6356                        readl(rxd + 0x8), readl(rxd + 0xc));
6357                 rxd += (4 * sizeof(u32));
6358                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6359                        i,
6360                        readl(rxd + 0x0), readl(rxd + 0x4),
6361                        readl(rxd + 0x8), readl(rxd + 0xc));
6362         }
6363
6364         for (i = 0; i < 6; i++) {
6365                 unsigned long rxd;
6366
6367                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6368                         + (i * sizeof(struct tg3_rx_buffer_desc));
6369                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6370                        i,
6371                        readl(rxd + 0x0), readl(rxd + 0x4),
6372                        readl(rxd + 0x8), readl(rxd + 0xc));
6373                 rxd += (4 * sizeof(u32));
6374                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6375                        i,
6376                        readl(rxd + 0x0), readl(rxd + 0x4),
6377                        readl(rxd + 0x8), readl(rxd + 0xc));
6378         }
6379 }
6380 #endif
6381
6382 static struct net_device_stats *tg3_get_stats(struct net_device *);
6383 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6384
6385 static int tg3_close(struct net_device *dev)
6386 {
6387         struct tg3 *tp = netdev_priv(dev);
6388
6389         netif_stop_queue(dev);
6390
6391         del_timer_sync(&tp->timer);
6392
6393         spin_lock_irq(&tp->lock);
6394         spin_lock(&tp->tx_lock);
6395 #if 0
6396         tg3_dump_state(tp);
6397 #endif
6398
6399         tg3_disable_ints(tp);
6400
6401         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6402         tg3_free_rings(tp);
6403         tp->tg3_flags &=
6404                 ~(TG3_FLAG_INIT_COMPLETE |
6405                   TG3_FLAG_GOT_SERDES_FLOWCTL);
6406         netif_carrier_off(tp->dev);
6407
6408         spin_unlock(&tp->tx_lock);
6409         spin_unlock_irq(&tp->lock);
6410
6411         free_irq(tp->pdev->irq, dev);
6412         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6413                 pci_disable_msi(tp->pdev);
6414                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6415         }
6416
6417         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6418                sizeof(tp->net_stats_prev));
6419         memcpy(&tp->estats_prev, tg3_get_estats(tp),
6420                sizeof(tp->estats_prev));
6421
6422         tg3_free_consistent(tp);
6423
6424         return 0;
6425 }
6426
6427 static inline unsigned long get_stat64(tg3_stat64_t *val)
6428 {
6429         unsigned long ret;
6430
6431 #if (BITS_PER_LONG == 32)
6432         ret = val->low;
6433 #else
6434         ret = ((u64)val->high << 32) | ((u64)val->low);
6435 #endif
6436         return ret;
6437 }
6438
6439 static unsigned long calc_crc_errors(struct tg3 *tp)
6440 {
6441         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6442
6443         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6444             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6445              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6446                 unsigned long flags;
6447                 u32 val;
6448
6449                 spin_lock_irqsave(&tp->lock, flags);
6450                 if (!tg3_readphy(tp, 0x1e, &val)) {
6451                         tg3_writephy(tp, 0x1e, val | 0x8000);
6452                         tg3_readphy(tp, 0x14, &val);
6453                 } else
6454                         val = 0;
6455                 spin_unlock_irqrestore(&tp->lock, flags);
6456
6457                 tp->phy_crc_errors += val;
6458
6459                 return tp->phy_crc_errors;
6460         }
6461
6462         return get_stat64(&hw_stats->rx_fcs_errors);
6463 }
6464
6465 #define ESTAT_ADD(member) \
6466         estats->member =        old_estats->member + \
6467                                 get_stat64(&hw_stats->member)
6468
6469 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6470 {
6471         struct tg3_ethtool_stats *estats = &tp->estats;
6472         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6473         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6474
6475         if (!hw_stats)
6476                 return old_estats;
6477
6478         ESTAT_ADD(rx_octets);
6479         ESTAT_ADD(rx_fragments);
6480         ESTAT_ADD(rx_ucast_packets);
6481         ESTAT_ADD(rx_mcast_packets);
6482         ESTAT_ADD(rx_bcast_packets);
6483         ESTAT_ADD(rx_fcs_errors);
6484         ESTAT_ADD(rx_align_errors);
6485         ESTAT_ADD(rx_xon_pause_rcvd);
6486         ESTAT_ADD(rx_xoff_pause_rcvd);
6487         ESTAT_ADD(rx_mac_ctrl_rcvd);
6488         ESTAT_ADD(rx_xoff_entered);
6489         ESTAT_ADD(rx_frame_too_long_errors);
6490         ESTAT_ADD(rx_jabbers);
6491         ESTAT_ADD(rx_undersize_packets);
6492         ESTAT_ADD(rx_in_length_errors);
6493         ESTAT_ADD(rx_out_length_errors);
6494         ESTAT_ADD(rx_64_or_less_octet_packets);
6495         ESTAT_ADD(rx_65_to_127_octet_packets);
6496         ESTAT_ADD(rx_128_to_255_octet_packets);
6497         ESTAT_ADD(rx_256_to_511_octet_packets);
6498         ESTAT_ADD(rx_512_to_1023_octet_packets);
6499         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6500         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6501         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6502         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6503         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6504
6505         ESTAT_ADD(tx_octets);
6506         ESTAT_ADD(tx_collisions);
6507         ESTAT_ADD(tx_xon_sent);
6508         ESTAT_ADD(tx_xoff_sent);
6509         ESTAT_ADD(tx_flow_control);
6510         ESTAT_ADD(tx_mac_errors);
6511         ESTAT_ADD(tx_single_collisions);
6512         ESTAT_ADD(tx_mult_collisions);
6513         ESTAT_ADD(tx_deferred);
6514         ESTAT_ADD(tx_excessive_collisions);
6515         ESTAT_ADD(tx_late_collisions);
6516         ESTAT_ADD(tx_collide_2times);
6517         ESTAT_ADD(tx_collide_3times);
6518         ESTAT_ADD(tx_collide_4times);
6519         ESTAT_ADD(tx_collide_5times);
6520         ESTAT_ADD(tx_collide_6times);
6521         ESTAT_ADD(tx_collide_7times);
6522         ESTAT_ADD(tx_collide_8times);
6523         ESTAT_ADD(tx_collide_9times);
6524         ESTAT_ADD(tx_collide_10times);
6525         ESTAT_ADD(tx_collide_11times);
6526         ESTAT_ADD(tx_collide_12times);
6527         ESTAT_ADD(tx_collide_13times);
6528         ESTAT_ADD(tx_collide_14times);
6529         ESTAT_ADD(tx_collide_15times);
6530         ESTAT_ADD(tx_ucast_packets);
6531         ESTAT_ADD(tx_mcast_packets);
6532         ESTAT_ADD(tx_bcast_packets);
6533         ESTAT_ADD(tx_carrier_sense_errors);
6534         ESTAT_ADD(tx_discards);
6535         ESTAT_ADD(tx_errors);
6536
6537         ESTAT_ADD(dma_writeq_full);
6538         ESTAT_ADD(dma_write_prioq_full);
6539         ESTAT_ADD(rxbds_empty);
6540         ESTAT_ADD(rx_discards);
6541         ESTAT_ADD(rx_errors);
6542         ESTAT_ADD(rx_threshold_hit);
6543
6544         ESTAT_ADD(dma_readq_full);
6545         ESTAT_ADD(dma_read_prioq_full);
6546         ESTAT_ADD(tx_comp_queue_full);
6547
6548         ESTAT_ADD(ring_set_send_prod_index);
6549         ESTAT_ADD(ring_status_update);
6550         ESTAT_ADD(nic_irqs);
6551         ESTAT_ADD(nic_avoided_irqs);
6552         ESTAT_ADD(nic_tx_threshold_hit);
6553
6554         return estats;
6555 }
6556
6557 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6558 {
6559         struct tg3 *tp = netdev_priv(dev);
6560         struct net_device_stats *stats = &tp->net_stats;
6561         struct net_device_stats *old_stats = &tp->net_stats_prev;
6562         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6563
6564         if (!hw_stats)
6565                 return old_stats;
6566
6567         stats->rx_packets = old_stats->rx_packets +
6568                 get_stat64(&hw_stats->rx_ucast_packets) +
6569                 get_stat64(&hw_stats->rx_mcast_packets) +
6570                 get_stat64(&hw_stats->rx_bcast_packets);
6571
6572         stats->tx_packets = old_stats->tx_packets +
6573                 get_stat64(&hw_stats->tx_ucast_packets) +
6574                 get_stat64(&hw_stats->tx_mcast_packets) +
6575                 get_stat64(&hw_stats->tx_bcast_packets);
6576
6577         stats->rx_bytes = old_stats->rx_bytes +
6578                 get_stat64(&hw_stats->rx_octets);
6579         stats->tx_bytes = old_stats->tx_bytes +
6580                 get_stat64(&hw_stats->tx_octets);
6581
6582         stats->rx_errors = old_stats->rx_errors +
6583                 get_stat64(&hw_stats->rx_errors) +
6584                 get_stat64(&hw_stats->rx_discards);
6585         stats->tx_errors = old_stats->tx_errors +
6586                 get_stat64(&hw_stats->tx_errors) +
6587                 get_stat64(&hw_stats->tx_mac_errors) +
6588                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6589                 get_stat64(&hw_stats->tx_discards);
6590
6591         stats->multicast = old_stats->multicast +
6592                 get_stat64(&hw_stats->rx_mcast_packets);
6593         stats->collisions = old_stats->collisions +
6594                 get_stat64(&hw_stats->tx_collisions);
6595
6596         stats->rx_length_errors = old_stats->rx_length_errors +
6597                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6598                 get_stat64(&hw_stats->rx_undersize_packets);
6599
6600         stats->rx_over_errors = old_stats->rx_over_errors +
6601                 get_stat64(&hw_stats->rxbds_empty);
6602         stats->rx_frame_errors = old_stats->rx_frame_errors +
6603                 get_stat64(&hw_stats->rx_align_errors);
6604         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6605                 get_stat64(&hw_stats->tx_discards);
6606         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6607                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6608
6609         stats->rx_crc_errors = old_stats->rx_crc_errors +
6610                 calc_crc_errors(tp);
6611
6612         return stats;
6613 }
6614
6615 static inline u32 calc_crc(unsigned char *buf, int len)
6616 {
6617         u32 reg;
6618         u32 tmp;
6619         int j, k;
6620
6621         reg = 0xffffffff;
6622
6623         for (j = 0; j < len; j++) {
6624                 reg ^= buf[j];
6625
6626                 for (k = 0; k < 8; k++) {
6627                         tmp = reg & 0x01;
6628
6629                         reg >>= 1;
6630
6631                         if (tmp) {
6632                                 reg ^= 0xedb88320;
6633                         }
6634                 }
6635         }
6636
6637         return ~reg;
6638 }
6639
6640 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
6641 {
6642         /* accept or reject all multicast frames */
6643         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
6644         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
6645         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
6646         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
6647 }
6648
6649 static void __tg3_set_rx_mode(struct net_device *dev)
6650 {
6651         struct tg3 *tp = netdev_priv(dev);
6652         u32 rx_mode;
6653
6654         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
6655                                   RX_MODE_KEEP_VLAN_TAG);
6656
6657         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
6658          * flag clear.
6659          */
6660 #if TG3_VLAN_TAG_USED
6661         if (!tp->vlgrp &&
6662             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6663                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6664 #else
6665         /* By definition, VLAN is disabled always in this
6666          * case.
6667          */
6668         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
6669                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
6670 #endif
6671
6672         if (dev->flags & IFF_PROMISC) {
6673                 /* Promiscuous mode. */
6674                 rx_mode |= RX_MODE_PROMISC;
6675         } else if (dev->flags & IFF_ALLMULTI) {
6676                 /* Accept all multicast. */
6677                 tg3_set_multi (tp, 1);
6678         } else if (dev->mc_count < 1) {
6679                 /* Reject all multicast. */
6680                 tg3_set_multi (tp, 0);
6681         } else {
6682                 /* Accept one or more multicast(s). */
6683                 struct dev_mc_list *mclist;
6684                 unsigned int i;
6685                 u32 mc_filter[4] = { 0, };
6686                 u32 regidx;
6687                 u32 bit;
6688                 u32 crc;
6689
6690                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
6691                      i++, mclist = mclist->next) {
6692
6693                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
6694                         bit = ~crc & 0x7f;
6695                         regidx = (bit & 0x60) >> 5;
6696                         bit &= 0x1f;
6697                         mc_filter[regidx] |= (1 << bit);
6698                 }
6699
6700                 tw32(MAC_HASH_REG_0, mc_filter[0]);
6701                 tw32(MAC_HASH_REG_1, mc_filter[1]);
6702                 tw32(MAC_HASH_REG_2, mc_filter[2]);
6703                 tw32(MAC_HASH_REG_3, mc_filter[3]);
6704         }
6705
6706         if (rx_mode != tp->rx_mode) {
6707                 tp->rx_mode = rx_mode;
6708                 tw32_f(MAC_RX_MODE, rx_mode);
6709                 udelay(10);
6710         }
6711 }
6712
6713 static void tg3_set_rx_mode(struct net_device *dev)
6714 {
6715         struct tg3 *tp = netdev_priv(dev);
6716
6717         spin_lock_irq(&tp->lock);
6718         spin_lock(&tp->tx_lock);
6719         __tg3_set_rx_mode(dev);
6720         spin_unlock(&tp->tx_lock);
6721         spin_unlock_irq(&tp->lock);
6722 }
6723
6724 #define TG3_REGDUMP_LEN         (32 * 1024)
6725
6726 static int tg3_get_regs_len(struct net_device *dev)
6727 {
6728         return TG3_REGDUMP_LEN;
6729 }
6730
6731 static void tg3_get_regs(struct net_device *dev,
6732                 struct ethtool_regs *regs, void *_p)
6733 {
6734         u32 *p = _p;
6735         struct tg3 *tp = netdev_priv(dev);
6736         u8 *orig_p = _p;
6737         int i;
6738
6739         regs->version = 0;
6740
6741         memset(p, 0, TG3_REGDUMP_LEN);
6742
6743         spin_lock_irq(&tp->lock);
6744         spin_lock(&tp->tx_lock);
6745
6746 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
6747 #define GET_REG32_LOOP(base,len)                \
6748 do {    p = (u32 *)(orig_p + (base));           \
6749         for (i = 0; i < len; i += 4)            \
6750                 __GET_REG32((base) + i);        \
6751 } while (0)
6752 #define GET_REG32_1(reg)                        \
6753 do {    p = (u32 *)(orig_p + (reg));            \
6754         __GET_REG32((reg));                     \
6755 } while (0)
6756
6757         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
6758         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
6759         GET_REG32_LOOP(MAC_MODE, 0x4f0);
6760         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
6761         GET_REG32_1(SNDDATAC_MODE);
6762         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
6763         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
6764         GET_REG32_1(SNDBDC_MODE);
6765         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
6766         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
6767         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
6768         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
6769         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
6770         GET_REG32_1(RCVDCC_MODE);
6771         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
6772         GET_REG32_LOOP(RCVCC_MODE, 0x14);
6773         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
6774         GET_REG32_1(MBFREE_MODE);
6775         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
6776         GET_REG32_LOOP(MEMARB_MODE, 0x10);
6777         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
6778         GET_REG32_LOOP(RDMAC_MODE, 0x08);
6779         GET_REG32_LOOP(WDMAC_MODE, 0x08);
6780         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
6781         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
6782         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
6783         GET_REG32_LOOP(FTQ_RESET, 0x120);
6784         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
6785         GET_REG32_1(DMAC_MODE);
6786         GET_REG32_LOOP(GRC_MODE, 0x4c);
6787         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6788                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
6789
6790 #undef __GET_REG32
6791 #undef GET_REG32_LOOP
6792 #undef GET_REG32_1
6793
6794         spin_unlock(&tp->tx_lock);
6795         spin_unlock_irq(&tp->lock);
6796 }
6797
6798 static int tg3_get_eeprom_len(struct net_device *dev)
6799 {
6800         struct tg3 *tp = netdev_priv(dev);
6801
6802         return tp->nvram_size;
6803 }
6804
6805 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
6806
6807 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6808 {
6809         struct tg3 *tp = netdev_priv(dev);
6810         int ret;
6811         u8  *pd;
6812         u32 i, offset, len, val, b_offset, b_count;
6813
6814         offset = eeprom->offset;
6815         len = eeprom->len;
6816         eeprom->len = 0;
6817
6818         eeprom->magic = TG3_EEPROM_MAGIC;
6819
6820         if (offset & 3) {
6821                 /* adjustments to start on required 4 byte boundary */
6822                 b_offset = offset & 3;
6823                 b_count = 4 - b_offset;
6824                 if (b_count > len) {
6825                         /* i.e. offset=1 len=2 */
6826                         b_count = len;
6827                 }
6828                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
6829                 if (ret)
6830                         return ret;
6831                 val = cpu_to_le32(val);
6832                 memcpy(data, ((char*)&val) + b_offset, b_count);
6833                 len -= b_count;
6834                 offset += b_count;
6835                 eeprom->len += b_count;
6836         }
6837
6838         /* read bytes upto the last 4 byte boundary */
6839         pd = &data[eeprom->len];
6840         for (i = 0; i < (len - (len & 3)); i += 4) {
6841                 ret = tg3_nvram_read(tp, offset + i, &val);
6842                 if (ret) {
6843                         eeprom->len += i;
6844                         return ret;
6845                 }
6846                 val = cpu_to_le32(val);
6847                 memcpy(pd + i, &val, 4);
6848         }
6849         eeprom->len += i;
6850
6851         if (len & 3) {
6852                 /* read last bytes not ending on 4 byte boundary */
6853                 pd = &data[eeprom->len];
6854                 b_count = len & 3;
6855                 b_offset = offset + len - b_count;
6856                 ret = tg3_nvram_read(tp, b_offset, &val);
6857                 if (ret)
6858                         return ret;
6859                 val = cpu_to_le32(val);
6860                 memcpy(pd, ((char*)&val), b_count);
6861                 eeprom->len += b_count;
6862         }
6863         return 0;
6864 }
6865
6866 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
6867
6868 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
6869 {
6870         struct tg3 *tp = netdev_priv(dev);
6871         int ret;
6872         u32 offset, len, b_offset, odd_len, start, end;
6873         u8 *buf;
6874
6875         if (eeprom->magic != TG3_EEPROM_MAGIC)
6876                 return -EINVAL;
6877
6878         offset = eeprom->offset;
6879         len = eeprom->len;
6880
6881         if ((b_offset = (offset & 3))) {
6882                 /* adjustments to start on required 4 byte boundary */
6883                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
6884                 if (ret)
6885                         return ret;
6886                 start = cpu_to_le32(start);
6887                 len += b_offset;
6888                 offset &= ~3;
6889                 if (len < 4)
6890                         len = 4;
6891         }
6892
6893         odd_len = 0;
6894         if (len & 3) {
6895                 /* adjustments to end on required 4 byte boundary */
6896                 odd_len = 1;
6897                 len = (len + 3) & ~3;
6898                 ret = tg3_nvram_read(tp, offset+len-4, &end);
6899                 if (ret)
6900                         return ret;
6901                 end = cpu_to_le32(end);
6902         }
6903
6904         buf = data;
6905         if (b_offset || odd_len) {
6906                 buf = kmalloc(len, GFP_KERNEL);
6907                 if (buf == 0)
6908                         return -ENOMEM;
6909                 if (b_offset)
6910                         memcpy(buf, &start, 4);
6911                 if (odd_len)
6912                         memcpy(buf+len-4, &end, 4);
6913                 memcpy(buf + b_offset, data, eeprom->len);
6914         }
6915
6916         ret = tg3_nvram_write_block(tp, offset, len, buf);
6917
6918         if (buf != data)
6919                 kfree(buf);
6920
6921         return ret;
6922 }
6923
6924 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6925 {
6926         struct tg3 *tp = netdev_priv(dev);
6927
6928         cmd->supported = (SUPPORTED_Autoneg);
6929
6930         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
6931                 cmd->supported |= (SUPPORTED_1000baseT_Half |
6932                                    SUPPORTED_1000baseT_Full);
6933
6934         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES))
6935                 cmd->supported |= (SUPPORTED_100baseT_Half |
6936                                   SUPPORTED_100baseT_Full |
6937                                   SUPPORTED_10baseT_Half |
6938                                   SUPPORTED_10baseT_Full |
6939                                   SUPPORTED_MII);
6940         else
6941                 cmd->supported |= SUPPORTED_FIBRE;
6942
6943         cmd->advertising = tp->link_config.advertising;
6944         if (netif_running(dev)) {
6945                 cmd->speed = tp->link_config.active_speed;
6946                 cmd->duplex = tp->link_config.active_duplex;
6947         }
6948         cmd->port = 0;
6949         cmd->phy_address = PHY_ADDR;
6950         cmd->transceiver = 0;
6951         cmd->autoneg = tp->link_config.autoneg;
6952         cmd->maxtxpkt = 0;
6953         cmd->maxrxpkt = 0;
6954         return 0;
6955 }
6956
6957 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6958 {
6959         struct tg3 *tp = netdev_priv(dev);
6960
6961         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6962                 /* These are the only valid advertisement bits allowed.  */
6963                 if (cmd->autoneg == AUTONEG_ENABLE &&
6964                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
6965                                           ADVERTISED_1000baseT_Full |
6966                                           ADVERTISED_Autoneg |
6967                                           ADVERTISED_FIBRE)))
6968                         return -EINVAL;
6969         }
6970
6971         spin_lock_irq(&tp->lock);
6972         spin_lock(&tp->tx_lock);
6973
6974         tp->link_config.autoneg = cmd->autoneg;
6975         if (cmd->autoneg == AUTONEG_ENABLE) {
6976                 tp->link_config.advertising = cmd->advertising;
6977                 tp->link_config.speed = SPEED_INVALID;
6978                 tp->link_config.duplex = DUPLEX_INVALID;
6979         } else {
6980                 tp->link_config.advertising = 0;
6981                 tp->link_config.speed = cmd->speed;
6982                 tp->link_config.duplex = cmd->duplex;
6983         }
6984
6985         if (netif_running(dev))
6986                 tg3_setup_phy(tp, 1);
6987
6988         spin_unlock(&tp->tx_lock);
6989         spin_unlock_irq(&tp->lock);
6990
6991         return 0;
6992 }
6993
6994 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6995 {
6996         struct tg3 *tp = netdev_priv(dev);
6997
6998         strcpy(info->driver, DRV_MODULE_NAME);
6999         strcpy(info->version, DRV_MODULE_VERSION);
7000         strcpy(info->bus_info, pci_name(tp->pdev));
7001 }
7002
7003 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7004 {
7005         struct tg3 *tp = netdev_priv(dev);
7006
7007         wol->supported = WAKE_MAGIC;
7008         wol->wolopts = 0;
7009         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7010                 wol->wolopts = WAKE_MAGIC;
7011         memset(&wol->sopass, 0, sizeof(wol->sopass));
7012 }
7013
7014 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7015 {
7016         struct tg3 *tp = netdev_priv(dev);
7017
7018         if (wol->wolopts & ~WAKE_MAGIC)
7019                 return -EINVAL;
7020         if ((wol->wolopts & WAKE_MAGIC) &&
7021             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7022             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7023                 return -EINVAL;
7024
7025         spin_lock_irq(&tp->lock);
7026         if (wol->wolopts & WAKE_MAGIC)
7027                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7028         else
7029                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7030         spin_unlock_irq(&tp->lock);
7031
7032         return 0;
7033 }
7034
7035 static u32 tg3_get_msglevel(struct net_device *dev)
7036 {
7037         struct tg3 *tp = netdev_priv(dev);
7038         return tp->msg_enable;
7039 }
7040
7041 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7042 {
7043         struct tg3 *tp = netdev_priv(dev);
7044         tp->msg_enable = value;
7045 }
7046
7047 #if TG3_TSO_SUPPORT != 0
7048 static int tg3_set_tso(struct net_device *dev, u32 value)
7049 {
7050         struct tg3 *tp = netdev_priv(dev);
7051
7052         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7053                 if (value)
7054                         return -EINVAL;
7055                 return 0;
7056         }
7057         return ethtool_op_set_tso(dev, value);
7058 }
7059 #endif
7060
7061 static int tg3_nway_reset(struct net_device *dev)
7062 {
7063         struct tg3 *tp = netdev_priv(dev);
7064         u32 bmcr;
7065         int r;
7066
7067         if (!netif_running(dev))
7068                 return -EAGAIN;
7069
7070         spin_lock_irq(&tp->lock);
7071         r = -EINVAL;
7072         tg3_readphy(tp, MII_BMCR, &bmcr);
7073         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7074             (bmcr & BMCR_ANENABLE)) {
7075                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
7076                 r = 0;
7077         }
7078         spin_unlock_irq(&tp->lock);
7079
7080         return r;
7081 }
7082
7083 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7084 {
7085         struct tg3 *tp = netdev_priv(dev);
7086
7087         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7088         ering->rx_mini_max_pending = 0;
7089         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7090
7091         ering->rx_pending = tp->rx_pending;
7092         ering->rx_mini_pending = 0;
7093         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7094         ering->tx_pending = tp->tx_pending;
7095 }
7096
7097 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7098 {
7099         struct tg3 *tp = netdev_priv(dev);
7100
7101         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7102             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7103             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7104                 return -EINVAL;
7105
7106         if (netif_running(dev))
7107                 tg3_netif_stop(tp);
7108
7109         spin_lock_irq(&tp->lock);
7110         spin_lock(&tp->tx_lock);
7111
7112         tp->rx_pending = ering->rx_pending;
7113
7114         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7115             tp->rx_pending > 63)
7116                 tp->rx_pending = 63;
7117         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7118         tp->tx_pending = ering->tx_pending;
7119
7120         if (netif_running(dev)) {
7121                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7122                 tg3_init_hw(tp);
7123                 tg3_netif_start(tp);
7124         }
7125
7126         spin_unlock(&tp->tx_lock);
7127         spin_unlock_irq(&tp->lock);
7128
7129         return 0;
7130 }
7131
7132 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7133 {
7134         struct tg3 *tp = netdev_priv(dev);
7135
7136         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7137         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7138         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7139 }
7140
7141 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7142 {
7143         struct tg3 *tp = netdev_priv(dev);
7144
7145         if (netif_running(dev))
7146                 tg3_netif_stop(tp);
7147
7148         spin_lock_irq(&tp->lock);
7149         spin_lock(&tp->tx_lock);
7150         if (epause->autoneg)
7151                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7152         else
7153                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7154         if (epause->rx_pause)
7155                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7156         else
7157                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7158         if (epause->tx_pause)
7159                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7160         else
7161                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7162
7163         if (netif_running(dev)) {
7164                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7165                 tg3_init_hw(tp);
7166                 tg3_netif_start(tp);
7167         }
7168         spin_unlock(&tp->tx_lock);
7169         spin_unlock_irq(&tp->lock);
7170
7171         return 0;
7172 }
7173
7174 static u32 tg3_get_rx_csum(struct net_device *dev)
7175 {
7176         struct tg3 *tp = netdev_priv(dev);
7177         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7178 }
7179
7180 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7181 {
7182         struct tg3 *tp = netdev_priv(dev);
7183
7184         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7185                 if (data != 0)
7186                         return -EINVAL;
7187                 return 0;
7188         }
7189
7190         spin_lock_irq(&tp->lock);
7191         if (data)
7192                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7193         else
7194                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7195         spin_unlock_irq(&tp->lock);
7196
7197         return 0;
7198 }
7199
7200 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7201 {
7202         struct tg3 *tp = netdev_priv(dev);
7203
7204         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7205                 if (data != 0)
7206                         return -EINVAL;
7207                 return 0;
7208         }
7209
7210         if (data)
7211                 dev->features |= NETIF_F_IP_CSUM;
7212         else
7213                 dev->features &= ~NETIF_F_IP_CSUM;
7214
7215         return 0;
7216 }
7217
7218 static int tg3_get_stats_count (struct net_device *dev)
7219 {
7220         return TG3_NUM_STATS;
7221 }
7222
7223 static int tg3_get_test_count (struct net_device *dev)
7224 {
7225         return TG3_NUM_TEST;
7226 }
7227
7228 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7229 {
7230         switch (stringset) {
7231         case ETH_SS_STATS:
7232                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7233                 break;
7234         case ETH_SS_TEST:
7235                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7236                 break;
7237         default:
7238                 WARN_ON(1);     /* we need a WARN() */
7239                 break;
7240         }
7241 }
7242
7243 static void tg3_get_ethtool_stats (struct net_device *dev,
7244                                    struct ethtool_stats *estats, u64 *tmp_stats)
7245 {
7246         struct tg3 *tp = netdev_priv(dev);
7247         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7248 }
7249
7250 #define NVRAM_TEST_SIZE 0x100
7251
7252 static int tg3_test_nvram(struct tg3 *tp)
7253 {
7254         u32 *buf, csum;
7255         int i, j, err = 0;
7256
7257         buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7258         if (buf == NULL)
7259                 return -ENOMEM;
7260
7261         for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7262                 u32 val;
7263
7264                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7265                         break;
7266                 buf[j] = cpu_to_le32(val);
7267         }
7268         if (i < NVRAM_TEST_SIZE)
7269                 goto out;
7270
7271         err = -EIO;
7272         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7273                 goto out;
7274
7275         /* Bootstrap checksum at offset 0x10 */
7276         csum = calc_crc((unsigned char *) buf, 0x10);
7277         if(csum != cpu_to_le32(buf[0x10/4]))
7278                 goto out;
7279
7280         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7281         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7282         if (csum != cpu_to_le32(buf[0xfc/4]))
7283                  goto out;
7284
7285         err = 0;
7286
7287 out:
7288         kfree(buf);
7289         return err;
7290 }
7291
7292 #define TG3_SERDES_TIMEOUT_SEC  2
7293 #define TG3_COPPER_TIMEOUT_SEC  6
7294
7295 static int tg3_test_link(struct tg3 *tp)
7296 {
7297         int i, max;
7298
7299         if (!netif_running(tp->dev))
7300                 return -ENODEV;
7301
7302         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7303                 max = TG3_SERDES_TIMEOUT_SEC;
7304         else
7305                 max = TG3_COPPER_TIMEOUT_SEC;
7306
7307         for (i = 0; i < max; i++) {
7308                 if (netif_carrier_ok(tp->dev))
7309                         return 0;
7310
7311                 if (msleep_interruptible(1000))
7312                         break;
7313         }
7314
7315         return -EIO;
7316 }
7317
7318 /* Only test the commonly used registers */
7319 static int tg3_test_registers(struct tg3 *tp)
7320 {
7321         int i, is_5705;
7322         u32 offset, read_mask, write_mask, val, save_val, read_val;
7323         static struct {
7324                 u16 offset;
7325                 u16 flags;
7326 #define TG3_FL_5705     0x1
7327 #define TG3_FL_NOT_5705 0x2
7328 #define TG3_FL_NOT_5788 0x4
7329                 u32 read_mask;
7330                 u32 write_mask;
7331         } reg_tbl[] = {
7332                 /* MAC Control Registers */
7333                 { MAC_MODE, TG3_FL_NOT_5705,
7334                         0x00000000, 0x00ef6f8c },
7335                 { MAC_MODE, TG3_FL_5705,
7336                         0x00000000, 0x01ef6b8c },
7337                 { MAC_STATUS, TG3_FL_NOT_5705,
7338                         0x03800107, 0x00000000 },
7339                 { MAC_STATUS, TG3_FL_5705,
7340                         0x03800100, 0x00000000 },
7341                 { MAC_ADDR_0_HIGH, 0x0000,
7342                         0x00000000, 0x0000ffff },
7343                 { MAC_ADDR_0_LOW, 0x0000,
7344                         0x00000000, 0xffffffff },
7345                 { MAC_RX_MTU_SIZE, 0x0000,
7346                         0x00000000, 0x0000ffff },
7347                 { MAC_TX_MODE, 0x0000,
7348                         0x00000000, 0x00000070 },
7349                 { MAC_TX_LENGTHS, 0x0000,
7350                         0x00000000, 0x00003fff },
7351                 { MAC_RX_MODE, TG3_FL_NOT_5705,
7352                         0x00000000, 0x000007fc },
7353                 { MAC_RX_MODE, TG3_FL_5705,
7354                         0x00000000, 0x000007dc },
7355                 { MAC_HASH_REG_0, 0x0000,
7356                         0x00000000, 0xffffffff },
7357                 { MAC_HASH_REG_1, 0x0000,
7358                         0x00000000, 0xffffffff },
7359                 { MAC_HASH_REG_2, 0x0000,
7360                         0x00000000, 0xffffffff },
7361                 { MAC_HASH_REG_3, 0x0000,
7362                         0x00000000, 0xffffffff },
7363
7364                 /* Receive Data and Receive BD Initiator Control Registers. */
7365                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7366                         0x00000000, 0xffffffff },
7367                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7368                         0x00000000, 0xffffffff },
7369                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7370                         0x00000000, 0x00000003 },
7371                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7372                         0x00000000, 0xffffffff },
7373                 { RCVDBDI_STD_BD+0, 0x0000,
7374                         0x00000000, 0xffffffff },
7375                 { RCVDBDI_STD_BD+4, 0x0000,
7376                         0x00000000, 0xffffffff },
7377                 { RCVDBDI_STD_BD+8, 0x0000,
7378                         0x00000000, 0xffff0002 },
7379                 { RCVDBDI_STD_BD+0xc, 0x0000,
7380                         0x00000000, 0xffffffff },
7381
7382                 /* Receive BD Initiator Control Registers. */
7383                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7384                         0x00000000, 0xffffffff },
7385                 { RCVBDI_STD_THRESH, TG3_FL_5705,
7386                         0x00000000, 0x000003ff },
7387                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7388                         0x00000000, 0xffffffff },
7389
7390                 /* Host Coalescing Control Registers. */
7391                 { HOSTCC_MODE, TG3_FL_NOT_5705,
7392                         0x00000000, 0x00000004 },
7393                 { HOSTCC_MODE, TG3_FL_5705,
7394                         0x00000000, 0x000000f6 },
7395                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7396                         0x00000000, 0xffffffff },
7397                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7398                         0x00000000, 0x000003ff },
7399                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7400                         0x00000000, 0xffffffff },
7401                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7402                         0x00000000, 0x000003ff },
7403                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7404                         0x00000000, 0xffffffff },
7405                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7406                         0x00000000, 0x000000ff },
7407                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7408                         0x00000000, 0xffffffff },
7409                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7410                         0x00000000, 0x000000ff },
7411                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7412                         0x00000000, 0xffffffff },
7413                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7414                         0x00000000, 0xffffffff },
7415                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7416                         0x00000000, 0xffffffff },
7417                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7418                         0x00000000, 0x000000ff },
7419                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7420                         0x00000000, 0xffffffff },
7421                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7422                         0x00000000, 0x000000ff },
7423                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7424                         0x00000000, 0xffffffff },
7425                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7426                         0x00000000, 0xffffffff },
7427                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7428                         0x00000000, 0xffffffff },
7429                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7430                         0x00000000, 0xffffffff },
7431                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7432                         0x00000000, 0xffffffff },
7433                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7434                         0xffffffff, 0x00000000 },
7435                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7436                         0xffffffff, 0x00000000 },
7437
7438                 /* Buffer Manager Control Registers. */
7439                 { BUFMGR_MB_POOL_ADDR, 0x0000,
7440                         0x00000000, 0x007fff80 },
7441                 { BUFMGR_MB_POOL_SIZE, 0x0000,
7442                         0x00000000, 0x007fffff },
7443                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7444                         0x00000000, 0x0000003f },
7445                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7446                         0x00000000, 0x000001ff },
7447                 { BUFMGR_MB_HIGH_WATER, 0x0000,
7448                         0x00000000, 0x000001ff },
7449                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7450                         0xffffffff, 0x00000000 },
7451                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7452                         0xffffffff, 0x00000000 },
7453
7454                 /* Mailbox Registers */
7455                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7456                         0x00000000, 0x000001ff },
7457                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7458                         0x00000000, 0x000001ff },
7459                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7460                         0x00000000, 0x000007ff },
7461                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7462                         0x00000000, 0x000001ff },
7463
7464                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7465         };
7466
7467         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7468                 is_5705 = 1;
7469         else
7470                 is_5705 = 0;
7471
7472         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7473                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7474                         continue;
7475
7476                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7477                         continue;
7478
7479                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7480                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
7481                         continue;
7482
7483                 offset = (u32) reg_tbl[i].offset;
7484                 read_mask = reg_tbl[i].read_mask;
7485                 write_mask = reg_tbl[i].write_mask;
7486
7487                 /* Save the original register content */
7488                 save_val = tr32(offset);
7489
7490                 /* Determine the read-only value. */
7491                 read_val = save_val & read_mask;
7492
7493                 /* Write zero to the register, then make sure the read-only bits
7494                  * are not changed and the read/write bits are all zeros.
7495                  */
7496                 tw32(offset, 0);
7497
7498                 val = tr32(offset);
7499
7500                 /* Test the read-only and read/write bits. */
7501                 if (((val & read_mask) != read_val) || (val & write_mask))
7502                         goto out;
7503
7504                 /* Write ones to all the bits defined by RdMask and WrMask, then
7505                  * make sure the read-only bits are not changed and the
7506                  * read/write bits are all ones.
7507                  */
7508                 tw32(offset, read_mask | write_mask);
7509
7510                 val = tr32(offset);
7511
7512                 /* Test the read-only bits. */
7513                 if ((val & read_mask) != read_val)
7514                         goto out;
7515
7516                 /* Test the read/write bits. */
7517                 if ((val & write_mask) != write_mask)
7518                         goto out;
7519
7520                 tw32(offset, save_val);
7521         }
7522
7523         return 0;
7524
7525 out:
7526         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7527         tw32(offset, save_val);
7528         return -EIO;
7529 }
7530
7531 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7532 {
7533         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7534         int i;
7535         u32 j;
7536
7537         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7538                 for (j = 0; j < len; j += 4) {
7539                         u32 val;
7540
7541                         tg3_write_mem(tp, offset + j, test_pattern[i]);
7542                         tg3_read_mem(tp, offset + j, &val);
7543                         if (val != test_pattern[i])
7544                                 return -EIO;
7545                 }
7546         }
7547         return 0;
7548 }
7549
7550 static int tg3_test_memory(struct tg3 *tp)
7551 {
7552         static struct mem_entry {
7553                 u32 offset;
7554                 u32 len;
7555         } mem_tbl_570x[] = {
7556                 { 0x00000000, 0x01000},
7557                 { 0x00002000, 0x1c000},
7558                 { 0xffffffff, 0x00000}
7559         }, mem_tbl_5705[] = {
7560                 { 0x00000100, 0x0000c},
7561                 { 0x00000200, 0x00008},
7562                 { 0x00000b50, 0x00400},
7563                 { 0x00004000, 0x00800},
7564                 { 0x00006000, 0x01000},
7565                 { 0x00008000, 0x02000},
7566                 { 0x00010000, 0x0e000},
7567                 { 0xffffffff, 0x00000}
7568         };
7569         struct mem_entry *mem_tbl;
7570         int err = 0;
7571         int i;
7572
7573         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7574                 mem_tbl = mem_tbl_5705;
7575         else
7576                 mem_tbl = mem_tbl_570x;
7577
7578         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7579                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7580                     mem_tbl[i].len)) != 0)
7581                         break;
7582         }
7583
7584         return err;
7585 }
7586
7587 static int tg3_test_loopback(struct tg3 *tp)
7588 {
7589         u32 mac_mode, send_idx, rx_start_idx, rx_idx, tx_idx, opaque_key;
7590         u32 desc_idx;
7591         struct sk_buff *skb, *rx_skb;
7592         u8 *tx_data;
7593         dma_addr_t map;
7594         int num_pkts, tx_len, rx_len, i, err;
7595         struct tg3_rx_buffer_desc *desc;
7596
7597         if (!netif_running(tp->dev))
7598                 return -ENODEV;
7599
7600         err = -EIO;
7601
7602         tg3_abort_hw(tp, 1);
7603
7604         /* Clearing this flag to keep interrupts disabled */
7605         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7606         tg3_reset_hw(tp);
7607
7608         mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7609                    MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7610                    MAC_MODE_PORT_MODE_GMII;
7611         tw32(MAC_MODE, mac_mode);
7612
7613         tx_len = 1514;
7614         skb = dev_alloc_skb(tx_len);
7615         tx_data = skb_put(skb, tx_len);
7616         memcpy(tx_data, tp->dev->dev_addr, 6);
7617         memset(tx_data + 6, 0x0, 8);
7618
7619         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7620
7621         for (i = 14; i < tx_len; i++)
7622                 tx_data[i] = (u8) (i & 0xff);
7623
7624         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7625
7626         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7627              HOSTCC_MODE_NOW);
7628
7629         udelay(10);
7630
7631         rx_start_idx = tp->hw_status->idx[0].rx_producer;
7632
7633         send_idx = 0;
7634         num_pkts = 0;
7635
7636         tg3_set_txd(tp, send_idx, map, tx_len, 0, 1);
7637
7638         send_idx++;
7639         num_pkts++;
7640
7641         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
7642         tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
7643
7644         udelay(10);
7645
7646         for (i = 0; i < 10; i++) {
7647                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7648                        HOSTCC_MODE_NOW);
7649
7650                 udelay(10);
7651
7652                 tx_idx = tp->hw_status->idx[0].tx_consumer;
7653                 rx_idx = tp->hw_status->idx[0].rx_producer;
7654                 if ((tx_idx == send_idx) &&
7655                     (rx_idx == (rx_start_idx + num_pkts)))
7656                         break;
7657         }
7658
7659         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
7660         dev_kfree_skb(skb);
7661
7662         if (tx_idx != send_idx)
7663                 goto out;
7664
7665         if (rx_idx != rx_start_idx + num_pkts)
7666                 goto out;
7667
7668         desc = &tp->rx_rcb[rx_start_idx];
7669         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
7670         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
7671         if (opaque_key != RXD_OPAQUE_RING_STD)
7672                 goto out;
7673
7674         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
7675             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
7676                 goto out;
7677
7678         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
7679         if (rx_len != tx_len)
7680                 goto out;
7681
7682         rx_skb = tp->rx_std_buffers[desc_idx].skb;
7683
7684         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
7685         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
7686
7687         for (i = 14; i < tx_len; i++) {
7688                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
7689                         goto out;
7690         }
7691         err = 0;
7692
7693         /* tg3_free_rings will unmap and free the rx_skb */
7694 out:
7695         return err;
7696 }
7697
7698 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
7699                           u64 *data)
7700 {
7701         struct tg3 *tp = netdev_priv(dev);
7702
7703         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
7704
7705         if (tg3_test_nvram(tp) != 0) {
7706                 etest->flags |= ETH_TEST_FL_FAILED;
7707                 data[0] = 1;
7708         }
7709         if (tg3_test_link(tp) != 0) {
7710                 etest->flags |= ETH_TEST_FL_FAILED;
7711                 data[1] = 1;
7712         }
7713         if (etest->flags & ETH_TEST_FL_OFFLINE) {
7714                 if (netif_running(dev))
7715                         tg3_netif_stop(tp);
7716
7717                 spin_lock_irq(&tp->lock);
7718                 spin_lock(&tp->tx_lock);
7719
7720                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
7721                 tg3_nvram_lock(tp);
7722                 tg3_halt_cpu(tp, RX_CPU_BASE);
7723                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7724                         tg3_halt_cpu(tp, TX_CPU_BASE);
7725                 tg3_nvram_unlock(tp);
7726
7727                 if (tg3_test_registers(tp) != 0) {
7728                         etest->flags |= ETH_TEST_FL_FAILED;
7729                         data[2] = 1;
7730                 }
7731                 if (tg3_test_memory(tp) != 0) {
7732                         etest->flags |= ETH_TEST_FL_FAILED;
7733                         data[3] = 1;
7734                 }
7735                 if (tg3_test_loopback(tp) != 0) {
7736                         etest->flags |= ETH_TEST_FL_FAILED;
7737                         data[4] = 1;
7738                 }
7739
7740                 spin_unlock(&tp->tx_lock);
7741                 spin_unlock_irq(&tp->lock);
7742                 if (tg3_test_interrupt(tp) != 0) {
7743                         etest->flags |= ETH_TEST_FL_FAILED;
7744                         data[5] = 1;
7745                 }
7746                 spin_lock_irq(&tp->lock);
7747                 spin_lock(&tp->tx_lock);
7748
7749                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7750                 if (netif_running(dev)) {
7751                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7752                         tg3_init_hw(tp);
7753                         tg3_netif_start(tp);
7754                 }
7755                 spin_unlock(&tp->tx_lock);
7756                 spin_unlock_irq(&tp->lock);
7757         }
7758 }
7759
7760 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7761 {
7762         struct mii_ioctl_data *data = if_mii(ifr);
7763         struct tg3 *tp = netdev_priv(dev);
7764         int err;
7765
7766         switch(cmd) {
7767         case SIOCGMIIPHY:
7768                 data->phy_id = PHY_ADDR;
7769
7770                 /* fallthru */
7771         case SIOCGMIIREG: {
7772                 u32 mii_regval;
7773
7774                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7775                         break;                  /* We have no PHY */
7776
7777                 spin_lock_irq(&tp->lock);
7778                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7779                 spin_unlock_irq(&tp->lock);
7780
7781                 data->val_out = mii_regval;
7782
7783                 return err;
7784         }
7785
7786         case SIOCSMIIREG:
7787                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7788                         break;                  /* We have no PHY */
7789
7790                 if (!capable(CAP_NET_ADMIN))
7791                         return -EPERM;
7792
7793                 spin_lock_irq(&tp->lock);
7794                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7795                 spin_unlock_irq(&tp->lock);
7796
7797                 return err;
7798
7799         default:
7800                 /* do nothing */
7801                 break;
7802         }
7803         return -EOPNOTSUPP;
7804 }
7805
7806 #if TG3_VLAN_TAG_USED
7807 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7808 {
7809         struct tg3 *tp = netdev_priv(dev);
7810
7811         spin_lock_irq(&tp->lock);
7812         spin_lock(&tp->tx_lock);
7813
7814         tp->vlgrp = grp;
7815
7816         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7817         __tg3_set_rx_mode(dev);
7818
7819         spin_unlock(&tp->tx_lock);
7820         spin_unlock_irq(&tp->lock);
7821 }
7822
7823 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7824 {
7825         struct tg3 *tp = netdev_priv(dev);
7826
7827         spin_lock_irq(&tp->lock);
7828         spin_lock(&tp->tx_lock);
7829         if (tp->vlgrp)
7830                 tp->vlgrp->vlan_devices[vid] = NULL;
7831         spin_unlock(&tp->tx_lock);
7832         spin_unlock_irq(&tp->lock);
7833 }
7834 #endif
7835
7836 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7837 {
7838         struct tg3 *tp = netdev_priv(dev);
7839
7840         memcpy(ec, &tp->coal, sizeof(*ec));
7841         return 0;
7842 }
7843
7844 static struct ethtool_ops tg3_ethtool_ops = {
7845         .get_settings           = tg3_get_settings,
7846         .set_settings           = tg3_set_settings,
7847         .get_drvinfo            = tg3_get_drvinfo,
7848         .get_regs_len           = tg3_get_regs_len,
7849         .get_regs               = tg3_get_regs,
7850         .get_wol                = tg3_get_wol,
7851         .set_wol                = tg3_set_wol,
7852         .get_msglevel           = tg3_get_msglevel,
7853         .set_msglevel           = tg3_set_msglevel,
7854         .nway_reset             = tg3_nway_reset,
7855         .get_link               = ethtool_op_get_link,
7856         .get_eeprom_len         = tg3_get_eeprom_len,
7857         .get_eeprom             = tg3_get_eeprom,
7858         .set_eeprom             = tg3_set_eeprom,
7859         .get_ringparam          = tg3_get_ringparam,
7860         .set_ringparam          = tg3_set_ringparam,
7861         .get_pauseparam         = tg3_get_pauseparam,
7862         .set_pauseparam         = tg3_set_pauseparam,
7863         .get_rx_csum            = tg3_get_rx_csum,
7864         .set_rx_csum            = tg3_set_rx_csum,
7865         .get_tx_csum            = ethtool_op_get_tx_csum,
7866         .set_tx_csum            = tg3_set_tx_csum,
7867         .get_sg                 = ethtool_op_get_sg,
7868         .set_sg                 = ethtool_op_set_sg,
7869 #if TG3_TSO_SUPPORT != 0
7870         .get_tso                = ethtool_op_get_tso,
7871         .set_tso                = tg3_set_tso,
7872 #endif
7873         .self_test_count        = tg3_get_test_count,
7874         .self_test              = tg3_self_test,
7875         .get_strings            = tg3_get_strings,
7876         .get_stats_count        = tg3_get_stats_count,
7877         .get_ethtool_stats      = tg3_get_ethtool_stats,
7878         .get_coalesce           = tg3_get_coalesce,
7879 };
7880
7881 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
7882 {
7883         u32 cursize, val;
7884
7885         tp->nvram_size = EEPROM_CHIP_SIZE;
7886
7887         if (tg3_nvram_read(tp, 0, &val) != 0)
7888                 return;
7889
7890         if (swab32(val) != TG3_EEPROM_MAGIC)
7891                 return;
7892
7893         /*
7894          * Size the chip by reading offsets at increasing powers of two.
7895          * When we encounter our validation signature, we know the addressing
7896          * has wrapped around, and thus have our chip size.
7897          */
7898         cursize = 0x800;
7899
7900         while (cursize < tp->nvram_size) {
7901                 if (tg3_nvram_read(tp, cursize, &val) != 0)
7902                         return;
7903
7904                 if (swab32(val) == TG3_EEPROM_MAGIC)
7905                         break;
7906
7907                 cursize <<= 1;
7908         }
7909
7910         tp->nvram_size = cursize;
7911 }
7912
7913 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
7914 {
7915         u32 val;
7916
7917         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
7918                 if (val != 0) {
7919                         tp->nvram_size = (val >> 16) * 1024;
7920                         return;
7921                 }
7922         }
7923         tp->nvram_size = 0x20000;
7924 }
7925
7926 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7927 {
7928         u32 nvcfg1;
7929
7930         nvcfg1 = tr32(NVRAM_CFG1);
7931         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
7932                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
7933         }
7934         else {
7935                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
7936                 tw32(NVRAM_CFG1, nvcfg1);
7937         }
7938
7939         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7940                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7941                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7942                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7943                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7944                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7945                                 break;
7946                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
7947                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7948                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
7949                                 break;
7950                         case FLASH_VENDOR_ATMEL_EEPROM:
7951                                 tp->nvram_jedecnum = JEDEC_ATMEL;
7952                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
7953                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7954                                 break;
7955                         case FLASH_VENDOR_ST:
7956                                 tp->nvram_jedecnum = JEDEC_ST;
7957                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
7958                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7959                                 break;
7960                         case FLASH_VENDOR_SAIFUN:
7961                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
7962                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
7963                                 break;
7964                         case FLASH_VENDOR_SST_SMALL:
7965                         case FLASH_VENDOR_SST_LARGE:
7966                                 tp->nvram_jedecnum = JEDEC_SST;
7967                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
7968                                 break;
7969                 }
7970         }
7971         else {
7972                 tp->nvram_jedecnum = JEDEC_ATMEL;
7973                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
7974                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7975         }
7976 }
7977
7978 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7979 {
7980         u32 nvcfg1;
7981
7982         nvcfg1 = tr32(NVRAM_CFG1);
7983
7984         /* NVRAM protection for TPM */
7985         if (nvcfg1 & (1 << 27))
7986                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7987
7988         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7989                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7990                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
7991                         tp->nvram_jedecnum = JEDEC_ATMEL;
7992                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7993                         break;
7994                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
7995                         tp->nvram_jedecnum = JEDEC_ATMEL;
7996                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
7997                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
7998                         break;
7999                 case FLASH_5752VENDOR_ST_M45PE10:
8000                 case FLASH_5752VENDOR_ST_M45PE20:
8001                 case FLASH_5752VENDOR_ST_M45PE40:
8002                         tp->nvram_jedecnum = JEDEC_ST;
8003                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8004                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8005                         break;
8006         }
8007
8008         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8009                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8010                         case FLASH_5752PAGE_SIZE_256:
8011                                 tp->nvram_pagesize = 256;
8012                                 break;
8013                         case FLASH_5752PAGE_SIZE_512:
8014                                 tp->nvram_pagesize = 512;
8015                                 break;
8016                         case FLASH_5752PAGE_SIZE_1K:
8017                                 tp->nvram_pagesize = 1024;
8018                                 break;
8019                         case FLASH_5752PAGE_SIZE_2K:
8020                                 tp->nvram_pagesize = 2048;
8021                                 break;
8022                         case FLASH_5752PAGE_SIZE_4K:
8023                                 tp->nvram_pagesize = 4096;
8024                                 break;
8025                         case FLASH_5752PAGE_SIZE_264:
8026                                 tp->nvram_pagesize = 264;
8027                                 break;
8028                 }
8029         }
8030         else {
8031                 /* For eeprom, set pagesize to maximum eeprom size */
8032                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8033
8034                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8035                 tw32(NVRAM_CFG1, nvcfg1);
8036         }
8037 }
8038
8039 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8040 static void __devinit tg3_nvram_init(struct tg3 *tp)
8041 {
8042         int j;
8043
8044         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8045                 return;
8046
8047         tw32_f(GRC_EEPROM_ADDR,
8048              (EEPROM_ADDR_FSM_RESET |
8049               (EEPROM_DEFAULT_CLOCK_PERIOD <<
8050                EEPROM_ADDR_CLKPERD_SHIFT)));
8051
8052         /* XXX schedule_timeout() ... */
8053         for (j = 0; j < 100; j++)
8054                 udelay(10);
8055
8056         /* Enable seeprom accesses. */
8057         tw32_f(GRC_LOCAL_CTRL,
8058              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8059         udelay(100);
8060
8061         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8062             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8063                 tp->tg3_flags |= TG3_FLAG_NVRAM;
8064
8065                 tg3_enable_nvram_access(tp);
8066
8067                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8068                         tg3_get_5752_nvram_info(tp);
8069                 else
8070                         tg3_get_nvram_info(tp);
8071
8072                 tg3_get_nvram_size(tp);
8073
8074                 tg3_disable_nvram_access(tp);
8075
8076         } else {
8077                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8078
8079                 tg3_get_eeprom_size(tp);
8080         }
8081 }
8082
8083 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8084                                         u32 offset, u32 *val)
8085 {
8086         u32 tmp;
8087         int i;
8088
8089         if (offset > EEPROM_ADDR_ADDR_MASK ||
8090             (offset % 4) != 0)
8091                 return -EINVAL;
8092
8093         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8094                                         EEPROM_ADDR_DEVID_MASK |
8095                                         EEPROM_ADDR_READ);
8096         tw32(GRC_EEPROM_ADDR,
8097              tmp |
8098              (0 << EEPROM_ADDR_DEVID_SHIFT) |
8099              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8100               EEPROM_ADDR_ADDR_MASK) |
8101              EEPROM_ADDR_READ | EEPROM_ADDR_START);
8102
8103         for (i = 0; i < 10000; i++) {
8104                 tmp = tr32(GRC_EEPROM_ADDR);
8105
8106                 if (tmp & EEPROM_ADDR_COMPLETE)
8107                         break;
8108                 udelay(100);
8109         }
8110         if (!(tmp & EEPROM_ADDR_COMPLETE))
8111                 return -EBUSY;
8112
8113         *val = tr32(GRC_EEPROM_DATA);
8114         return 0;
8115 }
8116
8117 #define NVRAM_CMD_TIMEOUT 10000
8118
8119 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8120 {
8121         int i;
8122
8123         tw32(NVRAM_CMD, nvram_cmd);
8124         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8125                 udelay(10);
8126                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8127                         udelay(10);
8128                         break;
8129                 }
8130         }
8131         if (i == NVRAM_CMD_TIMEOUT) {
8132                 return -EBUSY;
8133         }
8134         return 0;
8135 }
8136
8137 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8138 {
8139         int ret;
8140
8141         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8142                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8143                 return -EINVAL;
8144         }
8145
8146         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8147                 return tg3_nvram_read_using_eeprom(tp, offset, val);
8148
8149         if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8150                 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8151                 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8152
8153                 offset = ((offset / tp->nvram_pagesize) <<
8154                           ATMEL_AT45DB0X1B_PAGE_POS) +
8155                         (offset % tp->nvram_pagesize);
8156         }
8157
8158         if (offset > NVRAM_ADDR_MSK)
8159                 return -EINVAL;
8160
8161         tg3_nvram_lock(tp);
8162
8163         tg3_enable_nvram_access(tp);
8164
8165         tw32(NVRAM_ADDR, offset);
8166         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8167                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8168
8169         if (ret == 0)
8170                 *val = swab32(tr32(NVRAM_RDDATA));
8171
8172         tg3_nvram_unlock(tp);
8173
8174         tg3_disable_nvram_access(tp);
8175
8176         return ret;
8177 }
8178
8179 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8180                                     u32 offset, u32 len, u8 *buf)
8181 {
8182         int i, j, rc = 0;
8183         u32 val;
8184
8185         for (i = 0; i < len; i += 4) {
8186                 u32 addr, data;
8187
8188                 addr = offset + i;
8189
8190                 memcpy(&data, buf + i, 4);
8191
8192                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8193
8194                 val = tr32(GRC_EEPROM_ADDR);
8195                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8196
8197                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8198                         EEPROM_ADDR_READ);
8199                 tw32(GRC_EEPROM_ADDR, val |
8200                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
8201                         (addr & EEPROM_ADDR_ADDR_MASK) |
8202                         EEPROM_ADDR_START |
8203                         EEPROM_ADDR_WRITE);
8204
8205                 for (j = 0; j < 10000; j++) {
8206                         val = tr32(GRC_EEPROM_ADDR);
8207
8208                         if (val & EEPROM_ADDR_COMPLETE)
8209                                 break;
8210                         udelay(100);
8211                 }
8212                 if (!(val & EEPROM_ADDR_COMPLETE)) {
8213                         rc = -EBUSY;
8214                         break;
8215                 }
8216         }
8217
8218         return rc;
8219 }
8220
8221 /* offset and length are dword aligned */
8222 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8223                 u8 *buf)
8224 {
8225         int ret = 0;
8226         u32 pagesize = tp->nvram_pagesize;
8227         u32 pagemask = pagesize - 1;
8228         u32 nvram_cmd;
8229         u8 *tmp;
8230
8231         tmp = kmalloc(pagesize, GFP_KERNEL);
8232         if (tmp == NULL)
8233                 return -ENOMEM;
8234
8235         while (len) {
8236                 int j;
8237                 u32 phy_addr, page_off, size;
8238
8239                 phy_addr = offset & ~pagemask;
8240
8241                 for (j = 0; j < pagesize; j += 4) {
8242                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
8243                                                 (u32 *) (tmp + j))))
8244                                 break;
8245                 }
8246                 if (ret)
8247                         break;
8248
8249                 page_off = offset & pagemask;
8250                 size = pagesize;
8251                 if (len < size)
8252                         size = len;
8253
8254                 len -= size;
8255
8256                 memcpy(tmp + page_off, buf, size);
8257
8258                 offset = offset + (pagesize - page_off);
8259
8260                 tg3_enable_nvram_access(tp);
8261
8262                 /*
8263                  * Before we can erase the flash page, we need
8264                  * to issue a special "write enable" command.
8265                  */
8266                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8267
8268                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8269                         break;
8270
8271                 /* Erase the target page */
8272                 tw32(NVRAM_ADDR, phy_addr);
8273
8274                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8275                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8276
8277                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8278                         break;
8279
8280                 /* Issue another write enable to start the write. */
8281                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8282
8283                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8284                         break;
8285
8286                 for (j = 0; j < pagesize; j += 4) {
8287                         u32 data;
8288
8289                         data = *((u32 *) (tmp + j));
8290                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
8291
8292                         tw32(NVRAM_ADDR, phy_addr + j);
8293
8294                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8295                                 NVRAM_CMD_WR;
8296
8297                         if (j == 0)
8298                                 nvram_cmd |= NVRAM_CMD_FIRST;
8299                         else if (j == (pagesize - 4))
8300                                 nvram_cmd |= NVRAM_CMD_LAST;
8301
8302                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8303                                 break;
8304                 }
8305                 if (ret)
8306                         break;
8307         }
8308
8309         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8310         tg3_nvram_exec_cmd(tp, nvram_cmd);
8311
8312         kfree(tmp);
8313
8314         return ret;
8315 }
8316
8317 /* offset and length are dword aligned */
8318 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8319                 u8 *buf)
8320 {
8321         int i, ret = 0;
8322
8323         for (i = 0; i < len; i += 4, offset += 4) {
8324                 u32 data, page_off, phy_addr, nvram_cmd;
8325
8326                 memcpy(&data, buf + i, 4);
8327                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8328
8329                 page_off = offset % tp->nvram_pagesize;
8330
8331                 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8332                         (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8333
8334                         phy_addr = ((offset / tp->nvram_pagesize) <<
8335                                     ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8336                 }
8337                 else {
8338                         phy_addr = offset;
8339                 }
8340
8341                 tw32(NVRAM_ADDR, phy_addr);
8342
8343                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8344
8345                 if ((page_off == 0) || (i == 0))
8346                         nvram_cmd |= NVRAM_CMD_FIRST;
8347                 else if (page_off == (tp->nvram_pagesize - 4))
8348                         nvram_cmd |= NVRAM_CMD_LAST;
8349
8350                 if (i == (len - 4))
8351                         nvram_cmd |= NVRAM_CMD_LAST;
8352
8353                 if ((tp->nvram_jedecnum == JEDEC_ST) &&
8354                         (nvram_cmd & NVRAM_CMD_FIRST)) {
8355
8356                         if ((ret = tg3_nvram_exec_cmd(tp,
8357                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8358                                 NVRAM_CMD_DONE)))
8359
8360                                 break;
8361                 }
8362                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8363                         /* We always do complete word writes to eeprom. */
8364                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8365                 }
8366
8367                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8368                         break;
8369         }
8370         return ret;
8371 }
8372
8373 /* offset and length are dword aligned */
8374 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8375 {
8376         int ret;
8377
8378         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8379                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8380                 return -EINVAL;
8381         }
8382
8383         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8384                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8385                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
8386                 udelay(40);
8387         }
8388
8389         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8390                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8391         }
8392         else {
8393                 u32 grc_mode;
8394
8395                 tg3_nvram_lock(tp);
8396
8397                 tg3_enable_nvram_access(tp);
8398                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8399                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8400                         tw32(NVRAM_WRITE1, 0x406);
8401
8402                 grc_mode = tr32(GRC_MODE);
8403                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8404
8405                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8406                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8407
8408                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
8409                                 buf);
8410                 }
8411                 else {
8412                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8413                                 buf);
8414                 }
8415
8416                 grc_mode = tr32(GRC_MODE);
8417                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8418
8419                 tg3_disable_nvram_access(tp);
8420                 tg3_nvram_unlock(tp);
8421         }
8422
8423         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8424                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8425                 udelay(40);
8426         }
8427
8428         return ret;
8429 }
8430
8431 struct subsys_tbl_ent {
8432         u16 subsys_vendor, subsys_devid;
8433         u32 phy_id;
8434 };
8435
8436 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8437         /* Broadcom boards. */
8438         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8439         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8440         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8441         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
8442         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8443         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8444         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
8445         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8446         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8447         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8448         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8449
8450         /* 3com boards. */
8451         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8452         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8453         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
8454         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8455         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8456
8457         /* DELL boards. */
8458         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8459         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8460         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8461         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8462
8463         /* Compaq boards. */
8464         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8465         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8466         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
8467         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8468         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8469
8470         /* IBM boards. */
8471         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8472 };
8473
8474 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8475 {
8476         int i;
8477
8478         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8479                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8480                      tp->pdev->subsystem_vendor) &&
8481                     (subsys_id_to_phy_id[i].subsys_devid ==
8482                      tp->pdev->subsystem_device))
8483                         return &subsys_id_to_phy_id[i];
8484         }
8485         return NULL;
8486 }
8487
8488 /* Since this function may be called in D3-hot power state during
8489  * tg3_init_one(), only config cycles are allowed.
8490  */
8491 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
8492 {
8493         u32 val;
8494
8495         /* Make sure register accesses (indirect or otherwise)
8496          * will function correctly.
8497          */
8498         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8499                                tp->misc_host_ctrl);
8500
8501         tp->phy_id = PHY_ID_INVALID;
8502         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8503
8504         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8505         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8506                 u32 nic_cfg, led_cfg;
8507                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
8508                 int eeprom_phy_serdes = 0;
8509
8510                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8511                 tp->nic_sram_data_cfg = nic_cfg;
8512
8513                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
8514                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
8515                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8516                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8517                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
8518                     (ver > 0) && (ver < 0x100))
8519                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
8520
8521                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
8522                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
8523                         eeprom_phy_serdes = 1;
8524
8525                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
8526                 if (nic_phy_id != 0) {
8527                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
8528                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
8529
8530                         eeprom_phy_id  = (id1 >> 16) << 10;
8531                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
8532                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
8533                 } else
8534                         eeprom_phy_id = 0;
8535
8536                 tp->phy_id = eeprom_phy_id;
8537                 if (eeprom_phy_serdes)
8538                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8539
8540                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8541                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
8542                                     SHASTA_EXT_LED_MODE_MASK);
8543                 else
8544                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
8545
8546                 switch (led_cfg) {
8547                 default:
8548                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
8549                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8550                         break;
8551
8552                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
8553                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8554                         break;
8555
8556                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
8557                         tp->led_ctrl = LED_CTRL_MODE_MAC;
8558                         break;
8559
8560                 case SHASTA_EXT_LED_SHARED:
8561                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
8562                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8563                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
8564                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8565                                                  LED_CTRL_MODE_PHY_2);
8566                         break;
8567
8568                 case SHASTA_EXT_LED_MAC:
8569                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
8570                         break;
8571
8572                 case SHASTA_EXT_LED_COMBO:
8573                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
8574                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
8575                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
8576                                                  LED_CTRL_MODE_PHY_2);
8577                         break;
8578
8579                 };
8580
8581                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8582                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
8583                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
8584                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
8585
8586                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
8587                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
8588                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
8589                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
8590
8591                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8592                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
8593                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8594                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
8595                 }
8596                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
8597                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
8598
8599                 if (cfg2 & (1 << 17))
8600                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
8601
8602                 /* serdes signal pre-emphasis in register 0x590 set by */
8603                 /* bootcode if bit 18 is set */
8604                 if (cfg2 & (1 << 18))
8605                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
8606         }
8607 }
8608
8609 static int __devinit tg3_phy_probe(struct tg3 *tp)
8610 {
8611         u32 hw_phy_id_1, hw_phy_id_2;
8612         u32 hw_phy_id, hw_phy_id_masked;
8613         int err;
8614
8615         /* Reading the PHY ID register can conflict with ASF
8616          * firwmare access to the PHY hardware.
8617          */
8618         err = 0;
8619         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
8620                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
8621         } else {
8622                 /* Now read the physical PHY_ID from the chip and verify
8623                  * that it is sane.  If it doesn't look good, we fall back
8624                  * to either the hard-coded table based PHY_ID and failing
8625                  * that the value found in the eeprom area.
8626                  */
8627                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
8628                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
8629
8630                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
8631                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
8632                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
8633
8634                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
8635         }
8636
8637         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
8638                 tp->phy_id = hw_phy_id;
8639                 if (hw_phy_id_masked == PHY_ID_BCM8002)
8640                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8641         } else {
8642                 if (tp->phy_id != PHY_ID_INVALID) {
8643                         /* Do nothing, phy ID already set up in
8644                          * tg3_get_eeprom_hw_cfg().
8645                          */
8646                 } else {
8647                         struct subsys_tbl_ent *p;
8648
8649                         /* No eeprom signature?  Try the hardcoded
8650                          * subsys device table.
8651                          */
8652                         p = lookup_by_subsys(tp);
8653                         if (!p)
8654                                 return -ENODEV;
8655
8656                         tp->phy_id = p->phy_id;
8657                         if (!tp->phy_id ||
8658                             tp->phy_id == PHY_ID_BCM8002)
8659                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
8660                 }
8661         }
8662
8663         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8664             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
8665                 u32 bmsr, adv_reg, tg3_ctrl;
8666
8667                 tg3_readphy(tp, MII_BMSR, &bmsr);
8668                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
8669                     (bmsr & BMSR_LSTATUS))
8670                         goto skip_phy_reset;
8671
8672                 err = tg3_phy_reset(tp);
8673                 if (err)
8674                         return err;
8675
8676                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
8677                            ADVERTISE_100HALF | ADVERTISE_100FULL |
8678                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
8679                 tg3_ctrl = 0;
8680                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
8681                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
8682                                     MII_TG3_CTRL_ADV_1000_FULL);
8683                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
8684                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
8685                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
8686                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
8687                 }
8688
8689                 if (!tg3_copper_is_advertising_all(tp)) {
8690                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8691
8692                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8693                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8694
8695                         tg3_writephy(tp, MII_BMCR,
8696                                      BMCR_ANENABLE | BMCR_ANRESTART);
8697                 }
8698                 tg3_phy_set_wirespeed(tp);
8699
8700                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
8701                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8702                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
8703         }
8704
8705 skip_phy_reset:
8706         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8707                 err = tg3_init_5401phy_dsp(tp);
8708                 if (err)
8709                         return err;
8710         }
8711
8712         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
8713                 err = tg3_init_5401phy_dsp(tp);
8714         }
8715
8716         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8717                 tp->link_config.advertising =
8718                         (ADVERTISED_1000baseT_Half |
8719                          ADVERTISED_1000baseT_Full |
8720                          ADVERTISED_Autoneg |
8721                          ADVERTISED_FIBRE);
8722         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8723                 tp->link_config.advertising &=
8724                         ~(ADVERTISED_1000baseT_Half |
8725                           ADVERTISED_1000baseT_Full);
8726
8727         return err;
8728 }
8729
8730 static void __devinit tg3_read_partno(struct tg3 *tp)
8731 {
8732         unsigned char vpd_data[256];
8733         int i;
8734
8735         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8736                 /* Sun decided not to put the necessary bits in the
8737                  * NVRAM of their onboard tg3 parts :(
8738                  */
8739                 strcpy(tp->board_part_number, "Sun 570X");
8740                 return;
8741         }
8742
8743         for (i = 0; i < 256; i += 4) {
8744                 u32 tmp;
8745
8746                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
8747                         goto out_not_found;
8748
8749                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
8750                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
8751                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
8752                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
8753         }
8754
8755         /* Now parse and find the part number. */
8756         for (i = 0; i < 256; ) {
8757                 unsigned char val = vpd_data[i];
8758                 int block_end;
8759
8760                 if (val == 0x82 || val == 0x91) {
8761                         i = (i + 3 +
8762                              (vpd_data[i + 1] +
8763                               (vpd_data[i + 2] << 8)));
8764                         continue;
8765                 }
8766
8767                 if (val != 0x90)
8768                         goto out_not_found;
8769
8770                 block_end = (i + 3 +
8771                              (vpd_data[i + 1] +
8772                               (vpd_data[i + 2] << 8)));
8773                 i += 3;
8774                 while (i < block_end) {
8775                         if (vpd_data[i + 0] == 'P' &&
8776                             vpd_data[i + 1] == 'N') {
8777                                 int partno_len = vpd_data[i + 2];
8778
8779                                 if (partno_len > 24)
8780                                         goto out_not_found;
8781
8782                                 memcpy(tp->board_part_number,
8783                                        &vpd_data[i + 3],
8784                                        partno_len);
8785
8786                                 /* Success. */
8787                                 return;
8788                         }
8789                 }
8790
8791                 /* Part number not found. */
8792                 goto out_not_found;
8793         }
8794
8795 out_not_found:
8796         strcpy(tp->board_part_number, "none");
8797 }
8798
8799 #ifdef CONFIG_SPARC64
8800 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
8801 {
8802         struct pci_dev *pdev = tp->pdev;
8803         struct pcidev_cookie *pcp = pdev->sysdata;
8804
8805         if (pcp != NULL) {
8806                 int node = pcp->prom_node;
8807                 u32 venid;
8808                 int err;
8809
8810                 err = prom_getproperty(node, "subsystem-vendor-id",
8811                                        (char *) &venid, sizeof(venid));
8812                 if (err == 0 || err == -1)
8813                         return 0;
8814                 if (venid == PCI_VENDOR_ID_SUN)
8815                         return 1;
8816         }
8817         return 0;
8818 }
8819 #endif
8820
8821 static int __devinit tg3_get_invariants(struct tg3 *tp)
8822 {
8823         static struct pci_device_id write_reorder_chipsets[] = {
8824                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8825                              PCI_DEVICE_ID_INTEL_82801AA_8) },
8826                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8827                              PCI_DEVICE_ID_INTEL_82801AB_8) },
8828                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8829                              PCI_DEVICE_ID_INTEL_82801BA_11) },
8830                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
8831                              PCI_DEVICE_ID_INTEL_82801BA_6) },
8832                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
8833                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
8834                 { },
8835         };
8836         u32 misc_ctrl_reg;
8837         u32 cacheline_sz_reg;
8838         u32 pci_state_reg, grc_misc_cfg;
8839         u32 val;
8840         u16 pci_cmd;
8841         int err;
8842
8843 #ifdef CONFIG_SPARC64
8844         if (tg3_is_sun_570X(tp))
8845                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
8846 #endif
8847
8848         /* If we have an AMD 762 or Intel ICH/ICH0/ICH2 chipset, write
8849          * reordering to the mailbox registers done by the host
8850          * controller can cause major troubles.  We read back from
8851          * every mailbox register write to force the writes to be
8852          * posted to the chip in order.
8853          */
8854         if (pci_dev_present(write_reorder_chipsets))
8855                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
8856
8857         /* Force memory write invalidate off.  If we leave it on,
8858          * then on 5700_BX chips we have to enable a workaround.
8859          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
8860          * to match the cacheline size.  The Broadcom driver have this
8861          * workaround but turns MWI off all the times so never uses
8862          * it.  This seems to suggest that the workaround is insufficient.
8863          */
8864         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8865         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
8866         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8867
8868         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
8869          * has the register indirect write enable bit set before
8870          * we try to access any of the MMIO registers.  It is also
8871          * critical that the PCI-X hw workaround situation is decided
8872          * before that as well.
8873          */
8874         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8875                               &misc_ctrl_reg);
8876
8877         tp->pci_chip_rev_id = (misc_ctrl_reg >>
8878                                MISC_HOST_CTRL_CHIPREV_SHIFT);
8879
8880         /* Wrong chip ID in 5752 A0. This code can be removed later
8881          * as A0 is not in production.
8882          */
8883         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8884                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8885
8886         /* Initialize misc host control in PCI block. */
8887         tp->misc_host_ctrl |= (misc_ctrl_reg &
8888                                MISC_HOST_CTRL_CHIPREV);
8889         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8890                                tp->misc_host_ctrl);
8891
8892         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8893                               &cacheline_sz_reg);
8894
8895         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
8896         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
8897         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
8898         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
8899
8900         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8901             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8902                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8903
8904         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
8905             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
8906                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
8907
8908         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8909                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
8910
8911         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
8912                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
8913
8914         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8915             tp->pci_lat_timer < 64) {
8916                 tp->pci_lat_timer = 64;
8917
8918                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
8919                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
8920                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
8921                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
8922
8923                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
8924                                        cacheline_sz_reg);
8925         }
8926
8927         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
8928                               &pci_state_reg);
8929
8930         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
8931                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
8932
8933                 /* If this is a 5700 BX chipset, and we are in PCI-X
8934                  * mode, enable register write workaround.
8935                  *
8936                  * The workaround is to use indirect register accesses
8937                  * for all chip writes not to mailbox registers.
8938                  */
8939                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
8940                         u32 pm_reg;
8941                         u16 pci_cmd;
8942
8943                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
8944
8945                         /* The chip can have it's power management PCI config
8946                          * space registers clobbered due to this bug.
8947                          * So explicitly force the chip into D0 here.
8948                          */
8949                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8950                                               &pm_reg);
8951                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
8952                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
8953                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
8954                                                pm_reg);
8955
8956                         /* Also, force SERR#/PERR# in PCI command. */
8957                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8958                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
8959                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8960                 }
8961         }
8962
8963         /* Back to back register writes can cause problems on this chip,
8964          * the workaround is to read back all reg writes except those to
8965          * mailbox regs.  See tg3_write_indirect_reg32().
8966          *
8967          * PCI Express 5750_A0 rev chips need this workaround too.
8968          */
8969         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
8970             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
8971              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
8972                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
8973
8974         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
8975                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
8976         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
8977                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
8978
8979         /* Chip-specific fixup from Broadcom driver */
8980         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
8981             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
8982                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
8983                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
8984         }
8985
8986         /* Get eeprom hw config before calling tg3_set_power_state().
8987          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
8988          * determined before calling tg3_set_power_state() so that
8989          * we know whether or not to switch out of Vaux power.
8990          * When the flag is set, it means that GPIO1 is used for eeprom
8991          * write protect and also implies that it is a LOM where GPIOs
8992          * are not used to switch power.
8993          */
8994         tg3_get_eeprom_hw_cfg(tp);
8995
8996         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
8997          * GPIO1 driven high will bring 5700's external PHY out of reset.
8998          * It is also used as eeprom write protect on LOMs.
8999          */
9000         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9001         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9002             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9003                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9004                                        GRC_LCLCTRL_GPIO_OUTPUT1);
9005         /* Unused GPIO3 must be driven as output on 5752 because there
9006          * are no pull-up resistors on unused GPIO pins.
9007          */
9008         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9009                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
9010
9011         /* Force the chip into D0. */
9012         err = tg3_set_power_state(tp, 0);
9013         if (err) {
9014                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9015                        pci_name(tp->pdev));
9016                 return err;
9017         }
9018
9019         /* 5700 B0 chips do not support checksumming correctly due
9020          * to hardware bugs.
9021          */
9022         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9023                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9024
9025         /* Pseudo-header checksum is done by hardware logic and not
9026          * the offload processers, so make the chip do the pseudo-
9027          * header checksums on receive.  For transmit it is more
9028          * convenient to do the pseudo-header checksum in software
9029          * as Linux does that on transmit for us in all cases.
9030          */
9031         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9032         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9033
9034         /* Derive initial jumbo mode from MTU assigned in
9035          * ether_setup() via the alloc_etherdev() call
9036          */
9037         if (tp->dev->mtu > ETH_DATA_LEN)
9038                 tp->tg3_flags |= TG3_FLAG_JUMBO_ENABLE;
9039
9040         /* Determine WakeOnLan speed to use. */
9041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9042             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9043             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9044             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9045                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9046         } else {
9047                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9048         }
9049
9050         /* A few boards don't want Ethernet@WireSpeed phy feature */
9051         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9052             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9053              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9054              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
9055                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9056
9057         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9058             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9059                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9060         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9061                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9062
9063         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9064                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9065
9066         tp->coalesce_mode = 0;
9067         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9068             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9069                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9070
9071         /* Initialize MAC MI mode, polling disabled. */
9072         tw32_f(MAC_MI_MODE, tp->mi_mode);
9073         udelay(80);
9074
9075         /* Initialize data/descriptor byte/word swapping. */
9076         val = tr32(GRC_MODE);
9077         val &= GRC_MODE_HOST_STACKUP;
9078         tw32(GRC_MODE, val | tp->grc_mode);
9079
9080         tg3_switch_clocks(tp);
9081
9082         /* Clear this out for sanity. */
9083         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9084
9085         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9086                               &pci_state_reg);
9087         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9088             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9089                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9090
9091                 if (chiprevid == CHIPREV_ID_5701_A0 ||
9092                     chiprevid == CHIPREV_ID_5701_B0 ||
9093                     chiprevid == CHIPREV_ID_5701_B2 ||
9094                     chiprevid == CHIPREV_ID_5701_B5) {
9095                         void __iomem *sram_base;
9096
9097                         /* Write some dummy words into the SRAM status block
9098                          * area, see if it reads back correctly.  If the return
9099                          * value is bad, force enable the PCIX workaround.
9100                          */
9101                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9102
9103                         writel(0x00000000, sram_base);
9104                         writel(0x00000000, sram_base + 4);
9105                         writel(0xffffffff, sram_base + 4);
9106                         if (readl(sram_base) != 0x00000000)
9107                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9108                 }
9109         }
9110
9111         udelay(50);
9112         tg3_nvram_init(tp);
9113
9114         grc_misc_cfg = tr32(GRC_MISC_CFG);
9115         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9116
9117         /* Broadcom's driver says that CIOBE multisplit has a bug */
9118 #if 0
9119         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9120             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9121                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9122                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9123         }
9124 #endif
9125         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9126             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9127              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9128                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9129
9130         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9131             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9132                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9133         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9134                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9135                                       HOSTCC_MODE_CLRTICK_TXBD);
9136
9137                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9138                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9139                                        tp->misc_host_ctrl);
9140         }
9141
9142         /* these are limited to 10/100 only */
9143         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9144              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9145             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9146              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9147              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9148               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9149               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9150             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9151              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9152               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9153                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9154
9155         err = tg3_phy_probe(tp);
9156         if (err) {
9157                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9158                        pci_name(tp->pdev), err);
9159                 /* ... but do not return immediately ... */
9160         }
9161
9162         tg3_read_partno(tp);
9163
9164         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9165                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9166         } else {
9167                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9168                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9169                 else
9170                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9171         }
9172
9173         /* 5700 {AX,BX} chips have a broken status block link
9174          * change bit implementation, so we must use the
9175          * status register in those cases.
9176          */
9177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9178                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9179         else
9180                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9181
9182         /* The led_ctrl is set during tg3_phy_probe, here we might
9183          * have to force the link status polling mechanism based
9184          * upon subsystem IDs.
9185          */
9186         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9187             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9188                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9189                                   TG3_FLAG_USE_LINKCHG_REG);
9190         }
9191
9192         /* For all SERDES we poll the MAC status register. */
9193         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9194                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9195         else
9196                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9197
9198         /* 5700 BX chips need to have their TX producer index mailboxes
9199          * written twice to workaround a bug.
9200          */
9201         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9202                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9203         else
9204                 tp->tg3_flags &= ~TG3_FLAG_TXD_MBOX_HWBUG;
9205
9206         /* It seems all chips can get confused if TX buffers
9207          * straddle the 4GB address boundary in some cases.
9208          */
9209         tp->dev->hard_start_xmit = tg3_start_xmit;
9210
9211         tp->rx_offset = 2;
9212         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9213             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9214                 tp->rx_offset = 0;
9215
9216         /* By default, disable wake-on-lan.  User can change this
9217          * using ETHTOOL_SWOL.
9218          */
9219         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9220
9221         return err;
9222 }
9223
9224 #ifdef CONFIG_SPARC64
9225 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9226 {
9227         struct net_device *dev = tp->dev;
9228         struct pci_dev *pdev = tp->pdev;
9229         struct pcidev_cookie *pcp = pdev->sysdata;
9230
9231         if (pcp != NULL) {
9232                 int node = pcp->prom_node;
9233
9234                 if (prom_getproplen(node, "local-mac-address") == 6) {
9235                         prom_getproperty(node, "local-mac-address",
9236                                          dev->dev_addr, 6);
9237                         return 0;
9238                 }
9239         }
9240         return -ENODEV;
9241 }
9242
9243 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9244 {
9245         struct net_device *dev = tp->dev;
9246
9247         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9248         return 0;
9249 }
9250 #endif
9251
9252 static int __devinit tg3_get_device_address(struct tg3 *tp)
9253 {
9254         struct net_device *dev = tp->dev;
9255         u32 hi, lo, mac_offset;
9256
9257 #ifdef CONFIG_SPARC64
9258         if (!tg3_get_macaddr_sparc(tp))
9259                 return 0;
9260 #endif
9261
9262         mac_offset = 0x7c;
9263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9264             !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {
9265                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9266                         mac_offset = 0xcc;
9267                 if (tg3_nvram_lock(tp))
9268                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9269                 else
9270                         tg3_nvram_unlock(tp);
9271         }
9272
9273         /* First try to get it from MAC address mailbox. */
9274         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9275         if ((hi >> 16) == 0x484b) {
9276                 dev->dev_addr[0] = (hi >>  8) & 0xff;
9277                 dev->dev_addr[1] = (hi >>  0) & 0xff;
9278
9279                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9280                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9281                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9282                 dev->dev_addr[4] = (lo >>  8) & 0xff;
9283                 dev->dev_addr[5] = (lo >>  0) & 0xff;
9284         }
9285         /* Next, try NVRAM. */
9286         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9287                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9288                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9289                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9290                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9291                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
9292                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
9293                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9294                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9295         }
9296         /* Finally just fetch it out of the MAC control regs. */
9297         else {
9298                 hi = tr32(MAC_ADDR_0_HIGH);
9299                 lo = tr32(MAC_ADDR_0_LOW);
9300
9301                 dev->dev_addr[5] = lo & 0xff;
9302                 dev->dev_addr[4] = (lo >> 8) & 0xff;
9303                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9304                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9305                 dev->dev_addr[1] = hi & 0xff;
9306                 dev->dev_addr[0] = (hi >> 8) & 0xff;
9307         }
9308
9309         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9310 #ifdef CONFIG_SPARC64
9311                 if (!tg3_get_default_macaddr_sparc(tp))
9312                         return 0;
9313 #endif
9314                 return -EINVAL;
9315         }
9316         return 0;
9317 }
9318
9319 #define BOUNDARY_SINGLE_CACHELINE       1
9320 #define BOUNDARY_MULTI_CACHELINE        2
9321
9322 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9323 {
9324         int cacheline_size;
9325         u8 byte;
9326         int goal;
9327
9328         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9329         if (byte == 0)
9330                 cacheline_size = 1024;
9331         else
9332                 cacheline_size = (int) byte * 4;
9333
9334         /* On 5703 and later chips, the boundary bits have no
9335          * effect.
9336          */
9337         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9338             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9339             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9340                 goto out;
9341
9342 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9343         goal = BOUNDARY_MULTI_CACHELINE;
9344 #else
9345 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9346         goal = BOUNDARY_SINGLE_CACHELINE;
9347 #else
9348         goal = 0;
9349 #endif
9350 #endif
9351
9352         if (!goal)
9353                 goto out;
9354
9355         /* PCI controllers on most RISC systems tend to disconnect
9356          * when a device tries to burst across a cache-line boundary.
9357          * Therefore, letting tg3 do so just wastes PCI bandwidth.
9358          *
9359          * Unfortunately, for PCI-E there are only limited
9360          * write-side controls for this, and thus for reads
9361          * we will still get the disconnects.  We'll also waste
9362          * these PCI cycles for both read and write for chips
9363          * other than 5700 and 5701 which do not implement the
9364          * boundary bits.
9365          */
9366         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9367             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9368                 switch (cacheline_size) {
9369                 case 16:
9370                 case 32:
9371                 case 64:
9372                 case 128:
9373                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9374                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9375                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9376                         } else {
9377                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9378                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9379                         }
9380                         break;
9381
9382                 case 256:
9383                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9384                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9385                         break;
9386
9387                 default:
9388                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9389                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9390                         break;
9391                 };
9392         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9393                 switch (cacheline_size) {
9394                 case 16:
9395                 case 32:
9396                 case 64:
9397                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9398                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9399                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9400                                 break;
9401                         }
9402                         /* fallthrough */
9403                 case 128:
9404                 default:
9405                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9406                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9407                         break;
9408                 };
9409         } else {
9410                 switch (cacheline_size) {
9411                 case 16:
9412                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9413                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9414                                         DMA_RWCTRL_WRITE_BNDRY_16);
9415                                 break;
9416                         }
9417                         /* fallthrough */
9418                 case 32:
9419                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9420                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9421                                         DMA_RWCTRL_WRITE_BNDRY_32);
9422                                 break;
9423                         }
9424                         /* fallthrough */
9425                 case 64:
9426                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9427                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9428                                         DMA_RWCTRL_WRITE_BNDRY_64);
9429                                 break;
9430                         }
9431                         /* fallthrough */
9432                 case 128:
9433                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
9434                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9435                                         DMA_RWCTRL_WRITE_BNDRY_128);
9436                                 break;
9437                         }
9438                         /* fallthrough */
9439                 case 256:
9440                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
9441                                 DMA_RWCTRL_WRITE_BNDRY_256);
9442                         break;
9443                 case 512:
9444                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
9445                                 DMA_RWCTRL_WRITE_BNDRY_512);
9446                         break;
9447                 case 1024:
9448                 default:
9449                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9450                                 DMA_RWCTRL_WRITE_BNDRY_1024);
9451                         break;
9452                 };
9453         }
9454
9455 out:
9456         return val;
9457 }
9458
9459 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
9460 {
9461         struct tg3_internal_buffer_desc test_desc;
9462         u32 sram_dma_descs;
9463         int i, ret;
9464
9465         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
9466
9467         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
9468         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
9469         tw32(RDMAC_STATUS, 0);
9470         tw32(WDMAC_STATUS, 0);
9471
9472         tw32(BUFMGR_MODE, 0);
9473         tw32(FTQ_RESET, 0);
9474
9475         test_desc.addr_hi = ((u64) buf_dma) >> 32;
9476         test_desc.addr_lo = buf_dma & 0xffffffff;
9477         test_desc.nic_mbuf = 0x00002100;
9478         test_desc.len = size;
9479
9480         /*
9481          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
9482          * the *second* time the tg3 driver was getting loaded after an
9483          * initial scan.
9484          *
9485          * Broadcom tells me:
9486          *   ...the DMA engine is connected to the GRC block and a DMA
9487          *   reset may affect the GRC block in some unpredictable way...
9488          *   The behavior of resets to individual blocks has not been tested.
9489          *
9490          * Broadcom noted the GRC reset will also reset all sub-components.
9491          */
9492         if (to_device) {
9493                 test_desc.cqid_sqid = (13 << 8) | 2;
9494
9495                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
9496                 udelay(40);
9497         } else {
9498                 test_desc.cqid_sqid = (16 << 8) | 7;
9499
9500                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
9501                 udelay(40);
9502         }
9503         test_desc.flags = 0x00000005;
9504
9505         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
9506                 u32 val;
9507
9508                 val = *(((u32 *)&test_desc) + i);
9509                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
9510                                        sram_dma_descs + (i * sizeof(u32)));
9511                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
9512         }
9513         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
9514
9515         if (to_device) {
9516                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
9517         } else {
9518                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
9519         }
9520
9521         ret = -ENODEV;
9522         for (i = 0; i < 40; i++) {
9523                 u32 val;
9524
9525                 if (to_device)
9526                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
9527                 else
9528                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
9529                 if ((val & 0xffff) == sram_dma_descs) {
9530                         ret = 0;
9531                         break;
9532                 }
9533
9534                 udelay(100);
9535         }
9536
9537         return ret;
9538 }
9539
9540 #define TEST_BUFFER_SIZE        0x2000
9541
9542 static int __devinit tg3_test_dma(struct tg3 *tp)
9543 {
9544         dma_addr_t buf_dma;
9545         u32 *buf, saved_dma_rwctrl;
9546         int ret;
9547
9548         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
9549         if (!buf) {
9550                 ret = -ENOMEM;
9551                 goto out_nofree;
9552         }
9553
9554         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
9555                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
9556
9557         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
9558
9559         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9560                 /* DMA read watermark not used on PCIE */
9561                 tp->dma_rwctrl |= 0x00180000;
9562         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
9563                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
9564                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
9565                         tp->dma_rwctrl |= 0x003f0000;
9566                 else
9567                         tp->dma_rwctrl |= 0x003f000f;
9568         } else {
9569                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9570                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9571                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
9572
9573                         if (ccval == 0x6 || ccval == 0x7)
9574                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
9575
9576                         /* Set bit 23 to enable PCIX hw bug fix */
9577                         tp->dma_rwctrl |= 0x009f0000;
9578                 } else {
9579                         tp->dma_rwctrl |= 0x001b000f;
9580                 }
9581         }
9582
9583         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
9584             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
9585                 tp->dma_rwctrl &= 0xfffffff0;
9586
9587         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9588             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
9589                 /* Remove this if it causes problems for some boards. */
9590                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
9591
9592                 /* On 5700/5701 chips, we need to set this bit.
9593                  * Otherwise the chip will issue cacheline transactions
9594                  * to streamable DMA memory with not all the byte
9595                  * enables turned on.  This is an error on several
9596                  * RISC PCI controllers, in particular sparc64.
9597                  *
9598                  * On 5703/5704 chips, this bit has been reassigned
9599                  * a different meaning.  In particular, it is used
9600                  * on those chips to enable a PCI-X workaround.
9601                  */
9602                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
9603         }
9604
9605         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9606
9607 #if 0
9608         /* Unneeded, already done by tg3_get_invariants.  */
9609         tg3_switch_clocks(tp);
9610 #endif
9611
9612         ret = 0;
9613         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9614             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
9615                 goto out;
9616
9617         /* It is best to perform DMA test with maximum write burst size
9618          * to expose the 5700/5701 write DMA bug.
9619          */
9620         saved_dma_rwctrl = tp->dma_rwctrl;
9621         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9622         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9623
9624         while (1) {
9625                 u32 *p = buf, i;
9626
9627                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
9628                         p[i] = i;
9629
9630                 /* Send the buffer to the chip. */
9631                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
9632                 if (ret) {
9633                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
9634                         break;
9635                 }
9636
9637 #if 0
9638                 /* validate data reached card RAM correctly. */
9639                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9640                         u32 val;
9641                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
9642                         if (le32_to_cpu(val) != p[i]) {
9643                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
9644                                 /* ret = -ENODEV here? */
9645                         }
9646                         p[i] = 0;
9647                 }
9648 #endif
9649                 /* Now read it back. */
9650                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
9651                 if (ret) {
9652                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
9653
9654                         break;
9655                 }
9656
9657                 /* Verify it. */
9658                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
9659                         if (p[i] == i)
9660                                 continue;
9661
9662                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9663                             DMA_RWCTRL_WRITE_BNDRY_16) {
9664                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9665                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9666                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9667                                 break;
9668                         } else {
9669                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
9670                                 ret = -ENODEV;
9671                                 goto out;
9672                         }
9673                 }
9674
9675                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
9676                         /* Success. */
9677                         ret = 0;
9678                         break;
9679                 }
9680         }
9681         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9682             DMA_RWCTRL_WRITE_BNDRY_16) {
9683                 /* DMA test passed without adjusting DMA boundary,
9684                  * just restore the calculated DMA boundary
9685                  */
9686                 tp->dma_rwctrl = saved_dma_rwctrl;
9687                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9688         }
9689
9690 out:
9691         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
9692 out_nofree:
9693         return ret;
9694 }
9695
9696 static void __devinit tg3_init_link_config(struct tg3 *tp)
9697 {
9698         tp->link_config.advertising =
9699                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
9700                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
9701                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
9702                  ADVERTISED_Autoneg | ADVERTISED_MII);
9703         tp->link_config.speed = SPEED_INVALID;
9704         tp->link_config.duplex = DUPLEX_INVALID;
9705         tp->link_config.autoneg = AUTONEG_ENABLE;
9706         netif_carrier_off(tp->dev);
9707         tp->link_config.active_speed = SPEED_INVALID;
9708         tp->link_config.active_duplex = DUPLEX_INVALID;
9709         tp->link_config.phy_is_low_power = 0;
9710         tp->link_config.orig_speed = SPEED_INVALID;
9711         tp->link_config.orig_duplex = DUPLEX_INVALID;
9712         tp->link_config.orig_autoneg = AUTONEG_INVALID;
9713 }
9714
9715 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9716 {
9717         tp->bufmgr_config.mbuf_read_dma_low_water =
9718                 DEFAULT_MB_RDMA_LOW_WATER;
9719         tp->bufmgr_config.mbuf_mac_rx_low_water =
9720                 DEFAULT_MB_MACRX_LOW_WATER;
9721         tp->bufmgr_config.mbuf_high_water =
9722                 DEFAULT_MB_HIGH_WATER;
9723
9724         tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9725                 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9726         tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9727                 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9728         tp->bufmgr_config.mbuf_high_water_jumbo =
9729                 DEFAULT_MB_HIGH_WATER_JUMBO;
9730
9731         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9732         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
9733 }
9734
9735 static char * __devinit tg3_phy_string(struct tg3 *tp)
9736 {
9737         switch (tp->phy_id & PHY_ID_MASK) {
9738         case PHY_ID_BCM5400:    return "5400";
9739         case PHY_ID_BCM5401:    return "5401";
9740         case PHY_ID_BCM5411:    return "5411";
9741         case PHY_ID_BCM5701:    return "5701";
9742         case PHY_ID_BCM5703:    return "5703";
9743         case PHY_ID_BCM5704:    return "5704";
9744         case PHY_ID_BCM5705:    return "5705";
9745         case PHY_ID_BCM5750:    return "5750";
9746         case PHY_ID_BCM5752:    return "5752";
9747         case PHY_ID_BCM8002:    return "8002/serdes";
9748         case 0:                 return "serdes";
9749         default:                return "unknown";
9750         };
9751 }
9752
9753 static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9754 {
9755         struct pci_dev *peer;
9756         unsigned int func, devnr = tp->pdev->devfn & ~7;
9757
9758         for (func = 0; func < 8; func++) {
9759                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
9760                 if (peer && peer != tp->pdev)
9761                         break;
9762                 pci_dev_put(peer);
9763         }
9764         if (!peer || peer == tp->pdev)
9765                 BUG();
9766
9767         /*
9768          * We don't need to keep the refcount elevated; there's no way
9769          * to remove one half of this device without removing the other
9770          */
9771         pci_dev_put(peer);
9772
9773         return peer;
9774 }
9775
9776 static void __devinit tg3_init_coal(struct tg3 *tp)
9777 {
9778         struct ethtool_coalesce *ec = &tp->coal;
9779
9780         memset(ec, 0, sizeof(*ec));
9781         ec->cmd = ETHTOOL_GCOALESCE;
9782         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9783         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9784         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9785         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9786         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9787         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9788         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9789         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9790         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9791
9792         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9793                                  HOSTCC_MODE_CLRTICK_TXBD)) {
9794                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9795                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9796                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9797                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9798         }
9799 }
9800
9801 static int __devinit tg3_init_one(struct pci_dev *pdev,
9802                                   const struct pci_device_id *ent)
9803 {
9804         static int tg3_version_printed = 0;
9805         unsigned long tg3reg_base, tg3reg_len;
9806         struct net_device *dev;
9807         struct tg3 *tp;
9808         int i, err, pci_using_dac, pm_cap;
9809
9810         if (tg3_version_printed++ == 0)
9811                 printk(KERN_INFO "%s", version);
9812
9813         err = pci_enable_device(pdev);
9814         if (err) {
9815                 printk(KERN_ERR PFX "Cannot enable PCI device, "
9816                        "aborting.\n");
9817                 return err;
9818         }
9819
9820         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9821                 printk(KERN_ERR PFX "Cannot find proper PCI device "
9822                        "base address, aborting.\n");
9823                 err = -ENODEV;
9824                 goto err_out_disable_pdev;
9825         }
9826
9827         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9828         if (err) {
9829                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
9830                        "aborting.\n");
9831                 goto err_out_disable_pdev;
9832         }
9833
9834         pci_set_master(pdev);
9835
9836         /* Find power-management capability. */
9837         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9838         if (pm_cap == 0) {
9839                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
9840                        "aborting.\n");
9841                 err = -EIO;
9842                 goto err_out_free_res;
9843         }
9844
9845         /* Configure DMA attributes. */
9846         err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
9847         if (!err) {
9848                 pci_using_dac = 1;
9849                 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
9850                 if (err < 0) {
9851                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
9852                                "for consistent allocations\n");
9853                         goto err_out_free_res;
9854                 }
9855         } else {
9856                 err = pci_set_dma_mask(pdev, 0xffffffffULL);
9857                 if (err) {
9858                         printk(KERN_ERR PFX "No usable DMA configuration, "
9859                                "aborting.\n");
9860                         goto err_out_free_res;
9861                 }
9862                 pci_using_dac = 0;
9863         }
9864
9865         tg3reg_base = pci_resource_start(pdev, 0);
9866         tg3reg_len = pci_resource_len(pdev, 0);
9867
9868         dev = alloc_etherdev(sizeof(*tp));
9869         if (!dev) {
9870                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
9871                 err = -ENOMEM;
9872                 goto err_out_free_res;
9873         }
9874
9875         SET_MODULE_OWNER(dev);
9876         SET_NETDEV_DEV(dev, &pdev->dev);
9877
9878         if (pci_using_dac)
9879                 dev->features |= NETIF_F_HIGHDMA;
9880         dev->features |= NETIF_F_LLTX;
9881 #if TG3_VLAN_TAG_USED
9882         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
9883         dev->vlan_rx_register = tg3_vlan_rx_register;
9884         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
9885 #endif
9886
9887         tp = netdev_priv(dev);
9888         tp->pdev = pdev;
9889         tp->dev = dev;
9890         tp->pm_cap = pm_cap;
9891         tp->mac_mode = TG3_DEF_MAC_MODE;
9892         tp->rx_mode = TG3_DEF_RX_MODE;
9893         tp->tx_mode = TG3_DEF_TX_MODE;
9894         tp->mi_mode = MAC_MI_MODE_BASE;
9895         if (tg3_debug > 0)
9896                 tp->msg_enable = tg3_debug;
9897         else
9898                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
9899
9900         /* The word/byte swap controls here control register access byte
9901          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
9902          * setting below.
9903          */
9904         tp->misc_host_ctrl =
9905                 MISC_HOST_CTRL_MASK_PCI_INT |
9906                 MISC_HOST_CTRL_WORD_SWAP |
9907                 MISC_HOST_CTRL_INDIR_ACCESS |
9908                 MISC_HOST_CTRL_PCISTATE_RW;
9909
9910         /* The NONFRM (non-frame) byte/word swap controls take effect
9911          * on descriptor entries, anything which isn't packet data.
9912          *
9913          * The StrongARM chips on the board (one for tx, one for rx)
9914          * are running in big-endian mode.
9915          */
9916         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
9917                         GRC_MODE_WSWAP_NONFRM_DATA);
9918 #ifdef __BIG_ENDIAN
9919         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
9920 #endif
9921         spin_lock_init(&tp->lock);
9922         spin_lock_init(&tp->tx_lock);
9923         spin_lock_init(&tp->indirect_lock);
9924         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
9925
9926         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
9927         if (tp->regs == 0UL) {
9928                 printk(KERN_ERR PFX "Cannot map device registers, "
9929                        "aborting.\n");
9930                 err = -ENOMEM;
9931                 goto err_out_free_dev;
9932         }
9933
9934         tg3_init_link_config(tp);
9935
9936         tg3_init_bufmgr_config(tp);
9937
9938         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
9939         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
9940         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
9941
9942         dev->open = tg3_open;
9943         dev->stop = tg3_close;
9944         dev->get_stats = tg3_get_stats;
9945         dev->set_multicast_list = tg3_set_rx_mode;
9946         dev->set_mac_address = tg3_set_mac_addr;
9947         dev->do_ioctl = tg3_ioctl;
9948         dev->tx_timeout = tg3_tx_timeout;
9949         dev->poll = tg3_poll;
9950         dev->ethtool_ops = &tg3_ethtool_ops;
9951         dev->weight = 64;
9952         dev->watchdog_timeo = TG3_TX_TIMEOUT;
9953         dev->change_mtu = tg3_change_mtu;
9954         dev->irq = pdev->irq;
9955 #ifdef CONFIG_NET_POLL_CONTROLLER
9956         dev->poll_controller = tg3_poll_controller;
9957 #endif
9958
9959         err = tg3_get_invariants(tp);
9960         if (err) {
9961                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
9962                        "aborting.\n");
9963                 goto err_out_iounmap;
9964         }
9965
9966         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9967                 tp->bufmgr_config.mbuf_read_dma_low_water =
9968                         DEFAULT_MB_RDMA_LOW_WATER_5705;
9969                 tp->bufmgr_config.mbuf_mac_rx_low_water =
9970                         DEFAULT_MB_MACRX_LOW_WATER_5705;
9971                 tp->bufmgr_config.mbuf_high_water =
9972                         DEFAULT_MB_HIGH_WATER_5705;
9973         }
9974
9975 #if TG3_TSO_SUPPORT != 0
9976         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
9977                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9978         }
9979         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9980             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9981             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
9982             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
9983                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9984         } else {
9985                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9986         }
9987
9988         /* TSO is off by default, user can enable using ethtool.  */
9989 #if 0
9990         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
9991                 dev->features |= NETIF_F_TSO;
9992 #endif
9993
9994 #endif
9995
9996         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
9997             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
9998             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
9999                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10000                 tp->rx_pending = 63;
10001         }
10002
10003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10004                 tp->pdev_peer = tg3_find_5704_peer(tp);
10005
10006         err = tg3_get_device_address(tp);
10007         if (err) {
10008                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10009                        "aborting.\n");
10010                 goto err_out_iounmap;
10011         }
10012
10013         /*
10014          * Reset chip in case UNDI or EFI driver did not shutdown
10015          * DMA self test will enable WDMAC and we'll see (spurious)
10016          * pending DMA on the PCI bus at that point.
10017          */
10018         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10019             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10020                 pci_save_state(tp->pdev);
10021                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10022                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10023         }
10024
10025         err = tg3_test_dma(tp);
10026         if (err) {
10027                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10028                 goto err_out_iounmap;
10029         }
10030
10031         /* Tigon3 can do ipv4 only... and some chips have buggy
10032          * checksumming.
10033          */
10034         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10035                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10036                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10037         } else
10038                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10039
10040         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10041                 dev->features &= ~NETIF_F_HIGHDMA;
10042
10043         /* flow control autonegotiation is default behavior */
10044         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10045
10046         tg3_init_coal(tp);
10047
10048         err = register_netdev(dev);
10049         if (err) {
10050                 printk(KERN_ERR PFX "Cannot register net device, "
10051                        "aborting.\n");
10052                 goto err_out_iounmap;
10053         }
10054
10055         pci_set_drvdata(pdev, dev);
10056
10057         /* Now that we have fully setup the chip, save away a snapshot
10058          * of the PCI config space.  We need to restore this after
10059          * GRC_MISC_CFG core clock resets and some resume events.
10060          */
10061         pci_save_state(tp->pdev);
10062
10063         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
10064                dev->name,
10065                tp->board_part_number,
10066                tp->pci_chip_rev_id,
10067                tg3_phy_string(tp),
10068                ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
10069                ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
10070                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
10071                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
10072                ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
10073                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10074
10075         for (i = 0; i < 6; i++)
10076                 printk("%2.2x%c", dev->dev_addr[i],
10077                        i == 5 ? '\n' : ':');
10078
10079         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10080                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10081                "TSOcap[%d] \n",
10082                dev->name,
10083                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10084                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10085                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10086                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10087                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10088                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10089                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10090         printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10091                dev->name, tp->dma_rwctrl);
10092
10093         return 0;
10094
10095 err_out_iounmap:
10096         iounmap(tp->regs);
10097
10098 err_out_free_dev:
10099         free_netdev(dev);
10100
10101 err_out_free_res:
10102         pci_release_regions(pdev);
10103
10104 err_out_disable_pdev:
10105         pci_disable_device(pdev);
10106         pci_set_drvdata(pdev, NULL);
10107         return err;
10108 }
10109
10110 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10111 {
10112         struct net_device *dev = pci_get_drvdata(pdev);
10113
10114         if (dev) {
10115                 struct tg3 *tp = netdev_priv(dev);
10116
10117                 unregister_netdev(dev);
10118                 iounmap(tp->regs);
10119                 free_netdev(dev);
10120                 pci_release_regions(pdev);
10121                 pci_disable_device(pdev);
10122                 pci_set_drvdata(pdev, NULL);
10123         }
10124 }
10125
10126 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10127 {
10128         struct net_device *dev = pci_get_drvdata(pdev);
10129         struct tg3 *tp = netdev_priv(dev);
10130         int err;
10131
10132         if (!netif_running(dev))
10133                 return 0;
10134
10135         tg3_netif_stop(tp);
10136
10137         del_timer_sync(&tp->timer);
10138
10139         spin_lock_irq(&tp->lock);
10140         spin_lock(&tp->tx_lock);
10141         tg3_disable_ints(tp);
10142         spin_unlock(&tp->tx_lock);
10143         spin_unlock_irq(&tp->lock);
10144
10145         netif_device_detach(dev);
10146
10147         spin_lock_irq(&tp->lock);
10148         spin_lock(&tp->tx_lock);
10149         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10150         spin_unlock(&tp->tx_lock);
10151         spin_unlock_irq(&tp->lock);
10152
10153         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10154         if (err) {
10155                 spin_lock_irq(&tp->lock);
10156                 spin_lock(&tp->tx_lock);
10157
10158                 tg3_init_hw(tp);
10159
10160                 tp->timer.expires = jiffies + tp->timer_offset;
10161                 add_timer(&tp->timer);
10162
10163                 netif_device_attach(dev);
10164                 tg3_netif_start(tp);
10165
10166                 spin_unlock(&tp->tx_lock);
10167                 spin_unlock_irq(&tp->lock);
10168         }
10169
10170         return err;
10171 }
10172
10173 static int tg3_resume(struct pci_dev *pdev)
10174 {
10175         struct net_device *dev = pci_get_drvdata(pdev);
10176         struct tg3 *tp = netdev_priv(dev);
10177         int err;
10178
10179         if (!netif_running(dev))
10180                 return 0;
10181
10182         pci_restore_state(tp->pdev);
10183
10184         err = tg3_set_power_state(tp, 0);
10185         if (err)
10186                 return err;
10187
10188         netif_device_attach(dev);
10189
10190         spin_lock_irq(&tp->lock);
10191         spin_lock(&tp->tx_lock);
10192
10193         tg3_init_hw(tp);
10194
10195         tp->timer.expires = jiffies + tp->timer_offset;
10196         add_timer(&tp->timer);
10197
10198         tg3_enable_ints(tp);
10199
10200         tg3_netif_start(tp);
10201
10202         spin_unlock(&tp->tx_lock);
10203         spin_unlock_irq(&tp->lock);
10204
10205         return 0;
10206 }
10207
10208 static struct pci_driver tg3_driver = {
10209         .name           = DRV_MODULE_NAME,
10210         .id_table       = tg3_pci_tbl,
10211         .probe          = tg3_init_one,
10212         .remove         = __devexit_p(tg3_remove_one),
10213         .suspend        = tg3_suspend,
10214         .resume         = tg3_resume
10215 };
10216
10217 static int __init tg3_init(void)
10218 {
10219         return pci_module_init(&tg3_driver);
10220 }
10221
10222 static void __exit tg3_cleanup(void)
10223 {
10224         pci_unregister_driver(&tg3_driver);
10225 }
10226
10227 module_init(tg3_init);
10228 module_exit(tg3_cleanup);