git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "vmx.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/desc.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 static int enable_vpid = 1;
  42 module_param(enable_vpid, bool, 0);
  43
  44 static int flexpriority_enabled = 1;
  45 module_param(flexpriority_enabled, bool, 0);
  46
  47 static int enable_ept = 1;
  48 module_param(enable_ept, bool, 0);
  49
  50 struct vmcs {
  51         u32 revision_id;
  52         u32 abort;
  53         char data[0];
  54 };
  55
  56 struct vcpu_vmx {
  57         struct kvm_vcpu       vcpu;
  58         struct list_head      local_vcpus_link;
  59         int                   launched;
  60         u8                    fail;
  61         u32                   idt_vectoring_info;
  62         struct kvm_msr_entry *guest_msrs;
  63         struct kvm_msr_entry *host_msrs;
  64         int                   nmsrs;
  65         int                   save_nmsrs;
  66         int                   msr_offset_efer;
  67 #ifdef CONFIG_X86_64
  68         int                   msr_offset_kernel_gs_base;
  69 #endif
  70         struct vmcs          *vmcs;
  71         struct {
  72                 int           loaded;
  73                 u16           fs_sel, gs_sel, ldt_sel;
  74                 int           gs_ldt_reload_needed;
  75                 int           fs_reload_needed;
  76                 int           guest_efer_loaded;
  77         } host_state;
  78         struct {
  79                 struct {
  80                         bool pending;
  81                         u8 vector;
  82                         unsigned rip;
  83                 } irq;
  84         } rmode;
  85         int vpid;
  86 };
  87
  88 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  89 {
  90         return container_of(vcpu, struct vcpu_vmx, vcpu);
  91 }
  92
  93 static int init_rmode(struct kvm *kvm);
  94 static u64 construct_eptp(unsigned long root_hpa);
  95
  96 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  97 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  98 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
  99
 100 static struct page *vmx_io_bitmap_a;
 101 static struct page *vmx_io_bitmap_b;
 102 static struct page *vmx_msr_bitmap;
 103
 104 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 105 static DEFINE_SPINLOCK(vmx_vpid_lock);
 106
 107 static struct vmcs_config {
 108         int size;
 109         int order;
 110         u32 revision_id;
 111         u32 pin_based_exec_ctrl;
 112         u32 cpu_based_exec_ctrl;
 113         u32 cpu_based_2nd_exec_ctrl;
 114         u32 vmexit_ctrl;
 115         u32 vmentry_ctrl;
 116 } vmcs_config;
 117
 118 struct vmx_capability {
 119         u32 ept;
 120         u32 vpid;
 121 } vmx_capability;
 122
 123 #define VMX_SEGMENT_FIELD(seg)                                  \
 124         [VCPU_SREG_##seg] = {                                   \
 125                 .selector = GUEST_##seg##_SELECTOR,             \
 126                 .base = GUEST_##seg##_BASE,                     \
 127                 .limit = GUEST_##seg##_LIMIT,                   \
 128                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 129         }
 130
 131 static struct kvm_vmx_segment_field {
 132         unsigned selector;
 133         unsigned base;
 134         unsigned limit;
 135         unsigned ar_bytes;
 136 } kvm_vmx_segment_fields[] = {
 137         VMX_SEGMENT_FIELD(CS),
 138         VMX_SEGMENT_FIELD(DS),
 139         VMX_SEGMENT_FIELD(ES),
 140         VMX_SEGMENT_FIELD(FS),
 141         VMX_SEGMENT_FIELD(GS),
 142         VMX_SEGMENT_FIELD(SS),
 143         VMX_SEGMENT_FIELD(TR),
 144         VMX_SEGMENT_FIELD(LDTR),
 145 };
 146
 147 /*
 148  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 149  * away by decrementing the array size.
 150  */
 151 static const u32 vmx_msr_index[] = {
 152 #ifdef CONFIG_X86_64
 153         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 154 #endif
 155         MSR_EFER, MSR_K6_STAR,
 156 };
 157 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 158
 159 static void load_msrs(struct kvm_msr_entry *e, int n)
 160 {
 161         int i;
 162
 163         for (i = 0; i < n; ++i)
 164                 wrmsrl(e[i].index, e[i].data);
 165 }
 166
 167 static void save_msrs(struct kvm_msr_entry *e, int n)
 168 {
 169         int i;
 170
 171         for (i = 0; i < n; ++i)
 172                 rdmsrl(e[i].index, e[i].data);
 173 }
 174
 175 static inline int is_page_fault(u32 intr_info)
 176 {
 177         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 178                              INTR_INFO_VALID_MASK)) ==
 179                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 180 }
 181
 182 static inline int is_no_device(u32 intr_info)
 183 {
 184         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 185                              INTR_INFO_VALID_MASK)) ==
 186                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 187 }
 188
 189 static inline int is_invalid_opcode(u32 intr_info)
 190 {
 191         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 192                              INTR_INFO_VALID_MASK)) ==
 193                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 194 }
 195
 196 static inline int is_external_interrupt(u32 intr_info)
 197 {
 198         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 199                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 200 }
 201
 202 static inline int cpu_has_vmx_msr_bitmap(void)
 203 {
 204         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
 205 }
 206
 207 static inline int cpu_has_vmx_tpr_shadow(void)
 208 {
 209         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 210 }
 211
 212 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 213 {
 214         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 215 }
 216
 217 static inline int cpu_has_secondary_exec_ctrls(void)
 218 {
 219         return (vmcs_config.cpu_based_exec_ctrl &
 220                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 221 }
 222
 223 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 224 {
 225         return flexpriority_enabled
 226                 && (vmcs_config.cpu_based_2nd_exec_ctrl &
 227                     SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 228 }
 229
 230 static inline int cpu_has_vmx_invept_individual_addr(void)
 231 {
 232         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
 233 }
 234
 235 static inline int cpu_has_vmx_invept_context(void)
 236 {
 237         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
 238 }
 239
 240 static inline int cpu_has_vmx_invept_global(void)
 241 {
 242         return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
 243 }
 244
 245 static inline int cpu_has_vmx_ept(void)
 246 {
 247         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 248                 SECONDARY_EXEC_ENABLE_EPT);
 249 }
 250
 251 static inline int vm_need_ept(void)
 252 {
 253         return (cpu_has_vmx_ept() && enable_ept);
 254 }
 255
 256 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 257 {
 258         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 259                 (irqchip_in_kernel(kvm)));
 260 }
 261
 262 static inline int cpu_has_vmx_vpid(void)
 263 {
 264         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 265                 SECONDARY_EXEC_ENABLE_VPID);
 266 }
 267
 268 static inline int cpu_has_virtual_nmis(void)
 269 {
 270         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 271 }
 272
 273 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 274 {
 275         int i;
 276
 277         for (i = 0; i < vmx->nmsrs; ++i)
 278                 if (vmx->guest_msrs[i].index == msr)
 279                         return i;
 280         return -1;
 281 }
 282
 283 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 284 {
 285     struct {
 286         u64 vpid : 16;
 287         u64 rsvd : 48;
 288         u64 gva;
 289     } operand = { vpid, 0, gva };
 290
 291     asm volatile (__ex(ASM_VMX_INVVPID)
 292                   /* CF==1 or ZF==1 --> rc = -1 */
 293                   "; ja 1f ; ud2 ; 1:"
 294                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 295 }
 296
 297 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 298 {
 299         struct {
 300                 u64 eptp, gpa;
 301         } operand = {eptp, gpa};
 302
 303         asm volatile (__ex(ASM_VMX_INVEPT)
 304                         /* CF==1 or ZF==1 --> rc = -1 */
 305                         "; ja 1f ; ud2 ; 1:\n"
 306                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 307 }
 308
 309 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 310 {
 311         int i;
 312
 313         i = __find_msr_index(vmx, msr);
 314         if (i >= 0)
 315                 return &vmx->guest_msrs[i];
 316         return NULL;
 317 }
 318
 319 static void vmcs_clear(struct vmcs *vmcs)
 320 {
 321         u64 phys_addr = __pa(vmcs);
 322         u8 error;
 323
 324         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 325                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 326                       : "cc", "memory");
 327         if (error)
 328                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 329                        vmcs, phys_addr);
 330 }
 331
 332 static void __vcpu_clear(void *arg)
 333 {
 334         struct vcpu_vmx *vmx = arg;
 335         int cpu = raw_smp_processor_id();
 336
 337         if (vmx->vcpu.cpu == cpu)
 338                 vmcs_clear(vmx->vmcs);
 339         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 340                 per_cpu(current_vmcs, cpu) = NULL;
 341         rdtscll(vmx->vcpu.arch.host_tsc);
 342         list_del(&vmx->local_vcpus_link);
 343         vmx->vcpu.cpu = -1;
 344         vmx->launched = 0;
 345 }
 346
 347 static void vcpu_clear(struct vcpu_vmx *vmx)
 348 {
 349         if (vmx->vcpu.cpu == -1)
 350                 return;
 351         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 352 }
 353
 354 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 355 {
 356         if (vmx->vpid == 0)
 357                 return;
 358
 359         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 360 }
 361
 362 static inline void ept_sync_global(void)
 363 {
 364         if (cpu_has_vmx_invept_global())
 365                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 366 }
 367
 368 static inline void ept_sync_context(u64 eptp)
 369 {
 370         if (vm_need_ept()) {
 371                 if (cpu_has_vmx_invept_context())
 372                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 373                 else
 374                         ept_sync_global();
 375         }
 376 }
 377
 378 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 379 {
 380         if (vm_need_ept()) {
 381                 if (cpu_has_vmx_invept_individual_addr())
 382                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 383                                         eptp, gpa);
 384                 else
 385                         ept_sync_context(eptp);
 386         }
 387 }
 388
 389 static unsigned long vmcs_readl(unsigned long field)
 390 {
 391         unsigned long value;
 392
 393         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 394                       : "=a"(value) : "d"(field) : "cc");
 395         return value;
 396 }
 397
 398 static u16 vmcs_read16(unsigned long field)
 399 {
 400         return vmcs_readl(field);
 401 }
 402
 403 static u32 vmcs_read32(unsigned long field)
 404 {
 405         return vmcs_readl(field);
 406 }
 407
 408 static u64 vmcs_read64(unsigned long field)
 409 {
 410 #ifdef CONFIG_X86_64
 411         return vmcs_readl(field);
 412 #else
 413         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 414 #endif
 415 }
 416
 417 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 418 {
 419         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 420                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 421         dump_stack();
 422 }
 423
 424 static void vmcs_writel(unsigned long field, unsigned long value)
 425 {
 426         u8 error;
 427
 428         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 429                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 430         if (unlikely(error))
 431                 vmwrite_error(field, value);
 432 }
 433
 434 static void vmcs_write16(unsigned long field, u16 value)
 435 {
 436         vmcs_writel(field, value);
 437 }
 438
 439 static void vmcs_write32(unsigned long field, u32 value)
 440 {
 441         vmcs_writel(field, value);
 442 }
 443
 444 static void vmcs_write64(unsigned long field, u64 value)
 445 {
 446         vmcs_writel(field, value);
 447 #ifndef CONFIG_X86_64
 448         asm volatile ("");
 449         vmcs_writel(field+1, value >> 32);
 450 #endif
 451 }
 452
 453 static void vmcs_clear_bits(unsigned long field, u32 mask)
 454 {
 455         vmcs_writel(field, vmcs_readl(field) & ~mask);
 456 }
 457
 458 static void vmcs_set_bits(unsigned long field, u32 mask)
 459 {
 460         vmcs_writel(field, vmcs_readl(field) | mask);
 461 }
 462
 463 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 464 {
 465         u32 eb;
 466
 467         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 468         if (!vcpu->fpu_active)
 469                 eb |= 1u << NM_VECTOR;
 470         if (vcpu->guest_debug.enabled)
 471                 eb |= 1u << 1;
 472         if (vcpu->arch.rmode.active)
 473                 eb = ~0;
 474         if (vm_need_ept())
 475                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 476         vmcs_write32(EXCEPTION_BITMAP, eb);
 477 }
 478
 479 static void reload_tss(void)
 480 {
 481         /*
 482          * VT restores TR but not its size.  Useless.
 483          */
 484         struct descriptor_table gdt;
 485         struct desc_struct *descs;
 486
 487         kvm_get_gdt(&gdt);
 488         descs = (void *)gdt.base;
 489         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 490         load_TR_desc();
 491 }
 492
 493 static void load_transition_efer(struct vcpu_vmx *vmx)
 494 {
 495         int efer_offset = vmx->msr_offset_efer;
 496         u64 host_efer = vmx->host_msrs[efer_offset].data;
 497         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 498         u64 ignore_bits;
 499
 500         if (efer_offset < 0)
 501                 return;
 502         /*
 503          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 504          * outside long mode
 505          */
 506         ignore_bits = EFER_NX | EFER_SCE;
 507 #ifdef CONFIG_X86_64
 508         ignore_bits |= EFER_LMA | EFER_LME;
 509         /* SCE is meaningful only in long mode on Intel */
 510         if (guest_efer & EFER_LMA)
 511                 ignore_bits &= ~(u64)EFER_SCE;
 512 #endif
 513         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 514                 return;
 515
 516         vmx->host_state.guest_efer_loaded = 1;
 517         guest_efer &= ~ignore_bits;
 518         guest_efer |= host_efer & ignore_bits;
 519         wrmsrl(MSR_EFER, guest_efer);
 520         vmx->vcpu.stat.efer_reload++;
 521 }
 522
 523 static void reload_host_efer(struct vcpu_vmx *vmx)
 524 {
 525         if (vmx->host_state.guest_efer_loaded) {
 526                 vmx->host_state.guest_efer_loaded = 0;
 527                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 528         }
 529 }
 530
 531 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 532 {
 533         struct vcpu_vmx *vmx = to_vmx(vcpu);
 534
 535         if (vmx->host_state.loaded)
 536                 return;
 537
 538         vmx->host_state.loaded = 1;
 539         /*
 540          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 541          * allow segment selectors with cpl > 0 or ti == 1.
 542          */
 543         vmx->host_state.ldt_sel = kvm_read_ldt();
 544         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 545         vmx->host_state.fs_sel = kvm_read_fs();
 546         if (!(vmx->host_state.fs_sel & 7)) {
 547                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 548                 vmx->host_state.fs_reload_needed = 0;
 549         } else {
 550                 vmcs_write16(HOST_FS_SELECTOR, 0);
 551                 vmx->host_state.fs_reload_needed = 1;
 552         }
 553         vmx->host_state.gs_sel = kvm_read_gs();
 554         if (!(vmx->host_state.gs_sel & 7))
 555                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 556         else {
 557                 vmcs_write16(HOST_GS_SELECTOR, 0);
 558                 vmx->host_state.gs_ldt_reload_needed = 1;
 559         }
 560
 561 #ifdef CONFIG_X86_64
 562         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 563         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 564 #else
 565         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 566         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 567 #endif
 568
 569 #ifdef CONFIG_X86_64
 570         if (is_long_mode(&vmx->vcpu))
 571                 save_msrs(vmx->host_msrs +
 572                           vmx->msr_offset_kernel_gs_base, 1);
 573
 574 #endif
 575         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 576         load_transition_efer(vmx);
 577 }
 578
 579 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 580 {
 581         unsigned long flags;
 582
 583         if (!vmx->host_state.loaded)
 584                 return;
 585
 586         ++vmx->vcpu.stat.host_state_reload;
 587         vmx->host_state.loaded = 0;
 588         if (vmx->host_state.fs_reload_needed)
 589                 kvm_load_fs(vmx->host_state.fs_sel);
 590         if (vmx->host_state.gs_ldt_reload_needed) {
 591                 kvm_load_ldt(vmx->host_state.ldt_sel);
 592                 /*
 593                  * If we have to reload gs, we must take care to
 594                  * preserve our gs base.
 595                  */
 596                 local_irq_save(flags);
 597                 kvm_load_gs(vmx->host_state.gs_sel);
 598 #ifdef CONFIG_X86_64
 599                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 600 #endif
 601                 local_irq_restore(flags);
 602         }
 603         reload_tss();
 604         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 605         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 606         reload_host_efer(vmx);
 607 }
 608
 609 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 610 {
 611         preempt_disable();
 612         __vmx_load_host_state(vmx);
 613         preempt_enable();
 614 }
 615
 616 /*
 617  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 618  * vcpu mutex is already taken.
 619  */
 620 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 621 {
 622         struct vcpu_vmx *vmx = to_vmx(vcpu);
 623         u64 phys_addr = __pa(vmx->vmcs);
 624         u64 tsc_this, delta, new_offset;
 625
 626         if (vcpu->cpu != cpu) {
 627                 vcpu_clear(vmx);
 628                 kvm_migrate_timers(vcpu);
 629                 vpid_sync_vcpu_all(vmx);
 630                 local_irq_disable();
 631                 list_add(&vmx->local_vcpus_link,
 632                          &per_cpu(vcpus_on_cpu, cpu));
 633                 local_irq_enable();
 634         }
 635
 636         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 637                 u8 error;
 638
 639                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 640                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 641                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 642                               : "cc");
 643                 if (error)
 644                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 645                                vmx->vmcs, phys_addr);
 646         }
 647
 648         if (vcpu->cpu != cpu) {
 649                 struct descriptor_table dt;
 650                 unsigned long sysenter_esp;
 651
 652                 vcpu->cpu = cpu;
 653                 /*
 654                  * Linux uses per-cpu TSS and GDT, so set these when switching
 655                  * processors.
 656                  */
 657                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 658                 kvm_get_gdt(&dt);
 659                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 660
 661                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 662                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 663
 664                 /*
 665                  * Make sure the time stamp counter is monotonous.
 666                  */
 667                 rdtscll(tsc_this);
 668                 if (tsc_this < vcpu->arch.host_tsc) {
 669                         delta = vcpu->arch.host_tsc - tsc_this;
 670                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 671                         vmcs_write64(TSC_OFFSET, new_offset);
 672                 }
 673         }
 674 }
 675
 676 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 677 {
 678         __vmx_load_host_state(to_vmx(vcpu));
 679 }
 680
 681 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 682 {
 683         if (vcpu->fpu_active)
 684                 return;
 685         vcpu->fpu_active = 1;
 686         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 687         if (vcpu->arch.cr0 & X86_CR0_TS)
 688                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 689         update_exception_bitmap(vcpu);
 690 }
 691
 692 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 693 {
 694         if (!vcpu->fpu_active)
 695                 return;
 696         vcpu->fpu_active = 0;
 697         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 698         update_exception_bitmap(vcpu);
 699 }
 700
 701 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 702 {
 703         return vmcs_readl(GUEST_RFLAGS);
 704 }
 705
 706 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 707 {
 708         if (vcpu->arch.rmode.active)
 709                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 710         vmcs_writel(GUEST_RFLAGS, rflags);
 711 }
 712
 713 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 714 {
 715         unsigned long rip;
 716         u32 interruptibility;
 717
 718         rip = vmcs_readl(GUEST_RIP);
 719         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 720         vmcs_writel(GUEST_RIP, rip);
 721
 722         /*
 723          * We emulated an instruction, so temporary interrupt blocking
 724          * should be removed, if set.
 725          */
 726         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 727         if (interruptibility & 3)
 728                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 729                              interruptibility & ~3);
 730         vcpu->arch.interrupt_window_open = 1;
 731 }
 732
 733 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 734                                 bool has_error_code, u32 error_code)
 735 {
 736         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 737                      nr | INTR_TYPE_EXCEPTION
 738                      | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
 739                      | INTR_INFO_VALID_MASK);
 740         if (has_error_code)
 741                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 742 }
 743
 744 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
 745 {
 746         struct vcpu_vmx *vmx = to_vmx(vcpu);
 747
 748         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
 749 }
 750
 751 /*
 752  * Swap MSR entry in host/guest MSR entry array.
 753  */
 754 #ifdef CONFIG_X86_64
 755 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 756 {
 757         struct kvm_msr_entry tmp;
 758
 759         tmp = vmx->guest_msrs[to];
 760         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 761         vmx->guest_msrs[from] = tmp;
 762         tmp = vmx->host_msrs[to];
 763         vmx->host_msrs[to] = vmx->host_msrs[from];
 764         vmx->host_msrs[from] = tmp;
 765 }
 766 #endif
 767
 768 /*
 769  * Set up the vmcs to automatically save and restore system
 770  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 771  * mode, as fiddling with msrs is very expensive.
 772  */
 773 static void setup_msrs(struct vcpu_vmx *vmx)
 774 {
 775         int save_nmsrs;
 776
 777         vmx_load_host_state(vmx);
 778         save_nmsrs = 0;
 779 #ifdef CONFIG_X86_64
 780         if (is_long_mode(&vmx->vcpu)) {
 781                 int index;
 782
 783                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 784                 if (index >= 0)
 785                         move_msr_up(vmx, index, save_nmsrs++);
 786                 index = __find_msr_index(vmx, MSR_LSTAR);
 787                 if (index >= 0)
 788                         move_msr_up(vmx, index, save_nmsrs++);
 789                 index = __find_msr_index(vmx, MSR_CSTAR);
 790                 if (index >= 0)
 791                         move_msr_up(vmx, index, save_nmsrs++);
 792                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 793                 if (index >= 0)
 794                         move_msr_up(vmx, index, save_nmsrs++);
 795                 /*
 796                  * MSR_K6_STAR is only needed on long mode guests, and only
 797                  * if efer.sce is enabled.
 798                  */
 799                 index = __find_msr_index(vmx, MSR_K6_STAR);
 800                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
 801                         move_msr_up(vmx, index, save_nmsrs++);
 802         }
 803 #endif
 804         vmx->save_nmsrs = save_nmsrs;
 805
 806 #ifdef CONFIG_X86_64
 807         vmx->msr_offset_kernel_gs_base =
 808                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 809 #endif
 810         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 811 }
 812
 813 /*
 814  * reads and returns guest's timestamp counter "register"
 815  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 816  */
 817 static u64 guest_read_tsc(void)
 818 {
 819         u64 host_tsc, tsc_offset;
 820
 821         rdtscll(host_tsc);
 822         tsc_offset = vmcs_read64(TSC_OFFSET);
 823         return host_tsc + tsc_offset;
 824 }
 825
 826 /*
 827  * writes 'guest_tsc' into guest's timestamp counter "register"
 828  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 829  */
 830 static void guest_write_tsc(u64 guest_tsc)
 831 {
 832         u64 host_tsc;
 833
 834         rdtscll(host_tsc);
 835         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 836 }
 837
 838 /*
 839  * Reads an msr value (of 'msr_index') into 'pdata'.
 840  * Returns 0 on success, non-0 otherwise.
 841  * Assumes vcpu_load() was already called.
 842  */
 843 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 844 {
 845         u64 data;
 846         struct kvm_msr_entry *msr;
 847
 848         if (!pdata) {
 849                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 850                 return -EINVAL;
 851         }
 852
 853         switch (msr_index) {
 854 #ifdef CONFIG_X86_64
 855         case MSR_FS_BASE:
 856                 data = vmcs_readl(GUEST_FS_BASE);
 857                 break;
 858         case MSR_GS_BASE:
 859                 data = vmcs_readl(GUEST_GS_BASE);
 860                 break;
 861         case MSR_EFER:
 862                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 863 #endif
 864         case MSR_IA32_TIME_STAMP_COUNTER:
 865                 data = guest_read_tsc();
 866                 break;
 867         case MSR_IA32_SYSENTER_CS:
 868                 data = vmcs_read32(GUEST_SYSENTER_CS);
 869                 break;
 870         case MSR_IA32_SYSENTER_EIP:
 871                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 872                 break;
 873         case MSR_IA32_SYSENTER_ESP:
 874                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 875                 break;
 876         default:
 877                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 878                 if (msr) {
 879                         data = msr->data;
 880                         break;
 881                 }
 882                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 883         }
 884
 885         *pdata = data;
 886         return 0;
 887 }
 888
 889 /*
 890  * Writes msr value into into the appropriate "register".
 891  * Returns 0 on success, non-0 otherwise.
 892  * Assumes vcpu_load() was already called.
 893  */
 894 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 895 {
 896         struct vcpu_vmx *vmx = to_vmx(vcpu);
 897         struct kvm_msr_entry *msr;
 898         int ret = 0;
 899
 900         switch (msr_index) {
 901 #ifdef CONFIG_X86_64
 902         case MSR_EFER:
 903                 vmx_load_host_state(vmx);
 904                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 905                 break;
 906         case MSR_FS_BASE:
 907                 vmcs_writel(GUEST_FS_BASE, data);
 908                 break;
 909         case MSR_GS_BASE:
 910                 vmcs_writel(GUEST_GS_BASE, data);
 911                 break;
 912 #endif
 913         case MSR_IA32_SYSENTER_CS:
 914                 vmcs_write32(GUEST_SYSENTER_CS, data);
 915                 break;
 916         case MSR_IA32_SYSENTER_EIP:
 917                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 918                 break;
 919         case MSR_IA32_SYSENTER_ESP:
 920                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 921                 break;
 922         case MSR_IA32_TIME_STAMP_COUNTER:
 923                 guest_write_tsc(data);
 924                 break;
 925         case MSR_P6_PERFCTR0:
 926         case MSR_P6_PERFCTR1:
 927         case MSR_P6_EVNTSEL0:
 928         case MSR_P6_EVNTSEL1:
 929                 /*
 930                  * Just discard all writes to the performance counters; this
 931                  * should keep both older linux and windows 64-bit guests
 932                  * happy
 933                  */
 934                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
 935
 936                 break;
 937         default:
 938                 vmx_load_host_state(vmx);
 939                 msr = find_msr_entry(vmx, msr_index);
 940                 if (msr) {
 941                         msr->data = data;
 942                         break;
 943                 }
 944                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 945         }
 946
 947         return ret;
 948 }
 949
 950 /*
 951  * Sync the rsp and rip registers into the vcpu structure.  This allows
 952  * registers to be accessed by indexing vcpu->arch.regs.
 953  */
 954 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 955 {
 956         vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 957         vcpu->arch.rip = vmcs_readl(GUEST_RIP);
 958 }
 959
 960 /*
 961  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 962  * modification.
 963  */
 964 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 965 {
 966         vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
 967         vmcs_writel(GUEST_RIP, vcpu->arch.rip);
 968 }
 969
 970 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 971 {
 972         unsigned long dr7 = 0x400;
 973         int old_singlestep;
 974
 975         old_singlestep = vcpu->guest_debug.singlestep;
 976
 977         vcpu->guest_debug.enabled = dbg->enabled;
 978         if (vcpu->guest_debug.enabled) {
 979                 int i;
 980
 981                 dr7 |= 0x200;  /* exact */
 982                 for (i = 0; i < 4; ++i) {
 983                         if (!dbg->breakpoints[i].enabled)
 984                                 continue;
 985                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 986                         dr7 |= 2 << (i*2);    /* global enable */
 987                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 988                 }
 989
 990                 vcpu->guest_debug.singlestep = dbg->singlestep;
 991         } else
 992                 vcpu->guest_debug.singlestep = 0;
 993
 994         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 995                 unsigned long flags;
 996
 997                 flags = vmcs_readl(GUEST_RFLAGS);
 998                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 999                 vmcs_writel(GUEST_RFLAGS, flags);
1000         }
1001
1002         update_exception_bitmap(vcpu);
1003         vmcs_writel(GUEST_DR7, dr7);
1004
1005         return 0;
1006 }
1007
1008 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1009 {
1010         struct vcpu_vmx *vmx = to_vmx(vcpu);
1011         u32 idtv_info_field;
1012
1013         idtv_info_field = vmx->idt_vectoring_info;
1014         if (idtv_info_field & INTR_INFO_VALID_MASK) {
1015                 if (is_external_interrupt(idtv_info_field))
1016                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
1017                 else
1018                         printk(KERN_DEBUG "pending exception: not handled yet\n");
1019         }
1020         return -1;
1021 }
1022
1023 static __init int cpu_has_kvm_support(void)
1024 {
1025         unsigned long ecx = cpuid_ecx(1);
1026         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1027 }
1028
1029 static __init int vmx_disabled_by_bios(void)
1030 {
1031         u64 msr;
1032
1033         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1034         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1035                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1036             == MSR_IA32_FEATURE_CONTROL_LOCKED;
1037         /* locked but not enabled */
1038 }
1039
1040 static void hardware_enable(void *garbage)
1041 {
1042         int cpu = raw_smp_processor_id();
1043         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1044         u64 old;
1045
1046         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1047         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1048         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1049                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1050             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
1051                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1052                 /* enable and lock */
1053                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1054                        MSR_IA32_FEATURE_CONTROL_LOCKED |
1055                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
1056         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1057         asm volatile (ASM_VMX_VMXON_RAX
1058                       : : "a"(&phys_addr), "m"(phys_addr)
1059                       : "memory", "cc");
1060 }
1061
1062 static void vmclear_local_vcpus(void)
1063 {
1064         int cpu = raw_smp_processor_id();
1065         struct vcpu_vmx *vmx, *n;
1066
1067         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1068                                  local_vcpus_link)
1069                 __vcpu_clear(vmx);
1070 }
1071
1072 static void hardware_disable(void *garbage)
1073 {
1074         vmclear_local_vcpus();
1075         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1076         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1077 }
1078
1079 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1080                                       u32 msr, u32 *result)
1081 {
1082         u32 vmx_msr_low, vmx_msr_high;
1083         u32 ctl = ctl_min | ctl_opt;
1084
1085         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1086
1087         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1088         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1089
1090         /* Ensure minimum (required) set of control bits are supported. */
1091         if (ctl_min & ~ctl)
1092                 return -EIO;
1093
1094         *result = ctl;
1095         return 0;
1096 }
1097
1098 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1099 {
1100         u32 vmx_msr_low, vmx_msr_high;
1101         u32 min, opt, min2, opt2;
1102         u32 _pin_based_exec_control = 0;
1103         u32 _cpu_based_exec_control = 0;
1104         u32 _cpu_based_2nd_exec_control = 0;
1105         u32 _vmexit_control = 0;
1106         u32 _vmentry_control = 0;
1107
1108         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1109         opt = PIN_BASED_VIRTUAL_NMIS;
1110         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1111                                 &_pin_based_exec_control) < 0)
1112                 return -EIO;
1113
1114         min = CPU_BASED_HLT_EXITING |
1115 #ifdef CONFIG_X86_64
1116               CPU_BASED_CR8_LOAD_EXITING |
1117               CPU_BASED_CR8_STORE_EXITING |
1118 #endif
1119               CPU_BASED_CR3_LOAD_EXITING |
1120               CPU_BASED_CR3_STORE_EXITING |
1121               CPU_BASED_USE_IO_BITMAPS |
1122               CPU_BASED_MOV_DR_EXITING |
1123               CPU_BASED_USE_TSC_OFFSETING;
1124         opt = CPU_BASED_TPR_SHADOW |
1125               CPU_BASED_USE_MSR_BITMAPS |
1126               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1127         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1128                                 &_cpu_based_exec_control) < 0)
1129                 return -EIO;
1130 #ifdef CONFIG_X86_64
1131         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1132                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1133                                            ~CPU_BASED_CR8_STORE_EXITING;
1134 #endif
1135         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1136                 min2 = 0;
1137                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1138                         SECONDARY_EXEC_WBINVD_EXITING |
1139                         SECONDARY_EXEC_ENABLE_VPID |
1140                         SECONDARY_EXEC_ENABLE_EPT;
1141                 if (adjust_vmx_controls(min2, opt2,
1142                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1143                                         &_cpu_based_2nd_exec_control) < 0)
1144                         return -EIO;
1145         }
1146 #ifndef CONFIG_X86_64
1147         if (!(_cpu_based_2nd_exec_control &
1148                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1149                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1150 #endif
1151         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1152                 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1153                 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1154                          CPU_BASED_CR3_STORE_EXITING);
1155                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1156                                         &_cpu_based_exec_control) < 0)
1157                         return -EIO;
1158                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1159                       vmx_capability.ept, vmx_capability.vpid);
1160         }
1161
1162         min = 0;
1163 #ifdef CONFIG_X86_64
1164         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1165 #endif
1166         opt = 0;
1167         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1168                                 &_vmexit_control) < 0)
1169                 return -EIO;
1170
1171         min = opt = 0;
1172         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1173                                 &_vmentry_control) < 0)
1174                 return -EIO;
1175
1176         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1177
1178         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1179         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1180                 return -EIO;
1181
1182 #ifdef CONFIG_X86_64
1183         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1184         if (vmx_msr_high & (1u<<16))
1185                 return -EIO;
1186 #endif
1187
1188         /* Require Write-Back (WB) memory type for VMCS accesses. */
1189         if (((vmx_msr_high >> 18) & 15) != 6)
1190                 return -EIO;
1191
1192         vmcs_conf->size = vmx_msr_high & 0x1fff;
1193         vmcs_conf->order = get_order(vmcs_config.size);
1194         vmcs_conf->revision_id = vmx_msr_low;
1195
1196         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1197         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1198         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1199         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1200         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1201
1202         return 0;
1203 }
1204
1205 static struct vmcs *alloc_vmcs_cpu(int cpu)
1206 {
1207         int node = cpu_to_node(cpu);
1208         struct page *pages;
1209         struct vmcs *vmcs;
1210
1211         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1212         if (!pages)
1213                 return NULL;
1214         vmcs = page_address(pages);
1215         memset(vmcs, 0, vmcs_config.size);
1216         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1217         return vmcs;
1218 }
1219
1220 static struct vmcs *alloc_vmcs(void)
1221 {
1222         return alloc_vmcs_cpu(raw_smp_processor_id());
1223 }
1224
1225 static void free_vmcs(struct vmcs *vmcs)
1226 {
1227         free_pages((unsigned long)vmcs, vmcs_config.order);
1228 }
1229
1230 static void free_kvm_area(void)
1231 {
1232         int cpu;
1233
1234         for_each_online_cpu(cpu)
1235                 free_vmcs(per_cpu(vmxarea, cpu));
1236 }
1237
1238 static __init int alloc_kvm_area(void)
1239 {
1240         int cpu;
1241
1242         for_each_online_cpu(cpu) {
1243                 struct vmcs *vmcs;
1244
1245                 vmcs = alloc_vmcs_cpu(cpu);
1246                 if (!vmcs) {
1247                         free_kvm_area();
1248                         return -ENOMEM;
1249                 }
1250
1251                 per_cpu(vmxarea, cpu) = vmcs;
1252         }
1253         return 0;
1254 }
1255
1256 static __init int hardware_setup(void)
1257 {
1258         if (setup_vmcs_config(&vmcs_config) < 0)
1259                 return -EIO;
1260
1261         if (boot_cpu_has(X86_FEATURE_NX))
1262                 kvm_enable_efer_bits(EFER_NX);
1263
1264         return alloc_kvm_area();
1265 }
1266
1267 static __exit void hardware_unsetup(void)
1268 {
1269         free_kvm_area();
1270 }
1271
1272 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1273 {
1274         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1275
1276         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1277                 vmcs_write16(sf->selector, save->selector);
1278                 vmcs_writel(sf->base, save->base);
1279                 vmcs_write32(sf->limit, save->limit);
1280                 vmcs_write32(sf->ar_bytes, save->ar);
1281         } else {
1282                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1283                         << AR_DPL_SHIFT;
1284                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1285         }
1286 }
1287
1288 static void enter_pmode(struct kvm_vcpu *vcpu)
1289 {
1290         unsigned long flags;
1291
1292         vcpu->arch.rmode.active = 0;
1293
1294         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1295         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1296         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1297
1298         flags = vmcs_readl(GUEST_RFLAGS);
1299         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1300         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1301         vmcs_writel(GUEST_RFLAGS, flags);
1302
1303         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1304                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1305
1306         update_exception_bitmap(vcpu);
1307
1308         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1309         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1310         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1311         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1312
1313         vmcs_write16(GUEST_SS_SELECTOR, 0);
1314         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1315
1316         vmcs_write16(GUEST_CS_SELECTOR,
1317                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1318         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1319 }
1320
1321 static gva_t rmode_tss_base(struct kvm *kvm)
1322 {
1323         if (!kvm->arch.tss_addr) {
1324                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1325                                  kvm->memslots[0].npages - 3;
1326                 return base_gfn << PAGE_SHIFT;
1327         }
1328         return kvm->arch.tss_addr;
1329 }
1330
1331 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1332 {
1333         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1334
1335         save->selector = vmcs_read16(sf->selector);
1336         save->base = vmcs_readl(sf->base);
1337         save->limit = vmcs_read32(sf->limit);
1338         save->ar = vmcs_read32(sf->ar_bytes);
1339         vmcs_write16(sf->selector, save->base >> 4);
1340         vmcs_write32(sf->base, save->base & 0xfffff);
1341         vmcs_write32(sf->limit, 0xffff);
1342         vmcs_write32(sf->ar_bytes, 0xf3);
1343 }
1344
1345 static void enter_rmode(struct kvm_vcpu *vcpu)
1346 {
1347         unsigned long flags;
1348
1349         vcpu->arch.rmode.active = 1;
1350
1351         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1352         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1353
1354         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1355         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1356
1357         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1358         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1359
1360         flags = vmcs_readl(GUEST_RFLAGS);
1361         vcpu->arch.rmode.save_iopl
1362                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1363
1364         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1365
1366         vmcs_writel(GUEST_RFLAGS, flags);
1367         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1368         update_exception_bitmap(vcpu);
1369
1370         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1371         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1372         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1373
1374         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1375         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1376         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1377                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1378         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1379
1380         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1381         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1382         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1383         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1384
1385         kvm_mmu_reset_context(vcpu);
1386         init_rmode(vcpu->kvm);
1387 }
1388
1389 #ifdef CONFIG_X86_64
1390
1391 static void enter_lmode(struct kvm_vcpu *vcpu)
1392 {
1393         u32 guest_tr_ar;
1394
1395         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1396         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1397                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1398                        __func__);
1399                 vmcs_write32(GUEST_TR_AR_BYTES,
1400                              (guest_tr_ar & ~AR_TYPE_MASK)
1401                              | AR_TYPE_BUSY_64_TSS);
1402         }
1403
1404         vcpu->arch.shadow_efer |= EFER_LMA;
1405
1406         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1407         vmcs_write32(VM_ENTRY_CONTROLS,
1408                      vmcs_read32(VM_ENTRY_CONTROLS)
1409                      | VM_ENTRY_IA32E_MODE);
1410 }
1411
1412 static void exit_lmode(struct kvm_vcpu *vcpu)
1413 {
1414         vcpu->arch.shadow_efer &= ~EFER_LMA;
1415
1416         vmcs_write32(VM_ENTRY_CONTROLS,
1417                      vmcs_read32(VM_ENTRY_CONTROLS)
1418                      & ~VM_ENTRY_IA32E_MODE);
1419 }
1420
1421 #endif
1422
1423 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1424 {
1425         vpid_sync_vcpu_all(to_vmx(vcpu));
1426         if (vm_need_ept())
1427                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1428 }
1429
1430 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1431 {
1432         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1433         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1434 }
1435
1436 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1437 {
1438         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439                 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1440                         printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1441                         return;
1442                 }
1443                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1444                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1445                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1446                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1447         }
1448 }
1449
1450 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1451
1452 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1453                                         unsigned long cr0,
1454                                         struct kvm_vcpu *vcpu)
1455 {
1456         if (!(cr0 & X86_CR0_PG)) {
1457                 /* From paging/starting to nonpaging */
1458                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1459                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1460                              (CPU_BASED_CR3_LOAD_EXITING |
1461                               CPU_BASED_CR3_STORE_EXITING));
1462                 vcpu->arch.cr0 = cr0;
1463                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1464                 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1465                 *hw_cr0 &= ~X86_CR0_WP;
1466         } else if (!is_paging(vcpu)) {
1467                 /* From nonpaging to paging */
1468                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1469                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1470                              ~(CPU_BASED_CR3_LOAD_EXITING |
1471                                CPU_BASED_CR3_STORE_EXITING));
1472                 vcpu->arch.cr0 = cr0;
1473                 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1474                 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1475                         *hw_cr0 &= ~X86_CR0_WP;
1476         }
1477 }
1478
1479 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1480                                         struct kvm_vcpu *vcpu)
1481 {
1482         if (!is_paging(vcpu)) {
1483                 *hw_cr4 &= ~X86_CR4_PAE;
1484                 *hw_cr4 |= X86_CR4_PSE;
1485         } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1486                 *hw_cr4 &= ~X86_CR4_PAE;
1487 }
1488
1489 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1490 {
1491         unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1492                                 KVM_VM_CR0_ALWAYS_ON;
1493
1494         vmx_fpu_deactivate(vcpu);
1495
1496         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1497                 enter_pmode(vcpu);
1498
1499         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1500                 enter_rmode(vcpu);
1501
1502 #ifdef CONFIG_X86_64
1503         if (vcpu->arch.shadow_efer & EFER_LME) {
1504                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1505                         enter_lmode(vcpu);
1506                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1507                         exit_lmode(vcpu);
1508         }
1509 #endif
1510
1511         if (vm_need_ept())
1512                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1513
1514         vmcs_writel(CR0_READ_SHADOW, cr0);
1515         vmcs_writel(GUEST_CR0, hw_cr0);
1516         vcpu->arch.cr0 = cr0;
1517
1518         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1519                 vmx_fpu_activate(vcpu);
1520 }
1521
1522 static u64 construct_eptp(unsigned long root_hpa)
1523 {
1524         u64 eptp;
1525
1526         /* TODO write the value reading from MSR */
1527         eptp = VMX_EPT_DEFAULT_MT |
1528                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1529         eptp |= (root_hpa & PAGE_MASK);
1530
1531         return eptp;
1532 }
1533
1534 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1535 {
1536         unsigned long guest_cr3;
1537         u64 eptp;
1538
1539         guest_cr3 = cr3;
1540         if (vm_need_ept()) {
1541                 eptp = construct_eptp(cr3);
1542                 vmcs_write64(EPT_POINTER, eptp);
1543                 ept_sync_context(eptp);
1544                 ept_load_pdptrs(vcpu);
1545                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1546                         VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1547         }
1548
1549         vmx_flush_tlb(vcpu);
1550         vmcs_writel(GUEST_CR3, guest_cr3);
1551         if (vcpu->arch.cr0 & X86_CR0_PE)
1552                 vmx_fpu_deactivate(vcpu);
1553 }
1554
1555 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1556 {
1557         unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1558                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1559
1560         vcpu->arch.cr4 = cr4;
1561         if (vm_need_ept())
1562                 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1563
1564         vmcs_writel(CR4_READ_SHADOW, cr4);
1565         vmcs_writel(GUEST_CR4, hw_cr4);
1566 }
1567
1568 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1569 {
1570         struct vcpu_vmx *vmx = to_vmx(vcpu);
1571         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1572
1573         vcpu->arch.shadow_efer = efer;
1574         if (!msr)
1575                 return;
1576         if (efer & EFER_LMA) {
1577                 vmcs_write32(VM_ENTRY_CONTROLS,
1578                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1579                                      VM_ENTRY_IA32E_MODE);
1580                 msr->data = efer;
1581
1582         } else {
1583                 vmcs_write32(VM_ENTRY_CONTROLS,
1584                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1585                                      ~VM_ENTRY_IA32E_MODE);
1586
1587                 msr->data = efer & ~EFER_LME;
1588         }
1589         setup_msrs(vmx);
1590 }
1591
1592 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1593 {
1594         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1595
1596         return vmcs_readl(sf->base);
1597 }
1598
1599 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1600                             struct kvm_segment *var, int seg)
1601 {
1602         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1603         u32 ar;
1604
1605         var->base = vmcs_readl(sf->base);
1606         var->limit = vmcs_read32(sf->limit);
1607         var->selector = vmcs_read16(sf->selector);
1608         ar = vmcs_read32(sf->ar_bytes);
1609         if (ar & AR_UNUSABLE_MASK)
1610                 ar = 0;
1611         var->type = ar & 15;
1612         var->s = (ar >> 4) & 1;
1613         var->dpl = (ar >> 5) & 3;
1614         var->present = (ar >> 7) & 1;
1615         var->avl = (ar >> 12) & 1;
1616         var->l = (ar >> 13) & 1;
1617         var->db = (ar >> 14) & 1;
1618         var->g = (ar >> 15) & 1;
1619         var->unusable = (ar >> 16) & 1;
1620 }
1621
1622 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1623 {
1624         struct kvm_segment kvm_seg;
1625
1626         if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1627                 return 0;
1628
1629         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1630                 return 3;
1631
1632         vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1633         return kvm_seg.selector & 3;
1634 }
1635
1636 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1637 {
1638         u32 ar;
1639
1640         if (var->unusable)
1641                 ar = 1 << 16;
1642         else {
1643                 ar = var->type & 15;
1644                 ar |= (var->s & 1) << 4;
1645                 ar |= (var->dpl & 3) << 5;
1646                 ar |= (var->present & 1) << 7;
1647                 ar |= (var->avl & 1) << 12;
1648                 ar |= (var->l & 1) << 13;
1649                 ar |= (var->db & 1) << 14;
1650                 ar |= (var->g & 1) << 15;
1651         }
1652         if (ar == 0) /* a 0 value means unusable */
1653                 ar = AR_UNUSABLE_MASK;
1654
1655         return ar;
1656 }
1657
1658 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1659                             struct kvm_segment *var, int seg)
1660 {
1661         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1662         u32 ar;
1663
1664         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1665                 vcpu->arch.rmode.tr.selector = var->selector;
1666                 vcpu->arch.rmode.tr.base = var->base;
1667                 vcpu->arch.rmode.tr.limit = var->limit;
1668                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1669                 return;
1670         }
1671         vmcs_writel(sf->base, var->base);
1672         vmcs_write32(sf->limit, var->limit);
1673         vmcs_write16(sf->selector, var->selector);
1674         if (vcpu->arch.rmode.active && var->s) {
1675                 /*
1676                  * Hack real-mode segments into vm86 compatibility.
1677                  */
1678                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1679                         vmcs_writel(sf->base, 0xf0000);
1680                 ar = 0xf3;
1681         } else
1682                 ar = vmx_segment_access_rights(var);
1683         vmcs_write32(sf->ar_bytes, ar);
1684 }
1685
1686 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1687 {
1688         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1689
1690         *db = (ar >> 14) & 1;
1691         *l = (ar >> 13) & 1;
1692 }
1693
1694 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1695 {
1696         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1697         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1698 }
1699
1700 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1701 {
1702         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1703         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1704 }
1705
1706 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1707 {
1708         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1709         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1710 }
1711
1712 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1713 {
1714         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1715         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1716 }
1717
1718 static int init_rmode_tss(struct kvm *kvm)
1719 {
1720         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1721         u16 data = 0;
1722         int ret = 0;
1723         int r;
1724
1725         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1726         if (r < 0)
1727                 goto out;
1728         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1729         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1730         if (r < 0)
1731                 goto out;
1732         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1733         if (r < 0)
1734                 goto out;
1735         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1736         if (r < 0)
1737                 goto out;
1738         data = ~0;
1739         r = kvm_write_guest_page(kvm, fn, &data,
1740                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1741                                  sizeof(u8));
1742         if (r < 0)
1743                 goto out;
1744
1745         ret = 1;
1746 out:
1747         return ret;
1748 }
1749
1750 static int init_rmode_identity_map(struct kvm *kvm)
1751 {
1752         int i, r, ret;
1753         pfn_t identity_map_pfn;
1754         u32 tmp;
1755
1756         if (!vm_need_ept())
1757                 return 1;
1758         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1759                 printk(KERN_ERR "EPT: identity-mapping pagetable "
1760                         "haven't been allocated!\n");
1761                 return 0;
1762         }
1763         if (likely(kvm->arch.ept_identity_pagetable_done))
1764                 return 1;
1765         ret = 0;
1766         identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1767         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1768         if (r < 0)
1769                 goto out;
1770         /* Set up identity-mapping pagetable for EPT in real mode */
1771         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1772                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1773                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1774                 r = kvm_write_guest_page(kvm, identity_map_pfn,
1775                                 &tmp, i * sizeof(tmp), sizeof(tmp));
1776                 if (r < 0)
1777                         goto out;
1778         }
1779         kvm->arch.ept_identity_pagetable_done = true;
1780         ret = 1;
1781 out:
1782         return ret;
1783 }
1784
1785 static void seg_setup(int seg)
1786 {
1787         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1788
1789         vmcs_write16(sf->selector, 0);
1790         vmcs_writel(sf->base, 0);
1791         vmcs_write32(sf->limit, 0xffff);
1792         vmcs_write32(sf->ar_bytes, 0x93);
1793 }
1794
1795 static int alloc_apic_access_page(struct kvm *kvm)
1796 {
1797         struct kvm_userspace_memory_region kvm_userspace_mem;
1798         int r = 0;
1799
1800         down_write(&kvm->slots_lock);
1801         if (kvm->arch.apic_access_page)
1802                 goto out;
1803         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1804         kvm_userspace_mem.flags = 0;
1805         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1806         kvm_userspace_mem.memory_size = PAGE_SIZE;
1807         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1808         if (r)
1809                 goto out;
1810
1811         down_read(&current->mm->mmap_sem);
1812         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1813         up_read(&current->mm->mmap_sem);
1814 out:
1815         up_write(&kvm->slots_lock);
1816         return r;
1817 }
1818
1819 static int alloc_identity_pagetable(struct kvm *kvm)
1820 {
1821         struct kvm_userspace_memory_region kvm_userspace_mem;
1822         int r = 0;
1823
1824         down_write(&kvm->slots_lock);
1825         if (kvm->arch.ept_identity_pagetable)
1826                 goto out;
1827         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1828         kvm_userspace_mem.flags = 0;
1829         kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1830         kvm_userspace_mem.memory_size = PAGE_SIZE;
1831         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1832         if (r)
1833                 goto out;
1834
1835         down_read(&current->mm->mmap_sem);
1836         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1837                         VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1838         up_read(&current->mm->mmap_sem);
1839 out:
1840         up_write(&kvm->slots_lock);
1841         return r;
1842 }
1843
1844 static void allocate_vpid(struct vcpu_vmx *vmx)
1845 {
1846         int vpid;
1847
1848         vmx->vpid = 0;
1849         if (!enable_vpid || !cpu_has_vmx_vpid())
1850                 return;
1851         spin_lock(&vmx_vpid_lock);
1852         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1853         if (vpid < VMX_NR_VPIDS) {
1854                 vmx->vpid = vpid;
1855                 __set_bit(vpid, vmx_vpid_bitmap);
1856         }
1857         spin_unlock(&vmx_vpid_lock);
1858 }
1859
1860 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1861 {
1862         void *va;
1863
1864         if (!cpu_has_vmx_msr_bitmap())
1865                 return;
1866
1867         /*
1868          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1869          * have the write-low and read-high bitmap offsets the wrong way round.
1870          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1871          */
1872         va = kmap(msr_bitmap);
1873         if (msr <= 0x1fff) {
1874                 __clear_bit(msr, va + 0x000); /* read-low */
1875                 __clear_bit(msr, va + 0x800); /* write-low */
1876         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1877                 msr &= 0x1fff;
1878                 __clear_bit(msr, va + 0x400); /* read-high */
1879                 __clear_bit(msr, va + 0xc00); /* write-high */
1880         }
1881         kunmap(msr_bitmap);
1882 }
1883
1884 /*
1885  * Sets up the vmcs for emulated real mode.
1886  */
1887 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1888 {
1889         u32 host_sysenter_cs;
1890         u32 junk;
1891         unsigned long a;
1892         struct descriptor_table dt;
1893         int i;
1894         unsigned long kvm_vmx_return;
1895         u32 exec_control;
1896
1897         /* I/O */
1898         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1899         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1900
1901         if (cpu_has_vmx_msr_bitmap())
1902                 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1903
1904         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1905
1906         /* Control */
1907         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1908                 vmcs_config.pin_based_exec_ctrl);
1909
1910         exec_control = vmcs_config.cpu_based_exec_ctrl;
1911         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1912                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1913 #ifdef CONFIG_X86_64
1914                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1915                                 CPU_BASED_CR8_LOAD_EXITING;
1916 #endif
1917         }
1918         if (!vm_need_ept())
1919                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1920                                 CPU_BASED_CR3_LOAD_EXITING;
1921         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1922
1923         if (cpu_has_secondary_exec_ctrls()) {
1924                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1925                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1926                         exec_control &=
1927                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1928                 if (vmx->vpid == 0)
1929                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1930                 if (!vm_need_ept())
1931                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
1932                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1933         }
1934
1935         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1936         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1937         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1938
1939         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1940         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1941         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1942
1943         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1944         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1945         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1946         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
1947         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
1948         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1949 #ifdef CONFIG_X86_64
1950         rdmsrl(MSR_FS_BASE, a);
1951         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1952         rdmsrl(MSR_GS_BASE, a);
1953         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1954 #else
1955         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1956         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1957 #endif
1958
1959         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1960
1961         kvm_get_idt(&dt);
1962         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1963
1964         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1965         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1966         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1967         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1968         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1969
1970         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1971         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1972         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1973         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1974         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1975         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1976
1977         for (i = 0; i < NR_VMX_MSR; ++i) {
1978                 u32 index = vmx_msr_index[i];
1979                 u32 data_low, data_high;
1980                 u64 data;
1981                 int j = vmx->nmsrs;
1982
1983                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1984                         continue;
1985                 if (wrmsr_safe(index, data_low, data_high) < 0)
1986                         continue;
1987                 data = data_low | ((u64)data_high << 32);
1988                 vmx->host_msrs[j].index = index;
1989                 vmx->host_msrs[j].reserved = 0;
1990                 vmx->host_msrs[j].data = data;
1991                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1992                 ++vmx->nmsrs;
1993         }
1994
1995         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1996
1997         /* 22.2.1, 20.8.1 */
1998         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1999
2000         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2001         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2002
2003
2004         return 0;
2005 }
2006
2007 static int init_rmode(struct kvm *kvm)
2008 {
2009         if (!init_rmode_tss(kvm))
2010                 return 0;
2011         if (!init_rmode_identity_map(kvm))
2012                 return 0;
2013         return 1;
2014 }
2015
2016 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2017 {
2018         struct vcpu_vmx *vmx = to_vmx(vcpu);
2019         u64 msr;
2020         int ret;
2021
2022         down_read(&vcpu->kvm->slots_lock);
2023         if (!init_rmode(vmx->vcpu.kvm)) {
2024                 ret = -ENOMEM;
2025                 goto out;
2026         }
2027
2028         vmx->vcpu.arch.rmode.active = 0;
2029
2030         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2031         kvm_set_cr8(&vmx->vcpu, 0);
2032         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2033         if (vmx->vcpu.vcpu_id == 0)
2034                 msr |= MSR_IA32_APICBASE_BSP;
2035         kvm_set_apic_base(&vmx->vcpu, msr);
2036
2037         fx_init(&vmx->vcpu);
2038
2039         /*
2040          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2041          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2042          */
2043         if (vmx->vcpu.vcpu_id == 0) {
2044                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2045                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2046         } else {
2047                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2048                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2049         }
2050         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2051         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2052
2053         seg_setup(VCPU_SREG_DS);
2054         seg_setup(VCPU_SREG_ES);
2055         seg_setup(VCPU_SREG_FS);
2056         seg_setup(VCPU_SREG_GS);
2057         seg_setup(VCPU_SREG_SS);
2058
2059         vmcs_write16(GUEST_TR_SELECTOR, 0);
2060         vmcs_writel(GUEST_TR_BASE, 0);
2061         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2062         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2063
2064         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2065         vmcs_writel(GUEST_LDTR_BASE, 0);
2066         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2067         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2068
2069         vmcs_write32(GUEST_SYSENTER_CS, 0);
2070         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2071         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2072
2073         vmcs_writel(GUEST_RFLAGS, 0x02);
2074         if (vmx->vcpu.vcpu_id == 0)
2075                 vmcs_writel(GUEST_RIP, 0xfff0);
2076         else
2077                 vmcs_writel(GUEST_RIP, 0);
2078         vmcs_writel(GUEST_RSP, 0);
2079
2080         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2081         vmcs_writel(GUEST_DR7, 0x400);
2082
2083         vmcs_writel(GUEST_GDTR_BASE, 0);
2084         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2085
2086         vmcs_writel(GUEST_IDTR_BASE, 0);
2087         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2088
2089         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2090         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2091         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2092
2093         guest_write_tsc(0);
2094
2095         /* Special registers */
2096         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2097
2098         setup_msrs(vmx);
2099
2100         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2101
2102         if (cpu_has_vmx_tpr_shadow()) {
2103                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2104                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2105                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2106                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2107                 vmcs_write32(TPR_THRESHOLD, 0);
2108         }
2109
2110         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2111                 vmcs_write64(APIC_ACCESS_ADDR,
2112                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2113
2114         if (vmx->vpid != 0)
2115                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2116
2117         vmx->vcpu.arch.cr0 = 0x60000010;
2118         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2119         vmx_set_cr4(&vmx->vcpu, 0);
2120         vmx_set_efer(&vmx->vcpu, 0);
2121         vmx_fpu_activate(&vmx->vcpu);
2122         update_exception_bitmap(&vmx->vcpu);
2123
2124         vpid_sync_vcpu_all(vmx);
2125
2126         ret = 0;
2127
2128 out:
2129         up_read(&vcpu->kvm->slots_lock);
2130         return ret;
2131 }
2132
2133 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2134 {
2135         struct vcpu_vmx *vmx = to_vmx(vcpu);
2136
2137         KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2138
2139         if (vcpu->arch.rmode.active) {
2140                 vmx->rmode.irq.pending = true;
2141                 vmx->rmode.irq.vector = irq;
2142                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
2143                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2144                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2145                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2146                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
2147                 return;
2148         }
2149         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2150                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2151 }
2152
2153 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2154 {
2155         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2156                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2157         vcpu->arch.nmi_pending = 0;
2158 }
2159
2160 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2161 {
2162         int word_index = __ffs(vcpu->arch.irq_summary);
2163         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2164         int irq = word_index * BITS_PER_LONG + bit_index;
2165
2166         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2167         if (!vcpu->arch.irq_pending[word_index])
2168                 clear_bit(word_index, &vcpu->arch.irq_summary);
2169         vmx_inject_irq(vcpu, irq);
2170 }
2171
2172
2173 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2174                                        struct kvm_run *kvm_run)
2175 {
2176         u32 cpu_based_vm_exec_control;
2177
2178         vcpu->arch.interrupt_window_open =
2179                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2180                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2181
2182         if (vcpu->arch.interrupt_window_open &&
2183             vcpu->arch.irq_summary &&
2184             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
2185                 /*
2186                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2187                  */
2188                 kvm_do_inject_irq(vcpu);
2189
2190         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2191         if (!vcpu->arch.interrupt_window_open &&
2192             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2193                 /*
2194                  * Interrupts blocked.  Wait for unblock.
2195                  */
2196                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2197         else
2198                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2199         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2200 }
2201
2202 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2203 {
2204         int ret;
2205         struct kvm_userspace_memory_region tss_mem = {
2206                 .slot = 8,
2207                 .guest_phys_addr = addr,
2208                 .memory_size = PAGE_SIZE * 3,
2209                 .flags = 0,
2210         };
2211
2212         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2213         if (ret)
2214                 return ret;
2215         kvm->arch.tss_addr = addr;
2216         return 0;
2217 }
2218
2219 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2220 {
2221         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2222
2223         set_debugreg(dbg->bp[0], 0);
2224         set_debugreg(dbg->bp[1], 1);
2225         set_debugreg(dbg->bp[2], 2);
2226         set_debugreg(dbg->bp[3], 3);
2227
2228         if (dbg->singlestep) {
2229                 unsigned long flags;
2230
2231                 flags = vmcs_readl(GUEST_RFLAGS);
2232                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2233                 vmcs_writel(GUEST_RFLAGS, flags);
2234         }
2235 }
2236
2237 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2238                                   int vec, u32 err_code)
2239 {
2240         if (!vcpu->arch.rmode.active)
2241                 return 0;
2242
2243         /*
2244          * Instruction with address size override prefix opcode 0x67
2245          * Cause the #SS fault with 0 error code in VM86 mode.
2246          */
2247         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2248                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2249                         return 1;
2250         return 0;
2251 }
2252
2253 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2254 {
2255         struct vcpu_vmx *vmx = to_vmx(vcpu);
2256         u32 intr_info, error_code;
2257         unsigned long cr2, rip;
2258         u32 vect_info;
2259         enum emulation_result er;
2260
2261         vect_info = vmx->idt_vectoring_info;
2262         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2263
2264         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2265                                                 !is_page_fault(intr_info))
2266                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2267                        "intr info 0x%x\n", __func__, vect_info, intr_info);
2268
2269         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2270                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2271                 set_bit(irq, vcpu->arch.irq_pending);
2272                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2273         }
2274
2275         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2276                 return 1;  /* already handled by vmx_vcpu_run() */
2277
2278         if (is_no_device(intr_info)) {
2279                 vmx_fpu_activate(vcpu);
2280                 return 1;
2281         }
2282
2283         if (is_invalid_opcode(intr_info)) {
2284                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2285                 if (er != EMULATE_DONE)
2286                         kvm_queue_exception(vcpu, UD_VECTOR);
2287                 return 1;
2288         }
2289
2290         error_code = 0;
2291         rip = vmcs_readl(GUEST_RIP);
2292         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2293                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2294         if (is_page_fault(intr_info)) {
2295                 /* EPT won't cause page fault directly */
2296                 if (vm_need_ept())
2297                         BUG();
2298                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2299                 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2300                             (u32)((u64)cr2 >> 32), handler);
2301                 if (vect_info & VECTORING_INFO_VALID_MASK)
2302                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
2303                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2304         }
2305
2306         if (vcpu->arch.rmode.active &&
2307             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2308                                                                 error_code)) {
2309                 if (vcpu->arch.halt_request) {
2310                         vcpu->arch.halt_request = 0;
2311                         return kvm_emulate_halt(vcpu);
2312                 }
2313                 return 1;
2314         }
2315
2316         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2317             (INTR_TYPE_EXCEPTION | 1)) {
2318                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2319                 return 0;
2320         }
2321         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2322         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2323         kvm_run->ex.error_code = error_code;
2324         return 0;
2325 }
2326
2327 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2328                                      struct kvm_run *kvm_run)
2329 {
2330         ++vcpu->stat.irq_exits;
2331         KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2332         return 1;
2333 }
2334
2335 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2336 {
2337         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2338         return 0;
2339 }
2340
2341 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2342 {
2343         unsigned long exit_qualification;
2344         int size, down, in, string, rep;
2345         unsigned port;
2346
2347         ++vcpu->stat.io_exits;
2348         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2349         string = (exit_qualification & 16) != 0;
2350
2351         if (string) {
2352                 if (emulate_instruction(vcpu,
2353                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2354                         return 0;
2355                 return 1;
2356         }
2357
2358         size = (exit_qualification & 7) + 1;
2359         in = (exit_qualification & 8) != 0;
2360         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2361         rep = (exit_qualification & 32) != 0;
2362         port = exit_qualification >> 16;
2363
2364         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2365 }
2366
2367 static void
2368 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2369 {
2370         /*
2371          * Patch in the VMCALL instruction:
2372          */
2373         hypercall[0] = 0x0f;
2374         hypercall[1] = 0x01;
2375         hypercall[2] = 0xc1;
2376 }
2377
2378 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2379 {
2380         unsigned long exit_qualification;
2381         int cr;
2382         int reg;
2383
2384         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2385         cr = exit_qualification & 15;
2386         reg = (exit_qualification >> 8) & 15;
2387         switch ((exit_qualification >> 4) & 3) {
2388         case 0: /* mov to cr */
2389                 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2390                             (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
2391                 switch (cr) {
2392                 case 0:
2393                         vcpu_load_rsp_rip(vcpu);
2394                         kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2395                         skip_emulated_instruction(vcpu);
2396                         return 1;
2397                 case 3:
2398                         vcpu_load_rsp_rip(vcpu);
2399                         kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2400                         skip_emulated_instruction(vcpu);
2401                         return 1;
2402                 case 4:
2403                         vcpu_load_rsp_rip(vcpu);
2404                         kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2405                         skip_emulated_instruction(vcpu);
2406                         return 1;
2407                 case 8:
2408                         vcpu_load_rsp_rip(vcpu);
2409                         kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2410                         skip_emulated_instruction(vcpu);
2411                         if (irqchip_in_kernel(vcpu->kvm))
2412                                 return 1;
2413                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2414                         return 0;
2415                 };
2416                 break;
2417         case 2: /* clts */
2418                 vcpu_load_rsp_rip(vcpu);
2419                 vmx_fpu_deactivate(vcpu);
2420                 vcpu->arch.cr0 &= ~X86_CR0_TS;
2421                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2422                 vmx_fpu_activate(vcpu);
2423                 KVMTRACE_0D(CLTS, vcpu, handler);
2424                 skip_emulated_instruction(vcpu);
2425                 return 1;
2426         case 1: /*mov from cr*/
2427                 switch (cr) {
2428                 case 3:
2429                         vcpu_load_rsp_rip(vcpu);
2430                         vcpu->arch.regs[reg] = vcpu->arch.cr3;
2431                         vcpu_put_rsp_rip(vcpu);
2432                         KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2433                                     (u32)vcpu->arch.regs[reg],
2434                                     (u32)((u64)vcpu->arch.regs[reg] >> 32),
2435                                     handler);
2436                         skip_emulated_instruction(vcpu);
2437                         return 1;
2438                 case 8:
2439                         vcpu_load_rsp_rip(vcpu);
2440                         vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2441                         vcpu_put_rsp_rip(vcpu);
2442                         KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2443                                     (u32)vcpu->arch.regs[reg], handler);
2444                         skip_emulated_instruction(vcpu);
2445                         return 1;
2446                 }
2447                 break;
2448         case 3: /* lmsw */
2449                 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2450
2451                 skip_emulated_instruction(vcpu);
2452                 return 1;
2453         default:
2454                 break;
2455         }
2456         kvm_run->exit_reason = 0;
2457         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2458                (int)(exit_qualification >> 4) & 3, cr);
2459         return 0;
2460 }
2461
2462 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2463 {
2464         unsigned long exit_qualification;
2465         unsigned long val;
2466         int dr, reg;
2467
2468         /*
2469          * FIXME: this code assumes the host is debugging the guest.
2470          *        need to deal with guest debugging itself too.
2471          */
2472         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2473         dr = exit_qualification & 7;
2474         reg = (exit_qualification >> 8) & 15;
2475         vcpu_load_rsp_rip(vcpu);
2476         if (exit_qualification & 16) {
2477                 /* mov from dr */
2478                 switch (dr) {
2479                 case 6:
2480                         val = 0xffff0ff0;
2481                         break;
2482                 case 7:
2483                         val = 0x400;
2484                         break;
2485                 default:
2486                         val = 0;
2487                 }
2488                 vcpu->arch.regs[reg] = val;
2489                 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2490         } else {
2491                 /* mov to dr */
2492         }
2493         vcpu_put_rsp_rip(vcpu);
2494         skip_emulated_instruction(vcpu);
2495         return 1;
2496 }
2497
2498 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2499 {
2500         kvm_emulate_cpuid(vcpu);
2501         return 1;
2502 }
2503
2504 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2505 {
2506         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2507         u64 data;
2508
2509         if (vmx_get_msr(vcpu, ecx, &data)) {
2510                 kvm_inject_gp(vcpu, 0);
2511                 return 1;
2512         }
2513
2514         KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2515                     handler);
2516
2517         /* FIXME: handling of bits 32:63 of rax, rdx */
2518         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2519         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2520         skip_emulated_instruction(vcpu);
2521         return 1;
2522 }
2523
2524 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2525 {
2526         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2527         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2528                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2529
2530         KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2531                     handler);
2532
2533         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2534                 kvm_inject_gp(vcpu, 0);
2535                 return 1;
2536         }
2537
2538         skip_emulated_instruction(vcpu);
2539         return 1;
2540 }
2541
2542 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2543                                       struct kvm_run *kvm_run)
2544 {
2545         return 1;
2546 }
2547
2548 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2549                                    struct kvm_run *kvm_run)
2550 {
2551         u32 cpu_based_vm_exec_control;
2552
2553         /* clear pending irq */
2554         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2555         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2556         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2557
2558         KVMTRACE_0D(PEND_INTR, vcpu, handler);
2559
2560         /*
2561          * If the user space waits to inject interrupts, exit as soon as
2562          * possible
2563          */
2564         if (kvm_run->request_interrupt_window &&
2565             !vcpu->arch.irq_summary) {
2566                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2567                 ++vcpu->stat.irq_window_exits;
2568                 return 0;
2569         }
2570         return 1;
2571 }
2572
2573 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2574 {
2575         skip_emulated_instruction(vcpu);
2576         return kvm_emulate_halt(vcpu);
2577 }
2578
2579 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2580 {
2581         skip_emulated_instruction(vcpu);
2582         kvm_emulate_hypercall(vcpu);
2583         return 1;
2584 }
2585
2586 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2587 {
2588         skip_emulated_instruction(vcpu);
2589         /* TODO: Add support for VT-d/pass-through device */
2590         return 1;
2591 }
2592
2593 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2594 {
2595         u64 exit_qualification;
2596         enum emulation_result er;
2597         unsigned long offset;
2598
2599         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2600         offset = exit_qualification & 0xffful;
2601
2602         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2603
2604         if (er !=  EMULATE_DONE) {
2605                 printk(KERN_ERR
2606                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2607                        offset);
2608                 return -ENOTSUPP;
2609         }
2610         return 1;
2611 }
2612
2613 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2614 {
2615         unsigned long exit_qualification;
2616         u16 tss_selector;
2617         int reason;
2618
2619         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2620
2621         reason = (u32)exit_qualification >> 30;
2622         tss_selector = exit_qualification;
2623
2624         return kvm_task_switch(vcpu, tss_selector, reason);
2625 }
2626
2627 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2628 {
2629         u64 exit_qualification;
2630         enum emulation_result er;
2631         gpa_t gpa;
2632         unsigned long hva;
2633         int gla_validity;
2634         int r;
2635
2636         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2637
2638         if (exit_qualification & (1 << 6)) {
2639                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2640                 return -ENOTSUPP;
2641         }
2642
2643         gla_validity = (exit_qualification >> 7) & 0x3;
2644         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2645                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2646                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2647                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2648                         (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2649                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2650                         (long unsigned int)exit_qualification);
2651                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2652                 kvm_run->hw.hardware_exit_reason = 0;
2653                 return -ENOTSUPP;
2654         }
2655
2656         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2657         hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2658         if (!kvm_is_error_hva(hva)) {
2659                 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2660                 if (r < 0) {
2661                         printk(KERN_ERR "EPT: Not enough memory!\n");
2662                         return -ENOMEM;
2663                 }
2664                 return 1;
2665         } else {
2666                 /* must be MMIO */
2667                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2668
2669                 if (er == EMULATE_FAIL) {
2670                         printk(KERN_ERR
2671                          "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2672                          er);
2673                         printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2674                          (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2675                          (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2676                         printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2677                                 (long unsigned int)exit_qualification);
2678                         return -ENOTSUPP;
2679                 } else if (er == EMULATE_DO_MMIO)
2680                         return 0;
2681         }
2682         return 1;
2683 }
2684
2685 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2686 {
2687         u32 cpu_based_vm_exec_control;
2688
2689         /* clear pending NMI */
2690         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2691         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2692         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2693         ++vcpu->stat.nmi_window_exits;
2694
2695         return 1;
2696 }
2697
2698 /*
2699  * The exit handlers return 1 if the exit was handled fully and guest execution
2700  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2701  * to be done to userspace and return 0.
2702  */
2703 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2704                                       struct kvm_run *kvm_run) = {
2705         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2706         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2707         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2708         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
2709         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2710         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2711         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2712         [EXIT_REASON_CPUID]                   = handle_cpuid,
2713         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2714         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2715         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2716         [EXIT_REASON_HLT]                     = handle_halt,
2717         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2718         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2719         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2720         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2721         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
2722         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
2723 };
2724
2725 static const int kvm_vmx_max_exit_handlers =
2726         ARRAY_SIZE(kvm_vmx_exit_handlers);
2727
2728 /*
2729  * The guest has exited.  See if we can fix it or if we need userspace
2730  * assistance.
2731  */
2732 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2733 {
2734         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2735         struct vcpu_vmx *vmx = to_vmx(vcpu);
2736         u32 vectoring_info = vmx->idt_vectoring_info;
2737
2738         KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2739                     (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2740
2741         /* Access CR3 don't cause VMExit in paging mode, so we need
2742          * to sync with guest real CR3. */
2743         if (vm_need_ept() && is_paging(vcpu)) {
2744                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2745                 ept_load_pdptrs(vcpu);
2746         }
2747
2748         if (unlikely(vmx->fail)) {
2749                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2750                 kvm_run->fail_entry.hardware_entry_failure_reason
2751                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2752                 return 0;
2753         }
2754
2755         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2756                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2757                         exit_reason != EXIT_REASON_EPT_VIOLATION))
2758                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2759                        "exit reason is 0x%x\n", __func__, exit_reason);
2760         if (exit_reason < kvm_vmx_max_exit_handlers
2761             && kvm_vmx_exit_handlers[exit_reason])
2762                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2763         else {
2764                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2765                 kvm_run->hw.hardware_exit_reason = exit_reason;
2766         }
2767         return 0;
2768 }
2769
2770 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2771 {
2772         int max_irr, tpr;
2773
2774         if (!vm_need_tpr_shadow(vcpu->kvm))
2775                 return;
2776
2777         if (!kvm_lapic_enabled(vcpu) ||
2778             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2779                 vmcs_write32(TPR_THRESHOLD, 0);
2780                 return;
2781         }
2782
2783         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2784         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2785 }
2786
2787 static void enable_irq_window(struct kvm_vcpu *vcpu)
2788 {
2789         u32 cpu_based_vm_exec_control;
2790
2791         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2792         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2793         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2794 }
2795
2796 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2797 {
2798         u32 cpu_based_vm_exec_control;
2799
2800         if (!cpu_has_virtual_nmis())
2801                 return;
2802
2803         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2804         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2805         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2806 }
2807
2808 static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
2809 {
2810         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2811         return !(guest_intr & (GUEST_INTR_STATE_NMI |
2812                                GUEST_INTR_STATE_MOV_SS |
2813                                GUEST_INTR_STATE_STI));
2814 }
2815
2816 static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
2817 {
2818         u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2819         return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
2820                                GUEST_INTR_STATE_STI)) &&
2821                 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2822 }
2823
2824 static void enable_intr_window(struct kvm_vcpu *vcpu)
2825 {
2826         if (vcpu->arch.nmi_pending)
2827                 enable_nmi_window(vcpu);
2828         else if (kvm_cpu_has_interrupt(vcpu))
2829                 enable_irq_window(vcpu);
2830 }
2831
2832 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2833 {
2834         struct vcpu_vmx *vmx = to_vmx(vcpu);
2835         u32 idtv_info_field, intr_info_field, exit_intr_info_field;
2836         int vector;
2837
2838         update_tpr_threshold(vcpu);
2839
2840         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2841         exit_intr_info_field = vmcs_read32(VM_EXIT_INTR_INFO);
2842         idtv_info_field = vmx->idt_vectoring_info;
2843         if (intr_info_field & INTR_INFO_VALID_MASK) {
2844                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2845                         /* TODO: fault when IDT_Vectoring */
2846                         if (printk_ratelimit())
2847                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2848                 }
2849                 enable_intr_window(vcpu);
2850                 return;
2851         }
2852         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2853                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2854                     == INTR_TYPE_EXT_INTR
2855                     && vcpu->arch.rmode.active) {
2856                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2857
2858                         vmx_inject_irq(vcpu, vect);
2859                         enable_intr_window(vcpu);
2860                         return;
2861                 }
2862
2863                 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2864
2865                 /*
2866                  * SDM 3: 25.7.1.2
2867                  * Clear bit "block by NMI" before VM entry if a NMI delivery
2868                  * faulted.
2869                  */
2870                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2871                     == INTR_TYPE_NMI_INTR && cpu_has_virtual_nmis())
2872                         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2873                                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2874                                 ~GUEST_INTR_STATE_NMI);
2875
2876                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field
2877                                 & ~INTR_INFO_RESVD_BITS_MASK);
2878                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2879                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2880
2881                 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2882                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2883                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2884                 enable_intr_window(vcpu);
2885                 return;
2886         }
2887         if (cpu_has_virtual_nmis()) {
2888                 /*
2889                  * SDM 3: 25.7.1.2
2890                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
2891                  * a guest IRET fault.
2892                  */
2893                 if ((exit_intr_info_field & INTR_INFO_UNBLOCK_NMI) &&
2894                     (exit_intr_info_field & INTR_INFO_VECTOR_MASK) != 8)
2895                         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2896                                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) |
2897                                 GUEST_INTR_STATE_NMI);
2898                 else if (vcpu->arch.nmi_pending) {
2899                         if (vmx_nmi_enabled(vcpu))
2900                                 vmx_inject_nmi(vcpu);
2901                         enable_intr_window(vcpu);
2902                         return;
2903                 }
2904
2905         }
2906         if (!kvm_cpu_has_interrupt(vcpu))
2907                 return;
2908         if (vmx_irq_enabled(vcpu)) {
2909                 vector = kvm_cpu_get_interrupt(vcpu);
2910                 vmx_inject_irq(vcpu, vector);
2911                 kvm_timer_intr_post(vcpu, vector);
2912         } else
2913                 enable_irq_window(vcpu);
2914 }
2915
2916 /*
2917  * Failure to inject an interrupt should give us the information
2918  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2919  * when fetching the interrupt redirection bitmap in the real-mode
2920  * tss, this doesn't happen.  So we do it ourselves.
2921  */
2922 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2923 {
2924         vmx->rmode.irq.pending = 0;
2925         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2926                 return;
2927         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2928         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2929                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2930                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2931                 return;
2932         }
2933         vmx->idt_vectoring_info =
2934                 VECTORING_INFO_VALID_MASK
2935                 | INTR_TYPE_EXT_INTR
2936                 | vmx->rmode.irq.vector;
2937 }
2938
2939 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2940 {
2941         struct vcpu_vmx *vmx = to_vmx(vcpu);
2942         u32 intr_info;
2943
2944         /*
2945          * Loading guest fpu may have cleared host cr0.ts
2946          */
2947         vmcs_writel(HOST_CR0, read_cr0());
2948
2949         asm(
2950                 /* Store host registers */
2951 #ifdef CONFIG_X86_64
2952                 "push %%rdx; push %%rbp;"
2953                 "push %%rcx \n\t"
2954 #else
2955                 "push %%edx; push %%ebp;"
2956                 "push %%ecx \n\t"
2957 #endif
2958                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
2959                 /* Check if vmlaunch of vmresume is needed */
2960                 "cmpl $0, %c[launched](%0) \n\t"
2961                 /* Load guest registers.  Don't clobber flags. */
2962 #ifdef CONFIG_X86_64
2963                 "mov %c[cr2](%0), %%rax \n\t"
2964                 "mov %%rax, %%cr2 \n\t"
2965                 "mov %c[rax](%0), %%rax \n\t"
2966                 "mov %c[rbx](%0), %%rbx \n\t"
2967                 "mov %c[rdx](%0), %%rdx \n\t"
2968                 "mov %c[rsi](%0), %%rsi \n\t"
2969                 "mov %c[rdi](%0), %%rdi \n\t"
2970                 "mov %c[rbp](%0), %%rbp \n\t"
2971                 "mov %c[r8](%0),  %%r8  \n\t"
2972                 "mov %c[r9](%0),  %%r9  \n\t"
2973                 "mov %c[r10](%0), %%r10 \n\t"
2974                 "mov %c[r11](%0), %%r11 \n\t"
2975                 "mov %c[r12](%0), %%r12 \n\t"
2976                 "mov %c[r13](%0), %%r13 \n\t"
2977                 "mov %c[r14](%0), %%r14 \n\t"
2978                 "mov %c[r15](%0), %%r15 \n\t"
2979                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2980 #else
2981                 "mov %c[cr2](%0), %%eax \n\t"
2982                 "mov %%eax,   %%cr2 \n\t"
2983                 "mov %c[rax](%0), %%eax \n\t"
2984                 "mov %c[rbx](%0), %%ebx \n\t"
2985                 "mov %c[rdx](%0), %%edx \n\t"
2986                 "mov %c[rsi](%0), %%esi \n\t"
2987                 "mov %c[rdi](%0), %%edi \n\t"
2988                 "mov %c[rbp](%0), %%ebp \n\t"
2989                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2990 #endif
2991                 /* Enter guest mode */
2992                 "jne .Llaunched \n\t"
2993                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
2994                 "jmp .Lkvm_vmx_return \n\t"
2995                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
2996                 ".Lkvm_vmx_return: "
2997                 /* Save guest registers, load host registers, keep flags */
2998 #ifdef CONFIG_X86_64
2999                 "xchg %0,     (%%rsp) \n\t"
3000                 "mov %%rax, %c[rax](%0) \n\t"
3001                 "mov %%rbx, %c[rbx](%0) \n\t"
3002                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
3003                 "mov %%rdx, %c[rdx](%0) \n\t"
3004                 "mov %%rsi, %c[rsi](%0) \n\t"
3005                 "mov %%rdi, %c[rdi](%0) \n\t"
3006                 "mov %%rbp, %c[rbp](%0) \n\t"
3007                 "mov %%r8,  %c[r8](%0) \n\t"
3008                 "mov %%r9,  %c[r9](%0) \n\t"
3009                 "mov %%r10, %c[r10](%0) \n\t"
3010                 "mov %%r11, %c[r11](%0) \n\t"
3011                 "mov %%r12, %c[r12](%0) \n\t"
3012                 "mov %%r13, %c[r13](%0) \n\t"
3013                 "mov %%r14, %c[r14](%0) \n\t"
3014                 "mov %%r15, %c[r15](%0) \n\t"
3015                 "mov %%cr2, %%rax   \n\t"
3016                 "mov %%rax, %c[cr2](%0) \n\t"
3017
3018                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
3019 #else
3020                 "xchg %0, (%%esp) \n\t"
3021                 "mov %%eax, %c[rax](%0) \n\t"
3022                 "mov %%ebx, %c[rbx](%0) \n\t"
3023                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
3024                 "mov %%edx, %c[rdx](%0) \n\t"
3025                 "mov %%esi, %c[rsi](%0) \n\t"
3026                 "mov %%edi, %c[rdi](%0) \n\t"
3027                 "mov %%ebp, %c[rbp](%0) \n\t"
3028                 "mov %%cr2, %%eax  \n\t"
3029                 "mov %%eax, %c[cr2](%0) \n\t"
3030
3031                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
3032 #endif
3033                 "setbe %c[fail](%0) \n\t"
3034               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3035                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3036                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3037                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3038                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3039                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3040                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3041                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3042                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3043                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3044 #ifdef CONFIG_X86_64
3045                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3046                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3047                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3048                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3049                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3050                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3051                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3052                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3053 #endif
3054                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3055               : "cc", "memory"
3056 #ifdef CONFIG_X86_64
3057                 , "rbx", "rdi", "rsi"
3058                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3059 #else
3060                 , "ebx", "edi", "rsi"
3061 #endif
3062               );
3063
3064         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3065         if (vmx->rmode.irq.pending)
3066                 fixup_rmode_irq(vmx);
3067
3068         vcpu->arch.interrupt_window_open =
3069                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3070                  (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
3071
3072         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3073         vmx->launched = 1;
3074
3075         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3076
3077         /* We need to handle NMIs before interrupts are enabled */
3078         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3079             (intr_info & INTR_INFO_VALID_MASK)) {
3080                 KVMTRACE_0D(NMI, vcpu, handler);
3081                 asm("int $2");
3082         }
3083 }
3084
3085 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3086 {
3087         struct vcpu_vmx *vmx = to_vmx(vcpu);
3088
3089         if (vmx->vmcs) {
3090                 vcpu_clear(vmx);
3091                 free_vmcs(vmx->vmcs);
3092                 vmx->vmcs = NULL;
3093         }
3094 }
3095
3096 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3097 {
3098         struct vcpu_vmx *vmx = to_vmx(vcpu);
3099
3100         spin_lock(&vmx_vpid_lock);
3101         if (vmx->vpid != 0)
3102                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3103         spin_unlock(&vmx_vpid_lock);
3104         vmx_free_vmcs(vcpu);
3105         kfree(vmx->host_msrs);
3106         kfree(vmx->guest_msrs);
3107         kvm_vcpu_uninit(vcpu);
3108         kmem_cache_free(kvm_vcpu_cache, vmx);
3109 }
3110
3111 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3112 {
3113         int err;
3114         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3115         int cpu;
3116
3117         if (!vmx)
3118                 return ERR_PTR(-ENOMEM);
3119
3120         allocate_vpid(vmx);
3121
3122         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3123         if (err)
3124                 goto free_vcpu;
3125
3126         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3127         if (!vmx->guest_msrs) {
3128                 err = -ENOMEM;
3129                 goto uninit_vcpu;
3130         }
3131
3132         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3133         if (!vmx->host_msrs)
3134                 goto free_guest_msrs;
3135
3136         vmx->vmcs = alloc_vmcs();
3137         if (!vmx->vmcs)
3138                 goto free_msrs;
3139
3140         vmcs_clear(vmx->vmcs);
3141
3142         cpu = get_cpu();
3143         vmx_vcpu_load(&vmx->vcpu, cpu);
3144         err = vmx_vcpu_setup(vmx);
3145         vmx_vcpu_put(&vmx->vcpu);
3146         put_cpu();
3147         if (err)
3148                 goto free_vmcs;
3149         if (vm_need_virtualize_apic_accesses(kvm))
3150                 if (alloc_apic_access_page(kvm) != 0)
3151                         goto free_vmcs;
3152
3153         if (vm_need_ept())
3154                 if (alloc_identity_pagetable(kvm) != 0)
3155                         goto free_vmcs;
3156
3157         return &vmx->vcpu;
3158
3159 free_vmcs:
3160         free_vmcs(vmx->vmcs);
3161 free_msrs:
3162         kfree(vmx->host_msrs);
3163 free_guest_msrs:
3164         kfree(vmx->guest_msrs);
3165 uninit_vcpu:
3166         kvm_vcpu_uninit(&vmx->vcpu);
3167 free_vcpu:
3168         kmem_cache_free(kvm_vcpu_cache, vmx);
3169         return ERR_PTR(err);
3170 }
3171
3172 static void __init vmx_check_processor_compat(void *rtn)
3173 {
3174         struct vmcs_config vmcs_conf;
3175
3176         *(int *)rtn = 0;
3177         if (setup_vmcs_config(&vmcs_conf) < 0)
3178                 *(int *)rtn = -EIO;
3179         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3180                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3181                                 smp_processor_id());
3182                 *(int *)rtn = -EIO;
3183         }
3184 }
3185
3186 static int get_ept_level(void)
3187 {
3188         return VMX_EPT_DEFAULT_GAW + 1;
3189 }
3190
3191 static struct kvm_x86_ops vmx_x86_ops = {
3192         .cpu_has_kvm_support = cpu_has_kvm_support,
3193         .disabled_by_bios = vmx_disabled_by_bios,
3194         .hardware_setup = hardware_setup,
3195         .hardware_unsetup = hardware_unsetup,
3196         .check_processor_compatibility = vmx_check_processor_compat,
3197         .hardware_enable = hardware_enable,
3198         .hardware_disable = hardware_disable,
3199         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3200
3201         .vcpu_create = vmx_create_vcpu,
3202         .vcpu_free = vmx_free_vcpu,
3203         .vcpu_reset = vmx_vcpu_reset,
3204
3205         .prepare_guest_switch = vmx_save_host_state,
3206         .vcpu_load = vmx_vcpu_load,
3207         .vcpu_put = vmx_vcpu_put,
3208
3209         .set_guest_debug = set_guest_debug,
3210         .guest_debug_pre = kvm_guest_debug_pre,
3211         .get_msr = vmx_get_msr,
3212         .set_msr = vmx_set_msr,
3213         .get_segment_base = vmx_get_segment_base,
3214         .get_segment = vmx_get_segment,
3215         .set_segment = vmx_set_segment,
3216         .get_cpl = vmx_get_cpl,
3217         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3218         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3219         .set_cr0 = vmx_set_cr0,
3220         .set_cr3 = vmx_set_cr3,
3221         .set_cr4 = vmx_set_cr4,
3222         .set_efer = vmx_set_efer,
3223         .get_idt = vmx_get_idt,
3224         .set_idt = vmx_set_idt,
3225         .get_gdt = vmx_get_gdt,
3226         .set_gdt = vmx_set_gdt,
3227         .cache_regs = vcpu_load_rsp_rip,
3228         .decache_regs = vcpu_put_rsp_rip,
3229         .get_rflags = vmx_get_rflags,
3230         .set_rflags = vmx_set_rflags,
3231
3232         .tlb_flush = vmx_flush_tlb,
3233
3234         .run = vmx_vcpu_run,
3235         .handle_exit = kvm_handle_exit,
3236         .skip_emulated_instruction = skip_emulated_instruction,
3237         .patch_hypercall = vmx_patch_hypercall,
3238         .get_irq = vmx_get_irq,
3239         .set_irq = vmx_inject_irq,
3240         .queue_exception = vmx_queue_exception,
3241         .exception_injected = vmx_exception_injected,
3242         .inject_pending_irq = vmx_intr_assist,
3243         .inject_pending_vectors = do_interrupt_requests,
3244
3245         .set_tss_addr = vmx_set_tss_addr,
3246         .get_tdp_level = get_ept_level,
3247 };
3248
3249 static int __init vmx_init(void)
3250 {
3251         void *va;
3252         int r;
3253
3254         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3255         if (!vmx_io_bitmap_a)
3256                 return -ENOMEM;
3257
3258         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3259         if (!vmx_io_bitmap_b) {
3260                 r = -ENOMEM;
3261                 goto out;
3262         }
3263
3264         vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3265         if (!vmx_msr_bitmap) {
3266                 r = -ENOMEM;
3267                 goto out1;
3268         }
3269
3270         /*
3271          * Allow direct access to the PC debug port (it is often used for I/O
3272          * delays, but the vmexits simply slow things down).
3273          */
3274         va = kmap(vmx_io_bitmap_a);
3275         memset(va, 0xff, PAGE_SIZE);
3276         clear_bit(0x80, va);
3277         kunmap(vmx_io_bitmap_a);
3278
3279         va = kmap(vmx_io_bitmap_b);
3280         memset(va, 0xff, PAGE_SIZE);
3281         kunmap(vmx_io_bitmap_b);
3282
3283         va = kmap(vmx_msr_bitmap);
3284         memset(va, 0xff, PAGE_SIZE);
3285         kunmap(vmx_msr_bitmap);
3286
3287         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3288
3289         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3290         if (r)
3291                 goto out2;
3292
3293         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3294         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3295         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3296         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3297         vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3298
3299         if (vm_need_ept()) {
3300                 bypass_guest_pf = 0;
3301                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3302                         VMX_EPT_WRITABLE_MASK |
3303                         VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3304                 kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
3305                                 VMX_EPT_FAKE_DIRTY_MASK, 0ull,
3306                                 VMX_EPT_EXECUTABLE_MASK);
3307                 kvm_enable_tdp();
3308         } else
3309                 kvm_disable_tdp();
3310
3311         if (bypass_guest_pf)
3312                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3313
3314         ept_sync_global();
3315
3316         return 0;
3317
3318 out2:
3319         __free_page(vmx_msr_bitmap);
3320 out1:
3321         __free_page(vmx_io_bitmap_b);
3322 out:
3323         __free_page(vmx_io_bitmap_a);
3324         return r;
3325 }
3326
3327 static void __exit vmx_exit(void)
3328 {
3329         __free_page(vmx_msr_bitmap);
3330         __free_page(vmx_io_bitmap_b);
3331         __free_page(vmx_io_bitmap_a);
3332
3333         kvm_exit();
3334 }
3335
3336 module_init(vmx_init)
3337 module_exit(vmx_exit)