git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  44 static DEFINE_MUTEX(pvr2_unit_mtx);
  45
  46 static int ctlchg;
  47 static int initusbreset = 1;
  48 static int procreload;
  49 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  50 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  51 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  52 static int init_pause_msec;
  53
  54 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  55 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  56 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  57 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  58 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  59 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  60 module_param(procreload, int, S_IRUGO|S_IWUSR);
  61 MODULE_PARM_DESC(procreload,
  62                  "Attempt init failure recovery with firmware reload");
  63 module_param_array(tuner,    int, NULL, 0444);
  64 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  65 module_param_array(video_std,    int, NULL, 0444);
  66 MODULE_PARM_DESC(video_std,"specify initial video standard");
  67 module_param_array(tolerance,    int, NULL, 0444);
  68 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  69
  70 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  71 #define PVR2_CTL_READ_ENDPOINT   0x81
  72
  73 #define PVR2_GPIO_IN 0x9008
  74 #define PVR2_GPIO_OUT 0x900c
  75 #define PVR2_GPIO_DIR 0x9020
  76
  77 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  78
  79 #define PVR2_FIRMWARE_ENDPOINT   0x02
  80
  81 /* size of a firmware chunk */
  82 #define FIRMWARE_CHUNK_SIZE 0x2000
  83
  84 /* Define the list of additional controls we'll dynamically construct based
  85    on query of the cx2341x module. */
  86 struct pvr2_mpeg_ids {
  87         const char *strid;
  88         int id;
  89 };
  90 static const struct pvr2_mpeg_ids mpeg_ids[] = {
  91         {
  92                 .strid = "audio_layer",
  93                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
  94         },{
  95                 .strid = "audio_bitrate",
  96                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
  97         },{
  98                 /* Already using audio_mode elsewhere :-( */
  99                 .strid = "mpeg_audio_mode",
 100                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 101         },{
 102                 .strid = "mpeg_audio_mode_extension",
 103                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 104         },{
 105                 .strid = "audio_emphasis",
 106                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 107         },{
 108                 .strid = "audio_crc",
 109                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 110         },{
 111                 .strid = "video_aspect",
 112                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 113         },{
 114                 .strid = "video_b_frames",
 115                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 116         },{
 117                 .strid = "video_gop_size",
 118                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 119         },{
 120                 .strid = "video_gop_closure",
 121                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 122         },{
 123                 .strid = "video_bitrate_mode",
 124                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 125         },{
 126                 .strid = "video_bitrate",
 127                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 128         },{
 129                 .strid = "video_bitrate_peak",
 130                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 131         },{
 132                 .strid = "video_temporal_decimation",
 133                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 134         },{
 135                 .strid = "stream_type",
 136                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 137         },{
 138                 .strid = "video_spatial_filter_mode",
 139                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 140         },{
 141                 .strid = "video_spatial_filter",
 142                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 143         },{
 144                 .strid = "video_luma_spatial_filter_type",
 145                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 146         },{
 147                 .strid = "video_chroma_spatial_filter_type",
 148                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 149         },{
 150                 .strid = "video_temporal_filter_mode",
 151                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 152         },{
 153                 .strid = "video_temporal_filter",
 154                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 155         },{
 156                 .strid = "video_median_filter_type",
 157                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 158         },{
 159                 .strid = "video_luma_median_filter_top",
 160                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 161         },{
 162                 .strid = "video_luma_median_filter_bottom",
 163                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 164         },{
 165                 .strid = "video_chroma_median_filter_top",
 166                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 167         },{
 168                 .strid = "video_chroma_median_filter_bottom",
 169                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 170         }
 171 };
 172 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 173
 174
 175 static const char *control_values_srate[] = {
 176         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 177         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 178         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 179 };
 180
 181
 182
 183 static const char *control_values_input[] = {
 184         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 185         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 186         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 187         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 188         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 189 };
 190
 191
 192 static const char *control_values_audiomode[] = {
 193         [V4L2_TUNER_MODE_MONO]   = "Mono",
 194         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 195         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 196         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 197         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 198 };
 199
 200
 201 static const char *control_values_hsm[] = {
 202         [PVR2_CVAL_HSM_FAIL] = "Fail",
 203         [PVR2_CVAL_HSM_HIGH] = "High",
 204         [PVR2_CVAL_HSM_FULL] = "Full",
 205 };
 206
 207
 208 static const char *pvr2_state_names[] = {
 209         [PVR2_STATE_NONE] =    "none",
 210         [PVR2_STATE_DEAD] =    "dead",
 211         [PVR2_STATE_COLD] =    "cold",
 212         [PVR2_STATE_WARM] =    "warm",
 213         [PVR2_STATE_ERROR] =   "error",
 214         [PVR2_STATE_READY] =   "ready",
 215         [PVR2_STATE_RUN] =     "run",
 216 };
 217
 218
 219 struct pvr2_fx2cmd_descdef {
 220         unsigned char id;
 221         unsigned char *desc;
 222 };
 223
 224 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 225         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 226         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 227         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 228         {FX2CMD_REG_WRITE, "write encoder register"},
 229         {FX2CMD_REG_READ, "read encoder register"},
 230         {FX2CMD_MEMSEL, "encoder memsel"},
 231         {FX2CMD_I2C_WRITE, "i2c write"},
 232         {FX2CMD_I2C_READ, "i2c read"},
 233         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 234         {FX2CMD_STREAMING_ON, "stream on"},
 235         {FX2CMD_STREAMING_OFF, "stream off"},
 236         {FX2CMD_FWPOST1, "fwpost1"},
 237         {FX2CMD_POWER_OFF, "power off"},
 238         {FX2CMD_POWER_ON, "power on"},
 239         {FX2CMD_DEEP_RESET, "deep reset"},
 240         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 241         {FX2CMD_GET_IR_CODE, "get IR code"},
 242         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 243         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 244         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 245         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 246         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 247         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 248         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 249 };
 250
 251
 252 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 253 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 254 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 255 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 256 static void pvr2_hdw_worker_poll(struct work_struct *work);
 257 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 258 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 259 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 260 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 261 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 262 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 263 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 264 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 265 static void pvr2_hdw_quiescent_timeout(unsigned long);
 266 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 267 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 268 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 269 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 270                                 unsigned int timeout,int probe_fl,
 271                                 void *write_data,unsigned int write_len,
 272                                 void *read_data,unsigned int read_len);
 273
 274
 275 static void trace_stbit(const char *name,int val)
 276 {
 277         pvr2_trace(PVR2_TRACE_STBITS,
 278                    "State bit %s <-- %s",
 279                    name,(val ? "true" : "false"));
 280 }
 281
 282 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 283 {
 284         struct pvr2_hdw *hdw = cptr->hdw;
 285         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 286                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 287         } else {
 288                 *vp = 0;
 289         }
 290         return 0;
 291 }
 292
 293 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 294 {
 295         struct pvr2_hdw *hdw = cptr->hdw;
 296         unsigned int slotId = hdw->freqProgSlot;
 297         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 298                 hdw->freqTable[slotId-1] = v;
 299                 /* Handle side effects correctly - if we're tuned to this
 300                    slot, then forgot the slot id relation since the stored
 301                    frequency has been changed. */
 302                 if (hdw->freqSelector) {
 303                         if (hdw->freqSlotRadio == slotId) {
 304                                 hdw->freqSlotRadio = 0;
 305                         }
 306                 } else {
 307                         if (hdw->freqSlotTelevision == slotId) {
 308                                 hdw->freqSlotTelevision = 0;
 309                         }
 310                 }
 311         }
 312         return 0;
 313 }
 314
 315 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 316 {
 317         *vp = cptr->hdw->freqProgSlot;
 318         return 0;
 319 }
 320
 321 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 322 {
 323         struct pvr2_hdw *hdw = cptr->hdw;
 324         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 325                 hdw->freqProgSlot = v;
 326         }
 327         return 0;
 328 }
 329
 330 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 331 {
 332         struct pvr2_hdw *hdw = cptr->hdw;
 333         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 334         return 0;
 335 }
 336
 337 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 338 {
 339         unsigned freq = 0;
 340         struct pvr2_hdw *hdw = cptr->hdw;
 341         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 342         if (slotId > 0) {
 343                 freq = hdw->freqTable[slotId-1];
 344                 if (!freq) return 0;
 345                 pvr2_hdw_set_cur_freq(hdw,freq);
 346         }
 347         if (hdw->freqSelector) {
 348                 hdw->freqSlotRadio = slotId;
 349         } else {
 350                 hdw->freqSlotTelevision = slotId;
 351         }
 352         return 0;
 353 }
 354
 355 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 356 {
 357         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 358         return 0;
 359 }
 360
 361 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 362 {
 363         return cptr->hdw->freqDirty != 0;
 364 }
 365
 366 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 367 {
 368         cptr->hdw->freqDirty = 0;
 369 }
 370
 371 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 372 {
 373         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 374         return 0;
 375 }
 376
 377 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 378 {
 379         /* Actual maximum depends on the video standard in effect. */
 380         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 381                 *vp = 480;
 382         } else {
 383                 *vp = 576;
 384         }
 385         return 0;
 386 }
 387
 388 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 389 {
 390         /* Actual minimum depends on device digitizer type. */
 391         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 392                 *vp = 75;
 393         } else {
 394                 *vp = 17;
 395         }
 396         return 0;
 397 }
 398
 399 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 400 {
 401         *vp = cptr->hdw->input_val;
 402         return 0;
 403 }
 404
 405 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 406 {
 407         return ((1 << v) & cptr->hdw->input_avail_mask) != 0;
 408 }
 409
 410 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 411 {
 412         struct pvr2_hdw *hdw = cptr->hdw;
 413
 414         if (hdw->input_val != v) {
 415                 hdw->input_val = v;
 416                 hdw->input_dirty = !0;
 417         }
 418
 419         /* Handle side effects - if we switch to a mode that needs the RF
 420            tuner, then select the right frequency choice as well and mark
 421            it dirty. */
 422         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 423                 hdw->freqSelector = 0;
 424                 hdw->freqDirty = !0;
 425         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
 426                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
 427                 hdw->freqSelector = 1;
 428                 hdw->freqDirty = !0;
 429         }
 430         return 0;
 431 }
 432
 433 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 434 {
 435         return cptr->hdw->input_dirty != 0;
 436 }
 437
 438 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 439 {
 440         cptr->hdw->input_dirty = 0;
 441 }
 442
 443
 444 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 445 {
 446         unsigned long fv;
 447         struct pvr2_hdw *hdw = cptr->hdw;
 448         if (hdw->tuner_signal_stale) {
 449                 pvr2_i2c_core_status_poll(hdw);
 450         }
 451         fv = hdw->tuner_signal_info.rangehigh;
 452         if (!fv) {
 453                 /* Safety fallback */
 454                 *vp = TV_MAX_FREQ;
 455                 return 0;
 456         }
 457         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 458                 fv = (fv * 125) / 2;
 459         } else {
 460                 fv = fv * 62500;
 461         }
 462         *vp = fv;
 463         return 0;
 464 }
 465
 466 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 467 {
 468         unsigned long fv;
 469         struct pvr2_hdw *hdw = cptr->hdw;
 470         if (hdw->tuner_signal_stale) {
 471                 pvr2_i2c_core_status_poll(hdw);
 472         }
 473         fv = hdw->tuner_signal_info.rangelow;
 474         if (!fv) {
 475                 /* Safety fallback */
 476                 *vp = TV_MIN_FREQ;
 477                 return 0;
 478         }
 479         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 480                 fv = (fv * 125) / 2;
 481         } else {
 482                 fv = fv * 62500;
 483         }
 484         *vp = fv;
 485         return 0;
 486 }
 487
 488 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 489 {
 490         return cptr->hdw->enc_stale != 0;
 491 }
 492
 493 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 494 {
 495         cptr->hdw->enc_stale = 0;
 496         cptr->hdw->enc_unsafe_stale = 0;
 497 }
 498
 499 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 500 {
 501         int ret;
 502         struct v4l2_ext_controls cs;
 503         struct v4l2_ext_control c1;
 504         memset(&cs,0,sizeof(cs));
 505         memset(&c1,0,sizeof(c1));
 506         cs.controls = &c1;
 507         cs.count = 1;
 508         c1.id = cptr->info->v4l_id;
 509         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 510                                 VIDIOC_G_EXT_CTRLS);
 511         if (ret) return ret;
 512         *vp = c1.value;
 513         return 0;
 514 }
 515
 516 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 517 {
 518         int ret;
 519         struct pvr2_hdw *hdw = cptr->hdw;
 520         struct v4l2_ext_controls cs;
 521         struct v4l2_ext_control c1;
 522         memset(&cs,0,sizeof(cs));
 523         memset(&c1,0,sizeof(c1));
 524         cs.controls = &c1;
 525         cs.count = 1;
 526         c1.id = cptr->info->v4l_id;
 527         c1.value = v;
 528         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 529                                 hdw->state_encoder_run, &cs,
 530                                 VIDIOC_S_EXT_CTRLS);
 531         if (ret == -EBUSY) {
 532                 /* Oops.  cx2341x is telling us it's not safe to change
 533                    this control while we're capturing.  Make a note of this
 534                    fact so that the pipeline will be stopped the next time
 535                    controls are committed.  Then go on ahead and store this
 536                    change anyway. */
 537                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 538                                         0, &cs,
 539                                         VIDIOC_S_EXT_CTRLS);
 540                 if (!ret) hdw->enc_unsafe_stale = !0;
 541         }
 542         if (ret) return ret;
 543         hdw->enc_stale = !0;
 544         return 0;
 545 }
 546
 547 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 548 {
 549         struct v4l2_queryctrl qctrl;
 550         struct pvr2_ctl_info *info;
 551         qctrl.id = cptr->info->v4l_id;
 552         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 553         /* Strip out the const so we can adjust a function pointer.  It's
 554            OK to do this here because we know this is a dynamically created
 555            control, so the underlying storage for the info pointer is (a)
 556            private to us, and (b) not in read-only storage.  Either we do
 557            this or we significantly complicate the underlying control
 558            implementation. */
 559         info = (struct pvr2_ctl_info *)(cptr->info);
 560         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 561                 if (info->set_value) {
 562                         info->set_value = NULL;
 563                 }
 564         } else {
 565                 if (!(info->set_value)) {
 566                         info->set_value = ctrl_cx2341x_set;
 567                 }
 568         }
 569         return qctrl.flags;
 570 }
 571
 572 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 573 {
 574         *vp = cptr->hdw->state_pipeline_req;
 575         return 0;
 576 }
 577
 578 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 579 {
 580         *vp = cptr->hdw->master_state;
 581         return 0;
 582 }
 583
 584 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 585 {
 586         int result = pvr2_hdw_is_hsm(cptr->hdw);
 587         *vp = PVR2_CVAL_HSM_FULL;
 588         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 589         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 590         return 0;
 591 }
 592
 593 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 594 {
 595         *vp = cptr->hdw->std_mask_avail;
 596         return 0;
 597 }
 598
 599 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 600 {
 601         struct pvr2_hdw *hdw = cptr->hdw;
 602         v4l2_std_id ns;
 603         ns = hdw->std_mask_avail;
 604         ns = (ns & ~m) | (v & m);
 605         if (ns == hdw->std_mask_avail) return 0;
 606         hdw->std_mask_avail = ns;
 607         pvr2_hdw_internal_set_std_avail(hdw);
 608         pvr2_hdw_internal_find_stdenum(hdw);
 609         return 0;
 610 }
 611
 612 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 613                                char *bufPtr,unsigned int bufSize,
 614                                unsigned int *len)
 615 {
 616         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 617         return 0;
 618 }
 619
 620 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 621                                const char *bufPtr,unsigned int bufSize,
 622                                int *mskp,int *valp)
 623 {
 624         int ret;
 625         v4l2_std_id id;
 626         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 627         if (ret < 0) return ret;
 628         if (mskp) *mskp = id;
 629         if (valp) *valp = id;
 630         return 0;
 631 }
 632
 633 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 634 {
 635         *vp = cptr->hdw->std_mask_cur;
 636         return 0;
 637 }
 638
 639 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 640 {
 641         struct pvr2_hdw *hdw = cptr->hdw;
 642         v4l2_std_id ns;
 643         ns = hdw->std_mask_cur;
 644         ns = (ns & ~m) | (v & m);
 645         if (ns == hdw->std_mask_cur) return 0;
 646         hdw->std_mask_cur = ns;
 647         hdw->std_dirty = !0;
 648         pvr2_hdw_internal_find_stdenum(hdw);
 649         return 0;
 650 }
 651
 652 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 653 {
 654         return cptr->hdw->std_dirty != 0;
 655 }
 656
 657 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 658 {
 659         cptr->hdw->std_dirty = 0;
 660 }
 661
 662 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 663 {
 664         struct pvr2_hdw *hdw = cptr->hdw;
 665         pvr2_i2c_core_status_poll(hdw);
 666         *vp = hdw->tuner_signal_info.signal;
 667         return 0;
 668 }
 669
 670 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 671 {
 672         int val = 0;
 673         unsigned int subchan;
 674         struct pvr2_hdw *hdw = cptr->hdw;
 675         pvr2_i2c_core_status_poll(hdw);
 676         subchan = hdw->tuner_signal_info.rxsubchans;
 677         if (subchan & V4L2_TUNER_SUB_MONO) {
 678                 val |= (1 << V4L2_TUNER_MODE_MONO);
 679         }
 680         if (subchan & V4L2_TUNER_SUB_STEREO) {
 681                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 682         }
 683         if (subchan & V4L2_TUNER_SUB_LANG1) {
 684                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 685         }
 686         if (subchan & V4L2_TUNER_SUB_LANG2) {
 687                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 688         }
 689         *vp = val;
 690         return 0;
 691 }
 692
 693
 694 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 695 {
 696         struct pvr2_hdw *hdw = cptr->hdw;
 697         if (v < 0) return -EINVAL;
 698         if (v > hdw->std_enum_cnt) return -EINVAL;
 699         hdw->std_enum_cur = v;
 700         if (!v) return 0;
 701         v--;
 702         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 703         hdw->std_mask_cur = hdw->std_defs[v].id;
 704         hdw->std_dirty = !0;
 705         return 0;
 706 }
 707
 708
 709 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 710 {
 711         *vp = cptr->hdw->std_enum_cur;
 712         return 0;
 713 }
 714
 715
 716 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 717 {
 718         return cptr->hdw->std_dirty != 0;
 719 }
 720
 721
 722 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 723 {
 724         cptr->hdw->std_dirty = 0;
 725 }
 726
 727
 728 #define DEFINT(vmin,vmax) \
 729         .type = pvr2_ctl_int, \
 730         .def.type_int.min_value = vmin, \
 731         .def.type_int.max_value = vmax
 732
 733 #define DEFENUM(tab) \
 734         .type = pvr2_ctl_enum, \
 735         .def.type_enum.count = ARRAY_SIZE(tab), \
 736         .def.type_enum.value_names = tab
 737
 738 #define DEFBOOL \
 739         .type = pvr2_ctl_bool
 740
 741 #define DEFMASK(msk,tab) \
 742         .type = pvr2_ctl_bitmask, \
 743         .def.type_bitmask.valid_bits = msk, \
 744         .def.type_bitmask.bit_names = tab
 745
 746 #define DEFREF(vname) \
 747         .set_value = ctrl_set_##vname, \
 748         .get_value = ctrl_get_##vname, \
 749         .is_dirty = ctrl_isdirty_##vname, \
 750         .clear_dirty = ctrl_cleardirty_##vname
 751
 752
 753 #define VCREATE_FUNCS(vname) \
 754 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 755 {*vp = cptr->hdw->vname##_val; return 0;} \
 756 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 757 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 758 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 759 {return cptr->hdw->vname##_dirty != 0;} \
 760 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 761 {cptr->hdw->vname##_dirty = 0;}
 762
 763 VCREATE_FUNCS(brightness)
 764 VCREATE_FUNCS(contrast)
 765 VCREATE_FUNCS(saturation)
 766 VCREATE_FUNCS(hue)
 767 VCREATE_FUNCS(volume)
 768 VCREATE_FUNCS(balance)
 769 VCREATE_FUNCS(bass)
 770 VCREATE_FUNCS(treble)
 771 VCREATE_FUNCS(mute)
 772 VCREATE_FUNCS(audiomode)
 773 VCREATE_FUNCS(res_hor)
 774 VCREATE_FUNCS(res_ver)
 775 VCREATE_FUNCS(srate)
 776
 777 /* Table definition of all controls which can be manipulated */
 778 static const struct pvr2_ctl_info control_defs[] = {
 779         {
 780                 .v4l_id = V4L2_CID_BRIGHTNESS,
 781                 .desc = "Brightness",
 782                 .name = "brightness",
 783                 .default_value = 128,
 784                 DEFREF(brightness),
 785                 DEFINT(0,255),
 786         },{
 787                 .v4l_id = V4L2_CID_CONTRAST,
 788                 .desc = "Contrast",
 789                 .name = "contrast",
 790                 .default_value = 68,
 791                 DEFREF(contrast),
 792                 DEFINT(0,127),
 793         },{
 794                 .v4l_id = V4L2_CID_SATURATION,
 795                 .desc = "Saturation",
 796                 .name = "saturation",
 797                 .default_value = 64,
 798                 DEFREF(saturation),
 799                 DEFINT(0,127),
 800         },{
 801                 .v4l_id = V4L2_CID_HUE,
 802                 .desc = "Hue",
 803                 .name = "hue",
 804                 .default_value = 0,
 805                 DEFREF(hue),
 806                 DEFINT(-128,127),
 807         },{
 808                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 809                 .desc = "Volume",
 810                 .name = "volume",
 811                 .default_value = 62000,
 812                 DEFREF(volume),
 813                 DEFINT(0,65535),
 814         },{
 815                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 816                 .desc = "Balance",
 817                 .name = "balance",
 818                 .default_value = 0,
 819                 DEFREF(balance),
 820                 DEFINT(-32768,32767),
 821         },{
 822                 .v4l_id = V4L2_CID_AUDIO_BASS,
 823                 .desc = "Bass",
 824                 .name = "bass",
 825                 .default_value = 0,
 826                 DEFREF(bass),
 827                 DEFINT(-32768,32767),
 828         },{
 829                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 830                 .desc = "Treble",
 831                 .name = "treble",
 832                 .default_value = 0,
 833                 DEFREF(treble),
 834                 DEFINT(-32768,32767),
 835         },{
 836                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 837                 .desc = "Mute",
 838                 .name = "mute",
 839                 .default_value = 0,
 840                 DEFREF(mute),
 841                 DEFBOOL,
 842         },{
 843                 .desc = "Video Source",
 844                 .name = "input",
 845                 .internal_id = PVR2_CID_INPUT,
 846                 .default_value = PVR2_CVAL_INPUT_TV,
 847                 .check_value = ctrl_check_input,
 848                 DEFREF(input),
 849                 DEFENUM(control_values_input),
 850         },{
 851                 .desc = "Audio Mode",
 852                 .name = "audio_mode",
 853                 .internal_id = PVR2_CID_AUDIOMODE,
 854                 .default_value = V4L2_TUNER_MODE_STEREO,
 855                 DEFREF(audiomode),
 856                 DEFENUM(control_values_audiomode),
 857         },{
 858                 .desc = "Horizontal capture resolution",
 859                 .name = "resolution_hor",
 860                 .internal_id = PVR2_CID_HRES,
 861                 .default_value = 720,
 862                 DEFREF(res_hor),
 863                 DEFINT(19,720),
 864         },{
 865                 .desc = "Vertical capture resolution",
 866                 .name = "resolution_ver",
 867                 .internal_id = PVR2_CID_VRES,
 868                 .default_value = 480,
 869                 DEFREF(res_ver),
 870                 DEFINT(17,576),
 871                 /* Hook in check for video standard and adjust maximum
 872                    depending on the standard. */
 873                 .get_max_value = ctrl_vres_max_get,
 874                 .get_min_value = ctrl_vres_min_get,
 875         },{
 876                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 877                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 878                 .desc = "Audio Sampling Frequency",
 879                 .name = "srate",
 880                 DEFREF(srate),
 881                 DEFENUM(control_values_srate),
 882         },{
 883                 .desc = "Tuner Frequency (Hz)",
 884                 .name = "frequency",
 885                 .internal_id = PVR2_CID_FREQUENCY,
 886                 .default_value = 0,
 887                 .set_value = ctrl_freq_set,
 888                 .get_value = ctrl_freq_get,
 889                 .is_dirty = ctrl_freq_is_dirty,
 890                 .clear_dirty = ctrl_freq_clear_dirty,
 891                 DEFINT(0,0),
 892                 /* Hook in check for input value (tv/radio) and adjust
 893                    max/min values accordingly */
 894                 .get_max_value = ctrl_freq_max_get,
 895                 .get_min_value = ctrl_freq_min_get,
 896         },{
 897                 .desc = "Channel",
 898                 .name = "channel",
 899                 .set_value = ctrl_channel_set,
 900                 .get_value = ctrl_channel_get,
 901                 DEFINT(0,FREQTABLE_SIZE),
 902         },{
 903                 .desc = "Channel Program Frequency",
 904                 .name = "freq_table_value",
 905                 .set_value = ctrl_channelfreq_set,
 906                 .get_value = ctrl_channelfreq_get,
 907                 DEFINT(0,0),
 908                 /* Hook in check for input value (tv/radio) and adjust
 909                    max/min values accordingly */
 910                 .get_max_value = ctrl_freq_max_get,
 911                 .get_min_value = ctrl_freq_min_get,
 912         },{
 913                 .desc = "Channel Program ID",
 914                 .name = "freq_table_channel",
 915                 .set_value = ctrl_channelprog_set,
 916                 .get_value = ctrl_channelprog_get,
 917                 DEFINT(0,FREQTABLE_SIZE),
 918         },{
 919                 .desc = "Streaming Enabled",
 920                 .name = "streaming_enabled",
 921                 .get_value = ctrl_streamingenabled_get,
 922                 DEFBOOL,
 923         },{
 924                 .desc = "USB Speed",
 925                 .name = "usb_speed",
 926                 .get_value = ctrl_hsm_get,
 927                 DEFENUM(control_values_hsm),
 928         },{
 929                 .desc = "Master State",
 930                 .name = "master_state",
 931                 .get_value = ctrl_masterstate_get,
 932                 DEFENUM(pvr2_state_names),
 933         },{
 934                 .desc = "Signal Present",
 935                 .name = "signal_present",
 936                 .get_value = ctrl_signal_get,
 937                 DEFINT(0,65535),
 938         },{
 939                 .desc = "Audio Modes Present",
 940                 .name = "audio_modes_present",
 941                 .get_value = ctrl_audio_modes_present_get,
 942                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
 943                    v4l.  Nothing outside of this module cares about this,
 944                    but I reuse it in order to also reuse the
 945                    control_values_audiomode string table. */
 946                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
 947                          (1 << V4L2_TUNER_MODE_STEREO)|
 948                          (1 << V4L2_TUNER_MODE_LANG1)|
 949                          (1 << V4L2_TUNER_MODE_LANG2)),
 950                         control_values_audiomode),
 951         },{
 952                 .desc = "Video Standards Available Mask",
 953                 .name = "video_standard_mask_available",
 954                 .internal_id = PVR2_CID_STDAVAIL,
 955                 .skip_init = !0,
 956                 .get_value = ctrl_stdavail_get,
 957                 .set_value = ctrl_stdavail_set,
 958                 .val_to_sym = ctrl_std_val_to_sym,
 959                 .sym_to_val = ctrl_std_sym_to_val,
 960                 .type = pvr2_ctl_bitmask,
 961         },{
 962                 .desc = "Video Standards In Use Mask",
 963                 .name = "video_standard_mask_active",
 964                 .internal_id = PVR2_CID_STDCUR,
 965                 .skip_init = !0,
 966                 .get_value = ctrl_stdcur_get,
 967                 .set_value = ctrl_stdcur_set,
 968                 .is_dirty = ctrl_stdcur_is_dirty,
 969                 .clear_dirty = ctrl_stdcur_clear_dirty,
 970                 .val_to_sym = ctrl_std_val_to_sym,
 971                 .sym_to_val = ctrl_std_sym_to_val,
 972                 .type = pvr2_ctl_bitmask,
 973         },{
 974                 .desc = "Video Standard Name",
 975                 .name = "video_standard",
 976                 .internal_id = PVR2_CID_STDENUM,
 977                 .skip_init = !0,
 978                 .get_value = ctrl_stdenumcur_get,
 979                 .set_value = ctrl_stdenumcur_set,
 980                 .is_dirty = ctrl_stdenumcur_is_dirty,
 981                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 982                 .type = pvr2_ctl_enum,
 983         }
 984 };
 985
 986 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
 987
 988
 989 const char *pvr2_config_get_name(enum pvr2_config cfg)
 990 {
 991         switch (cfg) {
 992         case pvr2_config_empty: return "empty";
 993         case pvr2_config_mpeg: return "mpeg";
 994         case pvr2_config_vbi: return "vbi";
 995         case pvr2_config_pcm: return "pcm";
 996         case pvr2_config_rawvideo: return "raw video";
 997         }
 998         return "<unknown>";
 999 }
1000
1001
1002 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1003 {
1004         return hdw->usb_dev;
1005 }
1006
1007
1008 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1009 {
1010         return hdw->serial_number;
1011 }
1012
1013
1014 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1015 {
1016         return hdw->bus_info;
1017 }
1018
1019
1020 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1021 {
1022         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1023 }
1024
1025 /* Set the currently tuned frequency and account for all possible
1026    driver-core side effects of this action. */
1027 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1028 {
1029         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1030                 if (hdw->freqSelector) {
1031                         /* Swing over to radio frequency selection */
1032                         hdw->freqSelector = 0;
1033                         hdw->freqDirty = !0;
1034                 }
1035                 if (hdw->freqValRadio != val) {
1036                         hdw->freqValRadio = val;
1037                         hdw->freqSlotRadio = 0;
1038                         hdw->freqDirty = !0;
1039                 }
1040         } else {
1041                 if (!(hdw->freqSelector)) {
1042                         /* Swing over to television frequency selection */
1043                         hdw->freqSelector = 1;
1044                         hdw->freqDirty = !0;
1045                 }
1046                 if (hdw->freqValTelevision != val) {
1047                         hdw->freqValTelevision = val;
1048                         hdw->freqSlotTelevision = 0;
1049                         hdw->freqDirty = !0;
1050                 }
1051         }
1052 }
1053
1054 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1055 {
1056         return hdw->unit_number;
1057 }
1058
1059
1060 /* Attempt to locate one of the given set of files.  Messages are logged
1061    appropriate to what has been found.  The return value will be 0 or
1062    greater on success (it will be the index of the file name found) and
1063    fw_entry will be filled in.  Otherwise a negative error is returned on
1064    failure.  If the return value is -ENOENT then no viable firmware file
1065    could be located. */
1066 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1067                                 const struct firmware **fw_entry,
1068                                 const char *fwtypename,
1069                                 unsigned int fwcount,
1070                                 const char *fwnames[])
1071 {
1072         unsigned int idx;
1073         int ret = -EINVAL;
1074         for (idx = 0; idx < fwcount; idx++) {
1075                 ret = request_firmware(fw_entry,
1076                                        fwnames[idx],
1077                                        &hdw->usb_dev->dev);
1078                 if (!ret) {
1079                         trace_firmware("Located %s firmware: %s;"
1080                                        " uploading...",
1081                                        fwtypename,
1082                                        fwnames[idx]);
1083                         return idx;
1084                 }
1085                 if (ret == -ENOENT) continue;
1086                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1087                            "request_firmware fatal error with code=%d",ret);
1088                 return ret;
1089         }
1090         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1091                    "***WARNING***"
1092                    " Device %s firmware"
1093                    " seems to be missing.",
1094                    fwtypename);
1095         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1096                    "Did you install the pvrusb2 firmware files"
1097                    " in their proper location?");
1098         if (fwcount == 1) {
1099                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1100                            "request_firmware unable to locate %s file %s",
1101                            fwtypename,fwnames[0]);
1102         } else {
1103                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1104                            "request_firmware unable to locate"
1105                            " one of the following %s files:",
1106                            fwtypename);
1107                 for (idx = 0; idx < fwcount; idx++) {
1108                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1109                                    "request_firmware: Failed to find %s",
1110                                    fwnames[idx]);
1111                 }
1112         }
1113         return ret;
1114 }
1115
1116
1117 /*
1118  * pvr2_upload_firmware1().
1119  *
1120  * Send the 8051 firmware to the device.  After the upload, arrange for
1121  * device to re-enumerate.
1122  *
1123  * NOTE : the pointer to the firmware data given by request_firmware()
1124  * is not suitable for an usb transaction.
1125  *
1126  */
1127 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1128 {
1129         const struct firmware *fw_entry = NULL;
1130         void  *fw_ptr;
1131         unsigned int pipe;
1132         int ret;
1133         u16 address;
1134
1135         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1136                 hdw->fw1_state = FW1_STATE_OK;
1137                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1138                            "Connected device type defines"
1139                            " no firmware to upload; ignoring firmware");
1140                 return -ENOTTY;
1141         }
1142
1143         hdw->fw1_state = FW1_STATE_FAILED; // default result
1144
1145         trace_firmware("pvr2_upload_firmware1");
1146
1147         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1148                                    hdw->hdw_desc->fx2_firmware.cnt,
1149                                    hdw->hdw_desc->fx2_firmware.lst);
1150         if (ret < 0) {
1151                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1152                 return ret;
1153         }
1154
1155         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1156         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1157
1158         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1159
1160         if (fw_entry->size != 0x2000){
1161                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1162                 release_firmware(fw_entry);
1163                 return -ENOMEM;
1164         }
1165
1166         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1167         if (fw_ptr == NULL){
1168                 release_firmware(fw_entry);
1169                 return -ENOMEM;
1170         }
1171
1172         /* We have to hold the CPU during firmware upload. */
1173         pvr2_hdw_cpureset_assert(hdw,1);
1174
1175         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1176            chunk. */
1177
1178         ret = 0;
1179         for(address = 0; address < fw_entry->size; address += 0x800) {
1180                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1181                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1182                                        0, fw_ptr, 0x800, HZ);
1183         }
1184
1185         trace_firmware("Upload done, releasing device's CPU");
1186
1187         /* Now release the CPU.  It will disconnect and reconnect later. */
1188         pvr2_hdw_cpureset_assert(hdw,0);
1189
1190         kfree(fw_ptr);
1191         release_firmware(fw_entry);
1192
1193         trace_firmware("Upload done (%d bytes sent)",ret);
1194
1195         /* We should have written 8192 bytes */
1196         if (ret == 8192) {
1197                 hdw->fw1_state = FW1_STATE_RELOAD;
1198                 return 0;
1199         }
1200
1201         return -EIO;
1202 }
1203
1204
1205 /*
1206  * pvr2_upload_firmware2()
1207  *
1208  * This uploads encoder firmware on endpoint 2.
1209  *
1210  */
1211
1212 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1213 {
1214         const struct firmware *fw_entry = NULL;
1215         void  *fw_ptr;
1216         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1217         int actual_length;
1218         int ret = 0;
1219         int fwidx;
1220         static const char *fw_files[] = {
1221                 CX2341X_FIRM_ENC_FILENAME,
1222         };
1223
1224         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1225                 return 0;
1226         }
1227
1228         trace_firmware("pvr2_upload_firmware2");
1229
1230         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1231                                    ARRAY_SIZE(fw_files), fw_files);
1232         if (ret < 0) return ret;
1233         fwidx = ret;
1234         ret = 0;
1235         /* Since we're about to completely reinitialize the encoder,
1236            invalidate our cached copy of its configuration state.  Next
1237            time we configure the encoder, then we'll fully configure it. */
1238         hdw->enc_cur_valid = 0;
1239
1240         /* Encoder is about to be reset so note that as far as we're
1241            concerned now, the encoder has never been run. */
1242         del_timer_sync(&hdw->encoder_run_timer);
1243         if (hdw->state_encoder_runok) {
1244                 hdw->state_encoder_runok = 0;
1245                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1246         }
1247
1248         /* First prepare firmware loading */
1249         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1250         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1251         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1252         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1253         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1254         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1255         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1256         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1257         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1258         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1259         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1260         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1261         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1262         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1263         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1264         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1265         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1266         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1267
1268         if (ret) {
1269                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1270                            "firmware2 upload prep failed, ret=%d",ret);
1271                 release_firmware(fw_entry);
1272                 return ret;
1273         }
1274
1275         /* Now send firmware */
1276
1277         fw_len = fw_entry->size;
1278
1279         if (fw_len % sizeof(u32)) {
1280                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1281                            "size of %s firmware"
1282                            " must be a multiple of %zu bytes",
1283                            fw_files[fwidx],sizeof(u32));
1284                 release_firmware(fw_entry);
1285                 return -1;
1286         }
1287
1288         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1289         if (fw_ptr == NULL){
1290                 release_firmware(fw_entry);
1291                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1292                            "failed to allocate memory for firmware2 upload");
1293                 return -ENOMEM;
1294         }
1295
1296         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1297
1298         fw_done = 0;
1299         for (fw_done = 0; fw_done < fw_len;) {
1300                 bcnt = fw_len - fw_done;
1301                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1302                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1303                 /* Usbsnoop log shows that we must swap bytes... */
1304                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1305                         ((u32 *)fw_ptr)[icnt] =
1306                                 ___swab32(((u32 *)fw_ptr)[icnt]);
1307
1308                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1309                                     &actual_length, HZ);
1310                 ret |= (actual_length != bcnt);
1311                 if (ret) break;
1312                 fw_done += bcnt;
1313         }
1314
1315         trace_firmware("upload of %s : %i / %i ",
1316                        fw_files[fwidx],fw_done,fw_len);
1317
1318         kfree(fw_ptr);
1319         release_firmware(fw_entry);
1320
1321         if (ret) {
1322                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1323                            "firmware2 upload transfer failure");
1324                 return ret;
1325         }
1326
1327         /* Finish upload */
1328
1329         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1330         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1331         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1332
1333         if (ret) {
1334                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335                            "firmware2 upload post-proc failure");
1336         }
1337         return ret;
1338 }
1339
1340
1341 static const char *pvr2_get_state_name(unsigned int st)
1342 {
1343         if (st < ARRAY_SIZE(pvr2_state_names)) {
1344                 return pvr2_state_names[st];
1345         }
1346         return "???";
1347 }
1348
1349 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1350 {
1351         if (!hdw->decoder_ctrl) {
1352                 if (!hdw->flag_decoder_missed) {
1353                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1354                                    "WARNING: No decoder present");
1355                         hdw->flag_decoder_missed = !0;
1356                         trace_stbit("flag_decoder_missed",
1357                                     hdw->flag_decoder_missed);
1358                 }
1359                 return -EIO;
1360         }
1361         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1362         return 0;
1363 }
1364
1365
1366 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1367 {
1368         if (hdw->decoder_ctrl == ptr) return;
1369         hdw->decoder_ctrl = ptr;
1370         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1371                 hdw->flag_decoder_missed = 0;
1372                 trace_stbit("flag_decoder_missed",
1373                             hdw->flag_decoder_missed);
1374                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1375                            "Decoder has appeared");
1376                 pvr2_hdw_state_sched(hdw);
1377         }
1378 }
1379
1380
1381 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1382 {
1383         return hdw->master_state;
1384 }
1385
1386
1387 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1388 {
1389         if (!hdw->flag_tripped) return 0;
1390         hdw->flag_tripped = 0;
1391         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1392                    "Clearing driver error statuss");
1393         return !0;
1394 }
1395
1396
1397 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1398 {
1399         int fl;
1400         LOCK_TAKE(hdw->big_lock); do {
1401                 fl = pvr2_hdw_untrip_unlocked(hdw);
1402         } while (0); LOCK_GIVE(hdw->big_lock);
1403         if (fl) pvr2_hdw_state_sched(hdw);
1404         return 0;
1405 }
1406
1407
1408 const char *pvr2_hdw_get_state_name(unsigned int id)
1409 {
1410         if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1411         return pvr2_state_names[id];
1412 }
1413
1414
1415 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1416 {
1417         return hdw->state_pipeline_req != 0;
1418 }
1419
1420
1421 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1422 {
1423         int ret,st;
1424         LOCK_TAKE(hdw->big_lock); do {
1425                 pvr2_hdw_untrip_unlocked(hdw);
1426                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1427                         hdw->state_pipeline_req = enable_flag != 0;
1428                         pvr2_trace(PVR2_TRACE_START_STOP,
1429                                    "/*--TRACE_STREAM--*/ %s",
1430                                    enable_flag ? "enable" : "disable");
1431                 }
1432                 pvr2_hdw_state_sched(hdw);
1433         } while (0); LOCK_GIVE(hdw->big_lock);
1434         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1435         if (enable_flag) {
1436                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1437                         if (st != PVR2_STATE_READY) return -EIO;
1438                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1439                 }
1440         }
1441         return 0;
1442 }
1443
1444
1445 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1446 {
1447         int fl;
1448         LOCK_TAKE(hdw->big_lock);
1449         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1450                 hdw->desired_stream_type = config;
1451                 hdw->state_pipeline_config = 0;
1452                 trace_stbit("state_pipeline_config",
1453                             hdw->state_pipeline_config);
1454                 pvr2_hdw_state_sched(hdw);
1455         }
1456         LOCK_GIVE(hdw->big_lock);
1457         if (fl) return 0;
1458         return pvr2_hdw_wait(hdw,0);
1459 }
1460
1461
1462 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1463 {
1464         int unit_number = hdw->unit_number;
1465         int tp = -1;
1466         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1467                 tp = tuner[unit_number];
1468         }
1469         if (tp < 0) return -EINVAL;
1470         hdw->tuner_type = tp;
1471         hdw->tuner_updated = !0;
1472         return 0;
1473 }
1474
1475
1476 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1477 {
1478         int unit_number = hdw->unit_number;
1479         int tp = 0;
1480         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1481                 tp = video_std[unit_number];
1482                 if (tp) return tp;
1483         }
1484         return 0;
1485 }
1486
1487
1488 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1489 {
1490         int unit_number = hdw->unit_number;
1491         int tp = 0;
1492         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1493                 tp = tolerance[unit_number];
1494         }
1495         return tp;
1496 }
1497
1498
1499 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1500 {
1501         /* Try a harmless request to fetch the eeprom's address over
1502            endpoint 1.  See what happens.  Only the full FX2 image can
1503            respond to this.  If this probe fails then likely the FX2
1504            firmware needs be loaded. */
1505         int result;
1506         LOCK_TAKE(hdw->ctl_lock); do {
1507                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1508                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1509                                            hdw->cmd_buffer,1,
1510                                            hdw->cmd_buffer,1);
1511                 if (result < 0) break;
1512         } while(0); LOCK_GIVE(hdw->ctl_lock);
1513         if (result) {
1514                 pvr2_trace(PVR2_TRACE_INIT,
1515                            "Probe of device endpoint 1 result status %d",
1516                            result);
1517         } else {
1518                 pvr2_trace(PVR2_TRACE_INIT,
1519                            "Probe of device endpoint 1 succeeded");
1520         }
1521         return result == 0;
1522 }
1523
1524 struct pvr2_std_hack {
1525         v4l2_std_id pat;  /* Pattern to match */
1526         v4l2_std_id msk;  /* Which bits we care about */
1527         v4l2_std_id std;  /* What additional standards or default to set */
1528 };
1529
1530 /* This data structure labels specific combinations of standards from
1531    tveeprom that we'll try to recognize.  If we recognize one, then assume
1532    a specified default standard to use.  This is here because tveeprom only
1533    tells us about available standards not the intended default standard (if
1534    any) for the device in question.  We guess the default based on what has
1535    been reported as available.  Note that this is only for guessing a
1536    default - which can always be overridden explicitly - and if the user
1537    has otherwise named a default then that default will always be used in
1538    place of this table. */
1539 static const struct pvr2_std_hack std_eeprom_maps[] = {
1540         {       /* PAL(B/G) */
1541                 .pat = V4L2_STD_B|V4L2_STD_GH,
1542                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1543         },
1544         {       /* NTSC(M) */
1545                 .pat = V4L2_STD_MN,
1546                 .std = V4L2_STD_NTSC_M,
1547         },
1548         {       /* PAL(I) */
1549                 .pat = V4L2_STD_PAL_I,
1550                 .std = V4L2_STD_PAL_I,
1551         },
1552         {       /* SECAM(L/L') */
1553                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1554                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1555         },
1556         {       /* PAL(D/D1/K) */
1557                 .pat = V4L2_STD_DK,
1558                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1559         },
1560 };
1561
1562 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1563 {
1564         char buf[40];
1565         unsigned int bcnt;
1566         v4l2_std_id std1,std2,std3;
1567
1568         std1 = get_default_standard(hdw);
1569         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1570
1571         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1572         pvr2_trace(PVR2_TRACE_STD,
1573                    "Supported video standard(s) reported available"
1574                    " in hardware: %.*s",
1575                    bcnt,buf);
1576
1577         hdw->std_mask_avail = hdw->std_mask_eeprom;
1578
1579         std2 = (std1|std3) & ~hdw->std_mask_avail;
1580         if (std2) {
1581                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1582                 pvr2_trace(PVR2_TRACE_STD,
1583                            "Expanding supported video standards"
1584                            " to include: %.*s",
1585                            bcnt,buf);
1586                 hdw->std_mask_avail |= std2;
1587         }
1588
1589         pvr2_hdw_internal_set_std_avail(hdw);
1590
1591         if (std1) {
1592                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1593                 pvr2_trace(PVR2_TRACE_STD,
1594                            "Initial video standard forced to %.*s",
1595                            bcnt,buf);
1596                 hdw->std_mask_cur = std1;
1597                 hdw->std_dirty = !0;
1598                 pvr2_hdw_internal_find_stdenum(hdw);
1599                 return;
1600         }
1601         if (std3) {
1602                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1603                 pvr2_trace(PVR2_TRACE_STD,
1604                            "Initial video standard"
1605                            " (determined by device type): %.*s",bcnt,buf);
1606                 hdw->std_mask_cur = std3;
1607                 hdw->std_dirty = !0;
1608                 pvr2_hdw_internal_find_stdenum(hdw);
1609                 return;
1610         }
1611
1612         {
1613                 unsigned int idx;
1614                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1615                         if (std_eeprom_maps[idx].msk ?
1616                             ((std_eeprom_maps[idx].pat ^
1617                              hdw->std_mask_eeprom) &
1618                              std_eeprom_maps[idx].msk) :
1619                             (std_eeprom_maps[idx].pat !=
1620                              hdw->std_mask_eeprom)) continue;
1621                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1622                                                   std_eeprom_maps[idx].std);
1623                         pvr2_trace(PVR2_TRACE_STD,
1624                                    "Initial video standard guessed as %.*s",
1625                                    bcnt,buf);
1626                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1627                         hdw->std_dirty = !0;
1628                         pvr2_hdw_internal_find_stdenum(hdw);
1629                         return;
1630                 }
1631         }
1632
1633         if (hdw->std_enum_cnt > 1) {
1634                 // Autoselect the first listed standard
1635                 hdw->std_enum_cur = 1;
1636                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1637                 hdw->std_dirty = !0;
1638                 pvr2_trace(PVR2_TRACE_STD,
1639                            "Initial video standard auto-selected to %s",
1640                            hdw->std_defs[hdw->std_enum_cur-1].name);
1641                 return;
1642         }
1643
1644         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1645                    "Unable to select a viable initial video standard");
1646 }
1647
1648
1649 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1650 {
1651         int ret;
1652         unsigned int idx;
1653         struct pvr2_ctrl *cptr;
1654         int reloadFl = 0;
1655         if (hdw->hdw_desc->fx2_firmware.cnt) {
1656                 if (!reloadFl) {
1657                         reloadFl =
1658                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1659                                  == 0);
1660                         if (reloadFl) {
1661                                 pvr2_trace(PVR2_TRACE_INIT,
1662                                            "USB endpoint config looks strange"
1663                                            "; possibly firmware needs to be"
1664                                            " loaded");
1665                         }
1666                 }
1667                 if (!reloadFl) {
1668                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1669                         if (reloadFl) {
1670                                 pvr2_trace(PVR2_TRACE_INIT,
1671                                            "Check for FX2 firmware failed"
1672                                            "; possibly firmware needs to be"
1673                                            " loaded");
1674                         }
1675                 }
1676                 if (reloadFl) {
1677                         if (pvr2_upload_firmware1(hdw) != 0) {
1678                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1679                                            "Failure uploading firmware1");
1680                         }
1681                         return;
1682                 }
1683         }
1684         hdw->fw1_state = FW1_STATE_OK;
1685
1686         if (initusbreset) {
1687                 pvr2_hdw_device_reset(hdw);
1688         }
1689         if (!pvr2_hdw_dev_ok(hdw)) return;
1690
1691         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1692                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1693         }
1694
1695         if (!hdw->hdw_desc->flag_no_powerup) {
1696                 pvr2_hdw_cmd_powerup(hdw);
1697                 if (!pvr2_hdw_dev_ok(hdw)) return;
1698         }
1699
1700         // This step MUST happen after the earlier powerup step.
1701         pvr2_i2c_core_init(hdw);
1702         if (!pvr2_hdw_dev_ok(hdw)) return;
1703
1704         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1705                 cptr = hdw->controls + idx;
1706                 if (cptr->info->skip_init) continue;
1707                 if (!cptr->info->set_value) continue;
1708                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1709         }
1710
1711         /* Set up special default values for the television and radio
1712            frequencies here.  It's not really important what these defaults
1713            are, but I set them to something usable in the Chicago area just
1714            to make driver testing a little easier. */
1715
1716         /* US Broadcast channel 7 (175.25 MHz) */
1717         hdw->freqValTelevision = 175250000L;
1718         /* 104.3 MHz, a usable FM station for my area */
1719         hdw->freqValRadio = 104300000L;
1720
1721         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1722         // thread-safe against the normal pvr2_send_request() mechanism.
1723         // (We should make it thread safe).
1724
1725         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1726                 ret = pvr2_hdw_get_eeprom_addr(hdw);
1727                 if (!pvr2_hdw_dev_ok(hdw)) return;
1728                 if (ret < 0) {
1729                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1730                                    "Unable to determine location of eeprom,"
1731                                    " skipping");
1732                 } else {
1733                         hdw->eeprom_addr = ret;
1734                         pvr2_eeprom_analyze(hdw);
1735                         if (!pvr2_hdw_dev_ok(hdw)) return;
1736                 }
1737         } else {
1738                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1739                 hdw->tuner_updated = !0;
1740                 hdw->std_mask_eeprom = V4L2_STD_ALL;
1741         }
1742
1743         pvr2_hdw_setup_std(hdw);
1744
1745         if (!get_default_tuner_type(hdw)) {
1746                 pvr2_trace(PVR2_TRACE_INIT,
1747                            "pvr2_hdw_setup: Tuner type overridden to %d",
1748                            hdw->tuner_type);
1749         }
1750
1751         pvr2_i2c_core_check_stale(hdw);
1752         hdw->tuner_updated = 0;
1753
1754         if (!pvr2_hdw_dev_ok(hdw)) return;
1755
1756         pvr2_hdw_commit_setup(hdw);
1757
1758         hdw->vid_stream = pvr2_stream_create();
1759         if (!pvr2_hdw_dev_ok(hdw)) return;
1760         pvr2_trace(PVR2_TRACE_INIT,
1761                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1762         if (hdw->vid_stream) {
1763                 idx = get_default_error_tolerance(hdw);
1764                 if (idx) {
1765                         pvr2_trace(PVR2_TRACE_INIT,
1766                                    "pvr2_hdw_setup: video stream %p"
1767                                    " setting tolerance %u",
1768                                    hdw->vid_stream,idx);
1769                 }
1770                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1771                                   PVR2_VID_ENDPOINT,idx);
1772         }
1773
1774         if (!pvr2_hdw_dev_ok(hdw)) return;
1775
1776         hdw->flag_init_ok = !0;
1777
1778         pvr2_hdw_state_sched(hdw);
1779 }
1780
1781
1782 /* Set up the structure and attempt to put the device into a usable state.
1783    This can be a time-consuming operation, which is why it is not done
1784    internally as part of the create() step. */
1785 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1786 {
1787         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1788         do {
1789                 pvr2_hdw_setup_low(hdw);
1790                 pvr2_trace(PVR2_TRACE_INIT,
1791                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1792                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1793                 if (pvr2_hdw_dev_ok(hdw)) {
1794                         if (hdw->flag_init_ok) {
1795                                 pvr2_trace(
1796                                         PVR2_TRACE_INFO,
1797                                         "Device initialization"
1798                                         " completed successfully.");
1799                                 break;
1800                         }
1801                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1802                                 pvr2_trace(
1803                                         PVR2_TRACE_INFO,
1804                                         "Device microcontroller firmware"
1805                                         " (re)loaded; it should now reset"
1806                                         " and reconnect.");
1807                                 break;
1808                         }
1809                         pvr2_trace(
1810                                 PVR2_TRACE_ERROR_LEGS,
1811                                 "Device initialization was not successful.");
1812                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1813                                 pvr2_trace(
1814                                         PVR2_TRACE_ERROR_LEGS,
1815                                         "Giving up since device"
1816                                         " microcontroller firmware"
1817                                         " appears to be missing.");
1818                                 break;
1819                         }
1820                 }
1821                 if (procreload) {
1822                         pvr2_trace(
1823                                 PVR2_TRACE_ERROR_LEGS,
1824                                 "Attempting pvrusb2 recovery by reloading"
1825                                 " primary firmware.");
1826                         pvr2_trace(
1827                                 PVR2_TRACE_ERROR_LEGS,
1828                                 "If this works, device should disconnect"
1829                                 " and reconnect in a sane state.");
1830                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1831                         pvr2_upload_firmware1(hdw);
1832                 } else {
1833                         pvr2_trace(
1834                                 PVR2_TRACE_ERROR_LEGS,
1835                                 "***WARNING*** pvrusb2 device hardware"
1836                                 " appears to be jammed"
1837                                 " and I can't clear it.");
1838                         pvr2_trace(
1839                                 PVR2_TRACE_ERROR_LEGS,
1840                                 "You might need to power cycle"
1841                                 " the pvrusb2 device"
1842                                 " in order to recover.");
1843                 }
1844         } while (0);
1845         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1846 }
1847
1848
1849 /* Perform second stage initialization.  Set callback pointer first so that
1850    we can avoid a possible initialization race (if the kernel thread runs
1851    before the callback has been set). */
1852 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1853                         void (*callback_func)(void *),
1854                         void *callback_data)
1855 {
1856         LOCK_TAKE(hdw->big_lock); do {
1857                 hdw->state_data = callback_data;
1858                 hdw->state_func = callback_func;
1859         } while (0); LOCK_GIVE(hdw->big_lock);
1860         pvr2_hdw_setup(hdw);
1861         return hdw->flag_init_ok;
1862 }
1863
1864
1865 /* Create, set up, and return a structure for interacting with the
1866    underlying hardware.  */
1867 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1868                                  const struct usb_device_id *devid)
1869 {
1870         unsigned int idx,cnt1,cnt2,m;
1871         struct pvr2_hdw *hdw;
1872         int valid_std_mask;
1873         struct pvr2_ctrl *cptr;
1874         const struct pvr2_device_desc *hdw_desc;
1875         __u8 ifnum;
1876         struct v4l2_queryctrl qctrl;
1877         struct pvr2_ctl_info *ciptr;
1878
1879         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
1880
1881         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1882         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1883                    hdw,hdw_desc->description);
1884         if (!hdw) goto fail;
1885
1886         init_timer(&hdw->quiescent_timer);
1887         hdw->quiescent_timer.data = (unsigned long)hdw;
1888         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1889
1890         init_timer(&hdw->encoder_wait_timer);
1891         hdw->encoder_wait_timer.data = (unsigned long)hdw;
1892         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1893
1894         init_timer(&hdw->encoder_run_timer);
1895         hdw->encoder_run_timer.data = (unsigned long)hdw;
1896         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
1897
1898         hdw->master_state = PVR2_STATE_DEAD;
1899
1900         init_waitqueue_head(&hdw->state_wait_data);
1901
1902         hdw->tuner_signal_stale = !0;
1903         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1904
1905         /* Calculate which inputs are OK */
1906         m = 0;
1907         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1908         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1909                 m |= 1 << PVR2_CVAL_INPUT_DTV;
1910         }
1911         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1912         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1913         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1914         hdw->input_avail_mask = m;
1915
1916         /* If not a hybrid device, pathway_state never changes.  So
1917            initialize it here to what it should forever be. */
1918         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1919                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1920         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1921                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1922         }
1923
1924         hdw->control_cnt = CTRLDEF_COUNT;
1925         hdw->control_cnt += MPEGDEF_COUNT;
1926         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1927                                 GFP_KERNEL);
1928         if (!hdw->controls) goto fail;
1929         hdw->hdw_desc = hdw_desc;
1930         for (idx = 0; idx < hdw->control_cnt; idx++) {
1931                 cptr = hdw->controls + idx;
1932                 cptr->hdw = hdw;
1933         }
1934         for (idx = 0; idx < 32; idx++) {
1935                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1936         }
1937         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1938                 cptr = hdw->controls + idx;
1939                 cptr->info = control_defs+idx;
1940         }
1941
1942         /* Ensure that default input choice is a valid one. */
1943         m = hdw->input_avail_mask;
1944         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1945                 if (!((1 << idx) & m)) continue;
1946                 hdw->input_val = idx;
1947                 break;
1948         }
1949
1950         /* Define and configure additional controls from cx2341x module. */
1951         hdw->mpeg_ctrl_info = kzalloc(
1952                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1953         if (!hdw->mpeg_ctrl_info) goto fail;
1954         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1955                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1956                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1957                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1958                 ciptr->name = mpeg_ids[idx].strid;
1959                 ciptr->v4l_id = mpeg_ids[idx].id;
1960                 ciptr->skip_init = !0;
1961                 ciptr->get_value = ctrl_cx2341x_get;
1962                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1963                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1964                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1965                 qctrl.id = ciptr->v4l_id;
1966                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1967                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1968                         ciptr->set_value = ctrl_cx2341x_set;
1969                 }
1970                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1971                         PVR2_CTLD_INFO_DESC_SIZE);
1972                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1973                 ciptr->default_value = qctrl.default_value;
1974                 switch (qctrl.type) {
1975                 default:
1976                 case V4L2_CTRL_TYPE_INTEGER:
1977                         ciptr->type = pvr2_ctl_int;
1978                         ciptr->def.type_int.min_value = qctrl.minimum;
1979                         ciptr->def.type_int.max_value = qctrl.maximum;
1980                         break;
1981                 case V4L2_CTRL_TYPE_BOOLEAN:
1982                         ciptr->type = pvr2_ctl_bool;
1983                         break;
1984                 case V4L2_CTRL_TYPE_MENU:
1985                         ciptr->type = pvr2_ctl_enum;
1986                         ciptr->def.type_enum.value_names =
1987                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1988                         for (cnt1 = 0;
1989                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1990                              cnt1++) { }
1991                         ciptr->def.type_enum.count = cnt1;
1992                         break;
1993                 }
1994                 cptr->info = ciptr;
1995         }
1996
1997         // Initialize video standard enum dynamic control
1998         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1999         if (cptr) {
2000                 memcpy(&hdw->std_info_enum,cptr->info,
2001                        sizeof(hdw->std_info_enum));
2002                 cptr->info = &hdw->std_info_enum;
2003
2004         }
2005         // Initialize control data regarding video standard masks
2006         valid_std_mask = pvr2_std_get_usable();
2007         for (idx = 0; idx < 32; idx++) {
2008                 if (!(valid_std_mask & (1 << idx))) continue;
2009                 cnt1 = pvr2_std_id_to_str(
2010                         hdw->std_mask_names[idx],
2011                         sizeof(hdw->std_mask_names[idx])-1,
2012                         1 << idx);
2013                 hdw->std_mask_names[idx][cnt1] = 0;
2014         }
2015         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2016         if (cptr) {
2017                 memcpy(&hdw->std_info_avail,cptr->info,
2018                        sizeof(hdw->std_info_avail));
2019                 cptr->info = &hdw->std_info_avail;
2020                 hdw->std_info_avail.def.type_bitmask.bit_names =
2021                         hdw->std_mask_ptrs;
2022                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2023                         valid_std_mask;
2024         }
2025         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2026         if (cptr) {
2027                 memcpy(&hdw->std_info_cur,cptr->info,
2028                        sizeof(hdw->std_info_cur));
2029                 cptr->info = &hdw->std_info_cur;
2030                 hdw->std_info_cur.def.type_bitmask.bit_names =
2031                         hdw->std_mask_ptrs;
2032                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2033                         valid_std_mask;
2034         }
2035
2036         hdw->eeprom_addr = -1;
2037         hdw->unit_number = -1;
2038         hdw->v4l_minor_number_video = -1;
2039         hdw->v4l_minor_number_vbi = -1;
2040         hdw->v4l_minor_number_radio = -1;
2041         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2042         if (!hdw->ctl_write_buffer) goto fail;
2043         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2044         if (!hdw->ctl_read_buffer) goto fail;
2045         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2046         if (!hdw->ctl_write_urb) goto fail;
2047         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2048         if (!hdw->ctl_read_urb) goto fail;
2049
2050         mutex_lock(&pvr2_unit_mtx); do {
2051                 for (idx = 0; idx < PVR_NUM; idx++) {
2052                         if (unit_pointers[idx]) continue;
2053                         hdw->unit_number = idx;
2054                         unit_pointers[idx] = hdw;
2055                         break;
2056                 }
2057         } while (0); mutex_unlock(&pvr2_unit_mtx);
2058
2059         cnt1 = 0;
2060         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2061         cnt1 += cnt2;
2062         if (hdw->unit_number >= 0) {
2063                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2064                                  ('a' + hdw->unit_number));
2065                 cnt1 += cnt2;
2066         }
2067         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2068         hdw->name[cnt1] = 0;
2069
2070         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2071         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2072         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2073
2074         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2075                    hdw->unit_number,hdw->name);
2076
2077         hdw->tuner_type = -1;
2078         hdw->flag_ok = !0;
2079
2080         hdw->usb_intf = intf;
2081         hdw->usb_dev = interface_to_usbdev(intf);
2082
2083         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2084                   "usb %s address %d",
2085                   hdw->usb_dev->dev.bus_id,
2086                   hdw->usb_dev->devnum);
2087
2088         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2089         usb_set_interface(hdw->usb_dev,ifnum,0);
2090
2091         mutex_init(&hdw->ctl_lock_mutex);
2092         mutex_init(&hdw->big_lock_mutex);
2093
2094         return hdw;
2095  fail:
2096         if (hdw) {
2097                 del_timer_sync(&hdw->quiescent_timer);
2098                 del_timer_sync(&hdw->encoder_run_timer);
2099                 del_timer_sync(&hdw->encoder_wait_timer);
2100                 if (hdw->workqueue) {
2101                         flush_workqueue(hdw->workqueue);
2102                         destroy_workqueue(hdw->workqueue);
2103                         hdw->workqueue = NULL;
2104                 }
2105                 usb_free_urb(hdw->ctl_read_urb);
2106                 usb_free_urb(hdw->ctl_write_urb);
2107                 kfree(hdw->ctl_read_buffer);
2108                 kfree(hdw->ctl_write_buffer);
2109                 kfree(hdw->controls);
2110                 kfree(hdw->mpeg_ctrl_info);
2111                 kfree(hdw->std_defs);
2112                 kfree(hdw->std_enum_names);
2113                 kfree(hdw);
2114         }
2115         return NULL;
2116 }
2117
2118
2119 /* Remove _all_ associations between this driver and the underlying USB
2120    layer. */
2121 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2122 {
2123         if (hdw->flag_disconnected) return;
2124         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2125         if (hdw->ctl_read_urb) {
2126                 usb_kill_urb(hdw->ctl_read_urb);
2127                 usb_free_urb(hdw->ctl_read_urb);
2128                 hdw->ctl_read_urb = NULL;
2129         }
2130         if (hdw->ctl_write_urb) {
2131                 usb_kill_urb(hdw->ctl_write_urb);
2132                 usb_free_urb(hdw->ctl_write_urb);
2133                 hdw->ctl_write_urb = NULL;
2134         }
2135         if (hdw->ctl_read_buffer) {
2136                 kfree(hdw->ctl_read_buffer);
2137                 hdw->ctl_read_buffer = NULL;
2138         }
2139         if (hdw->ctl_write_buffer) {
2140                 kfree(hdw->ctl_write_buffer);
2141                 hdw->ctl_write_buffer = NULL;
2142         }
2143         hdw->flag_disconnected = !0;
2144         hdw->usb_dev = NULL;
2145         hdw->usb_intf = NULL;
2146         pvr2_hdw_render_useless(hdw);
2147 }
2148
2149
2150 /* Destroy hardware interaction structure */
2151 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2152 {
2153         if (!hdw) return;
2154         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2155         if (hdw->workqueue) {
2156                 flush_workqueue(hdw->workqueue);
2157                 destroy_workqueue(hdw->workqueue);
2158                 hdw->workqueue = NULL;
2159         }
2160         del_timer_sync(&hdw->quiescent_timer);
2161         del_timer_sync(&hdw->encoder_run_timer);
2162         del_timer_sync(&hdw->encoder_wait_timer);
2163         if (hdw->fw_buffer) {
2164                 kfree(hdw->fw_buffer);
2165                 hdw->fw_buffer = NULL;
2166         }
2167         if (hdw->vid_stream) {
2168                 pvr2_stream_destroy(hdw->vid_stream);
2169                 hdw->vid_stream = NULL;
2170         }
2171         if (hdw->decoder_ctrl) {
2172                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2173         }
2174         pvr2_i2c_core_done(hdw);
2175         pvr2_hdw_remove_usb_stuff(hdw);
2176         mutex_lock(&pvr2_unit_mtx); do {
2177                 if ((hdw->unit_number >= 0) &&
2178                     (hdw->unit_number < PVR_NUM) &&
2179                     (unit_pointers[hdw->unit_number] == hdw)) {
2180                         unit_pointers[hdw->unit_number] = NULL;
2181                 }
2182         } while (0); mutex_unlock(&pvr2_unit_mtx);
2183         kfree(hdw->controls);
2184         kfree(hdw->mpeg_ctrl_info);
2185         kfree(hdw->std_defs);
2186         kfree(hdw->std_enum_names);
2187         kfree(hdw);
2188 }
2189
2190
2191 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2192 {
2193         return (hdw && hdw->flag_ok);
2194 }
2195
2196
2197 /* Called when hardware has been unplugged */
2198 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2199 {
2200         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2201         LOCK_TAKE(hdw->big_lock);
2202         LOCK_TAKE(hdw->ctl_lock);
2203         pvr2_hdw_remove_usb_stuff(hdw);
2204         LOCK_GIVE(hdw->ctl_lock);
2205         LOCK_GIVE(hdw->big_lock);
2206 }
2207
2208
2209 // Attempt to autoselect an appropriate value for std_enum_cur given
2210 // whatever is currently in std_mask_cur
2211 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2212 {
2213         unsigned int idx;
2214         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2215                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2216                         hdw->std_enum_cur = idx;
2217                         return;
2218                 }
2219         }
2220         hdw->std_enum_cur = 0;
2221 }
2222
2223
2224 // Calculate correct set of enumerated standards based on currently known
2225 // set of available standards bits.
2226 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2227 {
2228         struct v4l2_standard *newstd;
2229         unsigned int std_cnt;
2230         unsigned int idx;
2231
2232         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2233
2234         if (hdw->std_defs) {
2235                 kfree(hdw->std_defs);
2236                 hdw->std_defs = NULL;
2237         }
2238         hdw->std_enum_cnt = 0;
2239         if (hdw->std_enum_names) {
2240                 kfree(hdw->std_enum_names);
2241                 hdw->std_enum_names = NULL;
2242         }
2243
2244         if (!std_cnt) {
2245                 pvr2_trace(
2246                         PVR2_TRACE_ERROR_LEGS,
2247                         "WARNING: Failed to identify any viable standards");
2248         }
2249         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2250         hdw->std_enum_names[0] = "none";
2251         for (idx = 0; idx < std_cnt; idx++) {
2252                 hdw->std_enum_names[idx+1] =
2253                         newstd[idx].name;
2254         }
2255         // Set up the dynamic control for this standard
2256         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2257         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2258         hdw->std_defs = newstd;
2259         hdw->std_enum_cnt = std_cnt+1;
2260         hdw->std_enum_cur = 0;
2261         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2262 }
2263
2264
2265 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2266                                struct v4l2_standard *std,
2267                                unsigned int idx)
2268 {
2269         int ret = -EINVAL;
2270         if (!idx) return ret;
2271         LOCK_TAKE(hdw->big_lock); do {
2272                 if (idx >= hdw->std_enum_cnt) break;
2273                 idx--;
2274                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2275                 ret = 0;
2276         } while (0); LOCK_GIVE(hdw->big_lock);
2277         return ret;
2278 }
2279
2280
2281 /* Get the number of defined controls */
2282 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2283 {
2284         return hdw->control_cnt;
2285 }
2286
2287
2288 /* Retrieve a control handle given its index (0..count-1) */
2289 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2290                                              unsigned int idx)
2291 {
2292         if (idx >= hdw->control_cnt) return NULL;
2293         return hdw->controls + idx;
2294 }
2295
2296
2297 /* Retrieve a control handle given its index (0..count-1) */
2298 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2299                                           unsigned int ctl_id)
2300 {
2301         struct pvr2_ctrl *cptr;
2302         unsigned int idx;
2303         int i;
2304
2305         /* This could be made a lot more efficient, but for now... */
2306         for (idx = 0; idx < hdw->control_cnt; idx++) {
2307                 cptr = hdw->controls + idx;
2308                 i = cptr->info->internal_id;
2309                 if (i && (i == ctl_id)) return cptr;
2310         }
2311         return NULL;
2312 }
2313
2314
2315 /* Given a V4L ID, retrieve the control structure associated with it. */
2316 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2317 {
2318         struct pvr2_ctrl *cptr;
2319         unsigned int idx;
2320         int i;
2321
2322         /* This could be made a lot more efficient, but for now... */
2323         for (idx = 0; idx < hdw->control_cnt; idx++) {
2324                 cptr = hdw->controls + idx;
2325                 i = cptr->info->v4l_id;
2326                 if (i && (i == ctl_id)) return cptr;
2327         }
2328         return NULL;
2329 }
2330
2331
2332 /* Given a V4L ID for its immediate predecessor, retrieve the control
2333    structure associated with it. */
2334 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2335                                             unsigned int ctl_id)
2336 {
2337         struct pvr2_ctrl *cptr,*cp2;
2338         unsigned int idx;
2339         int i;
2340
2341         /* This could be made a lot more efficient, but for now... */
2342         cp2 = NULL;
2343         for (idx = 0; idx < hdw->control_cnt; idx++) {
2344                 cptr = hdw->controls + idx;
2345                 i = cptr->info->v4l_id;
2346                 if (!i) continue;
2347                 if (i <= ctl_id) continue;
2348                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2349                 cp2 = cptr;
2350         }
2351         return cp2;
2352         return NULL;
2353 }
2354
2355
2356 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2357 {
2358         switch (tp) {
2359         case pvr2_ctl_int: return "integer";
2360         case pvr2_ctl_enum: return "enum";
2361         case pvr2_ctl_bool: return "boolean";
2362         case pvr2_ctl_bitmask: return "bitmask";
2363         }
2364         return "";
2365 }
2366
2367
2368 /* Figure out if we need to commit control changes.  If so, mark internal
2369    state flags to indicate this fact and return true.  Otherwise do nothing
2370    else and return false. */
2371 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2372 {
2373         unsigned int idx;
2374         struct pvr2_ctrl *cptr;
2375         int value;
2376         int commit_flag = 0;
2377         char buf[100];
2378         unsigned int bcnt,ccnt;
2379
2380         for (idx = 0; idx < hdw->control_cnt; idx++) {
2381                 cptr = hdw->controls + idx;
2382                 if (!cptr->info->is_dirty) continue;
2383                 if (!cptr->info->is_dirty(cptr)) continue;
2384                 commit_flag = !0;
2385
2386                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2387                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2388                                  cptr->info->name);
2389                 value = 0;
2390                 cptr->info->get_value(cptr,&value);
2391                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2392                                                 buf+bcnt,
2393                                                 sizeof(buf)-bcnt,&ccnt);
2394                 bcnt += ccnt;
2395                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2396                                   get_ctrl_typename(cptr->info->type));
2397                 pvr2_trace(PVR2_TRACE_CTL,
2398                            "/*--TRACE_COMMIT--*/ %.*s",
2399                            bcnt,buf);
2400         }
2401
2402         if (!commit_flag) {
2403                 /* Nothing has changed */
2404                 return 0;
2405         }
2406
2407         hdw->state_pipeline_config = 0;
2408         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2409         pvr2_hdw_state_sched(hdw);
2410
2411         return !0;
2412 }
2413
2414
2415 /* Perform all operations needed to commit all control changes.  This must
2416    be performed in synchronization with the pipeline state and is thus
2417    expected to be called as part of the driver's worker thread.  Return
2418    true if commit successful, otherwise return false to indicate that
2419    commit isn't possible at this time. */
2420 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2421 {
2422         unsigned int idx;
2423         struct pvr2_ctrl *cptr;
2424         int disruptive_change;
2425
2426         /* When video standard changes, reset the hres and vres values -
2427            but if the user has pending changes there, then let the changes
2428            take priority. */
2429         if (hdw->std_dirty) {
2430                 /* Rewrite the vertical resolution to be appropriate to the
2431                    video standard that has been selected. */
2432                 int nvres;
2433                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2434                         nvres = 480;
2435                 } else {
2436                         nvres = 576;
2437                 }
2438                 if (nvres != hdw->res_ver_val) {
2439                         hdw->res_ver_val = nvres;
2440                         hdw->res_ver_dirty = !0;
2441                 }
2442         }
2443
2444         if (hdw->input_dirty && hdw->state_pathway_ok &&
2445             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2446               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2447              hdw->pathway_state)) {
2448                 /* Change of mode being asked for... */
2449                 hdw->state_pathway_ok = 0;
2450                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2451         }
2452         if (!hdw->state_pathway_ok) {
2453                 /* Can't commit anything until pathway is ok. */
2454                 return 0;
2455         }
2456         /* If any of the below has changed, then we can't do the update
2457            while the pipeline is running.  Pipeline must be paused first
2458            and decoder -> encoder connection be made quiescent before we
2459            can proceed. */
2460         disruptive_change =
2461                 (hdw->std_dirty ||
2462                  hdw->enc_unsafe_stale ||
2463                  hdw->srate_dirty ||
2464                  hdw->res_ver_dirty ||
2465                  hdw->res_hor_dirty ||
2466                  hdw->input_dirty ||
2467                  (hdw->active_stream_type != hdw->desired_stream_type));
2468         if (disruptive_change && !hdw->state_pipeline_idle) {
2469                 /* Pipeline is not idle; we can't proceed.  Arrange to
2470                    cause pipeline to stop so that we can try this again
2471                    later.... */
2472                 hdw->state_pipeline_pause = !0;
2473                 return 0;
2474         }
2475
2476         if (hdw->srate_dirty) {
2477                 /* Write new sample rate into control structure since
2478                  * the master copy is stale.  We must track srate
2479                  * separate from the mpeg control structure because
2480                  * other logic also uses this value. */
2481                 struct v4l2_ext_controls cs;
2482                 struct v4l2_ext_control c1;
2483                 memset(&cs,0,sizeof(cs));
2484                 memset(&c1,0,sizeof(c1));
2485                 cs.controls = &c1;
2486                 cs.count = 1;
2487                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2488                 c1.value = hdw->srate_val;
2489                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2490         }
2491
2492         /* Scan i2c core at this point - before we clear all the dirty
2493            bits.  Various parts of the i2c core will notice dirty bits as
2494            appropriate and arrange to broadcast or directly send updates to
2495            the client drivers in order to keep everything in sync */
2496         pvr2_i2c_core_check_stale(hdw);
2497
2498         for (idx = 0; idx < hdw->control_cnt; idx++) {
2499                 cptr = hdw->controls + idx;
2500                 if (!cptr->info->clear_dirty) continue;
2501                 cptr->info->clear_dirty(cptr);
2502         }
2503
2504         if (hdw->active_stream_type != hdw->desired_stream_type) {
2505                 /* Handle any side effects of stream config here */
2506                 hdw->active_stream_type = hdw->desired_stream_type;
2507         }
2508
2509         /* Now execute i2c core update */
2510         pvr2_i2c_core_sync(hdw);
2511
2512         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2513             hdw->state_encoder_run) {
2514                 /* If encoder isn't running or it can't be touched, then
2515                    this will get worked out later when we start the
2516                    encoder. */
2517                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2518         }
2519
2520         hdw->state_pipeline_config = !0;
2521         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2522         return !0;
2523 }
2524
2525
2526 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2527 {
2528         int fl;
2529         LOCK_TAKE(hdw->big_lock);
2530         fl = pvr2_hdw_commit_setup(hdw);
2531         LOCK_GIVE(hdw->big_lock);
2532         if (!fl) return 0;
2533         return pvr2_hdw_wait(hdw,0);
2534 }
2535
2536
2537 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2538 {
2539         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2540         LOCK_TAKE(hdw->big_lock); do {
2541                 pvr2_i2c_core_sync(hdw);
2542         } while (0); LOCK_GIVE(hdw->big_lock);
2543 }
2544
2545
2546 static void pvr2_hdw_worker_poll(struct work_struct *work)
2547 {
2548         int fl = 0;
2549         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2550         LOCK_TAKE(hdw->big_lock); do {
2551                 fl = pvr2_hdw_state_eval(hdw);
2552         } while (0); LOCK_GIVE(hdw->big_lock);
2553         if (fl && hdw->state_func) {
2554                 hdw->state_func(hdw->state_data);
2555         }
2556 }
2557
2558
2559 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2560 {
2561         return wait_event_interruptible(
2562                 hdw->state_wait_data,
2563                 (hdw->state_stale == 0) &&
2564                 (!state || (hdw->master_state != state)));
2565 }
2566
2567
2568 /* Return name for this driver instance */
2569 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2570 {
2571         return hdw->name;
2572 }
2573
2574
2575 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2576 {
2577         return hdw->hdw_desc->description;
2578 }
2579
2580
2581 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2582 {
2583         return hdw->hdw_desc->shortname;
2584 }
2585
2586
2587 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2588 {
2589         int result;
2590         LOCK_TAKE(hdw->ctl_lock); do {
2591                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2592                 result = pvr2_send_request(hdw,
2593                                            hdw->cmd_buffer,1,
2594                                            hdw->cmd_buffer,1);
2595                 if (result < 0) break;
2596                 result = (hdw->cmd_buffer[0] != 0);
2597         } while(0); LOCK_GIVE(hdw->ctl_lock);
2598         return result;
2599 }
2600
2601
2602 /* Execute poll of tuner status */
2603 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2604 {
2605         LOCK_TAKE(hdw->big_lock); do {
2606                 pvr2_i2c_core_status_poll(hdw);
2607         } while (0); LOCK_GIVE(hdw->big_lock);
2608 }
2609
2610
2611 /* Return information about the tuner */
2612 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2613 {
2614         LOCK_TAKE(hdw->big_lock); do {
2615                 if (hdw->tuner_signal_stale) {
2616                         pvr2_i2c_core_status_poll(hdw);
2617                 }
2618                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2619         } while (0); LOCK_GIVE(hdw->big_lock);
2620         return 0;
2621 }
2622
2623
2624 /* Get handle to video output stream */
2625 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2626 {
2627         return hp->vid_stream;
2628 }
2629
2630
2631 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2632 {
2633         int nr = pvr2_hdw_get_unit_number(hdw);
2634         LOCK_TAKE(hdw->big_lock); do {
2635                 hdw->log_requested = !0;
2636                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2637                 pvr2_i2c_core_check_stale(hdw);
2638                 hdw->log_requested = 0;
2639                 pvr2_i2c_core_sync(hdw);
2640                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2641                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2642                 pvr2_hdw_state_log_state(hdw);
2643                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2644         } while (0); LOCK_GIVE(hdw->big_lock);
2645 }
2646
2647
2648 /* Grab EEPROM contents, needed for direct method. */
2649 #define EEPROM_SIZE 8192
2650 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2651 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2652 {
2653         struct i2c_msg msg[2];
2654         u8 *eeprom;
2655         u8 iadd[2];
2656         u8 addr;
2657         u16 eepromSize;
2658         unsigned int offs;
2659         int ret;
2660         int mode16 = 0;
2661         unsigned pcnt,tcnt;
2662         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2663         if (!eeprom) {
2664                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2665                            "Failed to allocate memory"
2666                            " required to read eeprom");
2667                 return NULL;
2668         }
2669
2670         trace_eeprom("Value for eeprom addr from controller was 0x%x",
2671                      hdw->eeprom_addr);
2672         addr = hdw->eeprom_addr;
2673         /* Seems that if the high bit is set, then the *real* eeprom
2674            address is shifted right now bit position (noticed this in
2675            newer PVR USB2 hardware) */
2676         if (addr & 0x80) addr >>= 1;
2677
2678         /* FX2 documentation states that a 16bit-addressed eeprom is
2679            expected if the I2C address is an odd number (yeah, this is
2680            strange but it's what they do) */
2681         mode16 = (addr & 1);
2682         eepromSize = (mode16 ? EEPROM_SIZE : 256);
2683         trace_eeprom("Examining %d byte eeprom at location 0x%x"
2684                      " using %d bit addressing",eepromSize,addr,
2685                      mode16 ? 16 : 8);
2686
2687         msg[0].addr = addr;
2688         msg[0].flags = 0;
2689         msg[0].len = mode16 ? 2 : 1;
2690         msg[0].buf = iadd;
2691         msg[1].addr = addr;
2692         msg[1].flags = I2C_M_RD;
2693
2694         /* We have to do the actual eeprom data fetch ourselves, because
2695            (1) we're only fetching part of the eeprom, and (2) if we were
2696            getting the whole thing our I2C driver can't grab it in one
2697            pass - which is what tveeprom is otherwise going to attempt */
2698         memset(eeprom,0,EEPROM_SIZE);
2699         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2700                 pcnt = 16;
2701                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2702                 offs = tcnt + (eepromSize - EEPROM_SIZE);
2703                 if (mode16) {
2704                         iadd[0] = offs >> 8;
2705                         iadd[1] = offs;
2706                 } else {
2707                         iadd[0] = offs;
2708                 }
2709                 msg[1].len = pcnt;
2710                 msg[1].buf = eeprom+tcnt;
2711                 if ((ret = i2c_transfer(&hdw->i2c_adap,
2712                                         msg,ARRAY_SIZE(msg))) != 2) {
2713                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2714                                    "eeprom fetch set offs err=%d",ret);
2715                         kfree(eeprom);
2716                         return NULL;
2717                 }
2718         }
2719         return eeprom;
2720 }
2721
2722
2723 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2724                                 int prom_flag,
2725                                 int enable_flag)
2726 {
2727         int ret;
2728         u16 address;
2729         unsigned int pipe;
2730         LOCK_TAKE(hdw->big_lock); do {
2731                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
2732
2733                 if (!enable_flag) {
2734                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2735                                    "Cleaning up after CPU firmware fetch");
2736                         kfree(hdw->fw_buffer);
2737                         hdw->fw_buffer = NULL;
2738                         hdw->fw_size = 0;
2739                         if (hdw->fw_cpu_flag) {
2740                                 /* Now release the CPU.  It will disconnect
2741                                    and reconnect later. */
2742                                 pvr2_hdw_cpureset_assert(hdw,0);
2743                         }
2744                         break;
2745                 }
2746
2747                 hdw->fw_cpu_flag = (prom_flag == 0);
2748                 if (hdw->fw_cpu_flag) {
2749                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2750                                    "Preparing to suck out CPU firmware");
2751                         hdw->fw_size = 0x2000;
2752                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2753                         if (!hdw->fw_buffer) {
2754                                 hdw->fw_size = 0;
2755                                 break;
2756                         }
2757
2758                         /* We have to hold the CPU during firmware upload. */
2759                         pvr2_hdw_cpureset_assert(hdw,1);
2760
2761                         /* download the firmware from address 0000-1fff in 2048
2762                            (=0x800) bytes chunk. */
2763
2764                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2765                                    "Grabbing CPU firmware");
2766                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2767                         for(address = 0; address < hdw->fw_size;
2768                             address += 0x800) {
2769                                 ret = usb_control_msg(hdw->usb_dev,pipe,
2770                                                       0xa0,0xc0,
2771                                                       address,0,
2772                                                       hdw->fw_buffer+address,
2773                                                       0x800,HZ);
2774                                 if (ret < 0) break;
2775                         }
2776
2777                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2778                                    "Done grabbing CPU firmware");
2779                 } else {
2780                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2781                                    "Sucking down EEPROM contents");
2782                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2783                         if (!hdw->fw_buffer) {
2784                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2785                                            "EEPROM content suck failed.");
2786                                 break;
2787                         }
2788                         hdw->fw_size = EEPROM_SIZE;
2789                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2790                                    "Done sucking down EEPROM contents");
2791                 }
2792
2793         } while (0); LOCK_GIVE(hdw->big_lock);
2794 }
2795
2796
2797 /* Return true if we're in a mode for retrieval CPU firmware */
2798 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2799 {
2800         return hdw->fw_buffer != NULL;
2801 }
2802
2803
2804 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2805                        char *buf,unsigned int cnt)
2806 {
2807         int ret = -EINVAL;
2808         LOCK_TAKE(hdw->big_lock); do {
2809                 if (!buf) break;
2810                 if (!cnt) break;
2811
2812                 if (!hdw->fw_buffer) {
2813                         ret = -EIO;
2814                         break;
2815                 }
2816
2817                 if (offs >= hdw->fw_size) {
2818                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2819                                    "Read firmware data offs=%d EOF",
2820                                    offs);
2821                         ret = 0;
2822                         break;
2823                 }
2824
2825                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2826
2827                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2828
2829                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2830                            "Read firmware data offs=%d cnt=%d",
2831                            offs,cnt);
2832                 ret = cnt;
2833         } while (0); LOCK_GIVE(hdw->big_lock);
2834
2835         return ret;
2836 }
2837
2838
2839 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2840                                   enum pvr2_v4l_type index)
2841 {
2842         switch (index) {
2843         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2844         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2845         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2846         default: return -1;
2847         }
2848 }
2849
2850
2851 /* Store a v4l minor device number */
2852 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2853                                      enum pvr2_v4l_type index,int v)
2854 {
2855         switch (index) {
2856         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2857         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2858         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2859         default: break;
2860         }
2861 }
2862
2863
2864 static void pvr2_ctl_write_complete(struct urb *urb)
2865 {
2866         struct pvr2_hdw *hdw = urb->context;
2867         hdw->ctl_write_pend_flag = 0;
2868         if (hdw->ctl_read_pend_flag) return;
2869         complete(&hdw->ctl_done);
2870 }
2871
2872
2873 static void pvr2_ctl_read_complete(struct urb *urb)
2874 {
2875         struct pvr2_hdw *hdw = urb->context;
2876         hdw->ctl_read_pend_flag = 0;
2877         if (hdw->ctl_write_pend_flag) return;
2878         complete(&hdw->ctl_done);
2879 }
2880
2881
2882 static void pvr2_ctl_timeout(unsigned long data)
2883 {
2884         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2885         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2886                 hdw->ctl_timeout_flag = !0;
2887                 if (hdw->ctl_write_pend_flag)
2888                         usb_unlink_urb(hdw->ctl_write_urb);
2889                 if (hdw->ctl_read_pend_flag)
2890                         usb_unlink_urb(hdw->ctl_read_urb);
2891         }
2892 }
2893
2894
2895 /* Issue a command and get a response from the device.  This extended
2896    version includes a probe flag (which if set means that device errors
2897    should not be logged or treated as fatal) and a timeout in jiffies.
2898    This can be used to non-lethally probe the health of endpoint 1. */
2899 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2900                                 unsigned int timeout,int probe_fl,
2901                                 void *write_data,unsigned int write_len,
2902                                 void *read_data,unsigned int read_len)
2903 {
2904         unsigned int idx;
2905         int status = 0;
2906         struct timer_list timer;
2907         if (!hdw->ctl_lock_held) {
2908                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2909                            "Attempted to execute control transfer"
2910                            " without lock!!");
2911                 return -EDEADLK;
2912         }
2913         if (!hdw->flag_ok && !probe_fl) {
2914                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2915                            "Attempted to execute control transfer"
2916                            " when device not ok");
2917                 return -EIO;
2918         }
2919         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2920                 if (!probe_fl) {
2921                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2922                                    "Attempted to execute control transfer"
2923                                    " when USB is disconnected");
2924                 }
2925                 return -ENOTTY;
2926         }
2927
2928         /* Ensure that we have sane parameters */
2929         if (!write_data) write_len = 0;
2930         if (!read_data) read_len = 0;
2931         if (write_len > PVR2_CTL_BUFFSIZE) {
2932                 pvr2_trace(
2933                         PVR2_TRACE_ERROR_LEGS,
2934                         "Attempted to execute %d byte"
2935                         " control-write transfer (limit=%d)",
2936                         write_len,PVR2_CTL_BUFFSIZE);
2937                 return -EINVAL;
2938         }
2939         if (read_len > PVR2_CTL_BUFFSIZE) {
2940                 pvr2_trace(
2941                         PVR2_TRACE_ERROR_LEGS,
2942                         "Attempted to execute %d byte"
2943                         " control-read transfer (limit=%d)",
2944                         write_len,PVR2_CTL_BUFFSIZE);
2945                 return -EINVAL;
2946         }
2947         if ((!write_len) && (!read_len)) {
2948                 pvr2_trace(
2949                         PVR2_TRACE_ERROR_LEGS,
2950                         "Attempted to execute null control transfer?");
2951                 return -EINVAL;
2952         }
2953
2954
2955         hdw->cmd_debug_state = 1;
2956         if (write_len) {
2957                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2958         } else {
2959                 hdw->cmd_debug_code = 0;
2960         }
2961         hdw->cmd_debug_write_len = write_len;
2962         hdw->cmd_debug_read_len = read_len;
2963
2964         /* Initialize common stuff */
2965         init_completion(&hdw->ctl_done);
2966         hdw->ctl_timeout_flag = 0;
2967         hdw->ctl_write_pend_flag = 0;
2968         hdw->ctl_read_pend_flag = 0;
2969         init_timer(&timer);
2970         timer.expires = jiffies + timeout;
2971         timer.data = (unsigned long)hdw;
2972         timer.function = pvr2_ctl_timeout;
2973
2974         if (write_len) {
2975                 hdw->cmd_debug_state = 2;
2976                 /* Transfer write data to internal buffer */
2977                 for (idx = 0; idx < write_len; idx++) {
2978                         hdw->ctl_write_buffer[idx] =
2979                                 ((unsigned char *)write_data)[idx];
2980                 }
2981                 /* Initiate a write request */
2982                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2983                                   hdw->usb_dev,
2984                                   usb_sndbulkpipe(hdw->usb_dev,
2985                                                   PVR2_CTL_WRITE_ENDPOINT),
2986                                   hdw->ctl_write_buffer,
2987                                   write_len,
2988                                   pvr2_ctl_write_complete,
2989                                   hdw);
2990                 hdw->ctl_write_urb->actual_length = 0;
2991                 hdw->ctl_write_pend_flag = !0;
2992                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2993                 if (status < 0) {
2994                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2995                                    "Failed to submit write-control"
2996                                    " URB status=%d",status);
2997                         hdw->ctl_write_pend_flag = 0;
2998                         goto done;
2999                 }
3000         }
3001
3002         if (read_len) {
3003                 hdw->cmd_debug_state = 3;
3004                 memset(hdw->ctl_read_buffer,0x43,read_len);
3005                 /* Initiate a read request */
3006                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3007                                   hdw->usb_dev,
3008                                   usb_rcvbulkpipe(hdw->usb_dev,
3009                                                   PVR2_CTL_READ_ENDPOINT),
3010                                   hdw->ctl_read_buffer,
3011                                   read_len,
3012                                   pvr2_ctl_read_complete,
3013                                   hdw);
3014                 hdw->ctl_read_urb->actual_length = 0;
3015                 hdw->ctl_read_pend_flag = !0;
3016                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3017                 if (status < 0) {
3018                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3019                                    "Failed to submit read-control"
3020                                    " URB status=%d",status);
3021                         hdw->ctl_read_pend_flag = 0;
3022                         goto done;
3023                 }
3024         }
3025
3026         /* Start timer */
3027         add_timer(&timer);
3028
3029         /* Now wait for all I/O to complete */
3030         hdw->cmd_debug_state = 4;
3031         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3032                 wait_for_completion(&hdw->ctl_done);
3033         }
3034         hdw->cmd_debug_state = 5;
3035
3036         /* Stop timer */
3037         del_timer_sync(&timer);
3038
3039         hdw->cmd_debug_state = 6;
3040         status = 0;
3041
3042         if (hdw->ctl_timeout_flag) {
3043                 status = -ETIMEDOUT;
3044                 if (!probe_fl) {
3045                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3046                                    "Timed out control-write");
3047                 }
3048                 goto done;
3049         }
3050
3051         if (write_len) {
3052                 /* Validate results of write request */
3053                 if ((hdw->ctl_write_urb->status != 0) &&
3054                     (hdw->ctl_write_urb->status != -ENOENT) &&
3055                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3056                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3057                         /* USB subsystem is reporting some kind of failure
3058                            on the write */
3059                         status = hdw->ctl_write_urb->status;
3060                         if (!probe_fl) {
3061                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3062                                            "control-write URB failure,"
3063                                            " status=%d",
3064                                            status);
3065                         }
3066                         goto done;
3067                 }
3068                 if (hdw->ctl_write_urb->actual_length < write_len) {
3069                         /* Failed to write enough data */
3070                         status = -EIO;
3071                         if (!probe_fl) {
3072                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3073                                            "control-write URB short,"
3074                                            " expected=%d got=%d",
3075                                            write_len,
3076                                            hdw->ctl_write_urb->actual_length);
3077                         }
3078                         goto done;
3079                 }
3080         }
3081         if (read_len) {
3082                 /* Validate results of read request */
3083                 if ((hdw->ctl_read_urb->status != 0) &&
3084                     (hdw->ctl_read_urb->status != -ENOENT) &&
3085                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3086                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3087                         /* USB subsystem is reporting some kind of failure
3088                            on the read */
3089                         status = hdw->ctl_read_urb->status;
3090                         if (!probe_fl) {
3091                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3092                                            "control-read URB failure,"
3093                                            " status=%d",
3094                                            status);
3095                         }
3096                         goto done;
3097                 }
3098                 if (hdw->ctl_read_urb->actual_length < read_len) {
3099                         /* Failed to read enough data */
3100                         status = -EIO;
3101                         if (!probe_fl) {
3102                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3103                                            "control-read URB short,"
3104                                            " expected=%d got=%d",
3105                                            read_len,
3106                                            hdw->ctl_read_urb->actual_length);
3107                         }
3108                         goto done;
3109                 }
3110                 /* Transfer retrieved data out from internal buffer */
3111                 for (idx = 0; idx < read_len; idx++) {
3112                         ((unsigned char *)read_data)[idx] =
3113                                 hdw->ctl_read_buffer[idx];
3114                 }
3115         }
3116
3117  done:
3118
3119         hdw->cmd_debug_state = 0;
3120         if ((status < 0) && (!probe_fl)) {
3121                 pvr2_hdw_render_useless(hdw);
3122         }
3123         return status;
3124 }
3125
3126
3127 int pvr2_send_request(struct pvr2_hdw *hdw,
3128                       void *write_data,unsigned int write_len,
3129                       void *read_data,unsigned int read_len)
3130 {
3131         return pvr2_send_request_ex(hdw,HZ*4,0,
3132                                     write_data,write_len,
3133                                     read_data,read_len);
3134 }
3135
3136
3137 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3138 {
3139         int ret;
3140         unsigned int cnt = 1;
3141         unsigned int args = 0;
3142         LOCK_TAKE(hdw->ctl_lock);
3143         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3144         args = (cmdcode >> 8) & 0xffu;
3145         args = (args > 2) ? 2 : args;
3146         if (args) {
3147                 cnt += args;
3148                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3149                 if (args > 1) {
3150                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3151                 }
3152         }
3153         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3154                 unsigned int idx;
3155                 unsigned int ccnt,bcnt;
3156                 char tbuf[50];
3157                 cmdcode &= 0xffu;
3158                 bcnt = 0;
3159                 ccnt = scnprintf(tbuf+bcnt,
3160                                  sizeof(tbuf)-bcnt,
3161                                  "Sending FX2 command 0x%x",cmdcode);
3162                 bcnt += ccnt;
3163                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3164                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3165                                 ccnt = scnprintf(tbuf+bcnt,
3166                                                  sizeof(tbuf)-bcnt,
3167                                                  " \"%s\"",
3168                                                  pvr2_fx2cmd_desc[idx].desc);
3169                                 bcnt += ccnt;
3170                                 break;
3171                         }
3172                 }
3173                 if (args) {
3174                         ccnt = scnprintf(tbuf+bcnt,
3175                                          sizeof(tbuf)-bcnt,
3176                                          " (%u",hdw->cmd_buffer[1]);
3177                         bcnt += ccnt;
3178                         if (args > 1) {
3179                                 ccnt = scnprintf(tbuf+bcnt,
3180                                                  sizeof(tbuf)-bcnt,
3181                                                  ",%u",hdw->cmd_buffer[2]);
3182                                 bcnt += ccnt;
3183                         }
3184                         ccnt = scnprintf(tbuf+bcnt,
3185                                          sizeof(tbuf)-bcnt,
3186                                          ")");
3187                         bcnt += ccnt;
3188                 }
3189                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3190         }
3191         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3192         LOCK_GIVE(hdw->ctl_lock);
3193         return ret;
3194 }
3195
3196
3197 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3198 {
3199         int ret;
3200
3201         LOCK_TAKE(hdw->ctl_lock);
3202
3203         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3204         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3205         hdw->cmd_buffer[5] = 0;
3206         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3207         hdw->cmd_buffer[7] = reg & 0xff;
3208
3209
3210         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3211
3212         LOCK_GIVE(hdw->ctl_lock);
3213
3214         return ret;
3215 }
3216
3217
3218 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3219 {
3220         int ret = 0;
3221
3222         LOCK_TAKE(hdw->ctl_lock);
3223
3224         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3225         hdw->cmd_buffer[1] = 0;
3226         hdw->cmd_buffer[2] = 0;
3227         hdw->cmd_buffer[3] = 0;
3228         hdw->cmd_buffer[4] = 0;
3229         hdw->cmd_buffer[5] = 0;
3230         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3231         hdw->cmd_buffer[7] = reg & 0xff;
3232
3233         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3234         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3235
3236         LOCK_GIVE(hdw->ctl_lock);
3237
3238         return ret;
3239 }
3240
3241
3242 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3243 {
3244         if (!hdw->flag_ok) return;
3245         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3246                    "Device being rendered inoperable");
3247         if (hdw->vid_stream) {
3248                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3249         }
3250         hdw->flag_ok = 0;
3251         trace_stbit("flag_ok",hdw->flag_ok);
3252         pvr2_hdw_state_sched(hdw);
3253 }
3254
3255
3256 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3257 {
3258         int ret;
3259         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3260         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3261         if (ret == 1) {
3262                 ret = usb_reset_device(hdw->usb_dev);
3263                 usb_unlock_device(hdw->usb_dev);
3264         } else {
3265                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3266                            "Failed to lock USB device ret=%d",ret);
3267         }
3268         if (init_pause_msec) {
3269                 pvr2_trace(PVR2_TRACE_INFO,
3270                            "Waiting %u msec for hardware to settle",
3271                            init_pause_msec);
3272                 msleep(init_pause_msec);
3273         }
3274
3275 }
3276
3277
3278 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3279 {
3280         char da[1];
3281         unsigned int pipe;
3282         int ret;
3283
3284         if (!hdw->usb_dev) return;
3285
3286         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3287
3288         da[0] = val ? 0x01 : 0x00;
3289
3290         /* Write the CPUCS register on the 8051.  The lsb of the register
3291            is the reset bit; a 1 asserts reset while a 0 clears it. */
3292         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3293         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3294         if (ret < 0) {
3295                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3296                            "cpureset_assert(%d) error=%d",val,ret);
3297                 pvr2_hdw_render_useless(hdw);
3298         }
3299 }
3300
3301
3302 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3303 {
3304         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3305 }
3306
3307
3308 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3309 {
3310         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3311 }
3312
3313
3314 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3315 {
3316         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3317 }
3318
3319
3320 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3321 {
3322         if (!hdw->decoder_ctrl) {
3323                 pvr2_trace(PVR2_TRACE_INIT,
3324                            "Unable to reset decoder: nothing attached");
3325                 return -ENOTTY;
3326         }
3327
3328         if (!hdw->decoder_ctrl->force_reset) {
3329                 pvr2_trace(PVR2_TRACE_INIT,
3330                            "Unable to reset decoder: not implemented");
3331                 return -ENOTTY;
3332         }
3333
3334         pvr2_trace(PVR2_TRACE_INIT,
3335                    "Requesting decoder reset");
3336         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3337         return 0;
3338 }
3339
3340
3341 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3342 {
3343         hdw->flag_ok = !0;
3344         return pvr2_issue_simple_cmd(hdw,
3345                                      FX2CMD_HCW_DEMOD_RESETIN |
3346                                      (1 << 8) |
3347                                      ((onoff ? 1 : 0) << 16));
3348 }
3349
3350
3351 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3352 {
3353         hdw->flag_ok = !0;
3354         return pvr2_issue_simple_cmd(hdw,(onoff ?
3355                                           FX2CMD_ONAIR_DTV_POWER_ON :
3356                                           FX2CMD_ONAIR_DTV_POWER_OFF));
3357 }
3358
3359
3360 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3361                                                 int onoff)
3362 {
3363         return pvr2_issue_simple_cmd(hdw,(onoff ?
3364                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
3365                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
3366 }
3367
3368
3369 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3370 {
3371         int cmode;
3372         /* Compare digital/analog desired setting with current setting.  If
3373            they don't match, fix it... */
3374         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3375         if (cmode == hdw->pathway_state) {
3376                 /* They match; nothing to do */
3377                 return;
3378         }
3379
3380         switch (hdw->hdw_desc->digital_control_scheme) {
3381         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3382                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3383                 if (cmode == PVR2_PATHWAY_ANALOG) {
3384                         /* If moving to analog mode, also force the decoder
3385                            to reset.  If no decoder is attached, then it's
3386                            ok to ignore this because if/when the decoder
3387                            attaches, it will reset itself at that time. */
3388                         pvr2_hdw_cmd_decoder_reset(hdw);
3389                 }
3390                 break;
3391         case PVR2_DIGITAL_SCHEME_ONAIR:
3392                 /* Supposedly we should always have the power on whether in
3393                    digital or analog mode.  But for now do what appears to
3394                    work... */
3395                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3396                 break;
3397         default: break;
3398         }
3399
3400         pvr2_hdw_untrip_unlocked(hdw);
3401         hdw->pathway_state = cmode;
3402 }
3403
3404
3405 void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3406 {
3407         /* change some GPIO data
3408          *
3409          * note: bit d7 of dir appears to control the LED,
3410          * so we shut it off here.
3411          *
3412          */
3413         if (onoff) {
3414                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3415         } else {
3416                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3417         }
3418         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3419 }
3420
3421
3422 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3423
3424 static led_method_func led_methods[] = {
3425         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3426 };
3427
3428
3429 /* Toggle LED */
3430 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3431 {
3432         unsigned int scheme_id;
3433         led_method_func fp;
3434
3435         if ((!onoff) == (!hdw->led_on)) return;
3436
3437         hdw->led_on = onoff != 0;
3438
3439         scheme_id = hdw->hdw_desc->led_scheme;
3440         if (scheme_id < ARRAY_SIZE(led_methods)) {
3441                 fp = led_methods[scheme_id];
3442         } else {
3443                 fp = NULL;
3444         }
3445
3446         if (fp) (*fp)(hdw,onoff);
3447 }
3448
3449
3450 /* Stop / start video stream transport */
3451 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3452 {
3453         int ret;
3454
3455         /* If we're in analog mode, then just issue the usual analog
3456            command. */
3457         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3458                 return pvr2_issue_simple_cmd(hdw,
3459                                              (runFl ?
3460                                               FX2CMD_STREAMING_ON :
3461                                               FX2CMD_STREAMING_OFF));
3462                 /*Note: Not reached */
3463         }
3464
3465         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3466                 /* Whoops, we don't know what mode we're in... */
3467                 return -EINVAL;
3468         }
3469
3470         /* To get here we have to be in digital mode.  The mechanism here
3471            is unfortunately different for different vendors.  So we switch
3472            on the device's digital scheme attribute in order to figure out
3473            what to do. */
3474         switch (hdw->hdw_desc->digital_control_scheme) {
3475         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3476                 return pvr2_issue_simple_cmd(hdw,
3477                                              (runFl ?
3478                                               FX2CMD_HCW_DTV_STREAMING_ON :
3479                                               FX2CMD_HCW_DTV_STREAMING_OFF));
3480         case PVR2_DIGITAL_SCHEME_ONAIR:
3481                 ret = pvr2_issue_simple_cmd(hdw,
3482                                             (runFl ?
3483                                              FX2CMD_STREAMING_ON :
3484                                              FX2CMD_STREAMING_OFF));
3485                 if (ret) return ret;
3486                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3487         default:
3488                 return -EINVAL;
3489         }
3490 }
3491
3492
3493 /* Evaluate whether or not state_pathway_ok can change */
3494 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3495 {
3496         if (hdw->state_pathway_ok) {
3497                 /* Nothing to do if pathway is already ok */
3498                 return 0;
3499         }
3500         if (!hdw->state_pipeline_idle) {
3501                 /* Not allowed to change anything if pipeline is not idle */
3502                 return 0;
3503         }
3504         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3505         hdw->state_pathway_ok = !0;
3506         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3507         return !0;
3508 }
3509
3510
3511 /* Evaluate whether or not state_encoder_ok can change */
3512 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3513 {
3514         if (hdw->state_encoder_ok) return 0;
3515         if (hdw->flag_tripped) return 0;
3516         if (hdw->state_encoder_run) return 0;
3517         if (hdw->state_encoder_config) return 0;
3518         if (hdw->state_decoder_run) return 0;
3519         if (hdw->state_usbstream_run) return 0;
3520         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3521                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3522         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3523                 return 0;
3524         }
3525
3526         if (pvr2_upload_firmware2(hdw) < 0) {
3527                 hdw->flag_tripped = !0;
3528                 trace_stbit("flag_tripped",hdw->flag_tripped);
3529                 return !0;
3530         }
3531         hdw->state_encoder_ok = !0;
3532         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3533         return !0;
3534 }
3535
3536
3537 /* Evaluate whether or not state_encoder_config can change */
3538 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3539 {
3540         if (hdw->state_encoder_config) {
3541                 if (hdw->state_encoder_ok) {
3542                         if (hdw->state_pipeline_req &&
3543                             !hdw->state_pipeline_pause) return 0;
3544                 }
3545                 hdw->state_encoder_config = 0;
3546                 hdw->state_encoder_waitok = 0;
3547                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3548                 /* paranoia - solve race if timer just completed */
3549                 del_timer_sync(&hdw->encoder_wait_timer);
3550         } else {
3551                 if (!hdw->state_pathway_ok ||
3552                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3553                     !hdw->state_encoder_ok ||
3554                     !hdw->state_pipeline_idle ||
3555                     hdw->state_pipeline_pause ||
3556                     !hdw->state_pipeline_req ||
3557                     !hdw->state_pipeline_config) {
3558                         /* We must reset the enforced wait interval if
3559                            anything has happened that might have disturbed
3560                            the encoder.  This should be a rare case. */
3561                         if (timer_pending(&hdw->encoder_wait_timer)) {
3562                                 del_timer_sync(&hdw->encoder_wait_timer);
3563                         }
3564                         if (hdw->state_encoder_waitok) {
3565                                 /* Must clear the state - therefore we did
3566                                    something to a state bit and must also
3567                                    return true. */
3568                                 hdw->state_encoder_waitok = 0;
3569                                 trace_stbit("state_encoder_waitok",
3570                                             hdw->state_encoder_waitok);
3571                                 return !0;
3572                         }
3573                         return 0;
3574                 }
3575                 if (!hdw->state_encoder_waitok) {
3576                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3577                                 /* waitok flag wasn't set and timer isn't
3578                                    running.  Check flag once more to avoid
3579                                    a race then start the timer.  This is
3580                                    the point when we measure out a minimal
3581                                    quiet interval before doing something to
3582                                    the encoder. */
3583                                 if (!hdw->state_encoder_waitok) {
3584                                         hdw->encoder_wait_timer.expires =
3585                                                 jiffies + (HZ*50/1000);
3586                                         add_timer(&hdw->encoder_wait_timer);
3587                                 }
3588                         }
3589                         /* We can't continue until we know we have been
3590                            quiet for the interval measured by this
3591                            timer. */
3592                         return 0;
3593                 }
3594                 pvr2_encoder_configure(hdw);
3595                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3596         }
3597         trace_stbit("state_encoder_config",hdw->state_encoder_config);
3598         return !0;
3599 }
3600
3601
3602 /* Return true if the encoder should not be running. */
3603 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
3604 {
3605         if (!hdw->state_encoder_ok) {
3606                 /* Encoder isn't healthy at the moment, so stop it. */
3607                 return !0;
3608         }
3609         if (!hdw->state_pathway_ok) {
3610                 /* Mode is not understood at the moment (i.e. it wants to
3611                    change), so encoder must be stopped. */
3612                 return !0;
3613         }
3614
3615         switch (hdw->pathway_state) {
3616         case PVR2_PATHWAY_ANALOG:
3617                 if (!hdw->state_decoder_run) {
3618                         /* We're in analog mode and the decoder is not
3619                            running; thus the encoder should be stopped as
3620                            well. */
3621                         return !0;
3622                 }
3623                 break;
3624         case PVR2_PATHWAY_DIGITAL:
3625                 if (hdw->state_encoder_runok) {
3626                         /* This is a funny case.  We're in digital mode so
3627                            really the encoder should be stopped.  However
3628                            if it really is running, only kill it after
3629                            runok has been set.  This gives a chance for the
3630                            onair quirk to function (encoder must run
3631                            briefly first, at least once, before onair
3632                            digital streaming can work). */
3633                         return !0;
3634                 }
3635                 break;
3636         default:
3637                 /* Unknown mode; so encoder should be stopped. */
3638                 return !0;
3639         }
3640
3641         /* If we get here, we haven't found a reason to stop the
3642            encoder. */
3643         return 0;
3644 }
3645
3646
3647 /* Return true if the encoder should be running. */
3648 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
3649 {
3650         if (!hdw->state_encoder_ok) {
3651                 /* Don't run the encoder if it isn't healthy... */
3652                 return 0;
3653         }
3654         if (!hdw->state_pathway_ok) {
3655                 /* Don't run the encoder if we don't (yet) know what mode
3656                    we need to be in... */
3657                 return 0;
3658         }
3659
3660         switch (hdw->pathway_state) {
3661         case PVR2_PATHWAY_ANALOG:
3662                 if (hdw->state_decoder_run) {
3663                         /* In analog mode, if the decoder is running, then
3664                            run the encoder. */
3665                         return !0;
3666                 }
3667                 break;
3668         case PVR2_PATHWAY_DIGITAL:
3669                 if ((hdw->hdw_desc->digital_control_scheme ==
3670                      PVR2_DIGITAL_SCHEME_ONAIR) &&
3671                     !hdw->state_encoder_runok) {
3672                         /* This is a quirk.  OnAir hardware won't stream
3673                            digital until the encoder has been run at least
3674                            once, for a minimal period of time (empiricially
3675                            measured to be 1/4 second).  So if we're on
3676                            OnAir hardware and the encoder has never been
3677                            run at all, then start the encoder.  Normal
3678                            state machine logic in the driver will
3679                            automatically handle the remaining bits. */
3680                         return !0;
3681                 }
3682                 break;
3683         default:
3684                 /* For completeness (unknown mode; encoder won't run ever) */
3685                 break;
3686         }
3687         /* If we get here, then we haven't found any reason to run the
3688            encoder, so don't run it. */
3689         return 0;
3690 }
3691
3692
3693 /* Evaluate whether or not state_encoder_run can change */
3694 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3695 {
3696         if (hdw->state_encoder_run) {
3697                 if (!state_check_disable_encoder_run(hdw)) return 0;
3698                 if (hdw->state_encoder_ok) {
3699                         del_timer_sync(&hdw->encoder_run_timer);
3700                         if (pvr2_encoder_stop(hdw) < 0) return !0;
3701                 }
3702                 hdw->state_encoder_run = 0;
3703         } else {
3704                 if (!state_check_enable_encoder_run(hdw)) return 0;
3705                 if (pvr2_encoder_start(hdw) < 0) return !0;
3706                 hdw->state_encoder_run = !0;
3707                 if (!hdw->state_encoder_runok) {
3708                         hdw->encoder_run_timer.expires =
3709                                 jiffies + (HZ*250/1000);
3710                         add_timer(&hdw->encoder_run_timer);
3711                 }
3712         }
3713         trace_stbit("state_encoder_run",hdw->state_encoder_run);
3714         return !0;
3715 }
3716
3717
3718 /* Timeout function for quiescent timer. */
3719 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3720 {
3721         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3722         hdw->state_decoder_quiescent = !0;
3723         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3724         hdw->state_stale = !0;
3725         queue_work(hdw->workqueue,&hdw->workpoll);
3726 }
3727
3728
3729 /* Timeout function for encoder wait timer. */
3730 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3731 {
3732         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3733         hdw->state_encoder_waitok = !0;
3734         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3735         hdw->state_stale = !0;
3736         queue_work(hdw->workqueue,&hdw->workpoll);
3737 }
3738
3739
3740 /* Timeout function for encoder run timer. */
3741 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
3742 {
3743         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3744         if (!hdw->state_encoder_runok) {
3745                 hdw->state_encoder_runok = !0;
3746                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
3747                 hdw->state_stale = !0;
3748                 queue_work(hdw->workqueue,&hdw->workpoll);
3749         }
3750 }
3751
3752
3753 /* Evaluate whether or not state_decoder_run can change */
3754 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3755 {
3756         if (hdw->state_decoder_run) {
3757                 if (hdw->state_encoder_ok) {
3758                         if (hdw->state_pipeline_req &&
3759                             !hdw->state_pipeline_pause &&
3760                             hdw->state_pathway_ok) return 0;
3761                 }
3762                 if (!hdw->flag_decoder_missed) {
3763                         pvr2_decoder_enable(hdw,0);
3764                 }
3765                 hdw->state_decoder_quiescent = 0;
3766                 hdw->state_decoder_run = 0;
3767                 /* paranoia - solve race if timer just completed */
3768                 del_timer_sync(&hdw->quiescent_timer);
3769         } else {
3770                 if (!hdw->state_decoder_quiescent) {
3771                         if (!timer_pending(&hdw->quiescent_timer)) {
3772                                 /* We don't do something about the
3773                                    quiescent timer until right here because
3774                                    we also want to catch cases where the
3775                                    decoder was already not running (like
3776                                    after initialization) as opposed to
3777                                    knowing that we had just stopped it.
3778                                    The second flag check is here to cover a
3779                                    race - the timer could have run and set
3780                                    this flag just after the previous check
3781                                    but before we did the pending check. */
3782                                 if (!hdw->state_decoder_quiescent) {
3783                                         hdw->quiescent_timer.expires =
3784                                                 jiffies + (HZ*50/1000);
3785                                         add_timer(&hdw->quiescent_timer);
3786                                 }
3787                         }
3788                         /* Don't allow decoder to start again until it has
3789                            been quiesced first.  This little detail should
3790                            hopefully further stabilize the encoder. */
3791                         return 0;
3792                 }
3793                 if (!hdw->state_pathway_ok ||
3794                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3795                     !hdw->state_pipeline_req ||
3796                     hdw->state_pipeline_pause ||
3797                     !hdw->state_pipeline_config ||
3798                     !hdw->state_encoder_config ||
3799                     !hdw->state_encoder_ok) return 0;
3800                 del_timer_sync(&hdw->quiescent_timer);
3801                 if (hdw->flag_decoder_missed) return 0;
3802                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3803                 hdw->state_decoder_quiescent = 0;
3804                 hdw->state_decoder_run = !0;
3805         }
3806         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3807         trace_stbit("state_decoder_run",hdw->state_decoder_run);
3808         return !0;
3809 }
3810
3811
3812 /* Evaluate whether or not state_usbstream_run can change */
3813 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3814 {
3815         if (hdw->state_usbstream_run) {
3816                 int fl = !0;
3817                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3818                         fl = (hdw->state_encoder_ok &&
3819                               hdw->state_encoder_run);
3820                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3821                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3822                         fl = hdw->state_encoder_ok;
3823                 }
3824                 if (fl &&
3825                     hdw->state_pipeline_req &&
3826                     !hdw->state_pipeline_pause &&
3827                     hdw->state_pathway_ok) {
3828                         return 0;
3829                 }
3830                 pvr2_hdw_cmd_usbstream(hdw,0);
3831                 hdw->state_usbstream_run = 0;
3832         } else {
3833                 if (!hdw->state_pipeline_req ||
3834                     hdw->state_pipeline_pause ||
3835                     !hdw->state_pathway_ok) return 0;
3836                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3837                         if (!hdw->state_encoder_ok ||
3838                             !hdw->state_encoder_run) return 0;
3839                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3840                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3841                         if (!hdw->state_encoder_ok) return 0;
3842                         if (hdw->state_encoder_run) return 0;
3843                         if (hdw->hdw_desc->digital_control_scheme ==
3844                             PVR2_DIGITAL_SCHEME_ONAIR) {
3845                                 /* OnAir digital receivers won't stream
3846                                    unless the analog encoder has run first.
3847                                    Why?  I have no idea.  But don't even
3848                                    try until we know the analog side is
3849                                    known to have run. */
3850                                 if (!hdw->state_encoder_runok) return 0;
3851                         }
3852                 }
3853                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3854                 hdw->state_usbstream_run = !0;
3855         }
3856         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3857         return !0;
3858 }
3859
3860
3861 /* Attempt to configure pipeline, if needed */
3862 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3863 {
3864         if (hdw->state_pipeline_config ||
3865             hdw->state_pipeline_pause) return 0;
3866         pvr2_hdw_commit_execute(hdw);
3867         return !0;
3868 }
3869
3870
3871 /* Update pipeline idle and pipeline pause tracking states based on other
3872    inputs.  This must be called whenever the other relevant inputs have
3873    changed. */
3874 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3875 {
3876         unsigned int st;
3877         int updatedFl = 0;
3878         /* Update pipeline state */
3879         st = !(hdw->state_encoder_run ||
3880                hdw->state_decoder_run ||
3881                hdw->state_usbstream_run ||
3882                (!hdw->state_decoder_quiescent));
3883         if (!st != !hdw->state_pipeline_idle) {
3884                 hdw->state_pipeline_idle = st;
3885                 updatedFl = !0;
3886         }
3887         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3888                 hdw->state_pipeline_pause = 0;
3889                 updatedFl = !0;
3890         }
3891         return updatedFl;
3892 }
3893
3894
3895 typedef int (*state_eval_func)(struct pvr2_hdw *);
3896
3897 /* Set of functions to be run to evaluate various states in the driver. */
3898 static const state_eval_func eval_funcs[] = {
3899         state_eval_pathway_ok,
3900         state_eval_pipeline_config,
3901         state_eval_encoder_ok,
3902         state_eval_encoder_config,
3903         state_eval_decoder_run,
3904         state_eval_encoder_run,
3905         state_eval_usbstream_run,
3906 };
3907
3908
3909 /* Process various states and return true if we did anything interesting. */
3910 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3911 {
3912         unsigned int i;
3913         int state_updated = 0;
3914         int check_flag;
3915
3916         if (!hdw->state_stale) return 0;
3917         if ((hdw->fw1_state != FW1_STATE_OK) ||
3918             !hdw->flag_ok) {
3919                 hdw->state_stale = 0;
3920                 return !0;
3921         }
3922         /* This loop is the heart of the entire driver.  It keeps trying to
3923            evaluate various bits of driver state until nothing changes for
3924            one full iteration.  Each "bit of state" tracks some global
3925            aspect of the driver, e.g. whether decoder should run, if
3926            pipeline is configured, usb streaming is on, etc.  We separately
3927            evaluate each of those questions based on other driver state to
3928            arrive at the correct running configuration. */
3929         do {
3930                 check_flag = 0;
3931                 state_update_pipeline_state(hdw);
3932                 /* Iterate over each bit of state */
3933                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3934                         if ((*eval_funcs[i])(hdw)) {
3935                                 check_flag = !0;
3936                                 state_updated = !0;
3937                                 state_update_pipeline_state(hdw);
3938                         }
3939                 }
3940         } while (check_flag && hdw->flag_ok);
3941         hdw->state_stale = 0;
3942         trace_stbit("state_stale",hdw->state_stale);
3943         return state_updated;
3944 }
3945
3946
3947 static const char *pvr2_pathway_state_name(int id)
3948 {
3949         switch (id) {
3950         case PVR2_PATHWAY_ANALOG: return "analog";
3951         case PVR2_PATHWAY_DIGITAL: return "digital";
3952         default: return "unknown";
3953         }
3954 }
3955
3956
3957 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3958                                              char *buf,unsigned int acnt)
3959 {
3960         switch (which) {
3961         case 0:
3962                 return scnprintf(
3963                         buf,acnt,
3964                         "driver:%s%s%s%s%s <mode=%s>",
3965                         (hdw->flag_ok ? " <ok>" : " <fail>"),
3966                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3967                         (hdw->flag_disconnected ? " <disconnected>" :
3968                          " <connected>"),
3969                         (hdw->flag_tripped ? " <tripped>" : ""),
3970                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
3971                         pvr2_pathway_state_name(hdw->pathway_state));
3972
3973         case 1:
3974                 return scnprintf(
3975                         buf,acnt,
3976                         "pipeline:%s%s%s%s",
3977                         (hdw->state_pipeline_idle ? " <idle>" : ""),
3978                         (hdw->state_pipeline_config ?
3979                          " <configok>" : " <stale>"),
3980                         (hdw->state_pipeline_req ? " <req>" : ""),
3981                         (hdw->state_pipeline_pause ? " <pause>" : ""));
3982         case 2:
3983                 return scnprintf(
3984                         buf,acnt,
3985                         "worker:%s%s%s%s%s%s%s",
3986                         (hdw->state_decoder_run ?
3987                          " <decode:run>" :
3988                          (hdw->state_decoder_quiescent ?
3989                           "" : " <decode:stop>")),
3990                         (hdw->state_decoder_quiescent ?
3991                          " <decode:quiescent>" : ""),
3992                         (hdw->state_encoder_ok ?
3993                          "" : " <encode:init>"),
3994                         (hdw->state_encoder_run ?
3995                          (hdw->state_encoder_runok ?
3996                           " <encode:run>" :
3997                           " <encode:firstrun>") :
3998                          (hdw->state_encoder_runok ?
3999                           " <encode:stop>" :
4000                           " <encode:virgin>")),
4001                         (hdw->state_encoder_config ?
4002                          " <encode:configok>" :
4003                          (hdw->state_encoder_waitok ?
4004                           "" : " <encode:waitok>")),
4005                         (hdw->state_usbstream_run ?
4006                          " <usb:run>" : " <usb:stop>"),
4007                         (hdw->state_pathway_ok ?
4008                          " <pathway:ok>" : ""));
4009         case 3:
4010                 return scnprintf(
4011                         buf,acnt,
4012                         "state: %s",
4013                         pvr2_get_state_name(hdw->master_state));
4014         case 4: {
4015                 struct pvr2_stream_stats stats;
4016                 if (!hdw->vid_stream) break;
4017                 pvr2_stream_get_stats(hdw->vid_stream,
4018                                       &stats,
4019                                       0);
4020                 return scnprintf(
4021                         buf,acnt,
4022                         "Bytes streamed=%u"
4023                         " URBs: queued=%u idle=%u ready=%u"
4024                         " processed=%u failed=%u",
4025                         stats.bytes_processed,
4026                         stats.buffers_in_queue,
4027                         stats.buffers_in_idle,
4028                         stats.buffers_in_ready,
4029                         stats.buffers_processed,
4030                         stats.buffers_failed);
4031         }
4032         default: break;
4033         }
4034         return 0;
4035 }
4036
4037
4038 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4039                                    char *buf,unsigned int acnt)
4040 {
4041         unsigned int bcnt,ccnt,idx;
4042         bcnt = 0;
4043         LOCK_TAKE(hdw->big_lock);
4044         for (idx = 0; ; idx++) {
4045                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4046                 if (!ccnt) break;
4047                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4048                 if (!acnt) break;
4049                 buf[0] = '\n'; ccnt = 1;
4050                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4051         }
4052         LOCK_GIVE(hdw->big_lock);
4053         return bcnt;
4054 }
4055
4056
4057 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4058 {
4059         char buf[128];
4060         unsigned int idx,ccnt;
4061
4062         for (idx = 0; ; idx++) {
4063                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4064                 if (!ccnt) break;
4065                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4066         }
4067 }
4068
4069
4070 /* Evaluate and update the driver's current state, taking various actions
4071    as appropriate for the update. */
4072 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4073 {
4074         unsigned int st;
4075         int state_updated = 0;
4076         int callback_flag = 0;
4077         int analog_mode;
4078
4079         pvr2_trace(PVR2_TRACE_STBITS,
4080                    "Drive state check START");
4081         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4082                 pvr2_hdw_state_log_state(hdw);
4083         }
4084
4085         /* Process all state and get back over disposition */
4086         state_updated = pvr2_hdw_state_update(hdw);
4087
4088         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4089
4090         /* Update master state based upon all other states. */
4091         if (!hdw->flag_ok) {
4092                 st = PVR2_STATE_DEAD;
4093         } else if (hdw->fw1_state != FW1_STATE_OK) {
4094                 st = PVR2_STATE_COLD;
4095         } else if ((analog_mode ||
4096                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4097                    !hdw->state_encoder_ok) {
4098                 st = PVR2_STATE_WARM;
4099         } else if (hdw->flag_tripped ||
4100                    (analog_mode && hdw->flag_decoder_missed)) {
4101                 st = PVR2_STATE_ERROR;
4102         } else if (hdw->state_usbstream_run &&
4103                    (!analog_mode ||
4104                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4105                 st = PVR2_STATE_RUN;
4106         } else {
4107                 st = PVR2_STATE_READY;
4108         }
4109         if (hdw->master_state != st) {
4110                 pvr2_trace(PVR2_TRACE_STATE,
4111                            "Device state change from %s to %s",
4112                            pvr2_get_state_name(hdw->master_state),
4113                            pvr2_get_state_name(st));
4114                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4115                 hdw->master_state = st;
4116                 state_updated = !0;
4117                 callback_flag = !0;
4118         }
4119         if (state_updated) {
4120                 /* Trigger anyone waiting on any state changes here. */
4121                 wake_up(&hdw->state_wait_data);
4122         }
4123
4124         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4125                 pvr2_hdw_state_log_state(hdw);
4126         }
4127         pvr2_trace(PVR2_TRACE_STBITS,
4128                    "Drive state check DONE callback=%d",callback_flag);
4129
4130         return callback_flag;
4131 }
4132
4133
4134 /* Cause kernel thread to check / update driver state */
4135 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4136 {
4137         if (hdw->state_stale) return;
4138         hdw->state_stale = !0;
4139         trace_stbit("state_stale",hdw->state_stale);
4140         queue_work(hdw->workqueue,&hdw->workpoll);
4141 }
4142
4143
4144 void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
4145                                       struct pvr2_hdw_debug_info *ptr)
4146 {
4147         ptr->big_lock_held = hdw->big_lock_held;
4148         ptr->ctl_lock_held = hdw->ctl_lock_held;
4149         ptr->flag_disconnected = hdw->flag_disconnected;
4150         ptr->flag_init_ok = hdw->flag_init_ok;
4151         ptr->flag_ok = hdw->flag_ok;
4152         ptr->fw1_state = hdw->fw1_state;
4153         ptr->flag_decoder_missed = hdw->flag_decoder_missed;
4154         ptr->flag_tripped = hdw->flag_tripped;
4155         ptr->state_encoder_ok = hdw->state_encoder_ok;
4156         ptr->state_encoder_run = hdw->state_encoder_run;
4157         ptr->state_decoder_run = hdw->state_decoder_run;
4158         ptr->state_usbstream_run = hdw->state_usbstream_run;
4159         ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
4160         ptr->state_pipeline_config = hdw->state_pipeline_config;
4161         ptr->state_pipeline_req = hdw->state_pipeline_req;
4162         ptr->state_pipeline_pause = hdw->state_pipeline_pause;
4163         ptr->state_pipeline_idle = hdw->state_pipeline_idle;
4164         ptr->cmd_debug_state = hdw->cmd_debug_state;
4165         ptr->cmd_code = hdw->cmd_debug_code;
4166         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
4167         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
4168         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
4169         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
4170         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
4171         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
4172         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
4173 }
4174
4175
4176 void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
4177                                     struct pvr2_hdw_debug_info *ptr)
4178 {
4179         LOCK_TAKE(hdw->ctl_lock); do {
4180                 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
4181         } while(0); LOCK_GIVE(hdw->ctl_lock);
4182 }
4183
4184
4185 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4186 {
4187         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4188 }
4189
4190
4191 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4192 {
4193         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4194 }
4195
4196
4197 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4198 {
4199         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4200 }
4201
4202
4203 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4204 {
4205         u32 cval,nval;
4206         int ret;
4207         if (~msk) {
4208                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4209                 if (ret) return ret;
4210                 nval = (cval & ~msk) | (val & msk);
4211                 pvr2_trace(PVR2_TRACE_GPIO,
4212                            "GPIO direction changing 0x%x:0x%x"
4213                            " from 0x%x to 0x%x",
4214                            msk,val,cval,nval);
4215         } else {
4216                 nval = val;
4217                 pvr2_trace(PVR2_TRACE_GPIO,
4218                            "GPIO direction changing to 0x%x",nval);
4219         }
4220         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4221 }
4222
4223
4224 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4225 {
4226         u32 cval,nval;
4227         int ret;
4228         if (~msk) {
4229                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4230                 if (ret) return ret;
4231                 nval = (cval & ~msk) | (val & msk);
4232                 pvr2_trace(PVR2_TRACE_GPIO,
4233                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4234                            msk,val,cval,nval);
4235         } else {
4236                 nval = val;
4237                 pvr2_trace(PVR2_TRACE_GPIO,
4238                            "GPIO output changing to 0x%x",nval);
4239         }
4240         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4241 }
4242
4243
4244 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4245 {
4246         return hdw->input_avail_mask;
4247 }
4248
4249
4250 /* Find I2C address of eeprom */
4251 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4252 {
4253         int result;
4254         LOCK_TAKE(hdw->ctl_lock); do {
4255                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4256                 result = pvr2_send_request(hdw,
4257                                            hdw->cmd_buffer,1,
4258                                            hdw->cmd_buffer,1);
4259                 if (result < 0) break;
4260                 result = hdw->cmd_buffer[0];
4261         } while(0); LOCK_GIVE(hdw->ctl_lock);
4262         return result;
4263 }
4264
4265
4266 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4267                              u32 match_type, u32 match_chip, u64 reg_id,
4268                              int setFl,u64 *val_ptr)
4269 {
4270 #ifdef CONFIG_VIDEO_ADV_DEBUG
4271         struct pvr2_i2c_client *cp;
4272         struct v4l2_register req;
4273         int stat = 0;
4274         int okFl = 0;
4275
4276         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4277
4278         req.match_type = match_type;
4279         req.match_chip = match_chip;
4280         req.reg = reg_id;
4281         if (setFl) req.val = *val_ptr;
4282         mutex_lock(&hdw->i2c_list_lock); do {
4283                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4284                         if (!v4l2_chip_match_i2c_client(
4285                                     cp->client,
4286                                     req.match_type, req.match_chip)) {
4287                                 continue;
4288                         }
4289                         stat = pvr2_i2c_client_cmd(
4290                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4291                                     VIDIOC_DBG_G_REGISTER),&req);
4292                         if (!setFl) *val_ptr = req.val;
4293                         okFl = !0;
4294                         break;
4295                 }
4296         } while (0); mutex_unlock(&hdw->i2c_list_lock);
4297         if (okFl) {
4298                 return stat;
4299         }
4300         return -EINVAL;
4301 #else
4302         return -ENOSYS;
4303 #endif
4304 }
4305
4306
4307 /*
4308   Stuff for Emacs to see, in order to encourage consistent editing style:
4309   *** Local Variables: ***
4310   *** mode: c ***
4311   *** fill-column: 75 ***
4312   *** tab-width: 8 ***
4313   *** c-basic-offset: 8 ***
4314   *** End: ***
4315   */