2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
33 #include <mach/control.h>
35 #include <mach/mcbsp.h>
36 #include "omap-mcbsp.h"
39 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41 struct omap_mcbsp_data {
43 struct omap_mcbsp_reg_cfg regs;
46 * Flags indicating is the bus already activated and configured by
53 #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
55 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
58 * Stream DMA parameters. DMA request line and port address are set runtime
59 * since they are different between OMAP1 and later OMAPs
61 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
63 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
64 static const int omap1_dma_reqs[][2] = {
65 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
66 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
67 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
69 static const unsigned long omap1_mcbsp_port[][2] = {
70 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
71 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
72 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
73 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
74 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
75 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
78 static const int omap1_dma_reqs[][2] = {};
79 static const unsigned long omap1_mcbsp_port[][2] = {};
82 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
83 static const int omap24xx_dma_reqs[][2] = {
84 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
85 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
86 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
87 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
88 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
89 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
93 static const int omap24xx_dma_reqs[][2] = {};
96 #if defined(CONFIG_ARCH_OMAP2420)
97 static const unsigned long omap2420_mcbsp_port[][2] = {
98 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
99 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
100 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
101 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
104 static const unsigned long omap2420_mcbsp_port[][2] = {};
107 #if defined(CONFIG_ARCH_OMAP2430)
108 static const unsigned long omap2430_mcbsp_port[][2] = {
109 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
110 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
111 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
112 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
113 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
114 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
115 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
116 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
117 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
118 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
121 static const unsigned long omap2430_mcbsp_port[][2] = {};
124 #if defined(CONFIG_ARCH_OMAP34XX)
125 static const unsigned long omap34xx_mcbsp_port[][2] = {
126 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
128 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
129 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
130 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
131 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
132 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
133 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
134 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
135 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
138 static const unsigned long omap34xx_mcbsp_port[][2] = {};
141 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
142 struct snd_soc_dai *dai)
144 struct snd_soc_pcm_runtime *rtd = substream->private_data;
145 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
146 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
149 if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
151 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
152 * Set constraint for minimum buffer size to the same than FIFO
153 * size in order to avoid underruns in playback startup because
154 * HW is keeping the DMA request active until FIFO is filled.
156 snd_pcm_hw_constraint_minmax(substream->runtime,
157 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
160 if (!cpu_dai->active)
161 err = omap_mcbsp_request(mcbsp_data->bus_id);
166 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
167 struct snd_soc_dai *dai)
169 struct snd_soc_pcm_runtime *rtd = substream->private_data;
170 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
171 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
173 if (!cpu_dai->active) {
174 omap_mcbsp_free(mcbsp_data->bus_id);
175 mcbsp_data->configured = 0;
179 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
180 struct snd_soc_dai *dai)
182 struct snd_soc_pcm_runtime *rtd = substream->private_data;
183 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
184 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
188 case SNDRV_PCM_TRIGGER_START:
189 case SNDRV_PCM_TRIGGER_RESUME:
190 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
191 if (!mcbsp_data->active++)
192 omap_mcbsp_start(mcbsp_data->bus_id);
195 case SNDRV_PCM_TRIGGER_STOP:
196 case SNDRV_PCM_TRIGGER_SUSPEND:
197 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
198 if (!--mcbsp_data->active)
199 omap_mcbsp_stop(mcbsp_data->bus_id);
208 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
209 struct snd_pcm_hw_params *params,
210 struct snd_soc_dai *dai)
212 struct snd_soc_pcm_runtime *rtd = substream->private_data;
213 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
214 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
215 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
216 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
220 if (cpu_class_is_omap1()) {
221 dma = omap1_dma_reqs[bus_id][substream->stream];
222 port = omap1_mcbsp_port[bus_id][substream->stream];
223 } else if (cpu_is_omap2420()) {
224 dma = omap24xx_dma_reqs[bus_id][substream->stream];
225 port = omap2420_mcbsp_port[bus_id][substream->stream];
226 } else if (cpu_is_omap2430()) {
227 dma = omap24xx_dma_reqs[bus_id][substream->stream];
228 port = omap2430_mcbsp_port[bus_id][substream->stream];
229 } else if (cpu_is_omap343x()) {
230 dma = omap24xx_dma_reqs[bus_id][substream->stream];
231 port = omap34xx_mcbsp_port[bus_id][substream->stream];
235 omap_mcbsp_dai_dma_params[id][substream->stream].name =
236 substream->stream ? "Audio Capture" : "Audio Playback";
237 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
238 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
239 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
241 if (mcbsp_data->configured) {
242 /* McBSP already configured by another stream */
246 channels = params_channels(params);
249 /* Use dual-phase frames */
250 regs->rcr2 |= RPHASE;
251 regs->xcr2 |= XPHASE;
253 /* Set 1 word per (McBSP) frame */
254 regs->rcr2 |= RFRLEN2(1 - 1);
255 regs->rcr1 |= RFRLEN1(1 - 1);
256 regs->xcr2 |= XFRLEN2(1 - 1);
257 regs->xcr1 |= XFRLEN1(1 - 1);
260 /* Unsupported number of channels */
264 switch (params_format(params)) {
265 case SNDRV_PCM_FORMAT_S16_LE:
266 /* Set word lengths */
268 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
269 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
270 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
271 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
274 /* Unsupported PCM format */
278 /* Set FS period and length in terms of bit clock periods */
279 switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
280 case SND_SOC_DAIFMT_I2S:
281 regs->srgr2 |= FPER(wlen * 2 - 1);
282 regs->srgr1 |= FWID(wlen - 1);
284 case SND_SOC_DAIFMT_DSP_B:
285 regs->srgr2 |= FPER(wlen * channels - 1);
286 regs->srgr1 |= FWID(0);
290 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
291 mcbsp_data->configured = 1;
297 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
298 * cache is initialized here
300 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
303 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
304 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
305 unsigned int temp_fmt = fmt;
307 if (mcbsp_data->configured)
310 mcbsp_data->fmt = fmt;
311 memset(regs, 0, sizeof(*regs));
312 /* Generic McBSP register settings */
313 regs->spcr2 |= XINTM(3) | FREE;
314 regs->spcr1 |= RINTM(3);
317 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
318 regs->xccr = DXENDLY(1) | XDMAEN;
319 regs->rccr = RFULL_CYCLE | RDMAEN;
322 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
323 case SND_SOC_DAIFMT_I2S:
324 /* 1-bit data delay */
325 regs->rcr2 |= RDATDLY(1);
326 regs->xcr2 |= XDATDLY(1);
328 case SND_SOC_DAIFMT_DSP_B:
329 /* 0-bit data delay */
330 regs->rcr2 |= RDATDLY(0);
331 regs->xcr2 |= XDATDLY(0);
332 /* Invert FS polarity configuration */
333 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
336 /* Unsupported data format */
340 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
341 case SND_SOC_DAIFMT_CBS_CFS:
342 /* McBSP master. Set FS and bit clocks as outputs */
343 regs->pcr0 |= FSXM | FSRM |
345 /* Sample rate generator drives the FS */
348 case SND_SOC_DAIFMT_CBM_CFM:
352 /* Unsupported master/slave configuration */
356 /* Set bit clock (CLKX/CLKR) and FS polarities */
357 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
358 case SND_SOC_DAIFMT_NB_NF:
361 * FS active low. TX data driven on falling edge of bit clock
362 * and RX data sampled on rising edge of bit clock.
364 regs->pcr0 |= FSXP | FSRP |
367 case SND_SOC_DAIFMT_NB_IF:
368 regs->pcr0 |= CLKXP | CLKRP;
370 case SND_SOC_DAIFMT_IB_NF:
371 regs->pcr0 |= FSXP | FSRP;
373 case SND_SOC_DAIFMT_IB_IF:
382 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
385 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
386 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
388 if (div_id != OMAP_MCBSP_CLKGDV)
391 regs->srgr1 |= CLKGDV(div - 1);
396 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
400 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
402 if (cpu_class_is_omap1()) {
403 /* OMAP1's can use only external source clock */
404 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
410 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
413 if (cpu_is_omap343x())
414 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
416 switch (mcbsp_data->bus_id) {
418 reg = OMAP2_CONTROL_DEVCONF0;
422 reg = OMAP2_CONTROL_DEVCONF0;
441 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
442 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
444 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
449 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
450 int clk_id, unsigned int freq,
453 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
454 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
458 case OMAP_MCBSP_SYSCLK_CLK:
459 regs->srgr2 |= CLKSM;
461 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
462 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
463 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
466 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
467 regs->srgr2 |= CLKSM;
468 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
469 regs->pcr0 |= SCLKME;
478 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
479 .startup = omap_mcbsp_dai_startup,
480 .shutdown = omap_mcbsp_dai_shutdown,
481 .trigger = omap_mcbsp_dai_trigger,
482 .hw_params = omap_mcbsp_dai_hw_params,
483 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
484 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
485 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
488 #define OMAP_MCBSP_DAI_BUILDER(link_id) \
490 .name = "omap-mcbsp-dai-"#link_id, \
495 .rates = OMAP_MCBSP_RATES, \
496 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
501 .rates = OMAP_MCBSP_RATES, \
502 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
504 .ops = &omap_mcbsp_dai_ops, \
505 .private_data = &mcbsp_data[(link_id)].bus_id, \
508 struct snd_soc_dai omap_mcbsp_dai[] = {
509 OMAP_MCBSP_DAI_BUILDER(0),
510 OMAP_MCBSP_DAI_BUILDER(1),
512 OMAP_MCBSP_DAI_BUILDER(2),
515 OMAP_MCBSP_DAI_BUILDER(3),
516 OMAP_MCBSP_DAI_BUILDER(4),
520 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
522 static int __init snd_omap_mcbsp_init(void)
524 return snd_soc_register_dais(omap_mcbsp_dai,
525 ARRAY_SIZE(omap_mcbsp_dai));
527 module_init(snd_omap_mcbsp_init);
529 static void __exit snd_omap_mcbsp_exit(void)
531 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
533 module_exit(snd_omap_mcbsp_exit);
535 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
536 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
537 MODULE_LICENSE("GPL");