git.oblomov.eu Git - linux-2.6/blob - sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *   This program is free software; you can redistribute it and/or modify
  12  *   it under the terms of the GNU General Public License as published by
  13  *   the Free Software Foundation; either version 2 of the License, or
  14  *   (at your option) any later version.
  15  *
  16  *   This program is distributed in the hope that it will be useful,
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *   GNU General Public License for more details.
  20  *
  21  *   You should have received a copy of the GNU General Public License
  22  *   along with this program; if not, write to the Free Software
  23  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  24  *
  25  */
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <asm/io.h>
  33
  34 #include <sound/core.h>
  35 #include <sound/control.h>
  36 #include <sound/pcm.h>
  37 #include <sound/info.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/rawmidi.h>
  40 #include <sound/hwdep.h>
  41 #include <sound/initval.h>
  42
  43 #include <sound/hdspm.h>
  44
  45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
  46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
  47 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  48
  49 /* Disable precise pointer at start */
  50 static int precise_ptr[SNDRV_CARDS];
  51
  52 /* Send all playback to line outs */
  53 static int line_outs_monitor[SNDRV_CARDS];
  54
  55 /* Enable Analog Outs on Channel 63/64 by default */
  56 static int enable_monitor[SNDRV_CARDS];
  57
  58 module_param_array(index, int, NULL, 0444);
  59 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
  60
  61 module_param_array(id, charp, NULL, 0444);
  62 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
  63
  64 module_param_array(enable, bool, NULL, 0444);
  65 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
  66
  67 module_param_array(precise_ptr, bool, NULL, 0444);
  68 MODULE_PARM_DESC(precise_ptr, "Enable or disable precise pointer.");
  69
  70 module_param_array(line_outs_monitor, bool, NULL, 0444);
  71 MODULE_PARM_DESC(line_outs_monitor,
  72                  "Send playback streams to analog outs by default.");
  73
  74 module_param_array(enable_monitor, bool, NULL, 0444);
  75 MODULE_PARM_DESC(enable_monitor,
  76                  "Enable Analog Out on Channel 63/64 by default.");
  77
  78 MODULE_AUTHOR
  79       ("Winfried Ritsch <ritsch_AT_iem.at>, "
  80        "Paul Davis <paul@linuxaudiosystems.com>, "
  81        "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
  82        "Remy Bruno <remy.bruno@trinnov.com>");
  83 MODULE_DESCRIPTION("RME HDSPM");
  84 MODULE_LICENSE("GPL");
  85 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
  86
  87 /* --- Write registers. ---
  88   These are defined as byte-offsets from the iobase value.  */
  89
  90 #define HDSPM_controlRegister        64
  91 #define HDSPM_interruptConfirmation  96
  92 #define HDSPM_control2Reg            256  /* not in specs ???????? */
  93 #define HDSPM_freqReg                256  /* for AES32 */
  94 #define HDSPM_midiDataOut0           352  /* just believe in old code */
  95 #define HDSPM_midiDataOut1           356
  96 #define HDSPM_eeprom_wr              384  /* for AES32 */
  97
  98 /* DMA enable for 64 channels, only Bit 0 is relevant */
  99 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 100 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 101
 102 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 103    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 104 #define HDSPM_pageAddressBufferOut       8192
 105 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 106
 107 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 108
 109 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 110
 111 /* --- Read registers. ---
 112    These are defined as byte-offsets from the iobase value */
 113 #define HDSPM_statusRegister    0
 114 /*#define HDSPM_statusRegister2  96 */
 115 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 116  * offset 192, for AES32 *and* MADI
 117  * => need to check that offset 192 is working on MADI */
 118 #define HDSPM_statusRegister2  192
 119 #define HDSPM_timecodeRegister 128
 120
 121 #define HDSPM_midiDataIn0     360
 122 #define HDSPM_midiDataIn1     364
 123
 124 /* status is data bytes in MIDI-FIFO (0-128) */
 125 #define HDSPM_midiStatusOut0  384
 126 #define HDSPM_midiStatusOut1  388
 127 #define HDSPM_midiStatusIn0   392
 128 #define HDSPM_midiStatusIn1   396
 129
 130
 131 /* the meters are regular i/o-mapped registers, but offset
 132    considerably from the rest. the peak registers are reset
 133    when read; the least-significant 4 bits are full-scale counters;
 134    the actual peak value is in the most-significant 24 bits.
 135 */
 136 #define HDSPM_MADI_peakrmsbase  4096    /* 4096-8191 2x64x32Bit Meters */
 137
 138 /* --- Control Register bits --------- */
 139 #define HDSPM_Start                (1<<0) /* start engine */
 140
 141 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 142 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 143 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 144
 145 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Slave/Autosync */
 146
 147 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 148
 149 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 150 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 151 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 152 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 153
 154 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 155 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 156                                      56channelMODE=0 */ /* MADI ONLY*/
 157 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 158
 159 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 160                                      0=off, 1=on  */ /* MADI ONLY */
 161 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 162
 163 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 164                                     * -- MADI ONLY
 165                                     */
 166 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 167
 168 #define HDSPM_SyncRef0     (1<<16) /* 0=WOrd, 1=MADI */
 169 #define HDSPM_SyncRef1     (1<<17) /* for AES32: SyncRefN codes the AES # */
 170 #define HDSPM_SyncRef2     (1<<13)
 171 #define HDSPM_SyncRef3     (1<<25)
 172
 173 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 174 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 175                                       AES additional bits in
 176                                       lower 5 Audiodatabits ??? */
 177 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 178 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 179
 180 #define HDSPM_Midi0InterruptEnable (1<<22)
 181 #define HDSPM_Midi1InterruptEnable (1<<23)
 182
 183 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 184
 185 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 186 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 187 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 188
 189 #define HDSPM_wclk_sel (1<<30)
 190
 191 /* --- bit helper defines */
 192 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 193 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 194                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 195 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 196 #define HDSPM_InputOptical   0
 197 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 198 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 199                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 200 #define HDSPM_SyncRef_Word   0
 201 #define HDSPM_SyncRef_MADI   (HDSPM_SyncRef0)
 202
 203 #define HDSPM_SYNC_FROM_WORD 0  /* Preferred sync reference */
 204 #define HDSPM_SYNC_FROM_MADI 1  /* choices - used by "pref_sync_ref" */
 205
 206 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 207 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 208 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 209 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 210 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 211 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 212                                 HDSPM_Frequency0)
 213 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 214 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 215 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 216                                  HDSPM_Frequency0)
 217
 218 /* --- for internal discrimination */
 219 #define HDSPM_CLOCK_SOURCE_AUTOSYNC          0  /* Sample Clock Sources */
 220 #define HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ    1
 221 #define HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ  2
 222 #define HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ    3
 223 #define HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ    4
 224 #define HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ  5
 225 #define HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ    6
 226 #define HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ   7
 227 #define HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
 228 #define HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ   9
 229
 230 /* Synccheck Status */
 231 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 232 #define HDSPM_SYNC_CHECK_LOCK    1
 233 #define HDSPM_SYNC_CHECK_SYNC    2
 234
 235 /* AutoSync References - used by "autosync_ref" control switch */
 236 #define HDSPM_AUTOSYNC_FROM_WORD      0
 237 #define HDSPM_AUTOSYNC_FROM_MADI      1
 238 #define HDSPM_AUTOSYNC_FROM_NONE      2
 239
 240 /* Possible sources of MADI input */
 241 #define HDSPM_OPTICAL 0         /* optical   */
 242 #define HDSPM_COAXIAL 1         /* BNC */
 243
 244 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 245 #define hdspm_decode_latency(x)       (((x) & HDSPM_LatencyMask)>>1)
 246
 247 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 248 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 249
 250 /* --- control2 register bits --- */
 251 #define HDSPM_TMS             (1<<0)
 252 #define HDSPM_TCK             (1<<1)
 253 #define HDSPM_TDI             (1<<2)
 254 #define HDSPM_JTAG            (1<<3)
 255 #define HDSPM_PWDN            (1<<4)
 256 #define HDSPM_PROGRAM         (1<<5)
 257 #define HDSPM_CONFIG_MODE_0   (1<<6)
 258 #define HDSPM_CONFIG_MODE_1   (1<<7)
 259 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 260 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 261 #define HDSPM_RD_MULTIPLE     (1<<10)
 262
 263 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 264      that do not conflict with specific bits for AES32 seem to be valid also
 265      for the AES32
 266  */
 267 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 268 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 269 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 270                                          * (like inp0)
 271                                          */
 272 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 273
 274 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 275                                            /* since 64byte accurate last 6 bits
 276                                               are not used */
 277
 278 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 279 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 280
 281 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 282 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 283 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 284 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 285
 286 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 287                                          * Interrupt
 288                                          */
 289 #define HDSPM_midi0IRQPending   (1<<30) /* MIDI IRQ is pending  */
 290 #define HDSPM_midi1IRQPending   (1<<31) /* and aktiv */
 291
 292 /* --- status bit helpers */
 293 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 294                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 295 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 296 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 297 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 298 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 299 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 300 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 301 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 302 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 303 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 304
 305 /* Status2 Register bits */ /* MADI ONLY */
 306
 307 #define HDSPM_version0 (1<<0)   /* not realy defined but I guess */
 308 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 309 #define HDSPM_version2 (1<<2)
 310
 311 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 312 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 313
 314 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 315 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 316 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
 317 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
 318
 319 #define HDSPM_SelSyncRef0 (1<<8)        /* Sync Source in slave mode */
 320 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 321 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 322
 323 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 324
 325 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 326 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 327 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 328 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 329 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 330 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 331 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 332
 333
 334 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 335                                     HDSPM_SelSyncRef2)
 336 #define HDSPM_SelSyncRef_WORD      0
 337 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 338 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 339                                     HDSPM_SelSyncRef2)
 340
 341 /*
 342    For AES32, bits for status, status2 and timecode are different
 343 */
 344 /* status */
 345 #define HDSPM_AES32_wcLock      0x0200000
 346 #define HDSPM_AES32_wcFreq_bit  22
 347 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 348   HDSPM_bit2freq */
 349 #define HDSPM_AES32_syncref_bit  16
 350 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 351
 352 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 353 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 354 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 355 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 356 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 357 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 358 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 359 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 360 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 361 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
 362
 363 /*  status2 */
 364 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 365 #define HDSPM_LockAES   0x80
 366 #define HDSPM_LockAES1  0x80
 367 #define HDSPM_LockAES2  0x40
 368 #define HDSPM_LockAES3  0x20
 369 #define HDSPM_LockAES4  0x10
 370 #define HDSPM_LockAES5  0x8
 371 #define HDSPM_LockAES6  0x4
 372 #define HDSPM_LockAES7  0x2
 373 #define HDSPM_LockAES8  0x1
 374 /*
 375    Timecode
 376    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 377    AES i+1
 378  bits 3210
 379       0001  32kHz
 380       0010  44.1kHz
 381       0011  48kHz
 382       0100  64kHz
 383       0101  88.2kHz
 384       0110  96kHz
 385       0111  128kHz
 386       1000  176.4kHz
 387       1001  192kHz
 388   NB: Timecode register doesn't seem to work on AES32 card revision 230
 389 */
 390
 391 /* Mixer Values */
 392 #define UNITY_GAIN          32768       /* = 65536/2 */
 393 #define MINUS_INFINITY_GAIN 0
 394
 395 /* Number of channels for different Speed Modes */
 396 #define MADI_SS_CHANNELS       64
 397 #define MADI_DS_CHANNELS       32
 398 #define MADI_QS_CHANNELS       16
 399
 400 /* the size of a substream (1 mono data stream) */
 401 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 402 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 403
 404 /* the size of the area we need to allocate for DMA transfers. the
 405    size is the same regardless of the number of channels, and
 406    also the latency to use.
 407    for one direction !!!
 408 */
 409 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 410 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 411
 412 /* revisions >= 230 indicate AES32 card */
 413 #define HDSPM_AESREVISION 230
 414
 415 /* speed factor modes */
 416 #define HDSPM_SPEED_SINGLE 0
 417 #define HDSPM_SPEED_DOUBLE 1
 418 #define HDSPM_SPEED_QUAD   2
 419 /* names for speed modes */
 420 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 421
 422 struct hdspm_midi {
 423         struct hdspm *hdspm;
 424         int id;
 425         struct snd_rawmidi *rmidi;
 426         struct snd_rawmidi_substream *input;
 427         struct snd_rawmidi_substream *output;
 428         char istimer;           /* timer in use */
 429         struct timer_list timer;
 430         spinlock_t lock;
 431         int pending;
 432 };
 433
 434 struct hdspm {
 435         spinlock_t lock;
 436         /* only one playback and/or capture stream */
 437         struct snd_pcm_substream *capture_substream;
 438         struct snd_pcm_substream *playback_substream;
 439
 440         char *card_name;             /* for procinfo */
 441         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
 442
 443         unsigned char is_aes32;    /* indicates if card is AES32 */
 444
 445         int precise_ptr;        /* use precise pointers, to be tested */
 446         int monitor_outs;       /* set up monitoring outs init flag */
 447
 448         u32 control_register;   /* cached value */
 449         u32 control2_register;  /* cached value */
 450
 451         struct hdspm_midi midi[2];
 452         struct tasklet_struct midi_tasklet;
 453
 454         size_t period_bytes;
 455         unsigned char ss_channels;      /* channels of card in single speed */
 456         unsigned char ds_channels;      /* Double Speed */
 457         unsigned char qs_channels;      /* Quad Speed */
 458
 459         unsigned char *playback_buffer; /* suitably aligned address */
 460         unsigned char *capture_buffer;  /* suitably aligned address */
 461
 462         pid_t capture_pid;      /* process id which uses capture */
 463         pid_t playback_pid;     /* process id which uses capture */
 464         int running;            /* running status */
 465
 466         int last_external_sample_rate;  /* samplerate mystic ... */
 467         int last_internal_sample_rate;
 468         int system_sample_rate;
 469
 470         char *channel_map;      /* channel map for DS and Quadspeed */
 471
 472         int dev;                /* Hardware vars... */
 473         int irq;
 474         unsigned long port;
 475         void __iomem *iobase;
 476
 477         int irq_count;          /* for debug */
 478
 479         struct snd_card *card;  /* one card */
 480         struct snd_pcm *pcm;            /* has one pcm */
 481         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
 482         struct pci_dev *pci;    /* and an pci info */
 483
 484         /* Mixer vars */
 485         /* fast alsa mixer */
 486         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
 487         /* but input to much, so not used */
 488         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
 489         /* full mixer accessable over mixer ioctl or hwdep-device */
 490         struct hdspm_mixer *mixer;
 491
 492 };
 493
 494 /* These tables map the ALSA channels 1..N to the channels that we
 495    need to use in order to find the relevant channel buffer. RME
 496    refer to this kind of mapping as between "the ADAT channel and
 497    the DMA channel." We index it using the logical audio channel,
 498    and the value is the DMA channel (i.e. channel buffer number)
 499    where the data for that channel can be read/written from/to.
 500 */
 501
 502 static char channel_map_madi_ss[HDSPM_MAX_CHANNELS] = {
 503    0, 1, 2, 3, 4, 5, 6, 7,
 504    8, 9, 10, 11, 12, 13, 14, 15,
 505    16, 17, 18, 19, 20, 21, 22, 23,
 506    24, 25, 26, 27, 28, 29, 30, 31,
 507    32, 33, 34, 35, 36, 37, 38, 39,
 508    40, 41, 42, 43, 44, 45, 46, 47,
 509    48, 49, 50, 51, 52, 53, 54, 55,
 510    56, 57, 58, 59, 60, 61, 62, 63
 511 };
 512
 513
 514 static struct pci_device_id snd_hdspm_ids[] __devinitdata = {
 515         {
 516          .vendor = PCI_VENDOR_ID_XILINX,
 517          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
 518          .subvendor = PCI_ANY_ID,
 519          .subdevice = PCI_ANY_ID,
 520          .class = 0,
 521          .class_mask = 0,
 522          .driver_data = 0},
 523         {0,}
 524 };
 525
 526 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
 527
 528 /* prototypes */
 529 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
 530                                                    struct hdspm * hdspm);
 531 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
 532                                           struct hdspm * hdspm);
 533
 534 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm);
 535 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm);
 536 static int hdspm_autosync_ref(struct hdspm * hdspm);
 537 static int snd_hdspm_set_defaults(struct hdspm * hdspm);
 538 static void hdspm_set_sgbuf(struct hdspm * hdspm,
 539                             struct snd_pcm_substream *substream,
 540                              unsigned int reg, int channels);
 541
 542 static inline int HDSPM_bit2freq(int n)
 543 {
 544         static const int bit2freq_tab[] = {
 545                 0, 32000, 44100, 48000, 64000, 88200,
 546                 96000, 128000, 176400, 192000 };
 547         if (n < 1 || n > 9)
 548                 return 0;
 549         return bit2freq_tab[n];
 550 }
 551
 552 /* Write/read to/from HDSPM with Adresses in Bytes
 553    not words but only 32Bit writes are allowed */
 554
 555 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
 556                                unsigned int val)
 557 {
 558         writel(val, hdspm->iobase + reg);
 559 }
 560
 561 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
 562 {
 563         return readl(hdspm->iobase + reg);
 564 }
 565
 566 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
 567    mixer is write only on hardware so we have to cache him for read
 568    each fader is a u32, but uses only the first 16 bit */
 569
 570 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
 571                                      unsigned int in)
 572 {
 573         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
 574                 return 0;
 575
 576         return hdspm->mixer->ch[chan].in[in];
 577 }
 578
 579 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
 580                                      unsigned int pb)
 581 {
 582         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
 583                 return 0;
 584         return hdspm->mixer->ch[chan].pb[pb];
 585 }
 586
 587 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
 588                                       unsigned int in, unsigned short data)
 589 {
 590         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
 591                 return -1;
 592
 593         hdspm_write(hdspm,
 594                     HDSPM_MADI_mixerBase +
 595                     ((in + 128 * chan) * sizeof(u32)),
 596                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
 597         return 0;
 598 }
 599
 600 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
 601                                       unsigned int pb, unsigned short data)
 602 {
 603         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
 604                 return -1;
 605
 606         hdspm_write(hdspm,
 607                     HDSPM_MADI_mixerBase +
 608                     ((64 + pb + 128 * chan) * sizeof(u32)),
 609                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
 610         return 0;
 611 }
 612
 613
 614 /* enable DMA for specific channels, now available for DSP-MADI */
 615 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
 616 {
 617         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
 618 }
 619
 620 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
 621 {
 622         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
 623 }
 624
 625 /* check if same process is writing and reading */
 626 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
 627 {
 628         unsigned long flags;
 629         int ret = 1;
 630
 631         spin_lock_irqsave(&hdspm->lock, flags);
 632         if ((hdspm->playback_pid != hdspm->capture_pid) &&
 633             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
 634                 ret = 0;
 635         }
 636         spin_unlock_irqrestore(&hdspm->lock, flags);
 637         return ret;
 638 }
 639
 640 /* check for external sample rate */
 641 static int hdspm_external_sample_rate(struct hdspm *hdspm)
 642 {
 643         if (hdspm->is_aes32) {
 644                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 645                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
 646                 unsigned int timecode =
 647                         hdspm_read(hdspm, HDSPM_timecodeRegister);
 648
 649                 int syncref = hdspm_autosync_ref(hdspm);
 650
 651                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
 652                                 status & HDSPM_AES32_wcLock)
 653                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit)
 654                                               & 0xF);
 655                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
 656                         syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
 657                         status2 & (HDSPM_LockAES >>
 658                                   (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
 659                         return HDSPM_bit2freq((timecode >>
 660                           (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
 661                 return 0;
 662         } else {
 663                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
 664                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
 665                 unsigned int rate_bits;
 666                 int rate = 0;
 667
 668                 /* if wordclock has synced freq and wordclock is valid */
 669                 if ((status2 & HDSPM_wcLock) != 0 &&
 670                                 (status & HDSPM_SelSyncRef0) == 0) {
 671
 672                         rate_bits = status2 & HDSPM_wcFreqMask;
 673
 674                         switch (rate_bits) {
 675                         case HDSPM_wcFreq32:
 676                                 rate = 32000;
 677                                 break;
 678                         case HDSPM_wcFreq44_1:
 679                                 rate = 44100;
 680                                 break;
 681                         case HDSPM_wcFreq48:
 682                                 rate = 48000;
 683                                 break;
 684                         case HDSPM_wcFreq64:
 685                                 rate = 64000;
 686                                 break;
 687                         case HDSPM_wcFreq88_2:
 688                                 rate = 88200;
 689                                 break;
 690                         case HDSPM_wcFreq96:
 691                                 rate = 96000;
 692                                 break;
 693                                 /* Quadspeed Bit missing ???? */
 694                         default:
 695                                 rate = 0;
 696                                 break;
 697                         }
 698                 }
 699
 700                 /* if rate detected and Syncref is Word than have it,
 701                  * word has priority to MADI
 702                  */
 703                 if (rate != 0 &&
 704                     (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
 705                         return rate;
 706
 707                 /* maby a madi input (which is taken if sel sync is madi) */
 708                 if (status & HDSPM_madiLock) {
 709                         rate_bits = status & HDSPM_madiFreqMask;
 710
 711                         switch (rate_bits) {
 712                         case HDSPM_madiFreq32:
 713                                 rate = 32000;
 714                                 break;
 715                         case HDSPM_madiFreq44_1:
 716                                 rate = 44100;
 717                                 break;
 718                         case HDSPM_madiFreq48:
 719                                 rate = 48000;
 720                                 break;
 721                         case HDSPM_madiFreq64:
 722                                 rate = 64000;
 723                                 break;
 724                         case HDSPM_madiFreq88_2:
 725                                 rate = 88200;
 726                                 break;
 727                         case HDSPM_madiFreq96:
 728                                 rate = 96000;
 729                                 break;
 730                         case HDSPM_madiFreq128:
 731                                 rate = 128000;
 732                                 break;
 733                         case HDSPM_madiFreq176_4:
 734                                 rate = 176400;
 735                                 break;
 736                         case HDSPM_madiFreq192:
 737                                 rate = 192000;
 738                                 break;
 739                         default:
 740                                 rate = 0;
 741                                 break;
 742                         }
 743                 }
 744                 return rate;
 745         }
 746 }
 747
 748 /* Latency function */
 749 static inline void hdspm_compute_period_size(struct hdspm * hdspm)
 750 {
 751         hdspm->period_bytes =
 752             1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
 753 }
 754
 755 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm * hdspm)
 756 {
 757         int position;
 758
 759         position = hdspm_read(hdspm, HDSPM_statusRegister);
 760
 761         if (!hdspm->precise_ptr)
 762                 return (position & HDSPM_BufferID) ?
 763                         (hdspm->period_bytes / 4) : 0;
 764
 765         /* hwpointer comes in bytes and is 64Bytes accurate (by docu since
 766            PCI Burst)
 767            i have experimented that it is at most 64 Byte to much for playing
 768            so substraction of 64 byte should be ok for ALSA, but use it only
 769            for application where you know what you do since if you come to
 770            near with record pointer it can be a disaster */
 771
 772         position &= HDSPM_BufferPositionMask;
 773         position = ((position - 64) % (2 * hdspm->period_bytes)) / 4;
 774
 775         return position;
 776 }
 777
 778
 779 static inline void hdspm_start_audio(struct hdspm * s)
 780 {
 781         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
 782         hdspm_write(s, HDSPM_controlRegister, s->control_register);
 783 }
 784
 785 static inline void hdspm_stop_audio(struct hdspm * s)
 786 {
 787         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
 788         hdspm_write(s, HDSPM_controlRegister, s->control_register);
 789 }
 790
 791 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
 792 static void hdspm_silence_playback(struct hdspm *hdspm)
 793 {
 794         int i;
 795         int n = hdspm->period_bytes;
 796         void *buf = hdspm->playback_buffer;
 797
 798         if (buf == NULL)
 799                 return;
 800
 801         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
 802                 memset(buf, 0, n);
 803                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
 804         }
 805 }
 806
 807 static int hdspm_set_interrupt_interval(struct hdspm * s, unsigned int frames)
 808 {
 809         int n;
 810
 811         spin_lock_irq(&s->lock);
 812
 813         frames >>= 7;
 814         n = 0;
 815         while (frames) {
 816                 n++;
 817                 frames >>= 1;
 818         }
 819         s->control_register &= ~HDSPM_LatencyMask;
 820         s->control_register |= hdspm_encode_latency(n);
 821
 822         hdspm_write(s, HDSPM_controlRegister, s->control_register);
 823
 824         hdspm_compute_period_size(s);
 825
 826         spin_unlock_irq(&s->lock);
 827
 828         return 0;
 829 }
 830
 831 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
 832 {
 833         u64 n;
 834         u32 r;
 835
 836         if (rate >= 112000)
 837                 rate /= 4;
 838         else if (rate >= 56000)
 839                 rate /= 2;
 840
 841         /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 842 //      return 104857600000000 / rate; // 100 MHz
 843         return 110100480000000 / rate; // 105 MHz
 844         */
 845         /* n = 104857600000000ULL; */ /*  =  2^20 * 10^8 */
 846         n = 110100480000000ULL;    /* Value checked for AES32 and MADI */
 847         div64_32(&n, rate, &r);
 848         /* n should be less than 2^32 for being written to FREQ register */
 849         snd_BUG_ON(n >> 32);
 850         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
 851 }
 852
 853 /* dummy set rate lets see what happens */
 854 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
 855 {
 856         int current_rate;
 857         int rate_bits;
 858         int not_set = 0;
 859         int current_speed, target_speed;
 860
 861         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
 862            it (e.g. during module initialization).
 863          */
 864
 865         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
 866
 867                 /* SLAVE --- */
 868                 if (called_internally) {
 869
 870                   /* request from ctl or card initialization
 871                      just make a warning an remember setting
 872                      for future master mode switching */
 873
 874                         snd_printk(KERN_WARNING "HDSPM: "
 875                                    "Warning: device is not running "
 876                                    "as a clock master.\n");
 877                         not_set = 1;
 878                 } else {
 879
 880                         /* hw_param request while in AutoSync mode */
 881                         int external_freq =
 882                             hdspm_external_sample_rate(hdspm);
 883
 884                         if (hdspm_autosync_ref(hdspm) ==
 885                             HDSPM_AUTOSYNC_FROM_NONE) {
 886
 887                                 snd_printk(KERN_WARNING "HDSPM: "
 888                                            "Detected no Externel Sync \n");
 889                                 not_set = 1;
 890
 891                         } else if (rate != external_freq) {
 892
 893                                 snd_printk(KERN_WARNING "HDSPM: "
 894                                            "Warning: No AutoSync source for "
 895                                            "requested rate\n");
 896                                 not_set = 1;
 897                         }
 898                 }
 899         }
 900
 901         current_rate = hdspm->system_sample_rate;
 902
 903         /* Changing between Singe, Double and Quad speed is not
 904            allowed if any substreams are open. This is because such a change
 905            causes a shift in the location of the DMA buffers and a reduction
 906            in the number of available buffers.
 907
 908            Note that a similar but essentially insoluble problem exists for
 909            externally-driven rate changes. All we can do is to flag rate
 910            changes in the read/write routines.
 911          */
 912
 913         if (current_rate <= 48000)
 914                 current_speed = HDSPM_SPEED_SINGLE;
 915         else if (current_rate <= 96000)
 916                 current_speed = HDSPM_SPEED_DOUBLE;
 917         else
 918                 current_speed = HDSPM_SPEED_QUAD;
 919
 920         if (rate <= 48000)
 921                 target_speed = HDSPM_SPEED_SINGLE;
 922         else if (rate <= 96000)
 923                 target_speed = HDSPM_SPEED_DOUBLE;
 924         else
 925                 target_speed = HDSPM_SPEED_QUAD;
 926
 927         switch (rate) {
 928         case 32000:
 929                 rate_bits = HDSPM_Frequency32KHz;
 930                 break;
 931         case 44100:
 932                 rate_bits = HDSPM_Frequency44_1KHz;
 933                 break;
 934         case 48000:
 935                 rate_bits = HDSPM_Frequency48KHz;
 936                 break;
 937         case 64000:
 938                 rate_bits = HDSPM_Frequency64KHz;
 939                 break;
 940         case 88200:
 941                 rate_bits = HDSPM_Frequency88_2KHz;
 942                 break;
 943         case 96000:
 944                 rate_bits = HDSPM_Frequency96KHz;
 945                 break;
 946         case 128000:
 947                 rate_bits = HDSPM_Frequency128KHz;
 948                 break;
 949         case 176400:
 950                 rate_bits = HDSPM_Frequency176_4KHz;
 951                 break;
 952         case 192000:
 953                 rate_bits = HDSPM_Frequency192KHz;
 954                 break;
 955         default:
 956                 return -EINVAL;
 957         }
 958
 959         if (current_speed != target_speed
 960             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
 961                 snd_printk
 962                     (KERN_ERR "HDSPM: "
 963                      "cannot change from %s speed to %s speed mode "
 964                      "(capture PID = %d, playback PID = %d)\n",
 965                      hdspm_speed_names[current_speed],
 966                      hdspm_speed_names[target_speed],
 967                      hdspm->capture_pid, hdspm->playback_pid);
 968                 return -EBUSY;
 969         }
 970
 971         hdspm->control_register &= ~HDSPM_FrequencyMask;
 972         hdspm->control_register |= rate_bits;
 973         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
 974
 975         /* For AES32, need to set DDS value in FREQ register
 976            For MADI, also apparently */
 977         hdspm_set_dds_value(hdspm, rate);
 978
 979         if (hdspm->is_aes32 && rate != current_rate)
 980                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
 981
 982         /* For AES32 and for MADI (at least rev 204), channel_map needs to
 983          * always be channel_map_madi_ss, whatever the sample rate */
 984         hdspm->channel_map = channel_map_madi_ss;
 985
 986         hdspm->system_sample_rate = rate;
 987
 988         if (not_set != 0)
 989                 return -1;
 990
 991         return 0;
 992 }
 993
 994 /* mainly for init to 0 on load */
 995 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
 996 {
 997         int i, j;
 998         unsigned int gain;
 999
1000         if (sgain > UNITY_GAIN)
1001                 gain = UNITY_GAIN;
1002         else if (sgain < 0)
1003                 gain = 0;
1004         else
1005                 gain = sgain;
1006
1007         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1008                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1009                         hdspm_write_in_gain(hdspm, i, j, gain);
1010                         hdspm_write_pb_gain(hdspm, i, j, gain);
1011                 }
1012 }
1013
1014 /*----------------------------------------------------------------------------
1015    MIDI
1016   ----------------------------------------------------------------------------*/
1017
1018 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1019                                                       int id)
1020 {
1021         /* the hardware already does the relevant bit-mask with 0xff */
1022         if (id)
1023                 return hdspm_read(hdspm, HDSPM_midiDataIn1);
1024         else
1025                 return hdspm_read(hdspm, HDSPM_midiDataIn0);
1026 }
1027
1028 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1029                                               int val)
1030 {
1031         /* the hardware already does the relevant bit-mask with 0xff */
1032         if (id)
1033                 hdspm_write(hdspm, HDSPM_midiDataOut1, val);
1034         else
1035                 hdspm_write(hdspm, HDSPM_midiDataOut0, val);
1036 }
1037
1038 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1039 {
1040         if (id)
1041                 return (hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff);
1042         else
1043                 return (hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff);
1044 }
1045
1046 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1047 {
1048         int fifo_bytes_used;
1049
1050         if (id)
1051                 fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut1);
1052         else
1053                 fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut0);
1054         fifo_bytes_used &= 0xff;
1055
1056         if (fifo_bytes_used < 128)
1057                 return  128 - fifo_bytes_used;
1058         else
1059                 return 0;
1060 }
1061
1062 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1063 {
1064         while (snd_hdspm_midi_input_available (hdspm, id))
1065                 snd_hdspm_midi_read_byte (hdspm, id);
1066 }
1067
1068 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1069 {
1070         unsigned long flags;
1071         int n_pending;
1072         int to_write;
1073         int i;
1074         unsigned char buf[128];
1075
1076         /* Output is not interrupt driven */
1077
1078         spin_lock_irqsave (&hmidi->lock, flags);
1079         if (hmidi->output &&
1080             !snd_rawmidi_transmit_empty (hmidi->output)) {
1081                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1082                                                             hmidi->id);
1083                 if (n_pending > 0) {
1084                         if (n_pending > (int)sizeof (buf))
1085                                 n_pending = sizeof (buf);
1086
1087                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1088                                                          n_pending);
1089                         if (to_write > 0) {
1090                                 for (i = 0; i < to_write; ++i)
1091                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1092                                                                    hmidi->id,
1093                                                                    buf[i]);
1094                         }
1095                 }
1096         }
1097         spin_unlock_irqrestore (&hmidi->lock, flags);
1098         return 0;
1099 }
1100
1101 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1102 {
1103         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1104                                  * input FIFO size
1105                                  */
1106         unsigned long flags;
1107         int n_pending;
1108         int i;
1109
1110         spin_lock_irqsave (&hmidi->lock, flags);
1111         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1112         if (n_pending > 0) {
1113                 if (hmidi->input) {
1114                         if (n_pending > (int)sizeof (buf))
1115                                 n_pending = sizeof (buf);
1116                         for (i = 0; i < n_pending; ++i)
1117                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1118                                                                    hmidi->id);
1119                         if (n_pending)
1120                                 snd_rawmidi_receive (hmidi->input, buf,
1121                                                      n_pending);
1122                 } else {
1123                         /* flush the MIDI input FIFO */
1124                         while (n_pending--)
1125                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1126                                                           hmidi->id);
1127                 }
1128         }
1129         hmidi->pending = 0;
1130         if (hmidi->id)
1131                 hmidi->hdspm->control_register |= HDSPM_Midi1InterruptEnable;
1132         else
1133                 hmidi->hdspm->control_register |= HDSPM_Midi0InterruptEnable;
1134         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1135                     hmidi->hdspm->control_register);
1136         spin_unlock_irqrestore (&hmidi->lock, flags);
1137         return snd_hdspm_midi_output_write (hmidi);
1138 }
1139
1140 static void
1141 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1142 {
1143         struct hdspm *hdspm;
1144         struct hdspm_midi *hmidi;
1145         unsigned long flags;
1146         u32 ie;
1147
1148         hmidi = substream->rmidi->private_data;
1149         hdspm = hmidi->hdspm;
1150         ie = hmidi->id ?
1151                 HDSPM_Midi1InterruptEnable : HDSPM_Midi0InterruptEnable;
1152         spin_lock_irqsave (&hdspm->lock, flags);
1153         if (up) {
1154                 if (!(hdspm->control_register & ie)) {
1155                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1156                         hdspm->control_register |= ie;
1157                 }
1158         } else {
1159                 hdspm->control_register &= ~ie;
1160         }
1161
1162         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1163         spin_unlock_irqrestore (&hdspm->lock, flags);
1164 }
1165
1166 static void snd_hdspm_midi_output_timer(unsigned long data)
1167 {
1168         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1169         unsigned long flags;
1170
1171         snd_hdspm_midi_output_write(hmidi);
1172         spin_lock_irqsave (&hmidi->lock, flags);
1173
1174         /* this does not bump hmidi->istimer, because the
1175            kernel automatically removed the timer when it
1176            expired, and we are now adding it back, thus
1177            leaving istimer wherever it was set before.
1178         */
1179
1180         if (hmidi->istimer) {
1181                 hmidi->timer.expires = 1 + jiffies;
1182                 add_timer(&hmidi->timer);
1183         }
1184
1185         spin_unlock_irqrestore (&hmidi->lock, flags);
1186 }
1187
1188 static void
1189 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1190 {
1191         struct hdspm_midi *hmidi;
1192         unsigned long flags;
1193
1194         hmidi = substream->rmidi->private_data;
1195         spin_lock_irqsave (&hmidi->lock, flags);
1196         if (up) {
1197                 if (!hmidi->istimer) {
1198                         init_timer(&hmidi->timer);
1199                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1200                         hmidi->timer.data = (unsigned long) hmidi;
1201                         hmidi->timer.expires = 1 + jiffies;
1202                         add_timer(&hmidi->timer);
1203                         hmidi->istimer++;
1204                 }
1205         } else {
1206                 if (hmidi->istimer && --hmidi->istimer <= 0)
1207                         del_timer (&hmidi->timer);
1208         }
1209         spin_unlock_irqrestore (&hmidi->lock, flags);
1210         if (up)
1211                 snd_hdspm_midi_output_write(hmidi);
1212 }
1213
1214 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1215 {
1216         struct hdspm_midi *hmidi;
1217
1218         hmidi = substream->rmidi->private_data;
1219         spin_lock_irq (&hmidi->lock);
1220         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1221         hmidi->input = substream;
1222         spin_unlock_irq (&hmidi->lock);
1223
1224         return 0;
1225 }
1226
1227 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1228 {
1229         struct hdspm_midi *hmidi;
1230
1231         hmidi = substream->rmidi->private_data;
1232         spin_lock_irq (&hmidi->lock);
1233         hmidi->output = substream;
1234         spin_unlock_irq (&hmidi->lock);
1235
1236         return 0;
1237 }
1238
1239 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1240 {
1241         struct hdspm_midi *hmidi;
1242
1243         snd_hdspm_midi_input_trigger (substream, 0);
1244
1245         hmidi = substream->rmidi->private_data;
1246         spin_lock_irq (&hmidi->lock);
1247         hmidi->input = NULL;
1248         spin_unlock_irq (&hmidi->lock);
1249
1250         return 0;
1251 }
1252
1253 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1254 {
1255         struct hdspm_midi *hmidi;
1256
1257         snd_hdspm_midi_output_trigger (substream, 0);
1258
1259         hmidi = substream->rmidi->private_data;
1260         spin_lock_irq (&hmidi->lock);
1261         hmidi->output = NULL;
1262         spin_unlock_irq (&hmidi->lock);
1263
1264         return 0;
1265 }
1266
1267 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1268 {
1269         .open =         snd_hdspm_midi_output_open,
1270         .close =        snd_hdspm_midi_output_close,
1271         .trigger =      snd_hdspm_midi_output_trigger,
1272 };
1273
1274 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1275 {
1276         .open =         snd_hdspm_midi_input_open,
1277         .close =        snd_hdspm_midi_input_close,
1278         .trigger =      snd_hdspm_midi_input_trigger,
1279 };
1280
1281 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1282                                             struct hdspm *hdspm, int id)
1283 {
1284         int err;
1285         char buf[32];
1286
1287         hdspm->midi[id].id = id;
1288         hdspm->midi[id].hdspm = hdspm;
1289         spin_lock_init (&hdspm->midi[id].lock);
1290
1291         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1292         err = snd_rawmidi_new (card, buf, id, 1, 1, &hdspm->midi[id].rmidi);
1293         if (err < 0)
1294                 return err;
1295
1296         sprintf (hdspm->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1297         hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1298
1299         snd_rawmidi_set_ops(hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
1300                             &snd_hdspm_midi_output);
1301         snd_rawmidi_set_ops(hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
1302                             &snd_hdspm_midi_input);
1303
1304         hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1305                 SNDRV_RAWMIDI_INFO_INPUT |
1306                 SNDRV_RAWMIDI_INFO_DUPLEX;
1307
1308         return 0;
1309 }
1310
1311
1312 static void hdspm_midi_tasklet(unsigned long arg)
1313 {
1314         struct hdspm *hdspm = (struct hdspm *)arg;
1315
1316         if (hdspm->midi[0].pending)
1317                 snd_hdspm_midi_input_read (&hdspm->midi[0]);
1318         if (hdspm->midi[1].pending)
1319                 snd_hdspm_midi_input_read (&hdspm->midi[1]);
1320 }
1321
1322
1323 /*-----------------------------------------------------------------------------
1324   Status Interface
1325   ----------------------------------------------------------------------------*/
1326
1327 /* get the system sample rate which is set */
1328
1329 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1330 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1331   .name = xname, \
1332   .index = xindex, \
1333   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1334   .info = snd_hdspm_info_system_sample_rate, \
1335   .get = snd_hdspm_get_system_sample_rate \
1336 }
1337
1338 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1339                                              struct snd_ctl_elem_info *uinfo)
1340 {
1341         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1342         uinfo->count = 1;
1343         return 0;
1344 }
1345
1346 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1347                                             struct snd_ctl_elem_value *
1348                                             ucontrol)
1349 {
1350         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1351
1352         ucontrol->value.enumerated.item[0] = hdspm->system_sample_rate;
1353         return 0;
1354 }
1355
1356 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1357 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1358   .name = xname, \
1359   .index = xindex, \
1360   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1361   .info = snd_hdspm_info_autosync_sample_rate, \
1362   .get = snd_hdspm_get_autosync_sample_rate \
1363 }
1364
1365 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1366                                                struct snd_ctl_elem_info *uinfo)
1367 {
1368         static char *texts[] = { "32000", "44100", "48000",
1369                 "64000", "88200", "96000",
1370                 "128000", "176400", "192000",
1371                 "None"
1372         };
1373         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1374         uinfo->count = 1;
1375         uinfo->value.enumerated.items = 10;
1376         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1377                 uinfo->value.enumerated.item =
1378                     uinfo->value.enumerated.items - 1;
1379         strcpy(uinfo->value.enumerated.name,
1380                texts[uinfo->value.enumerated.item]);
1381         return 0;
1382 }
1383
1384 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
1385                                               struct snd_ctl_elem_value *
1386                                               ucontrol)
1387 {
1388         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1389
1390         switch (hdspm_external_sample_rate(hdspm)) {
1391         case 32000:
1392                 ucontrol->value.enumerated.item[0] = 0;
1393                 break;
1394         case 44100:
1395                 ucontrol->value.enumerated.item[0] = 1;
1396                 break;
1397         case 48000:
1398                 ucontrol->value.enumerated.item[0] = 2;
1399                 break;
1400         case 64000:
1401                 ucontrol->value.enumerated.item[0] = 3;
1402                 break;
1403         case 88200:
1404                 ucontrol->value.enumerated.item[0] = 4;
1405                 break;
1406         case 96000:
1407                 ucontrol->value.enumerated.item[0] = 5;
1408                 break;
1409         case 128000:
1410                 ucontrol->value.enumerated.item[0] = 6;
1411                 break;
1412         case 176400:
1413                 ucontrol->value.enumerated.item[0] = 7;
1414                 break;
1415         case 192000:
1416                 ucontrol->value.enumerated.item[0] = 8;
1417                 break;
1418
1419         default:
1420                 ucontrol->value.enumerated.item[0] = 9;
1421         }
1422         return 0;
1423 }
1424
1425 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
1426 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1427   .name = xname, \
1428   .index = xindex, \
1429   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1430   .info = snd_hdspm_info_system_clock_mode, \
1431   .get = snd_hdspm_get_system_clock_mode, \
1432 }
1433
1434
1435
1436 static int hdspm_system_clock_mode(struct hdspm * hdspm)
1437 {
1438         /* Always reflect the hardware info, rme is never wrong !!!! */
1439
1440         if (hdspm->control_register & HDSPM_ClockModeMaster)
1441                 return 0;
1442         return 1;
1443 }
1444
1445 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
1446                                             struct snd_ctl_elem_info *uinfo)
1447 {
1448         static char *texts[] = { "Master", "Slave" };
1449
1450         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1451         uinfo->count = 1;
1452         uinfo->value.enumerated.items = 2;
1453         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1454                 uinfo->value.enumerated.item =
1455                     uinfo->value.enumerated.items - 1;
1456         strcpy(uinfo->value.enumerated.name,
1457                texts[uinfo->value.enumerated.item]);
1458         return 0;
1459 }
1460
1461 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
1462                                            struct snd_ctl_elem_value *ucontrol)
1463 {
1464         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1465
1466         ucontrol->value.enumerated.item[0] =
1467             hdspm_system_clock_mode(hdspm);
1468         return 0;
1469 }
1470
1471 #define HDSPM_CLOCK_SOURCE(xname, xindex) \
1472 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1473   .name = xname, \
1474   .index = xindex, \
1475   .info = snd_hdspm_info_clock_source, \
1476   .get = snd_hdspm_get_clock_source, \
1477   .put = snd_hdspm_put_clock_source \
1478 }
1479
1480 static int hdspm_clock_source(struct hdspm * hdspm)
1481 {
1482         if (hdspm->control_register & HDSPM_ClockModeMaster) {
1483                 switch (hdspm->system_sample_rate) {
1484                 case 32000:
1485                         return 1;
1486                 case 44100:
1487                         return 2;
1488                 case 48000:
1489                         return 3;
1490                 case 64000:
1491                         return 4;
1492                 case 88200:
1493                         return 5;
1494                 case 96000:
1495                         return 6;
1496                 case 128000:
1497                         return 7;
1498                 case 176400:
1499                         return 8;
1500                 case 192000:
1501                         return 9;
1502                 default:
1503                         return 3;
1504                 }
1505         } else {
1506                 return 0;
1507         }
1508 }
1509
1510 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
1511 {
1512         int rate;
1513         switch (mode) {
1514
1515         case HDSPM_CLOCK_SOURCE_AUTOSYNC:
1516                 if (hdspm_external_sample_rate(hdspm) != 0) {
1517                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
1518                         hdspm_write(hdspm, HDSPM_controlRegister,
1519                                     hdspm->control_register);
1520                         return 0;
1521                 }
1522                 return -1;
1523         case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
1524                 rate = 32000;
1525                 break;
1526         case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1527                 rate = 44100;
1528                 break;
1529         case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
1530                 rate = 48000;
1531                 break;
1532         case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
1533                 rate = 64000;
1534                 break;
1535         case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1536                 rate = 88200;
1537                 break;
1538         case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
1539                 rate = 96000;
1540                 break;
1541         case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
1542                 rate = 128000;
1543                 break;
1544         case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1545                 rate = 176400;
1546                 break;
1547         case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
1548                 rate = 192000;
1549                 break;
1550
1551         default:
1552                 rate = 44100;
1553         }
1554         hdspm->control_register |= HDSPM_ClockModeMaster;
1555         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1556         hdspm_set_rate(hdspm, rate, 1);
1557         return 0;
1558 }
1559
1560 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
1561                                        struct snd_ctl_elem_info *uinfo)
1562 {
1563         static char *texts[] = { "AutoSync",
1564                 "Internal 32.0 kHz", "Internal 44.1 kHz",
1565                     "Internal 48.0 kHz",
1566                 "Internal 64.0 kHz", "Internal 88.2 kHz",
1567                     "Internal 96.0 kHz",
1568                 "Internal 128.0 kHz", "Internal 176.4 kHz",
1569                     "Internal 192.0 kHz"
1570         };
1571
1572         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1573         uinfo->count = 1;
1574         uinfo->value.enumerated.items = 10;
1575
1576         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1577                 uinfo->value.enumerated.item =
1578                     uinfo->value.enumerated.items - 1;
1579
1580         strcpy(uinfo->value.enumerated.name,
1581                texts[uinfo->value.enumerated.item]);
1582
1583         return 0;
1584 }
1585
1586 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
1587                                       struct snd_ctl_elem_value *ucontrol)
1588 {
1589         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1590
1591         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
1592         return 0;
1593 }
1594
1595 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
1596                                       struct snd_ctl_elem_value *ucontrol)
1597 {
1598         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1599         int change;
1600         int val;
1601
1602         if (!snd_hdspm_use_is_exclusive(hdspm))
1603                 return -EBUSY;
1604         val = ucontrol->value.enumerated.item[0];
1605         if (val < 0)
1606                 val = 0;
1607         if (val > 9)
1608                 val = 9;
1609         spin_lock_irq(&hdspm->lock);
1610         if (val != hdspm_clock_source(hdspm))
1611                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
1612         else
1613                 change = 0;
1614         spin_unlock_irq(&hdspm->lock);
1615         return change;
1616 }
1617
1618 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
1619 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1620   .name = xname, \
1621   .index = xindex, \
1622   .info = snd_hdspm_info_pref_sync_ref, \
1623   .get = snd_hdspm_get_pref_sync_ref, \
1624   .put = snd_hdspm_put_pref_sync_ref \
1625 }
1626
1627 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
1628 {
1629         /* Notice that this looks at the requested sync source,
1630            not the one actually in use.
1631          */
1632         if (hdspm->is_aes32) {
1633                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1634                 /* number gives AES index, except for 0 which
1635                    corresponds to WordClock */
1636                 case 0: return 0;
1637                 case HDSPM_SyncRef0: return 1;
1638                 case HDSPM_SyncRef1: return 2;
1639                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3;
1640                 case HDSPM_SyncRef2: return 4;
1641                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5;
1642                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6;
1643                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: return 7;
1644                 case HDSPM_SyncRef3: return 8;
1645                 }
1646         } else {
1647                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
1648                 case HDSPM_SyncRef_Word:
1649                         return HDSPM_SYNC_FROM_WORD;
1650                 case HDSPM_SyncRef_MADI:
1651                         return HDSPM_SYNC_FROM_MADI;
1652                 }
1653         }
1654
1655         return HDSPM_SYNC_FROM_WORD;
1656 }
1657
1658 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
1659 {
1660         hdspm->control_register &= ~HDSPM_SyncRefMask;
1661
1662         if (hdspm->is_aes32) {
1663                 switch (pref) {
1664                 case 0:
1665                        hdspm->control_register |= 0;
1666                        break;
1667                 case 1:
1668                        hdspm->control_register |= HDSPM_SyncRef0;
1669                        break;
1670                 case 2:
1671                        hdspm->control_register |= HDSPM_SyncRef1;
1672                        break;
1673                 case 3:
1674                        hdspm->control_register |= HDSPM_SyncRef1+HDSPM_SyncRef0;
1675                        break;
1676                 case 4:
1677                        hdspm->control_register |= HDSPM_SyncRef2;
1678                        break;
1679                 case 5:
1680                        hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef0;
1681                        break;
1682                 case 6:
1683                        hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1;
1684                        break;
1685                 case 7:
1686                        hdspm->control_register |=
1687                                HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
1688                        break;
1689                 case 8:
1690                        hdspm->control_register |= HDSPM_SyncRef3;
1691                        break;
1692                 default:
1693                        return -1;
1694                 }
1695         } else {
1696                 switch (pref) {
1697                 case HDSPM_SYNC_FROM_MADI:
1698                         hdspm->control_register |= HDSPM_SyncRef_MADI;
1699                         break;
1700                 case HDSPM_SYNC_FROM_WORD:
1701                         hdspm->control_register |= HDSPM_SyncRef_Word;
1702                         break;
1703                 default:
1704                         return -1;
1705                 }
1706         }
1707         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1708         return 0;
1709 }
1710
1711 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
1712                                         struct snd_ctl_elem_info *uinfo)
1713 {
1714         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1715
1716         if (hdspm->is_aes32) {
1717                 static char *texts[] = { "Word", "AES1", "AES2", "AES3",
1718                         "AES4", "AES5", "AES6", "AES7", "AES8" };
1719
1720                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1721                 uinfo->count = 1;
1722
1723                 uinfo->value.enumerated.items = 9;
1724
1725                 if (uinfo->value.enumerated.item >=
1726                     uinfo->value.enumerated.items)
1727                         uinfo->value.enumerated.item =
1728                                 uinfo->value.enumerated.items - 1;
1729                 strcpy(uinfo->value.enumerated.name,
1730                                 texts[uinfo->value.enumerated.item]);
1731         } else {
1732                 static char *texts[] = { "Word", "MADI" };
1733
1734                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1735                 uinfo->count = 1;
1736
1737                 uinfo->value.enumerated.items = 2;
1738
1739                 if (uinfo->value.enumerated.item >=
1740                     uinfo->value.enumerated.items)
1741                         uinfo->value.enumerated.item =
1742                                 uinfo->value.enumerated.items - 1;
1743                 strcpy(uinfo->value.enumerated.name,
1744                                 texts[uinfo->value.enumerated.item]);
1745         }
1746         return 0;
1747 }
1748
1749 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
1750                                        struct snd_ctl_elem_value *ucontrol)
1751 {
1752         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1753
1754         ucontrol->value.enumerated.item[0] = hdspm_pref_sync_ref(hdspm);
1755         return 0;
1756 }
1757
1758 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
1759                                        struct snd_ctl_elem_value *ucontrol)
1760 {
1761         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1762         int change, max;
1763         unsigned int val;
1764
1765         max = hdspm->is_aes32 ? 9 : 2;
1766
1767         if (!snd_hdspm_use_is_exclusive(hdspm))
1768                 return -EBUSY;
1769
1770         val = ucontrol->value.enumerated.item[0] % max;
1771
1772         spin_lock_irq(&hdspm->lock);
1773         change = (int) val != hdspm_pref_sync_ref(hdspm);
1774         hdspm_set_pref_sync_ref(hdspm, val);
1775         spin_unlock_irq(&hdspm->lock);
1776         return change;
1777 }
1778
1779 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
1780 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1781   .name = xname, \
1782   .index = xindex, \
1783   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1784   .info = snd_hdspm_info_autosync_ref, \
1785   .get = snd_hdspm_get_autosync_ref, \
1786 }
1787
1788 static int hdspm_autosync_ref(struct hdspm * hdspm)
1789 {
1790         if (hdspm->is_aes32) {
1791                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
1792                 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) &
1793                         0xF;
1794                 if (syncref == 0)
1795                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
1796                 if (syncref <= 8)
1797                         return syncref;
1798                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
1799         } else {
1800                 /* This looks at the autosync selected sync reference */
1801                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1802
1803                 switch (status2 & HDSPM_SelSyncRefMask) {
1804                 case HDSPM_SelSyncRef_WORD:
1805                         return HDSPM_AUTOSYNC_FROM_WORD;
1806                 case HDSPM_SelSyncRef_MADI:
1807                         return HDSPM_AUTOSYNC_FROM_MADI;
1808                 case HDSPM_SelSyncRef_NVALID:
1809                         return HDSPM_AUTOSYNC_FROM_NONE;
1810                 default:
1811                         return 0;
1812                 }
1813
1814                 return 0;
1815         }
1816 }
1817
1818 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
1819                                        struct snd_ctl_elem_info *uinfo)
1820 {
1821         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1822
1823         if (hdspm->is_aes32) {
1824                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
1825                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
1826
1827                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1828                 uinfo->count = 1;
1829                 uinfo->value.enumerated.items = 10;
1830                 if (uinfo->value.enumerated.item >=
1831                     uinfo->value.enumerated.items)
1832                         uinfo->value.enumerated.item =
1833                                 uinfo->value.enumerated.items - 1;
1834                 strcpy(uinfo->value.enumerated.name,
1835                                 texts[uinfo->value.enumerated.item]);
1836         } else {
1837                 static char *texts[] = { "WordClock", "MADI", "None" };
1838
1839                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1840                 uinfo->count = 1;
1841                 uinfo->value.enumerated.items = 3;
1842                 if (uinfo->value.enumerated.item >=
1843                     uinfo->value.enumerated.items)
1844                         uinfo->value.enumerated.item =
1845                                 uinfo->value.enumerated.items - 1;
1846                 strcpy(uinfo->value.enumerated.name,
1847                                 texts[uinfo->value.enumerated.item]);
1848         }
1849         return 0;
1850 }
1851
1852 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
1853                                       struct snd_ctl_elem_value *ucontrol)
1854 {
1855         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1856
1857         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
1858         return 0;
1859 }
1860
1861 #define HDSPM_LINE_OUT(xname, xindex) \
1862 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1863   .name = xname, \
1864   .index = xindex, \
1865   .info = snd_hdspm_info_line_out, \
1866   .get = snd_hdspm_get_line_out, \
1867   .put = snd_hdspm_put_line_out \
1868 }
1869
1870 static int hdspm_line_out(struct hdspm * hdspm)
1871 {
1872         return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
1873 }
1874
1875
1876 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
1877 {
1878         if (out)
1879                 hdspm->control_register |= HDSPM_LineOut;
1880         else
1881                 hdspm->control_register &= ~HDSPM_LineOut;
1882         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1883
1884         return 0;
1885 }
1886
1887 #define snd_hdspm_info_line_out         snd_ctl_boolean_mono_info
1888
1889 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
1890                                   struct snd_ctl_elem_value *ucontrol)
1891 {
1892         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1893
1894         spin_lock_irq(&hdspm->lock);
1895         ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
1896         spin_unlock_irq(&hdspm->lock);
1897         return 0;
1898 }
1899
1900 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
1901                                   struct snd_ctl_elem_value *ucontrol)
1902 {
1903         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1904         int change;
1905         unsigned int val;
1906
1907         if (!snd_hdspm_use_is_exclusive(hdspm))
1908                 return -EBUSY;
1909         val = ucontrol->value.integer.value[0] & 1;
1910         spin_lock_irq(&hdspm->lock);
1911         change = (int) val != hdspm_line_out(hdspm);
1912         hdspm_set_line_output(hdspm, val);
1913         spin_unlock_irq(&hdspm->lock);
1914         return change;
1915 }
1916
1917 #define HDSPM_TX_64(xname, xindex) \
1918 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1919   .name = xname, \
1920   .index = xindex, \
1921   .info = snd_hdspm_info_tx_64, \
1922   .get = snd_hdspm_get_tx_64, \
1923   .put = snd_hdspm_put_tx_64 \
1924 }
1925
1926 static int hdspm_tx_64(struct hdspm * hdspm)
1927 {
1928         return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
1929 }
1930
1931 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
1932 {
1933         if (out)
1934                 hdspm->control_register |= HDSPM_TX_64ch;
1935         else
1936                 hdspm->control_register &= ~HDSPM_TX_64ch;
1937         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1938
1939         return 0;
1940 }
1941
1942 #define snd_hdspm_info_tx_64            snd_ctl_boolean_mono_info
1943
1944 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
1945                                struct snd_ctl_elem_value *ucontrol)
1946 {
1947         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1948
1949         spin_lock_irq(&hdspm->lock);
1950         ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
1951         spin_unlock_irq(&hdspm->lock);
1952         return 0;
1953 }
1954
1955 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
1956                                struct snd_ctl_elem_value *ucontrol)
1957 {
1958         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1959         int change;
1960         unsigned int val;
1961
1962         if (!snd_hdspm_use_is_exclusive(hdspm))
1963                 return -EBUSY;
1964         val = ucontrol->value.integer.value[0] & 1;
1965         spin_lock_irq(&hdspm->lock);
1966         change = (int) val != hdspm_tx_64(hdspm);
1967         hdspm_set_tx_64(hdspm, val);
1968         spin_unlock_irq(&hdspm->lock);
1969         return change;
1970 }
1971
1972 #define HDSPM_C_TMS(xname, xindex) \
1973 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1974   .name = xname, \
1975   .index = xindex, \
1976   .info = snd_hdspm_info_c_tms, \
1977   .get = snd_hdspm_get_c_tms, \
1978   .put = snd_hdspm_put_c_tms \
1979 }
1980
1981 static int hdspm_c_tms(struct hdspm * hdspm)
1982 {
1983         return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
1984 }
1985
1986 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
1987 {
1988         if (out)
1989                 hdspm->control_register |= HDSPM_clr_tms;
1990         else
1991                 hdspm->control_register &= ~HDSPM_clr_tms;
1992         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1993
1994         return 0;
1995 }
1996
1997 #define snd_hdspm_info_c_tms            snd_ctl_boolean_mono_info
1998
1999 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2000                                struct snd_ctl_elem_value *ucontrol)
2001 {
2002         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2003
2004         spin_lock_irq(&hdspm->lock);
2005         ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2006         spin_unlock_irq(&hdspm->lock);
2007         return 0;
2008 }
2009
2010 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2011                                struct snd_ctl_elem_value *ucontrol)
2012 {
2013         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2014         int change;
2015         unsigned int val;
2016
2017         if (!snd_hdspm_use_is_exclusive(hdspm))
2018                 return -EBUSY;
2019         val = ucontrol->value.integer.value[0] & 1;
2020         spin_lock_irq(&hdspm->lock);
2021         change = (int) val != hdspm_c_tms(hdspm);
2022         hdspm_set_c_tms(hdspm, val);
2023         spin_unlock_irq(&hdspm->lock);
2024         return change;
2025 }
2026
2027 #define HDSPM_SAFE_MODE(xname, xindex) \
2028 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2029   .name = xname, \
2030   .index = xindex, \
2031   .info = snd_hdspm_info_safe_mode, \
2032   .get = snd_hdspm_get_safe_mode, \
2033   .put = snd_hdspm_put_safe_mode \
2034 }
2035
2036 static int hdspm_safe_mode(struct hdspm * hdspm)
2037 {
2038         return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2039 }
2040
2041 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2042 {
2043         if (out)
2044                 hdspm->control_register |= HDSPM_AutoInp;
2045         else
2046                 hdspm->control_register &= ~HDSPM_AutoInp;
2047         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2048
2049         return 0;
2050 }
2051
2052 #define snd_hdspm_info_safe_mode        snd_ctl_boolean_mono_info
2053
2054 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2055                                    struct snd_ctl_elem_value *ucontrol)
2056 {
2057         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2058
2059         spin_lock_irq(&hdspm->lock);
2060         ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2061         spin_unlock_irq(&hdspm->lock);
2062         return 0;
2063 }
2064
2065 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
2066                                    struct snd_ctl_elem_value *ucontrol)
2067 {
2068         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2069         int change;
2070         unsigned int val;
2071
2072         if (!snd_hdspm_use_is_exclusive(hdspm))
2073                 return -EBUSY;
2074         val = ucontrol->value.integer.value[0] & 1;
2075         spin_lock_irq(&hdspm->lock);
2076         change = (int) val != hdspm_safe_mode(hdspm);
2077         hdspm_set_safe_mode(hdspm, val);
2078         spin_unlock_irq(&hdspm->lock);
2079         return change;
2080 }
2081
2082 #define HDSPM_EMPHASIS(xname, xindex) \
2083 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2084   .name = xname, \
2085   .index = xindex, \
2086   .info = snd_hdspm_info_emphasis, \
2087   .get = snd_hdspm_get_emphasis, \
2088   .put = snd_hdspm_put_emphasis \
2089 }
2090
2091 static int hdspm_emphasis(struct hdspm * hdspm)
2092 {
2093         return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
2094 }
2095
2096 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
2097 {
2098         if (emp)
2099                 hdspm->control_register |= HDSPM_Emphasis;
2100         else
2101                 hdspm->control_register &= ~HDSPM_Emphasis;
2102         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2103
2104         return 0;
2105 }
2106
2107 #define snd_hdspm_info_emphasis         snd_ctl_boolean_mono_info
2108
2109 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
2110                                   struct snd_ctl_elem_value *ucontrol)
2111 {
2112         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2113
2114         spin_lock_irq(&hdspm->lock);
2115         ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
2116         spin_unlock_irq(&hdspm->lock);
2117         return 0;
2118 }
2119
2120 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
2121                                   struct snd_ctl_elem_value *ucontrol)
2122 {
2123         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2124         int change;
2125         unsigned int val;
2126
2127         if (!snd_hdspm_use_is_exclusive(hdspm))
2128                 return -EBUSY;
2129         val = ucontrol->value.integer.value[0] & 1;
2130         spin_lock_irq(&hdspm->lock);
2131         change = (int) val != hdspm_emphasis(hdspm);
2132         hdspm_set_emphasis(hdspm, val);
2133         spin_unlock_irq(&hdspm->lock);
2134         return change;
2135 }
2136
2137 #define HDSPM_DOLBY(xname, xindex) \
2138 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2139   .name = xname, \
2140   .index = xindex, \
2141   .info = snd_hdspm_info_dolby, \
2142   .get = snd_hdspm_get_dolby, \
2143   .put = snd_hdspm_put_dolby \
2144 }
2145
2146 static int hdspm_dolby(struct hdspm * hdspm)
2147 {
2148         return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
2149 }
2150
2151 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
2152 {
2153         if (dol)
2154                 hdspm->control_register |= HDSPM_Dolby;
2155         else
2156                 hdspm->control_register &= ~HDSPM_Dolby;
2157         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2158
2159         return 0;
2160 }
2161
2162 #define snd_hdspm_info_dolby            snd_ctl_boolean_mono_info
2163
2164 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
2165                                struct snd_ctl_elem_value *ucontrol)
2166 {
2167         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2168
2169         spin_lock_irq(&hdspm->lock);
2170         ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
2171         spin_unlock_irq(&hdspm->lock);
2172         return 0;
2173 }
2174
2175 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
2176                                struct snd_ctl_elem_value *ucontrol)
2177 {
2178         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2179         int change;
2180         unsigned int val;
2181
2182         if (!snd_hdspm_use_is_exclusive(hdspm))
2183                 return -EBUSY;
2184         val = ucontrol->value.integer.value[0] & 1;
2185         spin_lock_irq(&hdspm->lock);
2186         change = (int) val != hdspm_dolby(hdspm);
2187         hdspm_set_dolby(hdspm, val);
2188         spin_unlock_irq(&hdspm->lock);
2189         return change;
2190 }
2191
2192 #define HDSPM_PROFESSIONAL(xname, xindex) \
2193 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2194   .name = xname, \
2195   .index = xindex, \
2196   .info = snd_hdspm_info_professional, \
2197   .get = snd_hdspm_get_professional, \
2198   .put = snd_hdspm_put_professional \
2199 }
2200
2201 static int hdspm_professional(struct hdspm * hdspm)
2202 {
2203         return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
2204 }
2205
2206 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
2207 {
2208         if (dol)
2209                 hdspm->control_register |= HDSPM_Professional;
2210         else
2211                 hdspm->control_register &= ~HDSPM_Professional;
2212         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2213
2214         return 0;
2215 }
2216
2217 #define snd_hdspm_info_professional     snd_ctl_boolean_mono_info
2218
2219 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
2220                                       struct snd_ctl_elem_value *ucontrol)
2221 {
2222         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2223
2224         spin_lock_irq(&hdspm->lock);
2225         ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
2226         spin_unlock_irq(&hdspm->lock);
2227         return 0;
2228 }
2229
2230 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
2231                                       struct snd_ctl_elem_value *ucontrol)
2232 {
2233         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2234         int change;
2235         unsigned int val;
2236
2237         if (!snd_hdspm_use_is_exclusive(hdspm))
2238                 return -EBUSY;
2239         val = ucontrol->value.integer.value[0] & 1;
2240         spin_lock_irq(&hdspm->lock);
2241         change = (int) val != hdspm_professional(hdspm);
2242         hdspm_set_professional(hdspm, val);
2243         spin_unlock_irq(&hdspm->lock);
2244         return change;
2245 }
2246
2247 #define HDSPM_INPUT_SELECT(xname, xindex) \
2248 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2249   .name = xname, \
2250   .index = xindex, \
2251   .info = snd_hdspm_info_input_select, \
2252   .get = snd_hdspm_get_input_select, \
2253   .put = snd_hdspm_put_input_select \
2254 }
2255
2256 static int hdspm_input_select(struct hdspm * hdspm)
2257 {
2258         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
2259 }
2260
2261 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
2262 {
2263         if (out)
2264                 hdspm->control_register |= HDSPM_InputSelect0;
2265         else
2266                 hdspm->control_register &= ~HDSPM_InputSelect0;
2267         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2268
2269         return 0;
2270 }
2271
2272 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
2273                                        struct snd_ctl_elem_info *uinfo)
2274 {
2275         static char *texts[] = { "optical", "coaxial" };
2276
2277         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2278         uinfo->count = 1;
2279         uinfo->value.enumerated.items = 2;
2280
2281         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2282                 uinfo->value.enumerated.item =
2283                     uinfo->value.enumerated.items - 1;
2284         strcpy(uinfo->value.enumerated.name,
2285                texts[uinfo->value.enumerated.item]);
2286
2287         return 0;
2288 }
2289
2290 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
2291                                       struct snd_ctl_elem_value *ucontrol)
2292 {
2293         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2294
2295         spin_lock_irq(&hdspm->lock);
2296         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
2297         spin_unlock_irq(&hdspm->lock);
2298         return 0;
2299 }
2300
2301 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
2302                                       struct snd_ctl_elem_value *ucontrol)
2303 {
2304         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2305         int change;
2306         unsigned int val;
2307
2308         if (!snd_hdspm_use_is_exclusive(hdspm))
2309                 return -EBUSY;
2310         val = ucontrol->value.integer.value[0] & 1;
2311         spin_lock_irq(&hdspm->lock);
2312         change = (int) val != hdspm_input_select(hdspm);
2313         hdspm_set_input_select(hdspm, val);
2314         spin_unlock_irq(&hdspm->lock);
2315         return change;
2316 }
2317
2318 #define HDSPM_DS_WIRE(xname, xindex) \
2319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2320   .name = xname, \
2321   .index = xindex, \
2322   .info = snd_hdspm_info_ds_wire, \
2323   .get = snd_hdspm_get_ds_wire, \
2324   .put = snd_hdspm_put_ds_wire \
2325 }
2326
2327 static int hdspm_ds_wire(struct hdspm * hdspm)
2328 {
2329         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
2330 }
2331
2332 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
2333 {
2334         if (ds)
2335                 hdspm->control_register |= HDSPM_DS_DoubleWire;
2336         else
2337                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
2338         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2339
2340         return 0;
2341 }
2342
2343 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
2344                                   struct snd_ctl_elem_info *uinfo)
2345 {
2346         static char *texts[] = { "Single", "Double" };
2347
2348         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2349         uinfo->count = 1;
2350         uinfo->value.enumerated.items = 2;
2351
2352         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2353                 uinfo->value.enumerated.item =
2354                     uinfo->value.enumerated.items - 1;
2355         strcpy(uinfo->value.enumerated.name,
2356                texts[uinfo->value.enumerated.item]);
2357
2358         return 0;
2359 }
2360
2361 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
2362                                  struct snd_ctl_elem_value *ucontrol)
2363 {
2364         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2365
2366         spin_lock_irq(&hdspm->lock);
2367         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
2368         spin_unlock_irq(&hdspm->lock);
2369         return 0;
2370 }
2371
2372 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
2373                                  struct snd_ctl_elem_value *ucontrol)
2374 {
2375         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2376         int change;
2377         unsigned int val;
2378
2379         if (!snd_hdspm_use_is_exclusive(hdspm))
2380                 return -EBUSY;
2381         val = ucontrol->value.integer.value[0] & 1;
2382         spin_lock_irq(&hdspm->lock);
2383         change = (int) val != hdspm_ds_wire(hdspm);
2384         hdspm_set_ds_wire(hdspm, val);
2385         spin_unlock_irq(&hdspm->lock);
2386         return change;
2387 }
2388
2389 #define HDSPM_QS_WIRE(xname, xindex) \
2390 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2391   .name = xname, \
2392   .index = xindex, \
2393   .info = snd_hdspm_info_qs_wire, \
2394   .get = snd_hdspm_get_qs_wire, \
2395   .put = snd_hdspm_put_qs_wire \
2396 }
2397
2398 static int hdspm_qs_wire(struct hdspm * hdspm)
2399 {
2400         if (hdspm->control_register & HDSPM_QS_DoubleWire)
2401                 return 1;
2402         if (hdspm->control_register & HDSPM_QS_QuadWire)
2403                 return 2;
2404         return 0;
2405 }
2406
2407 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
2408 {
2409         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
2410         switch (mode) {
2411         case 0:
2412                 break;
2413         case 1:
2414                 hdspm->control_register |= HDSPM_QS_DoubleWire;
2415                 break;
2416         case 2:
2417                 hdspm->control_register |= HDSPM_QS_QuadWire;
2418                 break;
2419         }
2420         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2421
2422         return 0;
2423 }
2424
2425 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
2426                                        struct snd_ctl_elem_info *uinfo)
2427 {
2428         static char *texts[] = { "Single", "Double", "Quad" };
2429
2430         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2431         uinfo->count = 1;
2432         uinfo->value.enumerated.items = 3;
2433
2434         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2435                 uinfo->value.enumerated.item =
2436                     uinfo->value.enumerated.items - 1;
2437         strcpy(uinfo->value.enumerated.name,
2438                texts[uinfo->value.enumerated.item]);
2439
2440         return 0;
2441 }
2442
2443 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
2444                                       struct snd_ctl_elem_value *ucontrol)
2445 {
2446         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2447
2448         spin_lock_irq(&hdspm->lock);
2449         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
2450         spin_unlock_irq(&hdspm->lock);
2451         return 0;
2452 }
2453
2454 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
2455                                       struct snd_ctl_elem_value *ucontrol)
2456 {
2457         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2458         int change;
2459         int val;
2460
2461         if (!snd_hdspm_use_is_exclusive(hdspm))
2462                 return -EBUSY;
2463         val = ucontrol->value.integer.value[0];
2464         if (val < 0)
2465                 val = 0;
2466         if (val > 2)
2467                 val = 2;
2468         spin_lock_irq(&hdspm->lock);
2469         change = val != hdspm_qs_wire(hdspm);
2470         hdspm_set_qs_wire(hdspm, val);
2471         spin_unlock_irq(&hdspm->lock);
2472         return change;
2473 }
2474
2475 /*           Simple Mixer
2476   deprecated since to much faders ???
2477   MIXER interface says output (source, destination, value)
2478    where source > MAX_channels are playback channels
2479    on MADICARD
2480   - playback mixer matrix: [channelout+64] [output] [value]
2481   - input(thru) mixer matrix: [channelin] [output] [value]
2482   (better do 2 kontrols for seperation ?)
2483 */
2484
2485 #define HDSPM_MIXER(xname, xindex) \
2486 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2487   .name = xname, \
2488   .index = xindex, \
2489   .device = 0, \
2490   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2491                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2492   .info = snd_hdspm_info_mixer, \
2493   .get = snd_hdspm_get_mixer, \
2494   .put = snd_hdspm_put_mixer \
2495 }
2496
2497 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
2498                                 struct snd_ctl_elem_info *uinfo)
2499 {
2500         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2501         uinfo->count = 3;
2502         uinfo->value.integer.min = 0;
2503         uinfo->value.integer.max = 65535;
2504         uinfo->value.integer.step = 1;
2505         return 0;
2506 }
2507
2508 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
2509                                struct snd_ctl_elem_value *ucontrol)
2510 {
2511         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2512         int source;
2513         int destination;
2514
2515         source = ucontrol->value.integer.value[0];
2516         if (source < 0)
2517                 source = 0;
2518         else if (source >= 2 * HDSPM_MAX_CHANNELS)
2519                 source = 2 * HDSPM_MAX_CHANNELS - 1;
2520
2521         destination = ucontrol->value.integer.value[1];
2522         if (destination < 0)
2523                 destination = 0;
2524         else if (destination >= HDSPM_MAX_CHANNELS)
2525                 destination = HDSPM_MAX_CHANNELS - 1;
2526
2527         spin_lock_irq(&hdspm->lock);
2528         if (source >= HDSPM_MAX_CHANNELS)
2529                 ucontrol->value.integer.value[2] =
2530                     hdspm_read_pb_gain(hdspm, destination,
2531                                        source - HDSPM_MAX_CHANNELS);
2532         else
2533                 ucontrol->value.integer.value[2] =
2534                     hdspm_read_in_gain(hdspm, destination, source);
2535
2536         spin_unlock_irq(&hdspm->lock);
2537
2538         return 0;
2539 }
2540
2541 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
2542                                struct snd_ctl_elem_value *ucontrol)
2543 {
2544         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2545         int change;
2546         int source;
2547         int destination;
2548         int gain;
2549
2550         if (!snd_hdspm_use_is_exclusive(hdspm))
2551                 return -EBUSY;
2552
2553         source = ucontrol->value.integer.value[0];
2554         destination = ucontrol->value.integer.value[1];
2555
2556         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
2557                 return -1;
2558         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
2559                 return -1;
2560
2561         gain = ucontrol->value.integer.value[2];
2562
2563         spin_lock_irq(&hdspm->lock);
2564
2565         if (source >= HDSPM_MAX_CHANNELS)
2566                 change = gain != hdspm_read_pb_gain(hdspm, destination,
2567                                                     source -
2568                                                     HDSPM_MAX_CHANNELS);
2569         else
2570                 change = gain != hdspm_read_in_gain(hdspm, destination,
2571                                                     source);
2572
2573         if (change) {
2574                 if (source >= HDSPM_MAX_CHANNELS)
2575                         hdspm_write_pb_gain(hdspm, destination,
2576                                             source - HDSPM_MAX_CHANNELS,
2577                                             gain);
2578                 else
2579                         hdspm_write_in_gain(hdspm, destination, source,
2580                                             gain);
2581         }
2582         spin_unlock_irq(&hdspm->lock);
2583
2584         return change;
2585 }
2586
2587 /* The simple mixer control(s) provide gain control for the
2588    basic 1:1 mappings of playback streams to output
2589    streams.
2590 */
2591
2592 #define HDSPM_PLAYBACK_MIXER \
2593 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2594   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
2595                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2596   .info = snd_hdspm_info_playback_mixer, \
2597   .get = snd_hdspm_get_playback_mixer, \
2598   .put = snd_hdspm_put_playback_mixer \
2599 }
2600
2601 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
2602                                          struct snd_ctl_elem_info *uinfo)
2603 {
2604         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2605         uinfo->count = 1;
2606         uinfo->value.integer.min = 0;
2607         uinfo->value.integer.max = 65536;
2608         uinfo->value.integer.step = 1;
2609         return 0;
2610 }
2611
2612 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
2613                                         struct snd_ctl_elem_value *ucontrol)
2614 {
2615         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2616         int channel;
2617         int mapped_channel;
2618
2619         channel = ucontrol->id.index - 1;
2620
2621         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
2622                 return -EINVAL;
2623
2624         mapped_channel = hdspm->channel_map[channel];
2625         if (mapped_channel < 0)
2626                 return -EINVAL;
2627
2628         spin_lock_irq(&hdspm->lock);
2629         ucontrol->value.integer.value[0] =
2630             hdspm_read_pb_gain(hdspm, mapped_channel, mapped_channel);
2631         spin_unlock_irq(&hdspm->lock);
2632
2633         /*
2634         snd_printdd("get pb mixer index %d, channel %d, mapped_channel %d, "
2635                     "value %d\n",
2636                     ucontrol->id.index, channel, mapped_channel,
2637                     ucontrol->value.integer.value[0]);
2638         */
2639         return 0;
2640 }
2641
2642 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
2643                                         struct snd_ctl_elem_value *ucontrol)
2644 {
2645         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2646         int change;
2647         int channel;
2648         int mapped_channel;
2649         int gain;
2650
2651         if (!snd_hdspm_use_is_exclusive(hdspm))
2652                 return -EBUSY;
2653
2654         channel = ucontrol->id.index - 1;
2655
2656         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
2657                 return -EINVAL;
2658
2659         mapped_channel = hdspm->channel_map[channel];
2660         if (mapped_channel < 0)
2661                 return -EINVAL;
2662
2663         gain = ucontrol->value.integer.value[0];
2664
2665         spin_lock_irq(&hdspm->lock);
2666         change =
2667             gain != hdspm_read_pb_gain(hdspm, mapped_channel,
2668                                        mapped_channel);
2669         if (change)
2670                 hdspm_write_pb_gain(hdspm, mapped_channel, mapped_channel,
2671                                     gain);
2672         spin_unlock_irq(&hdspm->lock);
2673         return change;
2674 }
2675
2676 #define HDSPM_WC_SYNC_CHECK(xname, xindex) \
2677 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2678   .name = xname, \
2679   .index = xindex, \
2680   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2681   .info = snd_hdspm_info_sync_check, \
2682   .get = snd_hdspm_get_wc_sync_check \
2683 }
2684
2685 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
2686                                      struct snd_ctl_elem_info *uinfo)
2687 {
2688         static char *texts[] = { "No Lock", "Lock", "Sync" };
2689         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2690         uinfo->count = 1;
2691         uinfo->value.enumerated.items = 3;
2692         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2693                 uinfo->value.enumerated.item =
2694                     uinfo->value.enumerated.items - 1;
2695         strcpy(uinfo->value.enumerated.name,
2696                texts[uinfo->value.enumerated.item]);
2697         return 0;
2698 }
2699
2700 static int hdspm_wc_sync_check(struct hdspm * hdspm)
2701 {
2702         if (hdspm->is_aes32) {
2703                 int status = hdspm_read(hdspm, HDSPM_statusRegister);
2704                 if (status & HDSPM_AES32_wcLock) {
2705                         /* I don't know how to differenciate sync from lock.
2706                            Doing as if sync for now */
2707                         return 2;
2708                 }
2709                 return 0;
2710         } else {
2711                 int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2712                 if (status2 & HDSPM_wcLock) {
2713                         if (status2 & HDSPM_wcSync)
2714                                 return 2;
2715                         else
2716                                 return 1;
2717                 }
2718                 return 0;
2719         }
2720 }
2721
2722 static int snd_hdspm_get_wc_sync_check(struct snd_kcontrol *kcontrol,
2723                                        struct snd_ctl_elem_value *ucontrol)
2724 {
2725         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2726
2727         ucontrol->value.enumerated.item[0] = hdspm_wc_sync_check(hdspm);
2728         return 0;
2729 }
2730
2731
2732 #define HDSPM_MADI_SYNC_CHECK(xname, xindex) \
2733 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2734   .name = xname, \
2735   .index = xindex, \
2736   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2737   .info = snd_hdspm_info_sync_check, \
2738   .get = snd_hdspm_get_madisync_sync_check \
2739 }
2740
2741 static int hdspm_madisync_sync_check(struct hdspm * hdspm)
2742 {
2743         int status = hdspm_read(hdspm, HDSPM_statusRegister);
2744         if (status & HDSPM_madiLock) {
2745                 if (status & HDSPM_madiSync)
2746                         return 2;
2747                 else
2748                         return 1;
2749         }
2750         return 0;
2751 }
2752
2753 static int snd_hdspm_get_madisync_sync_check(struct snd_kcontrol *kcontrol,
2754                                              struct snd_ctl_elem_value *
2755                                              ucontrol)
2756 {
2757         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2758
2759         ucontrol->value.enumerated.item[0] =
2760             hdspm_madisync_sync_check(hdspm);
2761         return 0;
2762 }
2763
2764
2765 #define HDSPM_AES_SYNC_CHECK(xname, xindex) \
2766 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2767   .name = xname, \
2768   .index = xindex, \
2769   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2770   .info = snd_hdspm_info_sync_check, \
2771   .get = snd_hdspm_get_aes_sync_check \
2772 }
2773
2774 static int hdspm_aes_sync_check(struct hdspm * hdspm, int idx)
2775 {
2776         int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2777         if (status2 & (HDSPM_LockAES >> idx)) {
2778                 /* I don't know how to differenciate sync from lock.
2779                    Doing as if sync for now */
2780                 return 2;
2781         }
2782         return 0;
2783 }
2784
2785 static int snd_hdspm_get_aes_sync_check(struct snd_kcontrol *kcontrol,
2786                                         struct snd_ctl_elem_value *ucontrol)
2787 {
2788         int offset;
2789         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2790
2791         offset = ucontrol->id.index - 1;
2792         if (offset < 0 || offset >= 8)
2793                 return -EINVAL;
2794
2795         ucontrol->value.enumerated.item[0] =
2796                 hdspm_aes_sync_check(hdspm, offset);
2797         return 0;
2798 }
2799
2800
2801 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
2802
2803         HDSPM_MIXER("Mixer", 0),
2804 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2805         HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2806
2807         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2808         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2809         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2810         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2811 /* 'External Rate' complies with the alsa control naming scheme */
2812         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2813         HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2814         HDSPM_MADI_SYNC_CHECK("MADI Sync Lock Status", 0),
2815         HDSPM_LINE_OUT("Line Out", 0),
2816         HDSPM_TX_64("TX 64 channels mode", 0),
2817         HDSPM_C_TMS("Clear Track Marker", 0),
2818         HDSPM_SAFE_MODE("Safe Mode", 0),
2819         HDSPM_INPUT_SELECT("Input Select", 0),
2820 };
2821
2822 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
2823
2824         HDSPM_MIXER("Mixer", 0),
2825 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2826         HDSPM_CLOCK_SOURCE("Sample Clock Source", 0),
2827
2828         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2829         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
2830         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
2831         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2832 /* 'External Rate' complies with the alsa control naming scheme */
2833         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2834         HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2835 /*      HDSPM_AES_SYNC_CHECK("AES Lock Status", 0),*/ /* created in snd_hdspm_create_controls() */
2836         HDSPM_LINE_OUT("Line Out", 0),
2837         HDSPM_EMPHASIS("Emphasis", 0),
2838         HDSPM_DOLBY("Non Audio", 0),
2839         HDSPM_PROFESSIONAL("Professional", 0),
2840         HDSPM_C_TMS("Clear Track Marker", 0),
2841         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
2842         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
2843 };
2844
2845 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
2846
2847
2848 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
2849 {
2850         int i;
2851
2852         for (i = hdspm->ds_channels; i < hdspm->ss_channels; ++i) {
2853                 if (hdspm->system_sample_rate > 48000) {
2854                         hdspm->playback_mixer_ctls[i]->vd[0].access =
2855                             SNDRV_CTL_ELEM_ACCESS_INACTIVE |
2856                             SNDRV_CTL_ELEM_ACCESS_READ |
2857                             SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2858                 } else {
2859                         hdspm->playback_mixer_ctls[i]->vd[0].access =
2860                             SNDRV_CTL_ELEM_ACCESS_READWRITE |
2861                             SNDRV_CTL_ELEM_ACCESS_VOLATILE;
2862                 }
2863                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
2864                                SNDRV_CTL_EVENT_MASK_INFO,
2865                                &hdspm->playback_mixer_ctls[i]->id);
2866         }
2867
2868         return 0;
2869 }
2870
2871
2872 static int snd_hdspm_create_controls(struct snd_card *card, struct hdspm * hdspm)
2873 {
2874         unsigned int idx, limit;
2875         int err;
2876         struct snd_kcontrol *kctl;
2877
2878         /* add control list first */
2879         if (hdspm->is_aes32) {
2880                 struct snd_kcontrol_new aes_sync_ctl =
2881                         HDSPM_AES_SYNC_CHECK("AES Lock Status", 0);
2882
2883                 for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_aes32);
2884                      idx++) {
2885                         err = snd_ctl_add(card,
2886                                           snd_ctl_new1(&snd_hdspm_controls_aes32[idx],
2887                                                        hdspm));
2888                         if (err < 0)
2889                                 return err;
2890                 }
2891                 for (idx = 1; idx <= 8; idx++) {
2892                         aes_sync_ctl.index = idx;
2893                         err = snd_ctl_add(card,
2894                                           snd_ctl_new1(&aes_sync_ctl, hdspm));
2895                         if (err < 0)
2896                                 return err;
2897                 }
2898         } else {
2899                 for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_madi);
2900                      idx++) {
2901                         err = snd_ctl_add(card,
2902                                           snd_ctl_new1(&snd_hdspm_controls_madi[idx],
2903                                                        hdspm));
2904                         if (err < 0)
2905                                 return err;
2906                 }
2907         }
2908
2909         /* Channel playback mixer as default control
2910            Note: the whole matrix would be 128*HDSPM_MIXER_CHANNELS Faders,
2911            thats too * big for any alsamixer they are accesible via special
2912            IOCTL on hwdep and the mixer 2dimensional mixer control
2913         */
2914
2915         snd_hdspm_playback_mixer.name = "Chn";
2916         limit = HDSPM_MAX_CHANNELS;
2917
2918         /* The index values are one greater than the channel ID so that
2919          * alsamixer will display them correctly. We want to use the index
2920          * for fast lookup of the relevant channel, but if we use it at all,
2921          * most ALSA software does the wrong thing with it ...
2922          */
2923
2924         for (idx = 0; idx < limit; ++idx) {
2925                 snd_hdspm_playback_mixer.index = idx + 1;
2926                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
2927                 err = snd_ctl_add(card, kctl);
2928                 if (err < 0)
2929                         return err;
2930                 hdspm->playback_mixer_ctls[idx] = kctl;
2931         }
2932
2933         return 0;
2934 }
2935
2936 /*------------------------------------------------------------
2937    /proc interface
2938  ------------------------------------------------------------*/
2939
2940 static void
2941 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
2942                          struct snd_info_buffer *buffer)
2943 {
2944         struct hdspm *hdspm = entry->private_data;
2945         unsigned int status;
2946         unsigned int status2;
2947         char *pref_sync_ref;
2948         char *autosync_ref;
2949         char *system_clock_mode;
2950         char *clock_source;
2951         char *insel;
2952         char *syncref;
2953         int x, x2;
2954
2955         status = hdspm_read(hdspm, HDSPM_statusRegister);
2956         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2957
2958         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
2959                     hdspm->card_name, hdspm->card->number + 1,
2960                     hdspm->firmware_rev,
2961                     (status2 & HDSPM_version0) |
2962                     (status2 & HDSPM_version1) | (status2 &
2963                                                   HDSPM_version2));
2964
2965         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
2966                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
2967
2968         snd_iprintf(buffer, "--- System ---\n");
2969
2970         snd_iprintf(buffer,
2971                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
2972                     status & HDSPM_audioIRQPending,
2973                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
2974                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
2975                     hdspm->irq_count);
2976         snd_iprintf(buffer,
2977                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
2978                     "estimated= %ld (bytes)\n",
2979                     ((status & HDSPM_BufferID) ? 1 : 0),
2980                     (status & HDSPM_BufferPositionMask),
2981                     (status & HDSPM_BufferPositionMask) %
2982                     (2 * (int)hdspm->period_bytes),
2983                     ((status & HDSPM_BufferPositionMask) - 64) %
2984                     (2 * (int)hdspm->period_bytes),
2985                     (long) hdspm_hw_pointer(hdspm) * 4);
2986
2987         snd_iprintf(buffer,
2988                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
2989                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
2990                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
2991                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
2992                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
2993         snd_iprintf(buffer,
2994                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
2995                     "status2=0x%x\n",
2996                     hdspm->control_register, hdspm->control2_register,
2997                     status, status2);
2998
2999         snd_iprintf(buffer, "--- Settings ---\n");
3000
3001         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
3002                                            HDSPM_LatencyMask));
3003
3004         snd_iprintf(buffer,
3005                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
3006                     x, (unsigned long) hdspm->period_bytes);
3007
3008         snd_iprintf(buffer, "Line out: %s,   Precise Pointer: %s\n",
3009                     (hdspm->control_register & HDSPM_LineOut) ? "on " : "off",
3010                     (hdspm->precise_ptr) ? "on" : "off");
3011
3012         switch (hdspm->control_register & HDSPM_InputMask) {
3013         case HDSPM_InputOptical:
3014                 insel = "Optical";
3015                 break;
3016         case HDSPM_InputCoaxial:
3017                 insel = "Coaxial";
3018                 break;
3019         default:
3020                 insel = "Unkown";
3021         }
3022
3023         switch (hdspm->control_register & HDSPM_SyncRefMask) {
3024         case HDSPM_SyncRef_Word:
3025                 syncref = "WordClock";
3026                 break;
3027         case HDSPM_SyncRef_MADI:
3028                 syncref = "MADI";
3029                 break;
3030         default:
3031                 syncref = "Unkown";
3032         }
3033         snd_iprintf(buffer, "Inputsel = %s, SyncRef = %s\n", insel,
3034                     syncref);
3035
3036         snd_iprintf(buffer,
3037                     "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
3038                     "Auto Input %s\n",
3039                     (hdspm->
3040                      control_register & HDSPM_clr_tms) ? "on" : "off",
3041                     (hdspm->
3042                      control_register & HDSPM_TX_64ch) ? "64" : "56",
3043                     (hdspm->
3044                      control_register & HDSPM_AutoInp) ? "on" : "off");
3045
3046         switch (hdspm_clock_source(hdspm)) {
3047         case HDSPM_CLOCK_SOURCE_AUTOSYNC:
3048                 clock_source = "AutoSync";
3049                 break;
3050         case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3051                 clock_source = "Internal 32 kHz";
3052                 break;
3053         case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3054                 clock_source = "Internal 44.1 kHz";
3055                 break;
3056         case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3057                 clock_source = "Internal 48 kHz";
3058                 break;
3059         case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3060                 clock_source = "Internal 64 kHz";
3061                 break;
3062         case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3063                 clock_source = "Internal 88.2 kHz";
3064                 break;
3065         case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3066                 clock_source = "Internal 96 kHz";
3067                 break;
3068         default:
3069                 clock_source = "Error";
3070         }
3071         snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3072         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3073                 system_clock_mode = "Slave";
3074         else
3075                 system_clock_mode = "Master";
3076         snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
3077
3078         switch (hdspm_pref_sync_ref(hdspm)) {
3079         case HDSPM_SYNC_FROM_WORD:
3080                 pref_sync_ref = "Word Clock";
3081                 break;
3082         case HDSPM_SYNC_FROM_MADI:
3083                 pref_sync_ref = "MADI Sync";
3084                 break;
3085         default:
3086                 pref_sync_ref = "XXXX Clock";
3087                 break;
3088         }
3089         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
3090                     pref_sync_ref);
3091
3092         snd_iprintf(buffer, "System Clock Frequency: %d\n",
3093                     hdspm->system_sample_rate);
3094
3095
3096         snd_iprintf(buffer, "--- Status:\n");
3097
3098         x = status & HDSPM_madiSync;
3099         x2 = status2 & HDSPM_wcSync;
3100
3101         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
3102                     (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
3103                     "NoLock",
3104                     (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
3105                     "NoLock");
3106
3107         switch (hdspm_autosync_ref(hdspm)) {
3108         case HDSPM_AUTOSYNC_FROM_WORD:
3109                 autosync_ref = "Word Clock";
3110                 break;
3111         case HDSPM_AUTOSYNC_FROM_MADI:
3112                 autosync_ref = "MADI Sync";
3113                 break;
3114         case HDSPM_AUTOSYNC_FROM_NONE:
3115                 autosync_ref = "Input not valid";
3116                 break;
3117         default:
3118                 autosync_ref = "---";
3119                 break;
3120         }
3121         snd_iprintf(buffer,
3122                     "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
3123                     autosync_ref, hdspm_external_sample_rate(hdspm),
3124                     (status & HDSPM_madiFreqMask) >> 22,
3125                     (status2 & HDSPM_wcFreqMask) >> 5);
3126
3127         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
3128                     (status & HDSPM_AB_int) ? "Coax" : "Optical",
3129                     (status & HDSPM_RX_64ch) ? "64 channels" :
3130                     "56 channels");
3131
3132         snd_iprintf(buffer, "\n");
3133 }
3134
3135 static void
3136 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
3137                           struct snd_info_buffer *buffer)
3138 {
3139         struct hdspm *hdspm = entry->private_data;
3140         unsigned int status;
3141         unsigned int status2;
3142         unsigned int timecode;
3143         int pref_syncref;
3144         char *autosync_ref;
3145         char *system_clock_mode;
3146         char *clock_source;
3147         int x;
3148
3149         status = hdspm_read(hdspm, HDSPM_statusRegister);
3150         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3151         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
3152
3153         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
3154                     hdspm->card_name, hdspm->card->number + 1,
3155                     hdspm->firmware_rev);
3156
3157         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3158                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
3159
3160         snd_iprintf(buffer, "--- System ---\n");
3161
3162         snd_iprintf(buffer,
3163                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
3164                     status & HDSPM_audioIRQPending,
3165                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
3166                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
3167                     hdspm->irq_count);
3168         snd_iprintf(buffer,
3169                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
3170                     "estimated= %ld (bytes)\n",
3171                     ((status & HDSPM_BufferID) ? 1 : 0),
3172                     (status & HDSPM_BufferPositionMask),
3173                     (status & HDSPM_BufferPositionMask) %
3174                     (2 * (int)hdspm->period_bytes),
3175                     ((status & HDSPM_BufferPositionMask) - 64) %
3176                     (2 * (int)hdspm->period_bytes),
3177                     (long) hdspm_hw_pointer(hdspm) * 4);
3178
3179         snd_iprintf(buffer,
3180                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
3181                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
3182                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
3183                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
3184                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
3185         snd_iprintf(buffer,
3186                     "Register: ctrl1=0x%x, status1=0x%x, status2=0x%x, "
3187                     "timecode=0x%x\n",
3188                     hdspm->control_register,
3189                     status, status2, timecode);
3190
3191         snd_iprintf(buffer, "--- Settings ---\n");
3192
3193         x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
3194                                            HDSPM_LatencyMask));
3195
3196         snd_iprintf(buffer,
3197                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
3198                     x, (unsigned long) hdspm->period_bytes);
3199
3200         snd_iprintf(buffer, "Line out: %s,   Precise Pointer: %s\n",
3201                     (hdspm->
3202                      control_register & HDSPM_LineOut) ? "on " : "off",
3203                     (hdspm->precise_ptr) ? "on" : "off");
3204
3205         snd_iprintf(buffer,
3206                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
3207                     (hdspm->
3208                      control_register & HDSPM_clr_tms) ? "on" : "off",
3209                     (hdspm->
3210                      control_register & HDSPM_Emphasis) ? "on" : "off",
3211                     (hdspm->
3212                      control_register & HDSPM_Dolby) ? "on" : "off");
3213
3214         switch (hdspm_clock_source(hdspm)) {
3215         case HDSPM_CLOCK_SOURCE_AUTOSYNC:
3216                 clock_source = "AutoSync";
3217                 break;
3218         case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ:
3219                 clock_source = "Internal 32 kHz";
3220                 break;
3221         case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3222                 clock_source = "Internal 44.1 kHz";
3223                 break;
3224         case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ:
3225                 clock_source = "Internal 48 kHz";
3226                 break;
3227         case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ:
3228                 clock_source = "Internal 64 kHz";
3229                 break;
3230         case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3231                 clock_source = "Internal 88.2 kHz";
3232                 break;
3233         case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ:
3234                 clock_source = "Internal 96 kHz";
3235                 break;
3236         case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ:
3237                 clock_source = "Internal 128 kHz";
3238                 break;
3239         case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3240                 clock_source = "Internal 176.4 kHz";
3241                 break;
3242         case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ:
3243                 clock_source = "Internal 192 kHz";
3244                 break;
3245         default:
3246                 clock_source = "Error";
3247         }
3248         snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3249         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
3250                 system_clock_mode = "Slave";
3251         else
3252                 system_clock_mode = "Master";
3253         snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode);
3254
3255         pref_syncref = hdspm_pref_sync_ref(hdspm);
3256         if (pref_syncref == 0)
3257                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
3258         else
3259                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
3260                                 pref_syncref);
3261
3262         snd_iprintf(buffer, "System Clock Frequency: %d\n",
3263                     hdspm->system_sample_rate);
3264
3265         snd_iprintf(buffer, "Double speed: %s\n",
3266                         hdspm->control_register & HDSPM_DS_DoubleWire?
3267                         "Double wire" : "Single wire");
3268         snd_iprintf(buffer, "Quad speed: %s\n",
3269                         hdspm->control_register & HDSPM_QS_DoubleWire?
3270                         "Double wire" :
3271                         hdspm->control_register & HDSPM_QS_QuadWire?
3272                         "Quad wire" : "Single wire");
3273
3274         snd_iprintf(buffer, "--- Status:\n");
3275
3276         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
3277                     (status & HDSPM_AES32_wcLock)? "Sync   " : "No Lock",
3278                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
3279
3280         for (x = 0; x < 8; x++) {
3281                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
3282                             x+1,
3283                             (status2 & (HDSPM_LockAES >> x)) ?
3284                             "Sync   ": "No Lock",
3285                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
3286         }
3287
3288         switch (hdspm_autosync_ref(hdspm)) {
3289         case HDSPM_AES32_AUTOSYNC_FROM_NONE: autosync_ref="None"; break;
3290         case HDSPM_AES32_AUTOSYNC_FROM_WORD: autosync_ref="Word Clock"; break;
3291         case HDSPM_AES32_AUTOSYNC_FROM_AES1: autosync_ref="AES1"; break;
3292         case HDSPM_AES32_AUTOSYNC_FROM_AES2: autosync_ref="AES2"; break;
3293         case HDSPM_AES32_AUTOSYNC_FROM_AES3: autosync_ref="AES3"; break;
3294         case HDSPM_AES32_AUTOSYNC_FROM_AES4: autosync_ref="AES4"; break;
3295         case HDSPM_AES32_AUTOSYNC_FROM_AES5: autosync_ref="AES5"; break;
3296         case HDSPM_AES32_AUTOSYNC_FROM_AES6: autosync_ref="AES6"; break;
3297         case HDSPM_AES32_AUTOSYNC_FROM_AES7: autosync_ref="AES7"; break;
3298         case HDSPM_AES32_AUTOSYNC_FROM_AES8: autosync_ref="AES8"; break;
3299         default: autosync_ref = "---"; break;
3300         }
3301         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
3302
3303         snd_iprintf(buffer, "\n");
3304 }
3305
3306 #ifdef CONFIG_SND_DEBUG
3307 static void
3308 snd_hdspm_proc_read_debug(struct snd_info_entry * entry,
3309                           struct snd_info_buffer *buffer)
3310 {
3311         struct hdspm *hdspm = entry->private_data;
3312
3313         int j,i;
3314
3315         for (i = 0; i < 256 /* 1024*64 */; i += j) {
3316                 snd_iprintf(buffer, "0x%08X: ", i);
3317                 for (j = 0; j < 16; j += 4)
3318                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
3319                 snd_iprintf(buffer, "\n");
3320         }
3321 }
3322 #endif
3323
3324
3325
3326 static void __devinit snd_hdspm_proc_init(struct hdspm * hdspm)
3327 {
3328         struct snd_info_entry *entry;
3329
3330         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry))
3331                 snd_info_set_text_ops(entry, hdspm,
3332                                       hdspm->is_aes32 ?
3333                                       snd_hdspm_proc_read_aes32 :
3334                                       snd_hdspm_proc_read_madi);
3335 #ifdef CONFIG_SND_DEBUG
3336         /* debug file to read all hdspm registers */
3337         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
3338                 snd_info_set_text_ops(entry, hdspm,
3339                                 snd_hdspm_proc_read_debug);
3340 #endif
3341 }
3342
3343 /*------------------------------------------------------------
3344    hdspm intitialize
3345  ------------------------------------------------------------*/
3346
3347 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
3348 {
3349         unsigned int i;
3350
3351         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
3352            hold it (e.g. during module initialization).
3353          */
3354
3355         /* set defaults:       */
3356
3357         if (hdspm->is_aes32)
3358                 hdspm->control_register =
3359                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3360                         hdspm_encode_latency(7) | /* latency maximum =
3361                                                    * 8192 samples
3362                                                    */
3363                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
3364                         HDSPM_LineOut | /* Analog output in */
3365                         HDSPM_Professional;  /* Professional mode */
3366         else
3367                 hdspm->control_register =
3368                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
3369                         hdspm_encode_latency(7) | /* latency maximum =
3370                                                    * 8192 samples
3371                                                    */
3372                         HDSPM_InputCoaxial |    /* Input Coax not Optical */
3373                         HDSPM_SyncRef_MADI |    /* Madi is syncclock */
3374                         HDSPM_LineOut | /* Analog output in */
3375                         HDSPM_TX_64ch | /* transmit in 64ch mode */
3376                         HDSPM_AutoInp;  /* AutoInput chossing (takeover) */
3377
3378         /* ! HDSPM_Frequency0|HDSPM_Frequency1 = 44.1khz */
3379         /* !  HDSPM_DoubleSpeed HDSPM_QuadSpeed = normal speed */
3380         /* ! HDSPM_clr_tms = do not clear bits in track marks */
3381
3382         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3383
3384         if (!hdspm->is_aes32) {
3385                 /* No control2 register for AES32 */
3386 #ifdef SNDRV_BIG_ENDIAN
3387                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
3388 #else
3389                 hdspm->control2_register = 0;
3390 #endif
3391
3392                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
3393         }
3394         hdspm_compute_period_size(hdspm);
3395
3396         /* silence everything */
3397
3398         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
3399
3400         if (line_outs_monitor[hdspm->dev]) {
3401
3402                 snd_printk(KERN_INFO "HDSPM: "
3403                            "sending all playback streams to line outs.\n");
3404
3405                 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) {
3406                         if (hdspm_write_pb_gain(hdspm, i, i, UNITY_GAIN))
3407                                 return -EIO;
3408                 }
3409         }
3410
3411         /* set a default rate so that the channel map is set up. */
3412         hdspm->channel_map = channel_map_madi_ss;
3413         hdspm_set_rate(hdspm, 44100, 1);
3414
3415         return 0;
3416 }
3417
3418
3419 /*------------------------------------------------------------
3420    interrupt
3421  ------------------------------------------------------------*/
3422
3423 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
3424 {
3425         struct hdspm *hdspm = (struct hdspm *) dev_id;
3426         unsigned int status;
3427         int audio;
3428         int midi0;
3429         int midi1;
3430         unsigned int midi0status;
3431         unsigned int midi1status;
3432         int schedule = 0;
3433
3434         status = hdspm_read(hdspm, HDSPM_statusRegister);
3435
3436         audio = status & HDSPM_audioIRQPending;
3437         midi0 = status & HDSPM_midi0IRQPending;
3438         midi1 = status & HDSPM_midi1IRQPending;
3439
3440         if (!audio && !midi0 && !midi1)
3441                 return IRQ_NONE;
3442
3443         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
3444         hdspm->irq_count++;
3445
3446         midi0status = hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff;
3447         midi1status = hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff;
3448
3449         if (audio) {
3450
3451                 if (hdspm->capture_substream)
3452                         snd_pcm_period_elapsed(hdspm->capture_substream);
3453
3454                 if (hdspm->playback_substream)
3455                         snd_pcm_period_elapsed(hdspm->playback_substream);
3456         }
3457
3458         if (midi0 && midi0status) {
3459                 /* we disable interrupts for this input until processing
3460                  * is done
3461                  */
3462                 hdspm->control_register &= ~HDSPM_Midi0InterruptEnable;
3463                 hdspm_write(hdspm, HDSPM_controlRegister,
3464                             hdspm->control_register);
3465                 hdspm->midi[0].pending = 1;
3466                 schedule = 1;
3467         }
3468         if (midi1 && midi1status) {
3469                 /* we disable interrupts for this input until processing
3470                  * is done
3471                  */
3472                 hdspm->control_register &= ~HDSPM_Midi1InterruptEnable;
3473                 hdspm_write(hdspm, HDSPM_controlRegister,
3474                             hdspm->control_register);
3475                 hdspm->midi[1].pending = 1;
3476                 schedule = 1;
3477         }
3478         if (schedule)
3479                 tasklet_hi_schedule(&hdspm->midi_tasklet);
3480         return IRQ_HANDLED;
3481 }
3482
3483 /*------------------------------------------------------------
3484    pcm interface
3485   ------------------------------------------------------------*/
3486
3487
3488 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream *
3489                                               substream)
3490 {
3491         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3492         return hdspm_hw_pointer(hdspm);
3493 }
3494
3495 static char *hdspm_channel_buffer_location(struct hdspm * hdspm,
3496                                            int stream, int channel)
3497 {
3498         int mapped_channel;
3499
3500         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3501                 return NULL;
3502
3503         mapped_channel = hdspm->channel_map[channel];
3504         if (mapped_channel < 0)
3505                 return NULL;
3506
3507         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3508                 return hdspm->capture_buffer +
3509                     mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3510         else
3511                 return hdspm->playback_buffer +
3512                     mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3513 }
3514
3515
3516 /* dont know why need it ??? */
3517 static int snd_hdspm_playback_copy(struct snd_pcm_substream *substream,
3518                                    int channel, snd_pcm_uframes_t pos,
3519                                    void __user *src, snd_pcm_uframes_t count)
3520 {
3521         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3522         char *channel_buf;
3523
3524         if (snd_BUG_ON(pos + count > HDSPM_CHANNEL_BUFFER_BYTES / 4))
3525                 return -EINVAL;
3526
3527         channel_buf =
3528                 hdspm_channel_buffer_location(hdspm, substream->pstr->stream,
3529                                               channel);
3530
3531         if (snd_BUG_ON(!channel_buf))
3532                 return -EIO;
3533
3534         return copy_from_user(channel_buf + pos * 4, src, count * 4);
3535 }
3536
3537 static int snd_hdspm_capture_copy(struct snd_pcm_substream *substream,
3538                                   int channel, snd_pcm_uframes_t pos,
3539                                   void __user *dst, snd_pcm_uframes_t count)
3540 {
3541         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3542         char *channel_buf;
3543
3544         if (snd_BUG_ON(pos + count > HDSPM_CHANNEL_BUFFER_BYTES / 4))
3545                 return -EINVAL;
3546
3547         channel_buf =
3548                 hdspm_channel_buffer_location(hdspm, substream->pstr->stream,
3549                                               channel);
3550         if (snd_BUG_ON(!channel_buf))
3551                 return -EIO;
3552         return copy_to_user(dst, channel_buf + pos * 4, count * 4);
3553 }
3554
3555 static int snd_hdspm_hw_silence(struct snd_pcm_substream *substream,
3556                                 int channel, snd_pcm_uframes_t pos,
3557                                 snd_pcm_uframes_t count)
3558 {
3559         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3560         char *channel_buf;
3561
3562         channel_buf =
3563                 hdspm_channel_buffer_location(hdspm, substream->pstr->stream,
3564                                               channel);
3565         if (snd_BUG_ON(!channel_buf))
3566                 return -EIO;
3567         memset(channel_buf + pos * 4, 0, count * 4);
3568         return 0;
3569 }
3570
3571 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
3572 {
3573         struct snd_pcm_runtime *runtime = substream->runtime;
3574         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3575         struct snd_pcm_substream *other;
3576
3577         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3578                 other = hdspm->capture_substream;
3579         else
3580                 other = hdspm->playback_substream;
3581
3582         if (hdspm->running)
3583                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
3584         else
3585                 runtime->status->hw_ptr = 0;
3586         if (other) {
3587                 struct snd_pcm_substream *s;
3588                 struct snd_pcm_runtime *oruntime = other->runtime;
3589                 snd_pcm_group_for_each_entry(s, substream) {
3590                         if (s == other) {
3591                                 oruntime->status->hw_ptr =
3592                                     runtime->status->hw_ptr;
3593                                 break;
3594                         }
3595                 }
3596         }
3597         return 0;
3598 }
3599
3600 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
3601                                struct snd_pcm_hw_params *params)
3602 {
3603         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3604         int err;
3605         int i;
3606         pid_t this_pid;
3607         pid_t other_pid;
3608
3609         spin_lock_irq(&hdspm->lock);
3610
3611         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3612                 this_pid = hdspm->playback_pid;
3613                 other_pid = hdspm->capture_pid;
3614         } else {
3615                 this_pid = hdspm->capture_pid;
3616                 other_pid = hdspm->playback_pid;
3617         }
3618
3619         if (other_pid > 0 && this_pid != other_pid) {
3620
3621                 /* The other stream is open, and not by the same
3622                    task as this one. Make sure that the parameters
3623                    that matter are the same.
3624                  */
3625
3626                 if (params_rate(params) != hdspm->system_sample_rate) {
3627                         spin_unlock_irq(&hdspm->lock);
3628                         _snd_pcm_hw_param_setempty(params,
3629                                                    SNDRV_PCM_HW_PARAM_RATE);
3630                         return -EBUSY;
3631                 }
3632
3633                 if (params_period_size(params) != hdspm->period_bytes / 4) {
3634                         spin_unlock_irq(&hdspm->lock);
3635                         _snd_pcm_hw_param_setempty(params,
3636                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3637                         return -EBUSY;
3638                 }
3639
3640         }
3641         /* We're fine. */
3642         spin_unlock_irq(&hdspm->lock);
3643
3644         /* how to make sure that the rate matches an externally-set one ?   */
3645
3646         spin_lock_irq(&hdspm->lock);
3647         err = hdspm_set_rate(hdspm, params_rate(params), 0);
3648         if (err < 0) {
3649                 spin_unlock_irq(&hdspm->lock);
3650                 _snd_pcm_hw_param_setempty(params,
3651                                            SNDRV_PCM_HW_PARAM_RATE);
3652                 return err;
3653         }
3654         spin_unlock_irq(&hdspm->lock);
3655
3656         err = hdspm_set_interrupt_interval(hdspm,
3657                                            params_period_size(params));
3658         if (err < 0) {
3659                 _snd_pcm_hw_param_setempty(params,
3660                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3661                 return err;
3662         }
3663
3664         /* Memory allocation, takashi's method, dont know if we should
3665          * spinlock
3666          */
3667         /* malloc all buffer even if not enabled to get sure */
3668         /* Update for MADI rev 204: we need to allocate for all channels,
3669          * otherwise it doesn't work at 96kHz */
3670         err =
3671             snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
3672         if (err < 0)
3673                 return err;
3674
3675         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3676
3677                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
3678                                 params_channels(params));
3679
3680                 for (i = 0; i < params_channels(params); ++i)
3681                         snd_hdspm_enable_out(hdspm, i, 1);
3682
3683                 hdspm->playback_buffer =
3684                     (unsigned char *) substream->runtime->dma_area;
3685                 snd_printdd("Allocated sample buffer for playback at %p\n",
3686                                 hdspm->playback_buffer);
3687         } else {
3688                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
3689                                 params_channels(params));
3690
3691                 for (i = 0; i < params_channels(params); ++i)
3692                         snd_hdspm_enable_in(hdspm, i, 1);
3693
3694                 hdspm->capture_buffer =
3695                     (unsigned char *) substream->runtime->dma_area;
3696                 snd_printdd("Allocated sample buffer for capture at %p\n",
3697                                 hdspm->capture_buffer);
3698         }
3699         /*
3700            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
3701            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3702            "playback" : "capture",
3703            snd_pcm_sgbuf_get_addr(substream, 0));
3704          */
3705         /*
3706         snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
3707                         substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
3708                           "playback" : "capture",
3709                         params_rate(params), params_channels(params),
3710                         params_buffer_size(params));
3711         */
3712         return 0;
3713 }
3714
3715 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
3716 {
3717         int i;
3718         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3719
3720         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3721
3722                 /* params_channels(params) should be enough,
3723                    but to get sure in case of error */
3724                 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
3725                         snd_hdspm_enable_out(hdspm, i, 0);
3726
3727                 hdspm->playback_buffer = NULL;
3728         } else {
3729                 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i)
3730                         snd_hdspm_enable_in(hdspm, i, 0);
3731
3732                 hdspm->capture_buffer = NULL;
3733
3734         }
3735
3736         snd_pcm_lib_free_pages(substream);
3737
3738         return 0;
3739 }
3740
3741 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
3742                                   struct snd_pcm_channel_info * info)
3743 {
3744         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3745         int mapped_channel;
3746
3747         if (snd_BUG_ON(info->channel >= HDSPM_MAX_CHANNELS))
3748                 return -EINVAL;
3749
3750         mapped_channel = hdspm->channel_map[info->channel];
3751         if (mapped_channel < 0)
3752                 return -EINVAL;
3753
3754         info->offset = mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES;
3755         info->first = 0;
3756         info->step = 32;
3757         return 0;
3758 }
3759
3760 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
3761                            unsigned int cmd, void *arg)
3762 {
3763         switch (cmd) {
3764         case SNDRV_PCM_IOCTL1_RESET:
3765                 return snd_hdspm_reset(substream);
3766
3767         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3768         {
3769                 struct snd_pcm_channel_info *info = arg;
3770                 return snd_hdspm_channel_info(substream, info);
3771         }
3772         default:
3773                 break;
3774         }
3775
3776         return snd_pcm_lib_ioctl(substream, cmd, arg);
3777 }
3778
3779 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
3780 {
3781         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3782         struct snd_pcm_substream *other;
3783         int running;
3784
3785         spin_lock(&hdspm->lock);
3786         running = hdspm->running;
3787         switch (cmd) {
3788         case SNDRV_PCM_TRIGGER_START:
3789                 running |= 1 << substream->stream;
3790                 break;
3791         case SNDRV_PCM_TRIGGER_STOP:
3792                 running &= ~(1 << substream->stream);
3793                 break;
3794         default:
3795                 snd_BUG();
3796                 spin_unlock(&hdspm->lock);
3797                 return -EINVAL;
3798         }
3799         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3800                 other = hdspm->capture_substream;
3801         else
3802                 other = hdspm->playback_substream;
3803
3804         if (other) {
3805                 struct snd_pcm_substream *s;
3806                 snd_pcm_group_for_each_entry(s, substream) {
3807                         if (s == other) {
3808                                 snd_pcm_trigger_done(s, substream);
3809                                 if (cmd == SNDRV_PCM_TRIGGER_START)
3810                                         running |= 1 << s->stream;
3811                                 else
3812                                         running &= ~(1 << s->stream);
3813                                 goto _ok;
3814                         }
3815                 }
3816                 if (cmd == SNDRV_PCM_TRIGGER_START) {
3817                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
3818                             && substream->stream ==
3819                             SNDRV_PCM_STREAM_CAPTURE)
3820                                 hdspm_silence_playback(hdspm);
3821                 } else {
3822                         if (running &&
3823                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3824                                 hdspm_silence_playback(hdspm);
3825                 }
3826         } else {
3827                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3828                         hdspm_silence_playback(hdspm);
3829         }
3830       _ok:
3831         snd_pcm_trigger_done(substream, substream);
3832         if (!hdspm->running && running)
3833                 hdspm_start_audio(hdspm);
3834         else if (hdspm->running && !running)
3835                 hdspm_stop_audio(hdspm);
3836         hdspm->running = running;
3837         spin_unlock(&hdspm->lock);
3838
3839         return 0;
3840 }
3841
3842 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
3843 {
3844         return 0;
3845 }
3846
3847 static unsigned int period_sizes[] =
3848     { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
3849
3850 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
3851         .info = (SNDRV_PCM_INFO_MMAP |
3852                  SNDRV_PCM_INFO_MMAP_VALID |
3853                  SNDRV_PCM_INFO_NONINTERLEAVED |
3854                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
3855         .formats = SNDRV_PCM_FMTBIT_S32_LE,
3856         .rates = (SNDRV_PCM_RATE_32000 |
3857                   SNDRV_PCM_RATE_44100 |
3858                   SNDRV_PCM_RATE_48000 |
3859                   SNDRV_PCM_RATE_64000 |
3860                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
3861                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
3862         .rate_min = 32000,
3863         .rate_max = 192000,
3864         .channels_min = 1,
3865         .channels_max = HDSPM_MAX_CHANNELS,
3866         .buffer_bytes_max =
3867             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
3868         .period_bytes_min = (64 * 4),
3869         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
3870         .periods_min = 2,
3871         .periods_max = 2,
3872         .fifo_size = 0
3873 };
3874
3875 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
3876         .info = (SNDRV_PCM_INFO_MMAP |
3877                  SNDRV_PCM_INFO_MMAP_VALID |
3878                  SNDRV_PCM_INFO_NONINTERLEAVED |
3879                  SNDRV_PCM_INFO_SYNC_START),
3880         .formats = SNDRV_PCM_FMTBIT_S32_LE,
3881         .rates = (SNDRV_PCM_RATE_32000 |
3882                   SNDRV_PCM_RATE_44100 |
3883                   SNDRV_PCM_RATE_48000 |
3884                   SNDRV_PCM_RATE_64000 |
3885                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
3886                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
3887         .rate_min = 32000,
3888         .rate_max = 192000,
3889         .channels_min = 1,
3890         .channels_max = HDSPM_MAX_CHANNELS,
3891         .buffer_bytes_max =
3892             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
3893         .period_bytes_min = (64 * 4),
3894         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
3895         .periods_min = 2,
3896         .periods_max = 2,
3897         .fifo_size = 0
3898 };
3899
3900 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
3901         .count = ARRAY_SIZE(period_sizes),
3902         .list = period_sizes,
3903         .mask = 0
3904 };
3905
3906
3907 static int snd_hdspm_hw_rule_channels_rate(struct snd_pcm_hw_params *params,
3908                                            struct snd_pcm_hw_rule * rule)
3909 {
3910         struct hdspm *hdspm = rule->private;
3911         struct snd_interval *c =
3912             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
3913         struct snd_interval *r =
3914             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3915
3916         if (r->min > 48000 && r->max <= 96000) {
3917                 struct snd_interval t = {
3918                         .min = hdspm->ds_channels,
3919                         .max = hdspm->ds_channels,
3920                         .integer = 1,
3921                 };
3922                 return snd_interval_refine(c, &t);
3923         } else if (r->max < 64000) {
3924                 struct snd_interval t = {
3925                         .min = hdspm->ss_channels,
3926                         .max = hdspm->ss_channels,
3927                         .integer = 1,
3928                 };
3929                 return snd_interval_refine(c, &t);
3930         }
3931         return 0;
3932 }
3933
3934 static int snd_hdspm_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
3935                                            struct snd_pcm_hw_rule * rule)
3936 {
3937         struct hdspm *hdspm = rule->private;
3938         struct snd_interval *c =
3939             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
3940         struct snd_interval *r =
3941             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
3942
3943         if (c->min >= hdspm->ss_channels) {
3944                 struct snd_interval t = {
3945                         .min = 32000,
3946                         .max = 48000,
3947                         .integer = 1,
3948                 };
3949                 return snd_interval_refine(r, &t);
3950         } else if (c->max <= hdspm->ds_channels) {
3951                 struct snd_interval t = {
3952                         .min = 64000,
3953                         .max = 96000,
3954                         .integer = 1,
3955                 };
3956
3957                 return snd_interval_refine(r, &t);
3958         }
3959         return 0;
3960 }
3961
3962 static int snd_hdspm_hw_rule_channels(struct snd_pcm_hw_params *params,
3963                                       struct snd_pcm_hw_rule *rule)
3964 {
3965         unsigned int list[3];
3966         struct hdspm *hdspm = rule->private;
3967         struct snd_interval *c = hw_param_interval(params,
3968                         SNDRV_PCM_HW_PARAM_CHANNELS);
3969         if (hdspm->is_aes32) {
3970                 list[0] = hdspm->qs_channels;
3971                 list[1] = hdspm->ds_channels;
3972                 list[2] = hdspm->ss_channels;
3973                 return snd_interval_list(c, 3, list, 0);
3974         } else {
3975                 list[0] = hdspm->ds_channels;
3976                 list[1] = hdspm->ss_channels;
3977                 return snd_interval_list(c, 2, list, 0);
3978         }
3979 }
3980
3981
3982 static unsigned int hdspm_aes32_sample_rates[] = {
3983         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
3984 };
3985
3986 static struct snd_pcm_hw_constraint_list
3987 hdspm_hw_constraints_aes32_sample_rates = {
3988         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
3989         .list = hdspm_aes32_sample_rates,
3990         .mask = 0
3991 };
3992
3993 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
3994 {
3995         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
3996         struct snd_pcm_runtime *runtime = substream->runtime;
3997
3998         spin_lock_irq(&hdspm->lock);
3999
4000         snd_pcm_set_sync(substream);
4001
4002         runtime->hw = snd_hdspm_playback_subinfo;
4003
4004         if (hdspm->capture_substream == NULL)
4005                 hdspm_stop_audio(hdspm);
4006
4007         hdspm->playback_pid = current->pid;
4008         hdspm->playback_substream = substream;
4009
4010         spin_unlock_irq(&hdspm->lock);
4011
4012         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4013
4014         snd_pcm_hw_constraint_list(runtime, 0,
4015                                    SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
4016                                    &hw_constraints_period_sizes);
4017
4018         if (hdspm->is_aes32) {
4019                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4020                                 &hdspm_hw_constraints_aes32_sample_rates);
4021         } else {
4022                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4023                                      snd_hdspm_hw_rule_channels, hdspm,
4024                                      SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4025                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4026                                     snd_hdspm_hw_rule_channels_rate, hdspm,
4027                                     SNDRV_PCM_HW_PARAM_RATE, -1);
4028
4029                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4030                                     snd_hdspm_hw_rule_rate_channels, hdspm,
4031                                     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4032         }
4033         return 0;
4034 }
4035
4036 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
4037 {
4038         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
4039
4040         spin_lock_irq(&hdspm->lock);
4041
4042         hdspm->playback_pid = -1;
4043         hdspm->playback_substream = NULL;
4044
4045         spin_unlock_irq(&hdspm->lock);
4046
4047         return 0;
4048 }
4049
4050
4051 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
4052 {
4053         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
4054         struct snd_pcm_runtime *runtime = substream->runtime;
4055
4056         spin_lock_irq(&hdspm->lock);
4057         snd_pcm_set_sync(substream);
4058         runtime->hw = snd_hdspm_capture_subinfo;
4059
4060         if (hdspm->playback_substream == NULL)
4061                 hdspm_stop_audio(hdspm);
4062
4063         hdspm->capture_pid = current->pid;
4064         hdspm->capture_substream = substream;
4065
4066         spin_unlock_irq(&hdspm->lock);
4067
4068         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4069         snd_pcm_hw_constraint_list(runtime, 0,
4070                                    SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
4071                                    &hw_constraints_period_sizes);
4072         if (hdspm->is_aes32) {
4073                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4074                                 &hdspm_hw_constraints_aes32_sample_rates);
4075         } else {
4076                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4077                                      snd_hdspm_hw_rule_channels, hdspm,
4078                                      SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4079                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4080                                     snd_hdspm_hw_rule_channels_rate, hdspm,
4081                                     SNDRV_PCM_HW_PARAM_RATE, -1);
4082
4083                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4084                                     snd_hdspm_hw_rule_rate_channels, hdspm,
4085                                     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4086         }
4087         return 0;
4088 }
4089
4090 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
4091 {
4092         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
4093
4094         spin_lock_irq(&hdspm->lock);
4095
4096         hdspm->capture_pid = -1;
4097         hdspm->capture_substream = NULL;
4098
4099         spin_unlock_irq(&hdspm->lock);
4100         return 0;
4101 }
4102
4103 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep * hw, struct file *file)
4104 {
4105         /* we have nothing to initialize but the call is required */
4106         return 0;
4107 }
4108
4109
4110 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep * hw, struct file *file,
4111                                  unsigned int cmd, unsigned long arg)
4112 {
4113         struct hdspm *hdspm = hw->private_data;
4114         struct hdspm_mixer_ioctl mixer;
4115         struct hdspm_config_info info;
4116         struct hdspm_version hdspm_version;
4117         struct hdspm_peak_rms_ioctl rms;
4118
4119         switch (cmd) {
4120
4121         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
4122                 if (copy_from_user(&rms, (void __user *)arg, sizeof(rms)))
4123                         return -EFAULT;
4124                 /* maybe there is a chance to memorymap in future
4125                  * so dont touch just copy
4126                  */
4127                 if(copy_to_user_fromio((void __user *)rms.peak,
4128                                        hdspm->iobase+HDSPM_MADI_peakrmsbase,
4129                                        sizeof(struct hdspm_peak_rms)) != 0 )
4130                         return -EFAULT;
4131
4132                 break;
4133
4134
4135         case SNDRV_HDSPM_IOCTL_GET_CONFIG_INFO:
4136
4137                 spin_lock_irq(&hdspm->lock);
4138                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
4139                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
4140
4141                 info.system_sample_rate = hdspm->system_sample_rate;
4142                 info.autosync_sample_rate =
4143                     hdspm_external_sample_rate(hdspm);
4144                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
4145                 info.clock_source = hdspm_clock_source(hdspm);
4146                 info.autosync_ref = hdspm_autosync_ref(hdspm);
4147                 info.line_out = hdspm_line_out(hdspm);
4148                 info.passthru = 0;
4149                 spin_unlock_irq(&hdspm->lock);
4150                 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
4151                         return -EFAULT;
4152                 break;
4153
4154         case SNDRV_HDSPM_IOCTL_GET_VERSION:
4155                 hdspm_version.firmware_rev = hdspm->firmware_rev;
4156                 if (copy_to_user((void __user *) arg, &hdspm_version,
4157                                  sizeof(hdspm_version)))
4158                         return -EFAULT;
4159                 break;
4160
4161         case SNDRV_HDSPM_IOCTL_GET_MIXER:
4162                 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
4163                         return -EFAULT;
4164                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
4165                                  sizeof(struct hdspm_mixer)))
4166                         return -EFAULT;
4167                 break;
4168
4169         default:
4170                 return -EINVAL;
4171         }
4172         return 0;
4173 }
4174
4175 static struct snd_pcm_ops snd_hdspm_playback_ops = {
4176         .open = snd_hdspm_playback_open,
4177         .close = snd_hdspm_playback_release,
4178         .ioctl = snd_hdspm_ioctl,
4179         .hw_params = snd_hdspm_hw_params,
4180         .hw_free = snd_hdspm_hw_free,
4181         .prepare = snd_hdspm_prepare,
4182         .trigger = snd_hdspm_trigger,
4183         .pointer = snd_hdspm_hw_pointer,
4184         .copy = snd_hdspm_playback_copy,
4185         .silence = snd_hdspm_hw_silence,
4186         .page = snd_pcm_sgbuf_ops_page,
4187 };
4188
4189 static struct snd_pcm_ops snd_hdspm_capture_ops = {
4190         .open = snd_hdspm_capture_open,
4191         .close = snd_hdspm_capture_release,
4192         .ioctl = snd_hdspm_ioctl,
4193         .hw_params = snd_hdspm_hw_params,
4194         .hw_free = snd_hdspm_hw_free,
4195         .prepare = snd_hdspm_prepare,
4196         .trigger = snd_hdspm_trigger,
4197         .pointer = snd_hdspm_hw_pointer,
4198         .copy = snd_hdspm_capture_copy,
4199         .page = snd_pcm_sgbuf_ops_page,
4200 };
4201
4202 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
4203                                             struct hdspm * hdspm)
4204 {
4205         struct snd_hwdep *hw;
4206         int err;
4207
4208         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
4209         if (err < 0)
4210                 return err;
4211
4212         hdspm->hwdep = hw;
4213         hw->private_data = hdspm;
4214         strcpy(hw->name, "HDSPM hwdep interface");
4215
4216         hw->ops.open = snd_hdspm_hwdep_dummy_op;
4217         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
4218         hw->ops.release = snd_hdspm_hwdep_dummy_op;
4219
4220         return 0;
4221 }
4222
4223
4224 /*------------------------------------------------------------
4225    memory interface
4226  ------------------------------------------------------------*/
4227 static int __devinit snd_hdspm_preallocate_memory(struct hdspm * hdspm)
4228 {
4229         int err;
4230         struct snd_pcm *pcm;
4231         size_t wanted;
4232
4233         pcm = hdspm->pcm;
4234
4235         wanted = HDSPM_DMA_AREA_BYTES;
4236
4237         err =
4238              snd_pcm_lib_preallocate_pages_for_all(pcm,
4239                                                    SNDRV_DMA_TYPE_DEV_SG,
4240                                                    snd_dma_pci_data(hdspm->pci),
4241                                                    wanted,
4242                                                    wanted);
4243         if (err < 0) {
4244                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
4245
4246                 return err;
4247         } else
4248                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
4249
4250         return 0;
4251 }
4252
4253 static void hdspm_set_sgbuf(struct hdspm * hdspm,
4254                             struct snd_pcm_substream *substream,
4255                              unsigned int reg, int channels)
4256 {
4257         int i;
4258         for (i = 0; i < (channels * 16); i++)
4259                 hdspm_write(hdspm, reg + 4 * i,
4260                             snd_pcm_sgbuf_get_addr(substream, 4096 * i));
4261 }
4262
4263 /* ------------- ALSA Devices ---------------------------- */
4264 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
4265                                           struct hdspm * hdspm)
4266 {
4267         struct snd_pcm *pcm;
4268         int err;
4269
4270         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
4271         if (err < 0)
4272                 return err;
4273
4274         hdspm->pcm = pcm;
4275         pcm->private_data = hdspm;
4276         strcpy(pcm->name, hdspm->card_name);
4277
4278         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
4279                         &snd_hdspm_playback_ops);
4280         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
4281                         &snd_hdspm_capture_ops);
4282
4283         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4284
4285         err = snd_hdspm_preallocate_memory(hdspm);
4286         if (err < 0)
4287                 return err;
4288
4289         return 0;
4290 }
4291
4292 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
4293 {
4294         snd_hdspm_flush_midi_input(hdspm, 0);
4295         snd_hdspm_flush_midi_input(hdspm, 1);
4296 }
4297
4298 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
4299                                                    struct hdspm * hdspm)
4300 {
4301         int err;
4302
4303         snd_printdd("Create card...\n");
4304         err = snd_hdspm_create_pcm(card, hdspm);
4305         if (err < 0)
4306                 return err;
4307
4308         err = snd_hdspm_create_midi(card, hdspm, 0);
4309         if (err < 0)
4310                 return err;
4311
4312         err = snd_hdspm_create_midi(card, hdspm, 1);
4313         if (err < 0)
4314                 return err;
4315
4316         err = snd_hdspm_create_controls(card, hdspm);
4317         if (err < 0)
4318                 return err;
4319
4320         err = snd_hdspm_create_hwdep(card, hdspm);
4321         if (err < 0)
4322                 return err;
4323
4324         snd_printdd("proc init...\n");
4325         snd_hdspm_proc_init(hdspm);
4326
4327         hdspm->system_sample_rate = -1;
4328         hdspm->last_external_sample_rate = -1;
4329         hdspm->last_internal_sample_rate = -1;
4330         hdspm->playback_pid = -1;
4331         hdspm->capture_pid = -1;
4332         hdspm->capture_substream = NULL;
4333         hdspm->playback_substream = NULL;
4334
4335         snd_printdd("Set defaults...\n");
4336         err = snd_hdspm_set_defaults(hdspm);
4337         if (err < 0)
4338                 return err;
4339
4340         snd_printdd("Update mixer controls...\n");
4341         hdspm_update_simple_mixer_controls(hdspm);
4342
4343         snd_printdd("Initializeing complete ???\n");
4344
4345         err = snd_card_register(card);
4346         if (err < 0) {
4347                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
4348                 return err;
4349         }
4350
4351         snd_printdd("... yes now\n");
4352
4353         return 0;
4354 }
4355
4356 static int __devinit snd_hdspm_create(struct snd_card *card,
4357                                       struct hdspm *hdspm,
4358                                       int precise_ptr, int enable_monitor)
4359 {
4360         struct pci_dev *pci = hdspm->pci;
4361         int err;
4362         unsigned long io_extent;
4363
4364         hdspm->irq = -1;
4365
4366         spin_lock_init(&hdspm->midi[0].lock);
4367         spin_lock_init(&hdspm->midi[1].lock);
4368
4369         hdspm->card = card;
4370
4371         spin_lock_init(&hdspm->lock);
4372
4373         tasklet_init(&hdspm->midi_tasklet,
4374                      hdspm_midi_tasklet, (unsigned long) hdspm);
4375
4376         pci_read_config_word(hdspm->pci,
4377                              PCI_CLASS_REVISION, &hdspm->firmware_rev);
4378
4379         hdspm->is_aes32 = (hdspm->firmware_rev >= HDSPM_AESREVISION);
4380
4381         strcpy(card->mixername, "Xilinx FPGA");
4382         if (hdspm->is_aes32) {
4383                 strcpy(card->driver, "HDSPAES32");
4384                 hdspm->card_name = "RME HDSPM AES32";
4385         } else {
4386                 strcpy(card->driver, "HDSPM");
4387                 hdspm->card_name = "RME HDSPM MADI";
4388         }
4389
4390         err = pci_enable_device(pci);
4391         if (err < 0)
4392                 return err;
4393
4394         pci_set_master(hdspm->pci);
4395
4396         err = pci_request_regions(pci, "hdspm");
4397         if (err < 0)
4398                 return err;
4399
4400         hdspm->port = pci_resource_start(pci, 0);
4401         io_extent = pci_resource_len(pci, 0);
4402
4403         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
4404                    hdspm->port, hdspm->port + io_extent - 1);
4405
4406
4407         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
4408         if (!hdspm->iobase) {
4409                 snd_printk(KERN_ERR "HDSPM: "
4410                            "unable to remap region 0x%lx-0x%lx\n",
4411                            hdspm->port, hdspm->port + io_extent - 1);
4412                 return -EBUSY;
4413         }
4414         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
4415                    (unsigned long)hdspm->iobase, hdspm->port,
4416                    hdspm->port + io_extent - 1);
4417
4418         if (request_irq(pci->irq, snd_hdspm_interrupt,
4419                         IRQF_SHARED, "hdspm", hdspm)) {
4420                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
4421                 return -EBUSY;
4422         }
4423
4424         snd_printdd("use IRQ %d\n", pci->irq);
4425
4426         hdspm->irq = pci->irq;
4427         hdspm->precise_ptr = precise_ptr;
4428
4429         hdspm->monitor_outs = enable_monitor;
4430
4431         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
4432                    sizeof(struct hdspm_mixer));
4433         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
4434         if (!hdspm->mixer) {
4435                 snd_printk(KERN_ERR "HDSPM: "
4436                            "unable to kmalloc Mixer memory of %d Bytes\n",
4437                            (int)sizeof(struct hdspm_mixer));
4438                 return err;
4439         }
4440
4441         hdspm->ss_channels = MADI_SS_CHANNELS;
4442         hdspm->ds_channels = MADI_DS_CHANNELS;
4443         hdspm->qs_channels = MADI_QS_CHANNELS;
4444
4445         snd_printdd("create alsa devices.\n");
4446         err = snd_hdspm_create_alsa_devices(card, hdspm);
4447         if (err < 0)
4448                 return err;
4449
4450         snd_hdspm_initialize_midi_flush(hdspm);
4451
4452         return 0;
4453 }
4454
4455 static int snd_hdspm_free(struct hdspm * hdspm)
4456 {
4457
4458         if (hdspm->port) {
4459
4460                 /* stop th audio, and cancel all interrupts */
4461                 hdspm->control_register &=
4462                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
4463                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable);
4464                 hdspm_write(hdspm, HDSPM_controlRegister,
4465                             hdspm->control_register);
4466         }
4467
4468         if (hdspm->irq >= 0)
4469                 free_irq(hdspm->irq, (void *) hdspm);
4470
4471         kfree(hdspm->mixer);
4472
4473         if (hdspm->iobase)
4474                 iounmap(hdspm->iobase);
4475
4476         if (hdspm->port)
4477                 pci_release_regions(hdspm->pci);
4478
4479         pci_disable_device(hdspm->pci);
4480         return 0;
4481 }
4482
4483 static void snd_hdspm_card_free(struct snd_card *card)
4484 {
4485         struct hdspm *hdspm = card->private_data;
4486
4487         if (hdspm)
4488                 snd_hdspm_free(hdspm);
4489 }
4490
4491 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
4492                                      const struct pci_device_id *pci_id)
4493 {
4494         static int dev;
4495         struct hdspm *hdspm;
4496         struct snd_card *card;
4497         int err;
4498
4499         if (dev >= SNDRV_CARDS)
4500                 return -ENODEV;
4501         if (!enable[dev]) {
4502                 dev++;
4503                 return -ENOENT;
4504         }
4505
4506         card = snd_card_new(index[dev], id[dev],
4507                             THIS_MODULE, sizeof(struct hdspm));
4508         if (!card)
4509                 return -ENOMEM;
4510
4511         hdspm = card->private_data;
4512         card->private_free = snd_hdspm_card_free;
4513         hdspm->dev = dev;
4514         hdspm->pci = pci;
4515
4516         snd_card_set_dev(card, &pci->dev);
4517
4518         err = snd_hdspm_create(card, hdspm, precise_ptr[dev],
4519                                enable_monitor[dev]);
4520         if (err < 0) {
4521                 snd_card_free(card);
4522                 return err;
4523         }
4524
4525         strcpy(card->shortname, "HDSPM MADI");
4526         sprintf(card->longname, "%s at 0x%lx, irq %d", hdspm->card_name,
4527                 hdspm->port, hdspm->irq);
4528
4529         err = snd_card_register(card);
4530         if (err < 0) {
4531                 snd_card_free(card);
4532                 return err;
4533         }
4534
4535         pci_set_drvdata(pci, card);
4536
4537         dev++;
4538         return 0;
4539 }
4540
4541 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
4542 {
4543         snd_card_free(pci_get_drvdata(pci));
4544         pci_set_drvdata(pci, NULL);
4545 }
4546
4547 static struct pci_driver driver = {
4548         .name = "RME Hammerfall DSP MADI",
4549         .id_table = snd_hdspm_ids,
4550         .probe = snd_hdspm_probe,
4551         .remove = __devexit_p(snd_hdspm_remove),
4552 };
4553
4554
4555 static int __init alsa_card_hdspm_init(void)
4556 {
4557         return pci_register_driver(&driver);
4558 }
4559
4560 static void __exit alsa_card_hdspm_exit(void)
4561 {
4562         pci_unregister_driver(&driver);
4563 }
4564
4565 module_init(alsa_card_hdspm_init)
4566 module_exit(alsa_card_hdspm_exit)