Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for...
[linux-2.6] / arch / mips / tx4938 / common / irq.c
1 /*
2  * linux/arch/mps/tx4938/common/irq.c
3  *
4  * Common tx4938 irq handler
5  * Copyright (C) 2000-2001 Toshiba Corporation
6  *
7  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8  * terms of the GNU General Public License version 2. This program is
9  * licensed "as is" without any warranty of any kind, whether express
10  * or implied.
11  *
12  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13  */
14 #include <linux/errno.h>
15 #include <linux/init.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/timex.h>
24 #include <linux/slab.h>
25 #include <linux/random.h>
26 #include <linux/irq.h>
27 #include <asm/bitops.h>
28 #include <asm/bootinfo.h>
29 #include <asm/io.h>
30 #include <asm/irq.h>
31 #include <asm/mipsregs.h>
32 #include <asm/system.h>
33 #include <asm/tx4938/rbtx4938.h>
34
35 /**********************************************************************************/
36 /* Forwad definitions for all pic's                                               */
37 /**********************************************************************************/
38
39 static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
40 static void tx4938_irq_cp0_shutdown(unsigned int irq);
41 static void tx4938_irq_cp0_enable(unsigned int irq);
42 static void tx4938_irq_cp0_disable(unsigned int irq);
43 static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
44 static void tx4938_irq_cp0_end(unsigned int irq);
45
46 static unsigned int tx4938_irq_pic_startup(unsigned int irq);
47 static void tx4938_irq_pic_shutdown(unsigned int irq);
48 static void tx4938_irq_pic_enable(unsigned int irq);
49 static void tx4938_irq_pic_disable(unsigned int irq);
50 static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
51 static void tx4938_irq_pic_end(unsigned int irq);
52
53 /**********************************************************************************/
54 /* Kernel structs for all pic's                                                   */
55 /**********************************************************************************/
56 DEFINE_SPINLOCK(tx4938_cp0_lock);
57 DEFINE_SPINLOCK(tx4938_pic_lock);
58
59 #define TX4938_CP0_NAME "TX4938-CP0"
60 static struct irq_chip tx4938_irq_cp0_type = {
61         .typename = TX4938_CP0_NAME,
62         .startup = tx4938_irq_cp0_startup,
63         .shutdown = tx4938_irq_cp0_shutdown,
64         .enable = tx4938_irq_cp0_enable,
65         .disable = tx4938_irq_cp0_disable,
66         .ack = tx4938_irq_cp0_mask_and_ack,
67         .end = tx4938_irq_cp0_end,
68         .set_affinity = NULL
69 };
70
71 #define TX4938_PIC_NAME "TX4938-PIC"
72 static struct irq_chip tx4938_irq_pic_type = {
73         .typename = TX4938_PIC_NAME,
74         .startup = tx4938_irq_pic_startup,
75         .shutdown = tx4938_irq_pic_shutdown,
76         .enable = tx4938_irq_pic_enable,
77         .disable = tx4938_irq_pic_disable,
78         .ack = tx4938_irq_pic_mask_and_ack,
79         .end = tx4938_irq_pic_end,
80         .set_affinity = NULL
81 };
82
83 static struct irqaction tx4938_irq_pic_action = {
84         .handler = no_action,
85         .flags = 0,
86         .mask = CPU_MASK_NONE,
87         .name = TX4938_PIC_NAME
88 };
89
90 /**********************************************************************************/
91 /* Functions for cp0                                                              */
92 /**********************************************************************************/
93
94 #define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
95
96 static void __init
97 tx4938_irq_cp0_init(void)
98 {
99         int i;
100
101         for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) {
102                 irq_desc[i].status = IRQ_DISABLED;
103                 irq_desc[i].action = 0;
104                 irq_desc[i].depth = 1;
105                 irq_desc[i].chip = &tx4938_irq_cp0_type;
106         }
107
108         return;
109 }
110
111 static unsigned int
112 tx4938_irq_cp0_startup(unsigned int irq)
113 {
114         tx4938_irq_cp0_enable(irq);
115
116         return (0);
117 }
118
119 static void
120 tx4938_irq_cp0_shutdown(unsigned int irq)
121 {
122         tx4938_irq_cp0_disable(irq);
123 }
124
125 static void
126 tx4938_irq_cp0_enable(unsigned int irq)
127 {
128         unsigned long flags;
129
130         spin_lock_irqsave(&tx4938_cp0_lock, flags);
131
132         set_c0_status(tx4938_irq_cp0_mask(irq));
133
134         spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
135 }
136
137 static void
138 tx4938_irq_cp0_disable(unsigned int irq)
139 {
140         unsigned long flags;
141
142         spin_lock_irqsave(&tx4938_cp0_lock, flags);
143
144         clear_c0_status(tx4938_irq_cp0_mask(irq));
145
146         spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
147
148         return;
149 }
150
151 static void
152 tx4938_irq_cp0_mask_and_ack(unsigned int irq)
153 {
154         tx4938_irq_cp0_disable(irq);
155
156         return;
157 }
158
159 static void
160 tx4938_irq_cp0_end(unsigned int irq)
161 {
162         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
163                 tx4938_irq_cp0_enable(irq);
164         }
165
166         return;
167 }
168
169 /**********************************************************************************/
170 /* Functions for pic                                                              */
171 /**********************************************************************************/
172
173 u32
174 tx4938_irq_pic_addr(int irq)
175 {
176         /* MVMCP -- need to formulize this */
177         irq -= TX4938_IRQ_PIC_BEG;
178
179         switch (irq) {
180         case 17:
181         case 16:
182         case 1:
183         case 0:{
184                         return (TX4938_MKA(TX4938_IRC_IRLVL0));
185                 }
186         case 19:
187         case 18:
188         case 3:
189         case 2:{
190                         return (TX4938_MKA(TX4938_IRC_IRLVL1));
191                 }
192         case 21:
193         case 20:
194         case 5:
195         case 4:{
196                         return (TX4938_MKA(TX4938_IRC_IRLVL2));
197                 }
198         case 23:
199         case 22:
200         case 7:
201         case 6:{
202                         return (TX4938_MKA(TX4938_IRC_IRLVL3));
203                 }
204         case 25:
205         case 24:
206         case 9:
207         case 8:{
208                         return (TX4938_MKA(TX4938_IRC_IRLVL4));
209                 }
210         case 27:
211         case 26:
212         case 11:
213         case 10:{
214                         return (TX4938_MKA(TX4938_IRC_IRLVL5));
215                 }
216         case 29:
217         case 28:
218         case 13:
219         case 12:{
220                         return (TX4938_MKA(TX4938_IRC_IRLVL6));
221                 }
222         case 31:
223         case 30:
224         case 15:
225         case 14:{
226                         return (TX4938_MKA(TX4938_IRC_IRLVL7));
227                 }
228         }
229
230         return (0);
231 }
232
233 u32
234 tx4938_irq_pic_mask(int irq)
235 {
236         /* MVMCP -- need to formulize this */
237         irq -= TX4938_IRQ_PIC_BEG;
238
239         switch (irq) {
240         case 31:
241         case 29:
242         case 27:
243         case 25:
244         case 23:
245         case 21:
246         case 19:
247         case 17:{
248                         return (0x07000000);
249                 }
250         case 30:
251         case 28:
252         case 26:
253         case 24:
254         case 22:
255         case 20:
256         case 18:
257         case 16:{
258                         return (0x00070000);
259                 }
260         case 15:
261         case 13:
262         case 11:
263         case 9:
264         case 7:
265         case 5:
266         case 3:
267         case 1:{
268                         return (0x00000700);
269                 }
270         case 14:
271         case 12:
272         case 10:
273         case 8:
274         case 6:
275         case 4:
276         case 2:
277         case 0:{
278                         return (0x00000007);
279                 }
280         }
281         return (0x00000000);
282 }
283
284 static void
285 tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
286 {
287         unsigned long val = 0;
288
289         val = TX4938_RD(pic_reg);
290         val &= (~clr_bits);
291         val |= (set_bits);
292         TX4938_WR(pic_reg, val);
293         mmiowb();
294         TX4938_RD(pic_reg);
295
296         return;
297 }
298
299 static void __init
300 tx4938_irq_pic_init(void)
301 {
302         unsigned long flags;
303         int i;
304
305         for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) {
306                 irq_desc[i].status = IRQ_DISABLED;
307                 irq_desc[i].action = 0;
308                 irq_desc[i].depth = 2;
309                 irq_desc[i].chip = &tx4938_irq_pic_type;
310         }
311
312         setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
313
314         spin_lock_irqsave(&tx4938_pic_lock, flags);
315
316         TX4938_WR(0xff1ff640, 0x6);     /* irq level mask -- only accept hightest */
317         TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1);     /* irq enable */
318
319         spin_unlock_irqrestore(&tx4938_pic_lock, flags);
320
321         return;
322 }
323
324 static unsigned int
325 tx4938_irq_pic_startup(unsigned int irq)
326 {
327         tx4938_irq_pic_enable(irq);
328
329         return (0);
330 }
331
332 static void
333 tx4938_irq_pic_shutdown(unsigned int irq)
334 {
335         tx4938_irq_pic_disable(irq);
336
337         return;
338 }
339
340 static void
341 tx4938_irq_pic_enable(unsigned int irq)
342 {
343         unsigned long flags;
344
345         spin_lock_irqsave(&tx4938_pic_lock, flags);
346
347         tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
348                               tx4938_irq_pic_mask(irq));
349
350         spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351
352         return;
353 }
354
355 static void
356 tx4938_irq_pic_disable(unsigned int irq)
357 {
358         unsigned long flags;
359
360         spin_lock_irqsave(&tx4938_pic_lock, flags);
361
362         tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
363                               tx4938_irq_pic_mask(irq), 0);
364
365         spin_unlock_irqrestore(&tx4938_pic_lock, flags);
366
367         return;
368 }
369
370 static void
371 tx4938_irq_pic_mask_and_ack(unsigned int irq)
372 {
373         tx4938_irq_pic_disable(irq);
374
375         return;
376 }
377
378 static void
379 tx4938_irq_pic_end(unsigned int irq)
380 {
381         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
382                 tx4938_irq_pic_enable(irq);
383         }
384
385         return;
386 }
387
388 /**********************************************************************************/
389 /* Main init functions                                                            */
390 /**********************************************************************************/
391
392 void __init
393 tx4938_irq_init(void)
394 {
395         tx4938_irq_cp0_init();
396         tx4938_irq_pic_init();
397
398         return;
399 }
400
401 int
402 tx4938_irq_nested(void)
403 {
404         int sw_irq = 0;
405         u32 level2;
406
407         level2 = TX4938_RD(0xff1ff6a0);
408         if ((level2 & 0x10000) == 0) {
409                 level2 &= 0x1f;
410                 sw_irq = TX4938_IRQ_PIC_BEG + level2;
411                 if (sw_irq == 26) {
412                         {
413                                 extern int toshiba_rbtx4938_irq_nested(int sw_irq);
414                                 sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
415                         }
416                 }
417         }
418
419         wbflush();
420         return (sw_irq);
421 }
422
423 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
424 {
425         unsigned int pending = read_c0_cause() & read_c0_status();
426
427         if (pending & STATUSF_IP7)
428                 do_IRQ(TX4938_IRQ_CPU_TIMER, regs);
429         else if (pending & STATUSF_IP2) {
430                 int irq = tx4938_irq_nested();
431                 if (irq)
432                         do_IRQ(irq, regs);
433                 else
434                         spurious_interrupt(regs);
435         } else if (pending & STATUSF_IP1)
436                 do_IRQ(TX4938_IRQ_USER1, regs);
437         else if (pending & STATUSF_IP0)
438                 do_IRQ(TX4938_IRQ_USER0, regs);
439 }