2 * Sonics Silicon Backplane
3 * Broadcom Gigabit Ethernet core driver
5 * Copyright 2008, Broadcom Corporation
6 * Copyright 2008, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_driver_gige.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
18 MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
19 MODULE_AUTHOR("Michael Buesch");
20 MODULE_LICENSE("GPL");
23 static const struct ssb_device_id ssb_gige_tbl[] = {
24 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
27 /* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
30 static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
32 return ssb_read8(dev->dev, offset);
35 static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
37 return ssb_read16(dev->dev, offset);
40 static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
42 return ssb_read32(dev->dev, offset);
45 static inline void gige_write8(struct ssb_gige *dev,
48 ssb_write8(dev->dev, offset, value);
51 static inline void gige_write16(struct ssb_gige *dev,
52 u16 offset, u16 value)
54 ssb_write16(dev->dev, offset, value);
57 static inline void gige_write32(struct ssb_gige *dev,
58 u16 offset, u32 value)
60 ssb_write32(dev->dev, offset, value);
64 u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
66 BUG_ON(offset >= 256);
67 return gige_read8(dev, SSB_GIGE_PCICFG + offset);
71 u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
73 BUG_ON(offset >= 256);
74 return gige_read16(dev, SSB_GIGE_PCICFG + offset);
78 u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
80 BUG_ON(offset >= 256);
81 return gige_read32(dev, SSB_GIGE_PCICFG + offset);
85 void gige_pcicfg_write8(struct ssb_gige *dev,
86 unsigned int offset, u8 value)
88 BUG_ON(offset >= 256);
89 gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
93 void gige_pcicfg_write16(struct ssb_gige *dev,
94 unsigned int offset, u16 value)
96 BUG_ON(offset >= 256);
97 gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
101 void gige_pcicfg_write32(struct ssb_gige *dev,
102 unsigned int offset, u32 value)
104 BUG_ON(offset >= 256);
105 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
108 static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
109 int reg, int size, u32 *val)
111 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
114 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
115 return PCIBIOS_DEVICE_NOT_FOUND;
117 return PCIBIOS_DEVICE_NOT_FOUND;
119 spin_lock_irqsave(&dev->lock, flags);
122 *val = gige_pcicfg_read8(dev, reg);
125 *val = gige_pcicfg_read16(dev, reg);
128 *val = gige_pcicfg_read32(dev, reg);
133 spin_unlock_irqrestore(&dev->lock, flags);
135 return PCIBIOS_SUCCESSFUL;
138 static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
139 int reg, int size, u32 val)
141 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
144 if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
145 return PCIBIOS_DEVICE_NOT_FOUND;
147 return PCIBIOS_DEVICE_NOT_FOUND;
149 spin_lock_irqsave(&dev->lock, flags);
152 gige_pcicfg_write8(dev, reg, val);
155 gige_pcicfg_write16(dev, reg, val);
158 gige_pcicfg_write32(dev, reg, val);
163 spin_unlock_irqrestore(&dev->lock, flags);
165 return PCIBIOS_SUCCESSFUL;
168 static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
170 struct ssb_gige *dev;
171 u32 base, tmslow, tmshigh;
173 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
178 spin_lock_init(&dev->lock);
179 dev->pci_controller.pci_ops = &dev->pci_ops;
180 dev->pci_controller.io_resource = &dev->io_resource;
181 dev->pci_controller.mem_resource = &dev->mem_resource;
182 dev->pci_controller.io_map_base = 0x800;
183 dev->pci_ops.read = ssb_gige_pci_read_config;
184 dev->pci_ops.write = ssb_gige_pci_write_config;
186 dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
187 dev->io_resource.start = 0x800;
188 dev->io_resource.end = 0x8FF;
189 dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
191 if (!ssb_device_is_enabled(sdev))
192 ssb_device_enable(sdev, 0);
194 /* Setup BAR0. This is a 64k MMIO region. */
195 base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
196 gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
197 gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
199 dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
200 dev->mem_resource.start = base;
201 dev->mem_resource.end = base + 0x10000 - 1;
202 dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
204 /* Enable the memory region. */
205 gige_pcicfg_write16(dev, PCI_COMMAND,
206 gige_pcicfg_read16(dev, PCI_COMMAND)
207 | PCI_COMMAND_MEMORY);
209 /* Write flushing is controlled by the Flush Status Control register.
210 * We want to flush every register write with a timeout and we want
211 * to disable the IRQ mask while flushing to avoid concurrency.
212 * Note that automatic write flushing does _not_ work from
213 * an IRQ handler. The driver must flush manually by reading a register.
215 gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
217 /* Check if we have an RGMII or GMII PHY-bus.
218 * On RGMII do not bypass the DLLs */
219 tmslow = ssb_read32(sdev, SSB_TMSLOW);
220 tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
221 if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
222 tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
223 tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
226 tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
227 tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
230 tmslow |= SSB_GIGE_TMSLOW_DLLEN;
231 ssb_write32(sdev, SSB_TMSLOW, tmslow);
233 ssb_set_drvdata(sdev, dev);
234 register_pci_controller(&dev->pci_controller);
239 bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
241 if (!pdev->resource[0].name)
243 return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
245 EXPORT_SYMBOL(pdev_is_ssb_gige_core);
247 int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
248 struct pci_dev *pdev)
250 struct ssb_gige *dev = ssb_get_drvdata(sdev);
251 struct resource *res;
253 if (pdev->bus->ops != &dev->pci_ops) {
254 /* The PCI device is not on this SSB GigE bridge device. */
258 /* Fixup the PCI resources. */
259 res = &(pdev->resource[0]);
260 res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
261 res->name = dev->mem_resource.name;
262 res->start = dev->mem_resource.start;
263 res->end = dev->mem_resource.end;
265 /* Fixup interrupt lines. */
266 pdev->irq = ssb_mips_irq(sdev) + 2;
267 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
272 int ssb_gige_map_irq(struct ssb_device *sdev,
273 const struct pci_dev *pdev)
275 struct ssb_gige *dev = ssb_get_drvdata(sdev);
277 if (pdev->bus->ops != &dev->pci_ops) {
278 /* The PCI device is not on this SSB GigE bridge device. */
282 return ssb_mips_irq(sdev) + 2;
285 static struct ssb_driver ssb_gige_driver = {
287 .id_table = ssb_gige_tbl,
288 .probe = ssb_gige_probe,
291 int ssb_gige_init(void)
293 return ssb_driver_register(&ssb_gige_driver);