2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/trident.h>
27 #define VERSION "0.7.9-NEWAPI"
29 struct tridentfb_par {
30 void __iomem *io_virt; /* iospace virtual memory address */
34 void (*init_accel) (struct tridentfb_par *, int, int);
35 void (*wait_engine) (struct tridentfb_par *);
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
39 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
42 static unsigned char eng_oper; /* engine operation... */
43 static struct fb_ops tridentfb_ops;
45 static struct fb_fix_screeninfo tridentfb_fix = {
47 .type = FB_TYPE_PACKED_PIXELS,
49 .visual = FB_VISUAL_PSEUDOCOLOR,
50 .accel = FB_ACCEL_NONE,
53 /* defaults which are normally overriden by user values */
56 static char *mode_option __devinitdata = "640x480";
57 static int bpp __devinitdata = 8;
59 static int noaccel __devinitdata;
64 static int fp __devinitdata;
65 static int crt __devinitdata;
67 static int memsize __devinitdata;
68 static int memdiff __devinitdata;
71 module_param(mode_option, charp, 0);
72 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
73 module_param_named(mode, mode_option, charp, 0);
74 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
75 module_param(bpp, int, 0);
76 module_param(center, int, 0);
77 module_param(stretch, int, 0);
78 module_param(noaccel, int, 0);
79 module_param(memsize, int, 0);
80 module_param(memdiff, int, 0);
81 module_param(nativex, int, 0);
82 module_param(fp, int, 0);
83 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
84 module_param(crt, int, 0);
85 MODULE_PARM_DESC(crt, "Define if CRT is connected");
87 static int is_blade(int id)
89 return (id == BLADE3D) ||
90 (id == CYBERBLADEE4) ||
91 (id == CYBERBLADEi7) ||
92 (id == CYBERBLADEi7D) ||
93 (id == CYBERBLADEi1) ||
94 (id == CYBERBLADEi1D) ||
95 (id == CYBERBLADEAi1) ||
96 (id == CYBERBLADEAi1D);
99 static int is_xp(int id)
101 return (id == CYBERBLADEXPAi1) ||
102 (id == CYBERBLADEXPm8) ||
103 (id == CYBERBLADEXPm16);
106 static int is3Dchip(int id)
108 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
109 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
110 (id == CYBER9397) || (id == CYBER9397DVD) ||
111 (id == CYBER9520) || (id == CYBER9525DVD) ||
112 (id == IMAGE975) || (id == IMAGE985) ||
113 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
114 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
115 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
116 (id == CYBERBLADEXPAi1));
119 static int iscyber(int id)
135 case CYBERBLADEXPAi1:
143 case CYBERBLADEi7: /* VIA MPV4 integrated version */
146 /* case CYBERBLDAEXPm8: Strange */
147 /* case CYBERBLDAEXPm16: Strange */
152 #define CRT 0x3D0 /* CRTC registers offset for color display */
154 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
156 fb_writeb(val, p->io_virt + reg);
159 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
161 return fb_readb(p->io_virt + reg);
164 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
166 fb_writel(v, par->io_virt + r);
169 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
171 return fb_readl(par->io_virt + r);
175 * Blade specific acceleration.
178 #define point(x, y) ((y) << 16 | (x))
190 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
192 int v1 = (pitch >> 3) << 20;
209 v2 = v1 | (tmp << 29);
210 writemmr(par, 0x21C0, v2);
211 writemmr(par, 0x21C4, v2);
212 writemmr(par, 0x21B8, v2);
213 writemmr(par, 0x21BC, v2);
214 writemmr(par, 0x21D0, v1);
215 writemmr(par, 0x21D4, v1);
216 writemmr(par, 0x21C8, v1);
217 writemmr(par, 0x21CC, v1);
218 writemmr(par, 0x216C, 0);
221 static void blade_wait_engine(struct tridentfb_par *par)
223 while (readmmr(par, STA) & 0xFA800000) ;
226 static void blade_fill_rect(struct tridentfb_par *par,
227 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
229 writemmr(par, CLR, c);
230 writemmr(par, ROP, rop ? 0x66 : ROP_S);
231 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
233 writemmr(par, DR1, point(x, y));
234 writemmr(par, DR2, point(x + w - 1, y + h - 1));
237 static void blade_copy_rect(struct tridentfb_par *par,
238 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
243 s2 = point(x1 + w - 1, y1 + h - 1);
245 d2 = point(x2 + w - 1, y2 + h - 1);
247 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
250 writemmr(par, ROP, ROP_S);
251 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
253 writemmr(par, SR1, direction ? s2 : s1);
254 writemmr(par, SR2, direction ? s1 : s2);
255 writemmr(par, DR1, direction ? d2 : d1);
256 writemmr(par, DR2, direction ? d1 : d2);
260 * BladeXP specific acceleration functions
264 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
266 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
286 switch (pitch << (bpp >> 3)) {
302 t_outb(par, x, 0x2125);
322 writemmr(par, 0x2154, v1);
323 writemmr(par, 0x2150, v1);
324 t_outb(par, 3, 0x2126);
327 static void xp_wait_engine(struct tridentfb_par *par)
335 busy = t_inb(par, STA) & 0x80;
339 if (count == 10000000) {
345 t_outb(par, 0x00, 0x2120);
352 static void xp_fill_rect(struct tridentfb_par *par,
353 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
355 writemmr(par, 0x2127, ROP_P);
356 writemmr(par, 0x2158, c);
357 writemmr(par, 0x2128, 0x4000);
358 writemmr(par, 0x2140, masked_point(h, w));
359 writemmr(par, 0x2138, masked_point(y, x));
360 t_outb(par, 0x01, 0x2124);
361 t_outb(par, eng_oper, 0x2125);
364 static void xp_copy_rect(struct tridentfb_par *par,
365 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
368 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
372 if ((x1 < x2) && (y1 == y2)) {
390 writemmr(par, 0x2128, direction);
391 t_outb(par, ROP_S, 0x2127);
392 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
393 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
394 writemmr(par, 0x2140, masked_point(h, w));
395 t_outb(par, 0x01, 0x2124);
399 * Image specific acceleration functions
401 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
419 writemmr(par, 0x2120, 0xF0000000);
420 writemmr(par, 0x2120, 0x40000000 | tmp);
421 writemmr(par, 0x2120, 0x80000000);
422 writemmr(par, 0x2144, 0x00000000);
423 writemmr(par, 0x2148, 0x00000000);
424 writemmr(par, 0x2150, 0x00000000);
425 writemmr(par, 0x2154, 0x00000000);
426 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
427 writemmr(par, 0x216C, 0x00000000);
428 writemmr(par, 0x2170, 0x00000000);
429 writemmr(par, 0x217C, 0x00000000);
430 writemmr(par, 0x2120, 0x10000000);
431 writemmr(par, 0x2130, (2047 << 16) | 2047);
434 static void image_wait_engine(struct tridentfb_par *par)
436 while (readmmr(par, 0x2164) & 0xF0000000) ;
439 static void image_fill_rect(struct tridentfb_par *par,
440 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
442 writemmr(par, 0x2120, 0x80000000);
443 writemmr(par, 0x2120, 0x90000000 | ROP_S);
445 writemmr(par, 0x2144, c);
447 writemmr(par, DR1, point(x, y));
448 writemmr(par, DR2, point(x + w - 1, y + h - 1));
450 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
453 static void image_copy_rect(struct tridentfb_par *par,
454 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
459 s2 = point(x1 + w - 1, y1 + h - 1);
461 d2 = point(x2 + w - 1, y2 + h - 1);
463 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
466 writemmr(par, 0x2120, 0x80000000);
467 writemmr(par, 0x2120, 0x90000000 | ROP_S);
469 writemmr(par, SR1, direction ? s2 : s1);
470 writemmr(par, SR2, direction ? s1 : s2);
471 writemmr(par, DR1, direction ? d2 : d1);
472 writemmr(par, DR2, direction ? d1 : d2);
473 writemmr(par, 0x2124,
474 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
478 * Accel functions called by the upper layers
480 #ifdef CONFIG_FB_TRIDENT_ACCEL
481 static void tridentfb_fillrect(struct fb_info *info,
482 const struct fb_fillrect *fr)
484 struct tridentfb_par *par = info->par;
485 int bpp = info->var.bits_per_pixel;
496 col = ((u32 *)(info->pseudo_palette))[fr->color];
499 col = ((u32 *)(info->pseudo_palette))[fr->color];
503 par->fill_rect(par, fr->dx, fr->dy, fr->width,
504 fr->height, col, fr->rop);
505 par->wait_engine(par);
507 static void tridentfb_copyarea(struct fb_info *info,
508 const struct fb_copyarea *ca)
510 struct tridentfb_par *par = info->par;
512 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
513 ca->width, ca->height);
514 par->wait_engine(par);
516 #else /* !CONFIG_FB_TRIDENT_ACCEL */
517 #define tridentfb_fillrect cfb_fillrect
518 #define tridentfb_copyarea cfb_copyarea
519 #endif /* CONFIG_FB_TRIDENT_ACCEL */
523 * Hardware access functions
526 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
528 writeb(reg, par->io_virt + CRT + 4);
529 return readb(par->io_virt + CRT + 5);
532 static inline void write3X4(struct tridentfb_par *par, int reg,
535 writeb(reg, par->io_virt + CRT + 4);
536 writeb(val, par->io_virt + CRT + 5);
539 static inline unsigned char read3C4(struct tridentfb_par *par, int reg)
541 t_outb(par, reg, 0x3C4);
542 return t_inb(par, 0x3C5);
545 static inline void write3C4(struct tridentfb_par *par, int reg,
548 t_outb(par, reg, 0x3C4);
549 t_outb(par, val, 0x3C5);
552 static inline unsigned char read3CE(struct tridentfb_par *par, int reg)
554 t_outb(par, reg, 0x3CE);
555 return t_inb(par, 0x3CF);
558 static inline void writeAttr(struct tridentfb_par *par, int reg,
561 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
562 t_outb(par, reg, 0x3C0);
563 t_outb(par, val, 0x3C0);
566 static inline void write3CE(struct tridentfb_par *par, int reg,
569 t_outb(par, reg, 0x3CE);
570 t_outb(par, val, 0x3CF);
573 static void enable_mmio(void)
579 /* Unprotect registers */
580 outb(NewMode1, 0x3C4);
585 outb(inb(0x3D5) | 0x01, 0x3D5);
588 static void disable_mmio(struct tridentfb_par *par)
591 t_outb(par, 0x0B, 0x3C4);
594 /* Unprotect registers */
595 t_outb(par, NewMode1, 0x3C4);
596 t_outb(par, 0x80, 0x3C5);
599 t_outb(par, PCIReg, 0x3D4);
600 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
603 static void crtc_unlock(struct tridentfb_par *par)
605 write3X4(par, CRTVSyncEnd, read3X4(par, CRTVSyncEnd) & 0x7F);
608 /* Return flat panel's maximum x resolution */
609 static int __devinit get_nativex(struct tridentfb_par *par)
616 tmp = (read3CE(par, VertStretch) >> 4) & 3;
637 output("%dx%d flat panel found\n", x, y);
642 static void set_lwidth(struct tridentfb_par *par, int width)
644 write3X4(par, Offset, width & 0xFF);
645 write3X4(par, AddColReg,
646 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
649 /* For resolutions smaller than FP resolution stretch */
650 static void screen_stretch(struct tridentfb_par *par)
652 if (par->chip_id != CYBERBLADEXPAi1)
653 write3CE(par, BiosReg, 0);
655 write3CE(par, BiosReg, 8);
656 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
657 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
660 /* For resolutions smaller than FP resolution center */
661 static void screen_center(struct tridentfb_par *par)
663 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
664 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
667 /* Address of first shown pixel in display memory */
668 static void set_screen_start(struct tridentfb_par *par, int base)
671 write3X4(par, StartAddrLow, base & 0xFF);
672 write3X4(par, StartAddrHigh, (base & 0xFF00) >> 8);
673 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
674 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
675 tmp = read3X4(par, CRTHiOrd) & 0xF8;
676 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
679 /* Set dotclock frequency */
680 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
683 unsigned long f, fi, d, di;
684 unsigned char lo = 0, hi = 0;
687 for (k = 2; k >= 0; k--)
688 for (m = 0; m < 63; m++)
689 for (n = 0; n < 128; n++) {
690 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
691 if ((di = abs(fi - freq)) < d) {
700 if (is3Dchip(par->chip_id)) {
701 write3C4(par, ClockHigh, hi);
702 write3C4(par, ClockLow, lo);
707 debug("VCLK = %X %X\n", hi, lo);
710 /* Set number of lines for flat panels*/
711 static void set_number_of_lines(struct tridentfb_par *par, int lines)
713 int tmp = read3CE(par, CyberEnhance) & 0x8F;
716 else if (lines > 768)
718 else if (lines > 600)
720 else if (lines > 480)
722 write3CE(par, CyberEnhance, tmp);
726 * If we see that FP is active we assume we have one.
727 * Otherwise we have a CRT display. User can override.
729 static int __devinit is_flatpanel(struct tridentfb_par *par)
733 if (crt || !iscyber(par->chip_id))
735 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
738 /* Try detecting the video memory size */
739 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
741 unsigned char tmp, tmp2;
744 /* If memory size provided by user */
748 switch (par->chip_id) {
753 tmp = read3X4(par, SPR) & 0x0F;
769 k = 10 * Mb; /* XP */
775 k = 12 * Mb; /* XP */
778 k = 14 * Mb; /* XP */
781 k = 16 * Mb; /* XP */
785 tmp2 = read3C4(par, 0xC1);
815 output("framebuffer size = %d Kb\n", k / Kb);
819 /* See if we can handle the video mode described in var */
820 static int tridentfb_check_var(struct fb_var_screeninfo *var,
821 struct fb_info *info)
823 struct tridentfb_par *par = info->par;
824 int bpp = var->bits_per_pixel;
827 /* check color depth */
829 bpp = var->bits_per_pixel = 32;
830 /* check whether resolution fits on panel and in memory */
831 if (par->flatpanel && nativex && var->xres > nativex)
833 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
839 var->green.offset = 0;
840 var->blue.offset = 0;
842 var->green.length = 6;
843 var->blue.length = 6;
846 var->red.offset = 11;
847 var->green.offset = 5;
848 var->blue.offset = 0;
850 var->green.length = 6;
851 var->blue.length = 5;
854 var->red.offset = 16;
855 var->green.offset = 8;
856 var->blue.offset = 0;
858 var->green.length = 8;
859 var->blue.length = 8;
870 /* Pan the display */
871 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
872 struct fb_info *info)
874 struct tridentfb_par *par = info->par;
878 offset = (var->xoffset + (var->yoffset * var->xres))
879 * var->bits_per_pixel / 32;
880 info->var.xoffset = var->xoffset;
881 info->var.yoffset = var->yoffset;
882 set_screen_start(par, offset);
887 static void shadowmode_on(struct tridentfb_par *par)
889 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
892 static void shadowmode_off(struct tridentfb_par *par)
894 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
897 /* Set the hardware to the requested video mode */
898 static int tridentfb_set_par(struct fb_info *info)
900 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
901 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
902 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
903 struct fb_var_screeninfo *var = &info->var;
904 int bpp = var->bits_per_pixel;
909 hdispend = var->xres / 8 - 1;
910 hsyncstart = (var->xres + var->right_margin) / 8;
911 hsyncend = var->hsync_len / 8;
913 (var->xres + var->left_margin + var->right_margin +
914 var->hsync_len) / 8 - 10;
915 hblankstart = hdispend + 1;
916 hblankend = htotal + 5;
918 vdispend = var->yres - 1;
919 vsyncstart = var->yres + var->lower_margin;
920 vsyncend = var->vsync_len;
921 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
922 vblankstart = var->yres;
923 vblankend = vtotal + 2;
926 write3CE(par, CyberControl, 8);
928 if (par->flatpanel && var->xres < nativex) {
930 * on flat panels with native size larger
931 * than requested resolution decide whether
932 * we stretch or center
934 t_outb(par, 0xEB, 0x3C2);
944 t_outb(par, 0x2B, 0x3C2);
945 write3CE(par, CyberControl, 8);
948 /* vertical timing values */
949 write3X4(par, CRTVTotal, vtotal & 0xFF);
950 write3X4(par, CRTVDispEnd, vdispend & 0xFF);
951 write3X4(par, CRTVSyncStart, vsyncstart & 0xFF);
952 write3X4(par, CRTVSyncEnd, (vsyncend & 0x0F));
953 write3X4(par, CRTVBlankStart, vblankstart & 0xFF);
954 write3X4(par, CRTVBlankEnd, 0 /* p->vblankend & 0xFF */);
956 /* horizontal timing values */
957 write3X4(par, CRTHTotal, htotal & 0xFF);
958 write3X4(par, CRTHDispEnd, hdispend & 0xFF);
959 write3X4(par, CRTHSyncStart, hsyncstart & 0xFF);
960 write3X4(par, CRTHSyncEnd,
961 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
962 write3X4(par, CRTHBlankStart, hblankstart & 0xFF);
963 write3X4(par, CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */);
965 /* higher bits of vertical timing values */
967 if (vtotal & 0x100) tmp |= 0x01;
968 if (vdispend & 0x100) tmp |= 0x02;
969 if (vsyncstart & 0x100) tmp |= 0x04;
970 if (vblankstart & 0x100) tmp |= 0x08;
972 if (vtotal & 0x200) tmp |= 0x20;
973 if (vdispend & 0x200) tmp |= 0x40;
974 if (vsyncstart & 0x200) tmp |= 0x80;
975 write3X4(par, CRTOverflow, tmp);
977 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
978 if (vtotal & 0x400) tmp |= 0x80;
979 if (vblankstart & 0x400) tmp |= 0x40;
980 if (vsyncstart & 0x400) tmp |= 0x20;
981 if (vdispend & 0x400) tmp |= 0x10;
982 write3X4(par, CRTHiOrd, tmp);
985 if (htotal & 0x800) tmp |= 0x800 >> 11;
986 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
987 write3X4(par, HorizOverflow, tmp);
990 if (vblankstart & 0x200) tmp |= 0x20;
991 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
992 write3X4(par, CRTMaxScanLine, tmp);
994 write3X4(par, CRTLineCompare, 0xFF);
995 write3X4(par, CRTPRowScan, 0);
996 write3X4(par, CRTModeControl, 0xC3);
998 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1000 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1001 /* enable access extended memory */
1002 write3X4(par, CRTCModuleTest, tmp);
1004 /* enable GE for text acceleration */
1005 write3X4(par, GraphEngReg, 0x80);
1007 #ifdef CONFIG_FB_TRIDENT_ACCEL
1008 par->init_accel(par, info->var.xres, bpp);
1026 write3X4(par, PixelBusReg, tmp);
1029 if (iscyber(par->chip_id))
1031 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1033 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1034 write3X4(par, Performance, 0x92);
1035 /* MMIO & PCI read and write burst enable */
1036 write3X4(par, PCIReg, 0x07);
1038 /* convert from picoseconds to kHz */
1039 vclk = PICOS2KHZ(info->var.pixclock);
1042 set_vclk(par, vclk);
1044 write3C4(par, 0, 3);
1045 write3C4(par, 1, 1); /* set char clock 8 dots wide */
1046 /* enable 4 maps because needed in chain4 mode */
1047 write3C4(par, 2, 0x0F);
1048 write3C4(par, 3, 0);
1049 write3C4(par, 4, 0x0E); /* memory mode enable bitmaps ?? */
1051 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1052 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1053 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1054 write3CE(par, 0x6, 0x05); /* graphics mode */
1055 write3CE(par, 0x7, 0x0F); /* planes? */
1057 if (par->chip_id == CYBERBLADEXPAi1) {
1058 /* This fixes snow-effect in 32 bpp */
1059 write3X4(par, CRTHSyncStart, 0x84);
1062 /* graphics mode and support 256 color modes */
1063 writeAttr(par, 0x10, 0x41);
1064 writeAttr(par, 0x12, 0x0F); /* planes */
1065 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1068 for (tmp = 0; tmp < 0x10; tmp++)
1069 writeAttr(par, tmp, tmp);
1070 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1071 t_outb(par, 0x20, 0x3C0); /* enable attr */
1094 t_outb(par, tmp, 0x3C6);
1098 set_number_of_lines(par, info->var.yres);
1099 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1100 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1101 info->fix.line_length = info->var.xres * (bpp >> 3);
1102 info->cmap.len = (bpp == 8) ? 256 : 16;
1107 /* Set one color register */
1108 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1109 unsigned blue, unsigned transp,
1110 struct fb_info *info)
1112 int bpp = info->var.bits_per_pixel;
1113 struct tridentfb_par *par = info->par;
1115 if (regno >= info->cmap.len)
1119 t_outb(par, 0xFF, 0x3C6);
1120 t_outb(par, regno, 0x3C8);
1122 t_outb(par, red >> 10, 0x3C9);
1123 t_outb(par, green >> 10, 0x3C9);
1124 t_outb(par, blue >> 10, 0x3C9);
1126 } else if (regno < 16) {
1127 if (bpp == 16) { /* RGB 565 */
1130 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1131 ((blue & 0xF800) >> 11);
1133 ((u32 *)(info->pseudo_palette))[regno] = col;
1134 } else if (bpp == 32) /* ARGB 8888 */
1135 ((u32*)info->pseudo_palette)[regno] =
1136 ((transp & 0xFF00) << 16) |
1137 ((red & 0xFF00) << 8) |
1138 ((green & 0xFF00)) |
1139 ((blue & 0xFF00) >> 8);
1142 /* debug("exit\n"); */
1146 /* Try blanking the screen.For flat panels it does nothing */
1147 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1149 unsigned char PMCont, DPMSCont;
1150 struct tridentfb_par *par = info->par;
1155 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1156 PMCont = t_inb(par, 0x83C6) & 0xFC;
1157 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1158 switch (blank_mode) {
1159 case FB_BLANK_UNBLANK:
1160 /* Screen: On, HSync: On, VSync: On */
1161 case FB_BLANK_NORMAL:
1162 /* Screen: Off, HSync: On, VSync: On */
1166 case FB_BLANK_HSYNC_SUSPEND:
1167 /* Screen: Off, HSync: Off, VSync: On */
1171 case FB_BLANK_VSYNC_SUSPEND:
1172 /* Screen: Off, HSync: On, VSync: Off */
1176 case FB_BLANK_POWERDOWN:
1177 /* Screen: Off, HSync: Off, VSync: Off */
1183 write3CE(par, PowerStatus, DPMSCont);
1184 t_outb(par, 4, 0x83C8);
1185 t_outb(par, PMCont, 0x83C6);
1189 /* let fbcon do a softblank for us */
1190 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1193 static struct fb_ops tridentfb_ops = {
1194 .owner = THIS_MODULE,
1195 .fb_setcolreg = tridentfb_setcolreg,
1196 .fb_pan_display = tridentfb_pan_display,
1197 .fb_blank = tridentfb_blank,
1198 .fb_check_var = tridentfb_check_var,
1199 .fb_set_par = tridentfb_set_par,
1200 .fb_fillrect = tridentfb_fillrect,
1201 .fb_copyarea = tridentfb_copyarea,
1202 .fb_imageblit = cfb_imageblit,
1205 static int __devinit trident_pci_probe(struct pci_dev *dev,
1206 const struct pci_device_id *id)
1209 unsigned char revision;
1210 struct fb_info *info;
1211 struct tridentfb_par *default_par;
1216 err = pci_enable_device(dev);
1220 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1223 default_par = info->par;
1225 chip_id = id->device;
1227 if (chip_id == CYBERBLADEi1)
1228 output("*** Please do use cyblafb, Cyberblade/i1 support "
1229 "will soon be removed from tridentfb!\n");
1232 /* If PCI id is 0x9660 then further detect chip type */
1234 if (chip_id == TGUI9660) {
1235 outb(RevisionID, 0x3C4);
1236 revision = inb(0x3C5);
1241 chip_id = CYBER9397;
1244 chip_id = CYBER9397DVD;
1253 chip_id = CYBER9385;
1256 chip_id = CYBER9382;
1259 chip_id = CYBER9388;
1266 chip3D = is3Dchip(chip_id);
1268 if (is_xp(chip_id)) {
1269 default_par->init_accel = xp_init_accel;
1270 default_par->wait_engine = xp_wait_engine;
1271 default_par->fill_rect = xp_fill_rect;
1272 default_par->copy_rect = xp_copy_rect;
1273 } else if (is_blade(chip_id)) {
1274 default_par->init_accel = blade_init_accel;
1275 default_par->wait_engine = blade_wait_engine;
1276 default_par->fill_rect = blade_fill_rect;
1277 default_par->copy_rect = blade_copy_rect;
1279 default_par->init_accel = image_init_accel;
1280 default_par->wait_engine = image_wait_engine;
1281 default_par->fill_rect = image_fill_rect;
1282 default_par->copy_rect = image_copy_rect;
1285 default_par->chip_id = chip_id;
1287 /* acceleration is on by default for 3D chips */
1288 defaultaccel = chip3D && !noaccel;
1290 /* setup MMIO region */
1291 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1292 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1294 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1295 debug("request_region failed!\n");
1299 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1300 tridentfb_fix.mmio_len);
1302 if (!default_par->io_virt) {
1303 debug("ioremap failed\n");
1310 /* setup framebuffer memory */
1311 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1312 tridentfb_fix.smem_len = get_memsize(default_par);
1314 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1315 debug("request_mem_region failed!\n");
1316 disable_mmio(info->par);
1321 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1322 tridentfb_fix.smem_len);
1324 if (!info->screen_base) {
1325 debug("ioremap failed\n");
1330 output("%s board found\n", pci_name(dev));
1331 default_par->flatpanel = is_flatpanel(default_par);
1333 if (default_par->flatpanel)
1334 nativex = get_nativex(default_par);
1336 info->fix = tridentfb_fix;
1337 info->fbops = &tridentfb_ops;
1340 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1341 #ifdef CONFIG_FB_TRIDENT_ACCEL
1342 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1344 if (!fb_find_mode(&info->var, info,
1345 mode_option, NULL, 0, NULL, bpp)) {
1349 err = fb_alloc_cmap(&info->cmap, 256, 0);
1353 if (defaultaccel && default_par->init_accel)
1354 info->var.accel_flags |= FB_ACCELF_TEXT;
1356 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1357 info->var.activate |= FB_ACTIVATE_NOW;
1358 info->device = &dev->dev;
1359 if (register_framebuffer(info) < 0) {
1360 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1361 fb_dealloc_cmap(&info->cmap);
1365 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1366 info->node, info->fix.id, info->var.xres,
1367 info->var.yres, info->var.bits_per_pixel);
1369 pci_set_drvdata(dev, info);
1373 if (info->screen_base)
1374 iounmap(info->screen_base);
1375 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1376 disable_mmio(info->par);
1378 if (default_par->io_virt)
1379 iounmap(default_par->io_virt);
1380 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1381 framebuffer_release(info);
1385 static void __devexit trident_pci_remove(struct pci_dev *dev)
1387 struct fb_info *info = pci_get_drvdata(dev);
1388 struct tridentfb_par *par = info->par;
1390 unregister_framebuffer(info);
1391 iounmap(par->io_virt);
1392 iounmap(info->screen_base);
1393 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1394 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1395 pci_set_drvdata(dev, NULL);
1396 framebuffer_release(info);
1399 /* List of boards that we are trying to support */
1400 static struct pci_device_id trident_devices[] = {
1401 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1402 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1403 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1404 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1405 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1406 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1407 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1408 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1409 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1410 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1411 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1412 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1413 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1414 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1415 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1416 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1417 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1418 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1419 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1420 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1424 MODULE_DEVICE_TABLE(pci, trident_devices);
1426 static struct pci_driver tridentfb_pci_driver = {
1427 .name = "tridentfb",
1428 .id_table = trident_devices,
1429 .probe = trident_pci_probe,
1430 .remove = __devexit_p(trident_pci_remove)
1434 * Parse user specified options (`video=trident:')
1436 * video=trident:800x600,bpp=16,noaccel
1439 static int __init tridentfb_setup(char *options)
1442 if (!options || !*options)
1444 while ((opt = strsep(&options, ",")) != NULL) {
1447 if (!strncmp(opt, "noaccel", 7))
1449 else if (!strncmp(opt, "fp", 2))
1451 else if (!strncmp(opt, "crt", 3))
1453 else if (!strncmp(opt, "bpp=", 4))
1454 bpp = simple_strtoul(opt + 4, NULL, 0);
1455 else if (!strncmp(opt, "center", 6))
1457 else if (!strncmp(opt, "stretch", 7))
1459 else if (!strncmp(opt, "memsize=", 8))
1460 memsize = simple_strtoul(opt + 8, NULL, 0);
1461 else if (!strncmp(opt, "memdiff=", 8))
1462 memdiff = simple_strtoul(opt + 8, NULL, 0);
1463 else if (!strncmp(opt, "nativex=", 8))
1464 nativex = simple_strtoul(opt + 8, NULL, 0);
1472 static int __init tridentfb_init(void)
1475 char *option = NULL;
1477 if (fb_get_options("tridentfb", &option))
1479 tridentfb_setup(option);
1481 output("Trident framebuffer %s initializing\n", VERSION);
1482 return pci_register_driver(&tridentfb_pci_driver);
1485 static void __exit tridentfb_exit(void)
1487 pci_unregister_driver(&tridentfb_pci_driver);
1490 module_init(tridentfb_init);
1491 module_exit(tridentfb_exit);
1493 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1494 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1495 MODULE_LICENSE("GPL");