2 * MPC8610 HPCD Device Tree Source
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License Version 2 as published
8 * by the Free Software Foundation.
14 model = "MPC8610HPCD";
15 compatible = "fsl,MPC8610HPCD";
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1
38 timebase-frequency = <0>; // From uboot
39 bus-frequency = <0>; // From uboot
40 clock-frequency = <0>; // From uboot
45 device_type = "memory";
46 reg = <0x00000000 0x20000000>; // 512M at 0x0
49 board-control@e8000000 {
50 compatible = "fsl,fpga-pixis";
51 reg = <0xe8000000 32>; // pixis at 0xe8000000
57 #interrupt-cells = <2>;
59 compatible = "fsl,mpc8610-immr", "simple-bus";
60 ranges = <0x0 0xe0000000 0x00100000>;
61 reg = <0xe0000000 0x1000>;
68 compatible = "fsl-i2c";
71 interrupt-parent = <&mpic>;
75 compatible = "cirrus,cs4270";
77 /* MCLK source is a stand-alone oscillator */
78 clock-frequency = <12288000>;
86 compatible = "fsl-i2c";
89 interrupt-parent = <&mpic>;
93 serial0: serial@4500 {
95 device_type = "serial";
96 compatible = "ns16550";
98 clock-frequency = <0>;
100 interrupt-parent = <&mpic>;
103 serial1: serial@4600 {
105 device_type = "serial";
106 compatible = "ns16550";
107 reg = <0x4600 0x100>;
108 clock-frequency = <0>;
110 interrupt-parent = <&mpic>;
114 compatible = "fsl,diu";
117 interrupt-parent = <&mpic>;
120 mpic: interrupt-controller@40000 {
121 clock-frequency = <0>;
122 interrupt-controller;
123 #address-cells = <0>;
124 #interrupt-cells = <2>;
125 reg = <0x40000 0x40000>;
126 compatible = "chrp,open-pic";
127 device_type = "open-pic";
131 global-utilities@e0000 {
132 compatible = "fsl,mpc8610-guts";
133 reg = <0xe0000 0x1000>;
138 compatible = "fsl,mpc8610-ssi";
140 reg = <0x16000 0x100>;
141 interrupt-parent = <&mpic>;
143 fsl,mode = "i2s-slave";
144 codec-handle = <&cs4270>;
148 compatible = "fsl,mpc8610-ssi";
150 reg = <0x16100 0x100>;
151 interrupt-parent = <&mpic>;
156 #address-cells = <1>;
158 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
160 reg = <0x21300 0x4>; /* DMA general status register */
161 ranges = <0x0 0x21100 0x200>;
164 compatible = "fsl,mpc8610-dma-channel",
165 "fsl,eloplus-dma-channel";
168 interrupt-parent = <&mpic>;
172 compatible = "fsl,mpc8610-dma-channel",
173 "fsl,eloplus-dma-channel";
176 interrupt-parent = <&mpic>;
180 compatible = "fsl,mpc8610-dma-channel",
181 "fsl,eloplus-dma-channel";
184 interrupt-parent = <&mpic>;
188 compatible = "fsl,mpc8610-dma-channel",
189 "fsl,eloplus-dma-channel";
192 interrupt-parent = <&mpic>;
198 #address-cells = <1>;
200 compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
202 reg = <0xc300 0x4>; /* DMA general status register */
203 ranges = <0x0 0xc100 0x200>;
206 compatible = "fsl,mpc8610-dma-channel",
207 "fsl,mpc8540-dma-channel";
210 interrupt-parent = <&mpic>;
214 compatible = "fsl,mpc8610-dma-channel",
215 "fsl,mpc8540-dma-channel";
218 interrupt-parent = <&mpic>;
222 compatible = "fsl,mpc8610-dma-channel",
223 "fsl,mpc8540-dma-channel";
226 interrupt-parent = <&mpic>;
230 compatible = "fsl,mpc8610-dma-channel",
231 "fsl,mpc8540-dma-channel";
234 interrupt-parent = <&mpic>;
243 compatible = "fsl,mpc8610-pci";
245 #interrupt-cells = <1>;
247 #address-cells = <3>;
248 reg = <0xe0008000 0x1000>;
250 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
251 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
252 clock-frequency = <33333333>;
253 interrupt-parent = <&mpic>;
255 interrupt-map-mask = <0xf800 0 0 7>;
258 0x8800 0 0 1 &mpic 4 1
259 0x8800 0 0 2 &mpic 5 1
260 0x8800 0 0 3 &mpic 6 1
261 0x8800 0 0 4 &mpic 7 1
264 0x9000 0 0 1 &mpic 5 1
265 0x9000 0 0 2 &mpic 6 1
266 0x9000 0 0 3 &mpic 7 1
267 0x9000 0 0 4 &mpic 4 1
271 pci1: pcie@e000a000 {
273 compatible = "fsl,mpc8641-pcie";
275 #interrupt-cells = <1>;
277 #address-cells = <3>;
278 reg = <0xe000a000 0x1000>;
280 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
281 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
282 clock-frequency = <33333333>;
283 interrupt-parent = <&mpic>;
285 interrupt-map-mask = <0xf800 0 0 7>;
289 0xd800 0 0 1 &mpic 2 1
292 0xe000 0 0 1 &mpic 1 1
293 0xe000 0 0 2 &mpic 1 1
294 0xe000 0 0 3 &mpic 1 1
295 0xe000 0 0 4 &mpic 1 1
298 0xf800 0 0 1 &mpic 3 0
299 0xf800 0 0 2 &mpic 0 1
305 #address-cells = <3>;
307 ranges = <0x02000000 0x0 0xa0000000
308 0x02000000 0x0 0xa0000000
310 0x01000000 0x0 0x00000000
311 0x01000000 0x0 0x00000000
316 #address-cells = <3>;
317 ranges = <0x02000000 0x0 0xa0000000
318 0x02000000 0x0 0xa0000000
320 0x01000000 0x0 0x00000000
321 0x01000000 0x0 0x00000000
327 pci2: pcie@e0009000 {
328 #address-cells = <3>;
330 #interrupt-cells = <1>;
332 compatible = "fsl,mpc8641-pcie";
333 reg = <0xe0009000 0x00001000>;
334 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
335 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
337 interrupt-map-mask = <0xf800 0 0 7>;
338 interrupt-map = <0x0000 0 0 1 &mpic 4 1
339 0x0000 0 0 2 &mpic 5 1
340 0x0000 0 0 3 &mpic 6 1
341 0x0000 0 0 4 &mpic 7 1>;
342 interrupt-parent = <&mpic>;
344 clock-frequency = <33333333>;