Merge branch 'irq-fix' of git://www.modarm9.com/gitsrc/pub/people/ukleinek/linux...
[linux-2.6] / drivers / char / drm / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drm.h"
33 #include "i915_drv.h"
34
35 #include "drm_pciids.h"
36
37 static struct pci_device_id pciidlist[] = {
38         i915_PCI_IDS
39 };
40
41 enum pipe {
42     PIPE_A = 0,
43     PIPE_B,
44 };
45
46 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
47 {
48         struct drm_i915_private *dev_priv = dev->dev_private;
49
50         if (pipe == PIPE_A)
51                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
52         else
53                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
54 }
55
56 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
57 {
58         struct drm_i915_private *dev_priv = dev->dev_private;
59         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
60         u32 *array;
61         int i;
62
63         if (!i915_pipe_enabled(dev, pipe))
64                 return;
65
66         if (pipe == PIPE_A)
67                 array = dev_priv->save_palette_a;
68         else
69                 array = dev_priv->save_palette_b;
70
71         for(i = 0; i < 256; i++)
72                 array[i] = I915_READ(reg + (i << 2));
73 }
74
75 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
76 {
77         struct drm_i915_private *dev_priv = dev->dev_private;
78         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
79         u32 *array;
80         int i;
81
82         if (!i915_pipe_enabled(dev, pipe))
83                 return;
84
85         if (pipe == PIPE_A)
86                 array = dev_priv->save_palette_a;
87         else
88                 array = dev_priv->save_palette_b;
89
90         for(i = 0; i < 256; i++)
91                 I915_WRITE(reg + (i << 2), array[i]);
92 }
93
94 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
95 {
96         outb(reg, index_port);
97         return inb(data_port);
98 }
99
100 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
101 {
102         inb(st01);
103         outb(palette_enable | reg, VGA_AR_INDEX);
104         return inb(VGA_AR_DATA_READ);
105 }
106
107 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
108 {
109         inb(st01);
110         outb(palette_enable | reg, VGA_AR_INDEX);
111         outb(val, VGA_AR_DATA_WRITE);
112 }
113
114 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
115 {
116         outb(reg, index_port);
117         outb(val, data_port);
118 }
119
120 static void i915_save_vga(struct drm_device *dev)
121 {
122         struct drm_i915_private *dev_priv = dev->dev_private;
123         int i;
124         u16 cr_index, cr_data, st01;
125
126         /* VGA color palette registers */
127         dev_priv->saveDACMASK = inb(VGA_DACMASK);
128         /* DACCRX automatically increments during read */
129         outb(0, VGA_DACRX);
130         /* Read 3 bytes of color data from each index */
131         for (i = 0; i < 256 * 3; i++)
132                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
133
134         /* MSR bits */
135         dev_priv->saveMSR = inb(VGA_MSR_READ);
136         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
137                 cr_index = VGA_CR_INDEX_CGA;
138                 cr_data = VGA_CR_DATA_CGA;
139                 st01 = VGA_ST01_CGA;
140         } else {
141                 cr_index = VGA_CR_INDEX_MDA;
142                 cr_data = VGA_CR_DATA_MDA;
143                 st01 = VGA_ST01_MDA;
144         }
145
146         /* CRT controller regs */
147         i915_write_indexed(cr_index, cr_data, 0x11,
148                            i915_read_indexed(cr_index, cr_data, 0x11) &
149                            (~0x80));
150         for (i = 0; i < 0x24; i++)
151                 dev_priv->saveCR[i] =
152                         i915_read_indexed(cr_index, cr_data, i);
153         /* Make sure we don't turn off CR group 0 writes */
154         dev_priv->saveCR[0x11] &= ~0x80;
155
156         /* Attribute controller registers */
157         inb(st01);
158         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
159         for (i = 0; i < 20; i++)
160                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
161         inb(st01);
162         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
163         inb(st01);
164
165         /* Graphics controller registers */
166         for (i = 0; i < 9; i++)
167                 dev_priv->saveGR[i] =
168                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
169
170         dev_priv->saveGR[0x10] =
171                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
172         dev_priv->saveGR[0x11] =
173                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
174         dev_priv->saveGR[0x18] =
175                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
176
177         /* Sequencer registers */
178         for (i = 0; i < 8; i++)
179                 dev_priv->saveSR[i] =
180                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
181 }
182
183 static void i915_restore_vga(struct drm_device *dev)
184 {
185         struct drm_i915_private *dev_priv = dev->dev_private;
186         int i;
187         u16 cr_index, cr_data, st01;
188
189         /* MSR bits */
190         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
191         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
192                 cr_index = VGA_CR_INDEX_CGA;
193                 cr_data = VGA_CR_DATA_CGA;
194                 st01 = VGA_ST01_CGA;
195         } else {
196                 cr_index = VGA_CR_INDEX_MDA;
197                 cr_data = VGA_CR_DATA_MDA;
198                 st01 = VGA_ST01_MDA;
199         }
200
201         /* Sequencer registers, don't write SR07 */
202         for (i = 0; i < 7; i++)
203                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
204                                    dev_priv->saveSR[i]);
205
206         /* CRT controller regs */
207         /* Enable CR group 0 writes */
208         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
209         for (i = 0; i < 0x24; i++)
210                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
211
212         /* Graphics controller regs */
213         for (i = 0; i < 9; i++)
214                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
215                                    dev_priv->saveGR[i]);
216
217         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
218                            dev_priv->saveGR[0x10]);
219         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
220                            dev_priv->saveGR[0x11]);
221         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
222                            dev_priv->saveGR[0x18]);
223
224         /* Attribute controller registers */
225         inb(st01);
226         for (i = 0; i < 20; i++)
227                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
228         inb(st01); /* switch back to index mode */
229         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
230         inb(st01);
231
232         /* VGA color palette registers */
233         outb(dev_priv->saveDACMASK, VGA_DACMASK);
234         /* DACCRX automatically increments during read */
235         outb(0, VGA_DACWX);
236         /* Read 3 bytes of color data from each index */
237         for (i = 0; i < 256 * 3; i++)
238                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
239
240 }
241
242 static int i915_suspend(struct drm_device *dev, pm_message_t state)
243 {
244         struct drm_i915_private *dev_priv = dev->dev_private;
245         int i;
246
247         if (!dev || !dev_priv) {
248                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
249                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
250                 return -ENODEV;
251         }
252
253         if (state.event == PM_EVENT_PRETHAW)
254                 return 0;
255
256         pci_save_state(dev->pdev);
257         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
258
259         /* Pipe & plane A info */
260         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
261         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
262         dev_priv->saveFPA0 = I915_READ(FPA0);
263         dev_priv->saveFPA1 = I915_READ(FPA1);
264         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
265         if (IS_I965G(dev))
266                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
267         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
268         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
269         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
270         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
271         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
272         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
273         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
274
275         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
276         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
277         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
278         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
279         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
280         if (IS_I965G(dev)) {
281                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
282                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
283         }
284         i915_save_palette(dev, PIPE_A);
285         dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
286
287         /* Pipe & plane B info */
288         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
289         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
290         dev_priv->saveFPB0 = I915_READ(FPB0);
291         dev_priv->saveFPB1 = I915_READ(FPB1);
292         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
293         if (IS_I965G(dev))
294                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
295         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
296         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
297         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
298         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
299         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
300         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
301         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
302
303         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
304         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
305         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
306         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
307         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
308         if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
309                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
310                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
311         }
312         i915_save_palette(dev, PIPE_B);
313         dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
314
315         /* CRT state */
316         dev_priv->saveADPA = I915_READ(ADPA);
317
318         /* LVDS state */
319         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
320         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
321         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
322         if (IS_I965G(dev))
323                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
324         if (IS_MOBILE(dev) && !IS_I830(dev))
325                 dev_priv->saveLVDS = I915_READ(LVDS);
326         if (!IS_I830(dev) && !IS_845G(dev))
327                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
328         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
329         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
330         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
331
332         /* FIXME: save TV & SDVO state */
333
334         /* FBC state */
335         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
336         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
337         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
338         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
339
340         /* Interrupt state */
341         dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
342         dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
343         dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
344
345         /* VGA state */
346         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
347         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
348         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
349         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
350
351         /* Clock gating state */
352         dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
353
354         /* Cache mode state */
355         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
356
357         /* Memory Arbitration state */
358         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
359
360         /* Scratch space */
361         for (i = 0; i < 16; i++) {
362                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
363                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
364         }
365         for (i = 0; i < 3; i++)
366                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
367
368         i915_save_vga(dev);
369
370         if (state.event == PM_EVENT_SUSPEND) {
371                 /* Shut down the device */
372                 pci_disable_device(dev->pdev);
373                 pci_set_power_state(dev->pdev, PCI_D3hot);
374         }
375
376         return 0;
377 }
378
379 static int i915_resume(struct drm_device *dev)
380 {
381         struct drm_i915_private *dev_priv = dev->dev_private;
382         int i;
383
384         pci_set_power_state(dev->pdev, PCI_D0);
385         pci_restore_state(dev->pdev);
386         if (pci_enable_device(dev->pdev))
387                 return -1;
388
389         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
390
391         /* Pipe & plane A info */
392         /* Prime the clock */
393         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
394                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
395                            ~DPLL_VCO_ENABLE);
396                 udelay(150);
397         }
398         I915_WRITE(FPA0, dev_priv->saveFPA0);
399         I915_WRITE(FPA1, dev_priv->saveFPA1);
400         /* Actually enable it */
401         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
402         udelay(150);
403         if (IS_I965G(dev))
404                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
405         udelay(150);
406
407         /* Restore mode */
408         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
409         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
410         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
411         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
412         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
413         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
414         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
415
416         /* Restore plane info */
417         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
418         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
419         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
420         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
421         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
422         if (IS_I965G(dev)) {
423                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
424                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
425         }
426
427         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
428
429         i915_restore_palette(dev, PIPE_A);
430         /* Enable the plane */
431         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
432         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
433
434         /* Pipe & plane B info */
435         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
436                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
437                            ~DPLL_VCO_ENABLE);
438                 udelay(150);
439         }
440         I915_WRITE(FPB0, dev_priv->saveFPB0);
441         I915_WRITE(FPB1, dev_priv->saveFPB1);
442         /* Actually enable it */
443         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
444         udelay(150);
445         if (IS_I965G(dev))
446                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
447         udelay(150);
448
449         /* Restore mode */
450         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
451         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
452         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
453         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
454         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
455         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
456         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
457
458         /* Restore plane info */
459         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
460         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
461         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
462         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
463         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
464         if (IS_I965G(dev)) {
465                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
466                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
467         }
468
469         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
470
471         i915_restore_palette(dev, PIPE_B);
472         /* Enable the plane */
473         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
474         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
475
476         /* CRT state */
477         I915_WRITE(ADPA, dev_priv->saveADPA);
478
479         /* LVDS state */
480         if (IS_I965G(dev))
481                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
482         if (IS_MOBILE(dev) && !IS_I830(dev))
483                 I915_WRITE(LVDS, dev_priv->saveLVDS);
484         if (!IS_I830(dev) && !IS_845G(dev))
485                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
486
487         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
488         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
489         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
490         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
491         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
492         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
493
494         /* FIXME: restore TV & SDVO state */
495
496         /* FBC info */
497         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
498         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
499         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
500         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
501
502         /* VGA state */
503         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
504         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
505         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
506         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
507         udelay(150);
508
509         /* Clock gating state */
510         I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
511
512         /* Cache mode state */
513         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
514
515         /* Memory arbitration state */
516         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
517
518         for (i = 0; i < 16; i++) {
519                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
520                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
521         }
522         for (i = 0; i < 3; i++)
523                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
524
525         i915_restore_vga(dev);
526
527         return 0;
528 }
529
530 static struct drm_driver driver = {
531         /* don't use mtrr's here, the Xserver or user space app should
532          * deal with them for intel hardware.
533          */
534         .driver_features =
535             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
536             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
537         .load = i915_driver_load,
538         .unload = i915_driver_unload,
539         .lastclose = i915_driver_lastclose,
540         .preclose = i915_driver_preclose,
541         .suspend = i915_suspend,
542         .resume = i915_resume,
543         .device_is_agp = i915_driver_device_is_agp,
544         .get_vblank_counter = i915_get_vblank_counter,
545         .enable_vblank = i915_enable_vblank,
546         .disable_vblank = i915_disable_vblank,
547         .irq_preinstall = i915_driver_irq_preinstall,
548         .irq_postinstall = i915_driver_irq_postinstall,
549         .irq_uninstall = i915_driver_irq_uninstall,
550         .irq_handler = i915_driver_irq_handler,
551         .reclaim_buffers = drm_core_reclaim_buffers,
552         .get_map_ofs = drm_core_get_map_ofs,
553         .get_reg_ofs = drm_core_get_reg_ofs,
554         .ioctls = i915_ioctls,
555         .fops = {
556                  .owner = THIS_MODULE,
557                  .open = drm_open,
558                  .release = drm_release,
559                  .ioctl = drm_ioctl,
560                  .mmap = drm_mmap,
561                  .poll = drm_poll,
562                  .fasync = drm_fasync,
563 #ifdef CONFIG_COMPAT
564                  .compat_ioctl = i915_compat_ioctl,
565 #endif
566         },
567
568         .pci_driver = {
569                  .name = DRIVER_NAME,
570                  .id_table = pciidlist,
571         },
572
573         .name = DRIVER_NAME,
574         .desc = DRIVER_DESC,
575         .date = DRIVER_DATE,
576         .major = DRIVER_MAJOR,
577         .minor = DRIVER_MINOR,
578         .patchlevel = DRIVER_PATCHLEVEL,
579 };
580
581 static int __init i915_init(void)
582 {
583         driver.num_ioctls = i915_max_ioctl;
584         return drm_init(&driver);
585 }
586
587 static void __exit i915_exit(void)
588 {
589         drm_exit(&driver);
590 }
591
592 module_init(i915_init);
593 module_exit(i915_exit);
594
595 MODULE_AUTHOR(DRIVER_AUTHOR);
596 MODULE_DESCRIPTION(DRIVER_DESC);
597 MODULE_LICENSE("GPL and additional rights");